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-rw-r--r--drivers/gpu/nvgpu/pstate/pstate.c40
-rw-r--r--drivers/gpu/nvgpu/pstate/pstate.h9
2 files changed, 47 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index e9b9775e..0dc15201 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -234,7 +234,7 @@ static int parse_pstate_entry_5x(struct gk20a *g,
234 memset(pstate, 0, sizeof(struct pstate)); 234 memset(pstate, 0, sizeof(struct pstate));
235 pstate->super.type = CTRL_PERF_PSTATE_TYPE_3X; 235 pstate->super.type = CTRL_PERF_PSTATE_TYPE_3X;
236 pstate->num = 0x0F - entry->pstate_level; 236 pstate->num = 0x0F - entry->pstate_level;
237 pstate->clklist.clksetinfolistsize = hdr->clock_entry_count; 237 pstate->clklist.num_info = hdr->clock_entry_count;
238 238
239 gk20a_dbg_info("pstate P%u", pstate->num); 239 gk20a_dbg_info("pstate P%u", pstate->num);
240 240
@@ -357,3 +357,41 @@ static int pstate_sw_setup(struct gk20a *g)
357done: 357done:
358 return err; 358 return err;
359} 359}
360
361static struct pstate *pstate_find(struct gk20a *g, u32 num)
362{
363 struct pstates *pstates = &(g->perf_pmu.pstatesobjs);
364 struct pstate *pstate;
365 u8 i;
366
367 gk20a_dbg_info("pstates = %p", pstates);
368
369 BOARDOBJGRP_FOR_EACH(&pstates->super.super,
370 struct pstate *, pstate, i) {
371 gk20a_dbg_info("pstate=%p num=%u (looking for num=%u)",
372 pstate, pstate->num, num);
373 if (pstate->num == num)
374 return pstate;
375 }
376 return NULL;
377}
378
379struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g,
380 u32 pstate_num, enum nv_pmu_clk_clkwhich clkwhich)
381{
382 struct pstate *pstate = pstate_find(g, pstate_num);
383 struct clk_set_info *info;
384 u32 clkidx;
385
386 gk20a_dbg_info("pstate = %p", pstate);
387
388 if (!pstate)
389 return NULL;
390
391 for (clkidx = 0; clkidx < pstate->clklist.num_info; clkidx++) {
392 info = &pstate->clklist.clksetinfo[clkidx];
393 if (info->clkwhich == clkwhich)
394 return info;
395 }
396 return NULL;
397}
diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h
index 11fa4c77..4ae72aa9 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.h
+++ b/drivers/gpu/nvgpu/pstate/pstate.h
@@ -20,6 +20,10 @@
20 20
21#define CTRL_PERF_PSTATE_TYPE_3X 0x3 21#define CTRL_PERF_PSTATE_TYPE_3X 0x3
22 22
23#define CTRL_PERF_PSTATE_P0 0
24#define CTRL_PERF_PSTATE_P5 5
25#define CTRL_PERF_PSTATE_P8 8
26
23#define CLK_SET_INFO_MAX_SIZE (32) 27#define CLK_SET_INFO_MAX_SIZE (32)
24 28
25struct clk_set_info { 29struct clk_set_info {
@@ -30,7 +34,7 @@ struct clk_set_info {
30}; 34};
31 35
32struct clk_set_info_list { 36struct clk_set_info_list {
33 u32 clksetinfolistsize; 37 u32 num_info;
34 struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE]; 38 struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
35}; 39};
36 40
@@ -48,4 +52,7 @@ struct pstates {
48int gk20a_init_pstate_support(struct gk20a *g); 52int gk20a_init_pstate_support(struct gk20a *g);
49int gk20a_init_pstate_pmu_support(struct gk20a *g); 53int gk20a_init_pstate_pmu_support(struct gk20a *g);
50 54
55struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
56 enum nv_pmu_clk_clkwhich clkwhich);
57
51#endif /* __PSTATE_H__ */ 58#endif /* __PSTATE_H__ */