diff options
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif')
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifbios.h | 41 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h | 196 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifclk.h | 414 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifperf.h | 116 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h | 220 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifvolt.h | 33 |
6 files changed, 1020 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifbios.h b/drivers/gpu/nvgpu/pmuif/gpmuifbios.h new file mode 100644 index 00000000..2581d3fa --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifbios.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFBIOS_H_ | ||
14 | #define _GPMUIFBIOS_H_ | ||
15 | |||
16 | struct nv_pmu_bios_vfield_register_segment_super { | ||
17 | u8 type; | ||
18 | u8 low_bit; | ||
19 | u8 high_bit; | ||
20 | }; | ||
21 | |||
22 | struct nv_pmu_bios_vfield_register_segment_reg { | ||
23 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
24 | u32 addr; | ||
25 | }; | ||
26 | |||
27 | struct nv_pmu_bios_vfield_register_segment_index_reg { | ||
28 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
29 | u32 addr; | ||
30 | u32 reg_index; | ||
31 | u32 index; | ||
32 | }; | ||
33 | |||
34 | union nv_pmu_bios_vfield_register_segment { | ||
35 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
36 | struct nv_pmu_bios_vfield_register_segment_reg reg; | ||
37 | struct nv_pmu_bios_vfield_register_segment_index_reg index_reg; | ||
38 | }; | ||
39 | |||
40 | |||
41 | #endif /* _GPMUIFBIOS_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h new file mode 100644 index 00000000..7a061472 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h | |||
@@ -0,0 +1,196 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFBOARDOBJ_H_ | ||
14 | #define _GPMUIFBOARDOBJ_H_ | ||
15 | |||
16 | #include "gk20a/gk20a.h" | ||
17 | #include "gk20a/pmu_gk20a.h" | ||
18 | #include "ctrl/ctrlboardobj.h" | ||
19 | |||
20 | /* | ||
21 | * Base structure describing a BOARDOBJ for communication between Kernel and | ||
22 | * PMU. | ||
23 | */ | ||
24 | struct nv_pmu_boardobj { | ||
25 | u8 type; | ||
26 | }; | ||
27 | |||
28 | /* | ||
29 | * Base structure describing a BOARDOBJ for Query interface between Kernel and | ||
30 | * PMU. | ||
31 | */ | ||
32 | struct nv_pmu_boardobj_query { | ||
33 | u8 type; | ||
34 | }; | ||
35 | |||
36 | /* | ||
37 | * Virtual base structure describing a BOARDOBJGRP interface between Kernel and | ||
38 | * PMU. | ||
39 | */ | ||
40 | struct nv_pmu_boardobjgrp_super { | ||
41 | u8 type; | ||
42 | u8 class_id; | ||
43 | u8 obj_slots; | ||
44 | u8 rsvd; | ||
45 | }; | ||
46 | |||
47 | struct nv_pmu_boardobjgrp { | ||
48 | struct nv_pmu_boardobjgrp_super super; | ||
49 | u32 obj_mask; | ||
50 | }; | ||
51 | |||
52 | struct nv_pmu_boardobjgrp_e32 { | ||
53 | struct nv_pmu_boardobjgrp_super super; | ||
54 | struct ctrl_boardobjgrp_mask_e32 obj_mask; | ||
55 | }; | ||
56 | |||
57 | struct nv_pmu_boardobjgrp_e255 { | ||
58 | struct nv_pmu_boardobjgrp_super super; | ||
59 | struct ctrl_boardobjgrp_mask_e255 obj_mask; | ||
60 | }; | ||
61 | |||
62 | struct nv_pmu_boardobj_cmd_grp_payload { | ||
63 | struct pmu_allocation_v3 dmem_buf; | ||
64 | struct flcn_mem_desc_v0 fb; | ||
65 | u8 hdr_size; | ||
66 | u8 entry_size; | ||
67 | }; | ||
68 | |||
69 | struct nv_pmu_boardobj_cmd_grp { | ||
70 | u8 cmd_type; | ||
71 | u8 pad[2]; | ||
72 | u8 class_id; | ||
73 | struct nv_pmu_boardobj_cmd_grp_payload grp; | ||
74 | }; | ||
75 | |||
76 | #define NV_PMU_BOARDOBJ_GRP_ALLOC_OFFSET \ | ||
77 | (NV_OFFSETOF(NV_PMU_BOARDOBJ_CMD_GRP, grp)) | ||
78 | |||
79 | struct nv_pmu_boardobj_cmd { | ||
80 | union { | ||
81 | u8 cmd_type; | ||
82 | struct nv_pmu_boardobj_cmd_grp grp; | ||
83 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
84 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
85 | }; | ||
86 | }; | ||
87 | |||
88 | struct nv_pmu_boardobj_msg_grp { | ||
89 | u8 msg_type; | ||
90 | bool b_success; | ||
91 | flcn_status flcn_status; | ||
92 | u8 class_id; | ||
93 | }; | ||
94 | |||
95 | struct nv_pmu_boardobj_msg { | ||
96 | union { | ||
97 | u8 msg_type; | ||
98 | struct nv_pmu_boardobj_msg_grp grp; | ||
99 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
100 | struct nv_pmu_boardobj_msg_grp grp_get_status; | ||
101 | }; | ||
102 | }; | ||
103 | |||
104 | /* | ||
105 | * Macro generating structures describing classes which implement | ||
106 | * NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. | ||
107 | * | ||
108 | * @para _eng Name of implementing engine in which this structure is | ||
109 | * found. | ||
110 | * @param _class Class ID of Objects within Board Object Group. | ||
111 | * @param _slots Max number of elements this group can contain. | ||
112 | */ | ||
113 | #define NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, _slots) \ | ||
114 | NV_PMU_MAKE_ALIGNED_STRUCT( \ | ||
115 | nv_pmu_##_eng##_##_class##_boardobjgrp_set_header, one_structure); \ | ||
116 | NV_PMU_MAKE_ALIGNED_UNION( \ | ||
117 | nv_pmu_##_eng##_##_class##_boardobj_set_union, one_union); \ | ||
118 | struct nv_pmu_##_eng##_##_class##_boardobj_grp_set { \ | ||
119 | union nv_pmu_##_eng##_##_class##_boardobjgrp_set_header_aligned hdr; \ | ||
120 | union nv_pmu_##_eng##_##_class##_boardobj_set_union_aligned objects[(_slots)];\ | ||
121 | } | ||
122 | |||
123 | /* | ||
124 | * Macro generating structures describing classes which implement | ||
125 | * NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. | ||
126 | * | ||
127 | * @para _eng Name of implementing engine in which this structure is | ||
128 | * found. | ||
129 | * @param _class Class ID of Objects within Board Object Group. | ||
130 | */ | ||
131 | #define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(_eng, _class) \ | ||
132 | NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ | ||
133 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) | ||
134 | |||
135 | /* | ||
136 | * Macro generating structures describing classes which implement | ||
137 | * NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. | ||
138 | * | ||
139 | * @para _eng Name of implementing engine in which this structure is | ||
140 | * found. | ||
141 | * @param _class Class ID of Objects within Board Object Group. | ||
142 | */ | ||
143 | #define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(_eng, _class) \ | ||
144 | NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ | ||
145 | CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) | ||
146 | |||
147 | /* | ||
148 | * Macro generating structures for querying dynamic state for classes which | ||
149 | * implement NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS | ||
150 | * interface. | ||
151 | * | ||
152 | * @para _eng Name of implementing engine in which this structure is | ||
153 | * found. | ||
154 | * @param _class Class ID of Objects within Board Object Group. | ||
155 | * @param _slots Max number of elements this group can contain. | ||
156 | */ | ||
157 | #define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, _slots) \ | ||
158 | NV_PMU_MAKE_ALIGNED_STRUCT( \ | ||
159 | nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header, struct); \ | ||
160 | NV_PMU_MAKE_ALIGNED_UNION( \ | ||
161 | nv_pmu_##_eng##_##_class##_boardobj_get_status_union, union); \ | ||
162 | struct nv_pmu_##_eng##_##_class##_boardobj_grp_get_status { \ | ||
163 | union nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header_aligned \ | ||
164 | hdr; \ | ||
165 | union nv_pmu_##_eng##_##_class##_boardobj_get_status_union_aligned \ | ||
166 | objects[(_slots)]; \ | ||
167 | } | ||
168 | |||
169 | /* | ||
170 | * Macro generating structures for querying dynamic state for classes which | ||
171 | * implement NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS | ||
172 | * interface. | ||
173 | * | ||
174 | * @para _eng Name of implementing engine in which this structure is | ||
175 | * found. | ||
176 | * @param _class Class ID of Objects within Board Object Group. | ||
177 | */ | ||
178 | #define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(_eng, _class) \ | ||
179 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ | ||
180 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) | ||
181 | |||
182 | /* | ||
183 | * Macro generating structures for querying dynamic state for classes which | ||
184 | * implement NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS | ||
185 | * interface. | ||
186 | * | ||
187 | * @para _eng Name of implementing engine in which this structure is | ||
188 | * found. | ||
189 | * @param _class Class ID of Objects within Board Object Group. | ||
190 | */ | ||
191 | #define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(_eng, _class) \ | ||
192 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ | ||
193 | CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) | ||
194 | |||
195 | |||
196 | #endif /* _GPMUIFBOARDOBJ_H_ */ | ||
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h new file mode 100644 index 00000000..36b9aace --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h | |||
@@ -0,0 +1,414 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _GPMUIFCLK_H_ | ||
15 | #define _GPMUIFCLK_H_ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | #include "gk20a/pmu_gk20a.h" | ||
19 | #include "ctrl/ctrlboardobj.h" | ||
20 | #include "ctrl/ctrlvolt.h" | ||
21 | #include "ctrl/ctrlperf.h" | ||
22 | #include "ctrl/ctrlclk.h" | ||
23 | #include "pmuif/gpmuifboardobj.h" | ||
24 | #include "pmuif/gpmuifvolt.h" | ||
25 | #include "gk20a/pmu_common.h" | ||
26 | |||
27 | enum nv_pmu_clk_clkwhich { | ||
28 | clkwhich_mclk = 5, | ||
29 | clkwhich_dispclk = 7, | ||
30 | clkwhich_gpc2clk = 17, | ||
31 | clkwhich_xbar2clk = 19, | ||
32 | clkwhich_sys2clk = 20, | ||
33 | clkwhich_hub2clk = 21, | ||
34 | clkwhich_pwrclk = 24, | ||
35 | clkwhich_nvdclk = 25, | ||
36 | clkwhich_pciegenclk = 31, | ||
37 | }; | ||
38 | |||
39 | /* | ||
40 | * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId" | ||
41 | * argument for communications between Kernel and PMU via the various generic | ||
42 | * BOARDOBJGRP interfaces. | ||
43 | */ | ||
44 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00 | ||
45 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01 | ||
46 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 | ||
47 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 | ||
48 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 | ||
49 | |||
50 | /*! | ||
51 | * CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the | ||
52 | * CLK_DOMAIN feature. | ||
53 | */ | ||
54 | struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { | ||
55 | struct nv_pmu_boardobjgrp_e32 super; | ||
56 | u32 vbios_domains; | ||
57 | struct ctrl_boardobjgrp_mask_e32 master_domains_mask; | ||
58 | u16 cntr_sampling_periodms; | ||
59 | bool b_override_o_v_o_c; | ||
60 | bool b_debug_mode; | ||
61 | bool b_enforce_vf_monotonicity; | ||
62 | u8 volt_rails_max; | ||
63 | struct ctrl_clk_clk_delta deltas; | ||
64 | }; | ||
65 | |||
66 | struct nv_pmu_clk_clk_domain_boardobj_set { | ||
67 | struct nv_pmu_boardobj super; | ||
68 | enum nv_pmu_clk_clkwhich domain; | ||
69 | u32 api_domain; | ||
70 | u8 perf_domain_grp_idx; | ||
71 | }; | ||
72 | |||
73 | struct nv_pmu_clk_clk_domain_3x_boardobj_set { | ||
74 | struct nv_pmu_clk_clk_domain_boardobj_set super; | ||
75 | bool b_noise_aware_capable; | ||
76 | }; | ||
77 | |||
78 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set { | ||
79 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; | ||
80 | u16 freq_mhz; | ||
81 | }; | ||
82 | |||
83 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { | ||
84 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; | ||
85 | u8 clk_prog_idx_first; | ||
86 | u8 clk_prog_idx_last; | ||
87 | u8 noise_unaware_ordering_index; | ||
88 | u8 noise_aware_ordering_index; | ||
89 | bool b_force_noise_unaware_ordering; | ||
90 | int factory_offset_khz; | ||
91 | short freq_delta_min_mhz; | ||
92 | short freq_delta_max_mhz; | ||
93 | struct ctrl_clk_clk_delta deltas; | ||
94 | }; | ||
95 | |||
96 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { | ||
97 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
98 | u32 slave_idxs_mask; | ||
99 | }; | ||
100 | |||
101 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { | ||
102 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
103 | u8 master_idx; | ||
104 | }; | ||
105 | |||
106 | union nv_pmu_clk_clk_domain_boardobj_set_union { | ||
107 | struct nv_pmu_boardobj board_obj; | ||
108 | struct nv_pmu_clk_clk_domain_boardobj_set super; | ||
109 | struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; | ||
110 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; | ||
111 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; | ||
112 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; | ||
113 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; | ||
114 | }; | ||
115 | |||
116 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); | ||
117 | |||
118 | struct nv_pmu_clk_clk_prog_boardobjgrp_set_header { | ||
119 | struct nv_pmu_boardobjgrp_e255 super; | ||
120 | u8 slave_entry_count; | ||
121 | u8 vf_entry_count; | ||
122 | }; | ||
123 | |||
124 | struct nv_pmu_clk_clk_prog_boardobj_set { | ||
125 | struct nv_pmu_boardobj super; | ||
126 | }; | ||
127 | |||
128 | struct nv_pmu_clk_clk_prog_1x_boardobj_set { | ||
129 | struct nv_pmu_clk_clk_prog_boardobj_set super; | ||
130 | u8 source; | ||
131 | u16 freq_max_mhz; | ||
132 | union ctrl_clk_clk_prog_1x_source_data source_data; | ||
133 | }; | ||
134 | |||
135 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { | ||
136 | struct nv_pmu_clk_clk_prog_1x_boardobj_set super; | ||
137 | bool b_o_c_o_v_enabled; | ||
138 | struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ | ||
139 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; | ||
140 | struct ctrl_clk_clk_delta deltas; | ||
141 | }; | ||
142 | |||
143 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { | ||
144 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | ||
145 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ | ||
146 | CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | ||
147 | }; | ||
148 | |||
149 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { | ||
150 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | ||
151 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry | ||
152 | slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | ||
153 | }; | ||
154 | |||
155 | union nv_pmu_clk_clk_prog_boardobj_set_union { | ||
156 | struct nv_pmu_boardobj board_obj; | ||
157 | struct nv_pmu_clk_clk_prog_boardobj_set super; | ||
158 | struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x; | ||
159 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master; | ||
160 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio; | ||
161 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table; | ||
162 | }; | ||
163 | |||
164 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog); | ||
165 | |||
166 | struct nv_pmu_clk_lut_device_desc { | ||
167 | u8 vselect_mode; | ||
168 | u16 hysteresis_threshold; | ||
169 | }; | ||
170 | |||
171 | struct nv_pmu_clk_regime_desc { | ||
172 | u8 regime_id; | ||
173 | u16 fixed_freq_regime_limit_mhz; | ||
174 | }; | ||
175 | |||
176 | struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header { | ||
177 | struct nv_pmu_boardobjgrp_e32 super; | ||
178 | struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask; | ||
179 | u32 lut_step_size_uv; | ||
180 | u32 lut_min_voltage_uv; | ||
181 | u8 lut_num_entries; | ||
182 | u16 max_min_freq_mhz; | ||
183 | }; | ||
184 | |||
185 | struct nv_pmu_clk_clk_fll_device_boardobj_set { | ||
186 | struct nv_pmu_boardobj super; | ||
187 | u8 id; | ||
188 | u8 mdiv; | ||
189 | u8 vin_idx_logic; | ||
190 | u8 vin_idx_sram; | ||
191 | u8 rail_idx_for_lut; | ||
192 | u16 input_freq_mhz; | ||
193 | u32 clk_domain; | ||
194 | struct nv_pmu_clk_lut_device_desc lut_device; | ||
195 | struct nv_pmu_clk_regime_desc regime_desc; | ||
196 | u8 min_freq_vfe_idx; | ||
197 | u8 freq_ctrl_idx; | ||
198 | struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; | ||
199 | }; | ||
200 | |||
201 | union nv_pmu_clk_clk_fll_device_boardobj_set_union { | ||
202 | struct nv_pmu_boardobj board_obj; | ||
203 | struct nv_pmu_clk_clk_fll_device_boardobj_set super; | ||
204 | }; | ||
205 | |||
206 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device); | ||
207 | |||
208 | struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header { | ||
209 | struct nv_pmu_boardobjgrp_e32 super; | ||
210 | bool b_vin_is_disable_allowed; | ||
211 | }; | ||
212 | |||
213 | struct nv_pmu_clk_clk_vin_device_boardobj_set { | ||
214 | struct nv_pmu_boardobj super; | ||
215 | u8 id; | ||
216 | u8 volt_domain; | ||
217 | u32 slope; | ||
218 | u32 intercept; | ||
219 | u32 flls_shared_mask; | ||
220 | }; | ||
221 | |||
222 | union nv_pmu_clk_clk_vin_device_boardobj_set_union { | ||
223 | struct nv_pmu_boardobj board_obj; | ||
224 | struct nv_pmu_clk_clk_vin_device_boardobj_set super; | ||
225 | }; | ||
226 | |||
227 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device); | ||
228 | |||
229 | struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header { | ||
230 | struct nv_pmu_boardobjgrp_e255 super; | ||
231 | }; | ||
232 | |||
233 | struct nv_pmu_clk_clk_vf_point_boardobj_set { | ||
234 | struct nv_pmu_boardobj super; | ||
235 | u8 vfe_equ_idx; | ||
236 | u8 volt_rail_idx; | ||
237 | }; | ||
238 | |||
239 | struct nv_pmu_clk_clk_vf_point_freq_boardobj_set { | ||
240 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
241 | u16 freq_mhz; | ||
242 | int volt_delta_uv; | ||
243 | }; | ||
244 | |||
245 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_set { | ||
246 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
247 | u32 source_voltage_uv; | ||
248 | u8 vf_gain_vfe_equ_idx; | ||
249 | u8 clk_domain_idx; | ||
250 | int freq_delta_khz; | ||
251 | }; | ||
252 | |||
253 | union nv_pmu_clk_clk_vf_point_boardobj_set_union { | ||
254 | struct nv_pmu_boardobj board_obj; | ||
255 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
256 | struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq; | ||
257 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt; | ||
258 | }; | ||
259 | |||
260 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point); | ||
261 | |||
262 | struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header { | ||
263 | struct nv_pmu_boardobjgrp_e255 super; | ||
264 | }; | ||
265 | |||
266 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status { | ||
267 | struct nv_pmu_boardobj super; | ||
268 | struct ctrl_clk_vf_pair pair; | ||
269 | }; | ||
270 | |||
271 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status { | ||
272 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; | ||
273 | u16 vf_gain_value; | ||
274 | }; | ||
275 | |||
276 | union nv_pmu_clk_clk_vf_point_boardobj_get_status_union { | ||
277 | struct nv_pmu_boardobj board_obj; | ||
278 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; | ||
279 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt; | ||
280 | }; | ||
281 | |||
282 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point); | ||
283 | |||
284 | #define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12) | ||
285 | |||
286 | struct nv_pmu_clk_clk_domain_list { | ||
287 | u8 num_domains; | ||
288 | struct ctrl_clk_clk_domain_list_item clk_domains[ | ||
289 | NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; | ||
290 | }; | ||
291 | |||
292 | struct nv_pmu_clk_vf_change_inject { | ||
293 | u8 flags; | ||
294 | struct nv_pmu_clk_clk_domain_list clk_list; | ||
295 | struct nv_pmu_volt_volt_rail_list volt_list; | ||
296 | }; | ||
297 | |||
298 | #define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) | ||
299 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) | ||
300 | |||
301 | struct nv_pmu_clk_load_payload_freq_controllers { | ||
302 | struct ctrl_boardobjgrp_mask_e32 load_mask; | ||
303 | }; | ||
304 | |||
305 | struct nv_pmu_clk_load { | ||
306 | u8 feature; | ||
307 | u32 action_mask; | ||
308 | union { | ||
309 | struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; | ||
310 | } payload; | ||
311 | }; | ||
312 | |||
313 | /* CLK CMD ID definitions. */ | ||
314 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
315 | #define NV_PMU_CLK_CMD_ID_RPC (0x00000001) | ||
316 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
317 | |||
318 | #define NV_PMU_CLK_RPC_ID_LOAD (0x00000002) | ||
319 | #define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001) | ||
320 | |||
321 | struct nv_pmu_clk_cmd_rpc { | ||
322 | u8 cmd_type; | ||
323 | u8 pad[3]; | ||
324 | struct nv_pmu_allocation request; | ||
325 | }; | ||
326 | |||
327 | #define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \ | ||
328 | (offsetof(struct nv_pmu_clk_cmd_rpc, request)) | ||
329 | |||
330 | struct nv_pmu_clk_cmd { | ||
331 | union { | ||
332 | u8 cmd_type; | ||
333 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
334 | struct nv_pmu_clk_cmd_rpc rpc; | ||
335 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
336 | }; | ||
337 | }; | ||
338 | |||
339 | struct nv_pmu_clk_rpc { | ||
340 | u8 function; | ||
341 | bool b_supported; | ||
342 | bool b_success; | ||
343 | flcn_status flcn_status; | ||
344 | union { | ||
345 | struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; | ||
346 | struct nv_pmu_clk_load clk_load; | ||
347 | } params; | ||
348 | }; | ||
349 | |||
350 | /* CLK MSG ID definitions */ | ||
351 | #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
352 | #define NV_PMU_CLK_MSG_ID_RPC (0x00000001) | ||
353 | #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
354 | |||
355 | struct nv_pmu_clk_msg_rpc { | ||
356 | u8 msg_type; | ||
357 | u8 rsvd[3]; | ||
358 | struct nv_pmu_allocation response; | ||
359 | }; | ||
360 | |||
361 | #define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \ | ||
362 | offsetof(struct nv_pmu_clk_msg_rpc, response) | ||
363 | |||
364 | struct nv_pmu_clk_msg { | ||
365 | union { | ||
366 | u8 msg_type; | ||
367 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
368 | struct nv_pmu_clk_msg_rpc rpc; | ||
369 | struct nv_pmu_boardobj_msg_grp grp_get_status; | ||
370 | }; | ||
371 | }; | ||
372 | |||
373 | struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header { | ||
374 | struct nv_pmu_boardobjgrp_e32 super; | ||
375 | }; | ||
376 | |||
377 | struct nv_pmu_clk_clk_vin_device_boardobj_get_status { | ||
378 | struct nv_pmu_boardobj_query super; | ||
379 | u32 actual_voltage_uv; | ||
380 | u32 corrected_voltage_uv; | ||
381 | u8 sampled_code; | ||
382 | u8 override_code; | ||
383 | }; | ||
384 | |||
385 | union nv_pmu_clk_clk_vin_device_boardobj_get_status_union { | ||
386 | struct nv_pmu_boardobj_query board_obj; | ||
387 | struct nv_pmu_clk_clk_vin_device_boardobj_get_status super; | ||
388 | }; | ||
389 | |||
390 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device); | ||
391 | |||
392 | struct nv_pmu_clk_lut_vf_entry { | ||
393 | u32 entry; | ||
394 | }; | ||
395 | |||
396 | struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header { | ||
397 | struct nv_pmu_boardobjgrp_e32 super; | ||
398 | }; | ||
399 | |||
400 | struct nv_pmu_clk_clk_fll_device_boardobj_get_status { | ||
401 | struct nv_pmu_boardobj_query super; | ||
402 | u8 current_regime_id; | ||
403 | u16 min_freq_mhz; | ||
404 | struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)]; | ||
405 | }; | ||
406 | |||
407 | union nv_pmu_clk_clk_fll_device_boardobj_get_status_union { | ||
408 | struct nv_pmu_boardobj_query board_obj; | ||
409 | struct nv_pmu_clk_clk_fll_device_boardobj_get_status super; | ||
410 | }; | ||
411 | |||
412 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device); | ||
413 | |||
414 | #endif /*_GPMUIFCLK_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/pmuif/gpmuifperf.h new file mode 100644 index 00000000..b1d2f3fd --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifperf.h | |||
@@ -0,0 +1,116 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPERF_H_ | ||
14 | #define _GPMUIFPERF_H_ | ||
15 | |||
16 | #include "gpmuifvolt.h" | ||
17 | #include "gpmuifperfvfe.h" | ||
18 | |||
19 | /* | ||
20 | * Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId" | ||
21 | * argument for communications between Kernel and PMU via the various generic | ||
22 | * BOARDOBJGRP interfaces. | ||
23 | */ | ||
24 | #define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00 | ||
25 | #define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01 | ||
26 | |||
27 | #define NV_PMU_PERF_CMD_ID_RPC (0x00000002) | ||
28 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) | ||
29 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) | ||
30 | |||
31 | struct nv_pmu_perf_cmd_set_object { | ||
32 | u8 cmd_type; | ||
33 | u8 pad[2]; | ||
34 | u8 object_type; | ||
35 | struct nv_pmu_allocation object; | ||
36 | }; | ||
37 | |||
38 | #define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \ | ||
39 | (offsetof(struct nv_pmu_perf_cmd_set_object, object)) | ||
40 | |||
41 | /* RPC IDs */ | ||
42 | #define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001) | ||
43 | |||
44 | /*! | ||
45 | * Command requesting execution of the perf RPC. | ||
46 | */ | ||
47 | struct nv_pmu_perf_cmd_rpc { | ||
48 | u8 cmd_type; | ||
49 | u8 pad[3]; | ||
50 | struct nv_pmu_allocation request; | ||
51 | }; | ||
52 | |||
53 | #define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \ | ||
54 | offsetof(struct nv_pmu_perf_cmd_rpc, request) | ||
55 | |||
56 | /*! | ||
57 | * Simply a union of all specific PERF commands. Forms the general packet | ||
58 | * exchanged between the Kernel and PMU when sending and receiving PERF commands | ||
59 | * (respectively). | ||
60 | */ | ||
61 | struct nv_pmu_perf_cmd { | ||
62 | union { | ||
63 | u8 cmd_type; | ||
64 | struct nv_pmu_perf_cmd_set_object set_object; | ||
65 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
66 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
67 | }; | ||
68 | }; | ||
69 | |||
70 | /*! | ||
71 | * Defines the data structure used to invoke PMU perf RPCs. Same structure is | ||
72 | * used to return the result of the RPC execution. | ||
73 | */ | ||
74 | struct nv_pmu_perf_rpc { | ||
75 | u8 function; | ||
76 | bool b_supported; | ||
77 | bool b_success; | ||
78 | flcn_status flcn_status; | ||
79 | union { | ||
80 | struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval; | ||
81 | struct nv_pmu_perf_rpc_vfe_load vfe_load; | ||
82 | } params; | ||
83 | }; | ||
84 | |||
85 | |||
86 | /* PERF Message-type Definitions */ | ||
87 | #define NV_PMU_PERF_MSG_ID_RPC (0x00000003) | ||
88 | #define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004) | ||
89 | #define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006) | ||
90 | |||
91 | /*! | ||
92 | * Message carrying the result of the perf RPC execution. | ||
93 | */ | ||
94 | struct nv_pmu_perf_msg_rpc { | ||
95 | u8 msg_type; | ||
96 | u8 rsvd[3]; | ||
97 | struct nv_pmu_allocation response; | ||
98 | }; | ||
99 | |||
100 | #define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \ | ||
101 | (offsetof(struct nv_pmu_perf_msg_rpc, response)) | ||
102 | |||
103 | /*! | ||
104 | * Simply a union of all specific PERF messages. Forms the general packet | ||
105 | * exchanged between the Kernel and PMU when sending and receiving PERF messages | ||
106 | * (respectively). | ||
107 | */ | ||
108 | struct nv_pmu_perf_msg { | ||
109 | union { | ||
110 | u8 msg_type; | ||
111 | struct nv_pmu_perf_msg_rpc rpc; | ||
112 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
113 | }; | ||
114 | }; | ||
115 | |||
116 | #endif /* _GPMUIFPERF_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h new file mode 100644 index 00000000..6bad6445 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h | |||
@@ -0,0 +1,220 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPERFVFE_H_ | ||
14 | #define _GPMUIFPERFVFE_H_ | ||
15 | |||
16 | #include "gpmuifbios.h" | ||
17 | #include "gpmuifboardobj.h" | ||
18 | |||
19 | #define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 | ||
20 | #define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 | ||
21 | #define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 | ||
22 | #define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 | ||
23 | |||
24 | struct nv_pmu_perf_vfe_var_value { | ||
25 | u8 var_type; | ||
26 | u8 reserved[3]; | ||
27 | u32 var_value; | ||
28 | }; | ||
29 | |||
30 | union nv_pmu_perf_vfe_equ_result { | ||
31 | u32 freq_m_hz; | ||
32 | u32 voltu_v; | ||
33 | u32 vf_gain; | ||
34 | int volt_deltau_v; | ||
35 | }; | ||
36 | |||
37 | struct nv_pmu_perf_rpc_vfe_equ_eval { | ||
38 | u8 equ_idx; | ||
39 | u8 var_count; | ||
40 | u8 output_type; | ||
41 | struct nv_pmu_perf_vfe_var_value var_values[ | ||
42 | NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX]; | ||
43 | union nv_pmu_perf_vfe_equ_result result; | ||
44 | }; | ||
45 | |||
46 | struct nv_pmu_perf_rpc_vfe_load { | ||
47 | bool b_load; | ||
48 | }; | ||
49 | |||
50 | struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header { | ||
51 | struct nv_pmu_boardobjgrp_e32 super; | ||
52 | }; | ||
53 | |||
54 | struct nv_pmu_perf_vfe_var_get_status_super { | ||
55 | struct nv_pmu_boardobj_query board_obj; | ||
56 | }; | ||
57 | |||
58 | struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { | ||
59 | struct nv_pmu_perf_vfe_var_get_status_super super; | ||
60 | u32 fuse_value_integer; | ||
61 | u32 fuse_value_hw_integer; | ||
62 | u8 fuse_version; | ||
63 | bool b_version_check_failed; | ||
64 | }; | ||
65 | |||
66 | union nv_pmu_perf_vfe_var_boardobj_get_status_union { | ||
67 | struct nv_pmu_boardobj_query board_obj; | ||
68 | struct nv_pmu_perf_vfe_var_get_status_super super; | ||
69 | struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status; | ||
70 | }; | ||
71 | |||
72 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var); | ||
73 | |||
74 | struct nv_pmu_vfe_var { | ||
75 | struct nv_pmu_boardobj super; | ||
76 | u32 out_range_min; | ||
77 | u32 out_range_max; | ||
78 | }; | ||
79 | |||
80 | struct nv_pmu_vfe_var_derived { | ||
81 | struct nv_pmu_vfe_var super; | ||
82 | }; | ||
83 | |||
84 | struct nv_pmu_vfe_var_derived_product { | ||
85 | struct nv_pmu_vfe_var_derived super; | ||
86 | u8 var_idx0; | ||
87 | u8 var_idx1; | ||
88 | }; | ||
89 | |||
90 | struct nv_pmu_vfe_var_derived_sum { | ||
91 | struct nv_pmu_vfe_var_derived super; | ||
92 | u8 var_idx0; | ||
93 | u8 var_idx1; | ||
94 | }; | ||
95 | |||
96 | struct nv_pmu_vfe_var_single { | ||
97 | struct nv_pmu_vfe_var super; | ||
98 | u8 override_type; | ||
99 | u32 override_value; | ||
100 | }; | ||
101 | |||
102 | struct nv_pmu_vfe_var_single_frequency { | ||
103 | struct nv_pmu_vfe_var_single super; | ||
104 | }; | ||
105 | |||
106 | struct nv_pmu_vfe_var_single_sensed { | ||
107 | struct nv_pmu_vfe_var_single super; | ||
108 | }; | ||
109 | |||
110 | struct nv_pmu_vfe_var_single_sensed_fuse_info { | ||
111 | u8 segment_count; | ||
112 | union nv_pmu_bios_vfield_register_segment segments[ | ||
113 | NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; | ||
114 | }; | ||
115 | |||
116 | struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info { | ||
117 | struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; | ||
118 | u32 fuse_val_default; | ||
119 | int hw_correction_scale; | ||
120 | int hw_correction_offset; | ||
121 | u8 v_field_id; | ||
122 | }; | ||
123 | |||
124 | struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info { | ||
125 | struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; | ||
126 | u8 ver_expected; | ||
127 | bool b_ver_check; | ||
128 | bool b_use_default_on_ver_check_fail; | ||
129 | u8 v_field_id_ver; | ||
130 | }; | ||
131 | |||
132 | struct nv_pmu_vfe_var_single_sensed_fuse_override_info { | ||
133 | u32 fuse_val_override; | ||
134 | bool b_fuse_regkey_override; | ||
135 | }; | ||
136 | |||
137 | struct nv_pmu_vfe_var_single_sensed_fuse { | ||
138 | struct nv_pmu_vfe_var_single_sensed super; | ||
139 | struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; | ||
140 | struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; | ||
141 | struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; | ||
142 | }; | ||
143 | |||
144 | struct nv_pmu_vfe_var_single_sensed_temp { | ||
145 | struct nv_pmu_vfe_var_single_sensed super; | ||
146 | u8 therm_channel_index; | ||
147 | int temp_hysteresis_positive; | ||
148 | int temp_hysteresis_negative; | ||
149 | int temp_default; | ||
150 | }; | ||
151 | |||
152 | struct nv_pmu_vfe_var_single_voltage { | ||
153 | struct nv_pmu_vfe_var_single super; | ||
154 | }; | ||
155 | |||
156 | struct nv_pmu_perf_vfe_var_boardobjgrp_set_header { | ||
157 | struct nv_pmu_boardobjgrp_e32 super; | ||
158 | u8 polling_periodms; | ||
159 | }; | ||
160 | |||
161 | union nv_pmu_perf_vfe_var_boardobj_set_union { | ||
162 | struct nv_pmu_boardobj board_obj; | ||
163 | struct nv_pmu_vfe_var var; | ||
164 | struct nv_pmu_vfe_var_derived var_derived; | ||
165 | struct nv_pmu_vfe_var_derived_product var_derived_product; | ||
166 | struct nv_pmu_vfe_var_derived_sum var_derived_sum; | ||
167 | struct nv_pmu_vfe_var_single var_single; | ||
168 | struct nv_pmu_vfe_var_single_frequency var_single_frequiency; | ||
169 | struct nv_pmu_vfe_var_single_sensed var_single_sensed; | ||
170 | struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse; | ||
171 | struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp; | ||
172 | struct nv_pmu_vfe_var_single_voltage var_single_voltage; | ||
173 | }; | ||
174 | |||
175 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var); | ||
176 | |||
177 | struct nv_pmu_vfe_equ { | ||
178 | struct nv_pmu_boardobj super; | ||
179 | u8 var_idx; | ||
180 | u8 equ_idx_next; | ||
181 | u8 output_type; | ||
182 | u32 out_range_min; | ||
183 | u32 out_range_max; | ||
184 | }; | ||
185 | |||
186 | struct nv_pmu_vfe_equ_compare { | ||
187 | struct nv_pmu_vfe_equ super; | ||
188 | u8 func_id; | ||
189 | u8 equ_idx_true; | ||
190 | u8 equ_idx_false; | ||
191 | u32 criteria; | ||
192 | }; | ||
193 | |||
194 | struct nv_pmu_vfe_equ_minmax { | ||
195 | struct nv_pmu_vfe_equ super; | ||
196 | bool b_max; | ||
197 | u8 equ_idx0; | ||
198 | u8 equ_idx1; | ||
199 | }; | ||
200 | |||
201 | struct nv_pmu_vfe_equ_quadratic { | ||
202 | struct nv_pmu_vfe_equ super; | ||
203 | u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT]; | ||
204 | }; | ||
205 | |||
206 | struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header { | ||
207 | struct nv_pmu_boardobjgrp_e255 super; | ||
208 | }; | ||
209 | |||
210 | union nv_pmu_perf_vfe_equ_boardobj_set_union { | ||
211 | struct nv_pmu_boardobj board_obj; | ||
212 | struct nv_pmu_vfe_equ equ; | ||
213 | struct nv_pmu_vfe_equ_compare equ_comapre; | ||
214 | struct nv_pmu_vfe_equ_minmax equ_minmax; | ||
215 | struct nv_pmu_vfe_equ_quadratic equ_quadratic; | ||
216 | }; | ||
217 | |||
218 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ); | ||
219 | |||
220 | #endif /* _GPMUIFPERFVFE_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h new file mode 100644 index 00000000..c480b1cf --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFVOLT_H_ | ||
14 | #define _GPMUIFVOLT_H_ | ||
15 | |||
16 | #include "ctrl/ctrlvolt.h" | ||
17 | |||
18 | /*! | ||
19 | * Structure containing the number of voltage rails and the list of rail items | ||
20 | * @ref CTRL_PERF_VOLT_RAIL_LIST_ITEM. | ||
21 | */ | ||
22 | struct nv_pmu_volt_volt_rail_list { | ||
23 | /*! | ||
24 | * Number of VOLT_RAILs that require the voltage change. | ||
25 | */ | ||
26 | u8 num_rails; | ||
27 | /*! | ||
28 | * List of @ref CTRL_PERF_VOLT_RAIL_LIST_ITEM entries. | ||
29 | */ | ||
30 | struct ctrl_perf_volt_rail_list_item rails[2]; | ||
31 | }; | ||
32 | |||
33 | #endif /* _GPMUIFVOLT_H_*/ | ||