diff options
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif')
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h new file mode 100644 index 00000000..7d5c8d41 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h | |||
@@ -0,0 +1,101 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFRPPG_H_ | ||
14 | #define _GPMUIFRPPG_H_ | ||
15 | |||
16 | #define NV_PMU_RPPG_CTRL_ID_GR (0x0000) | ||
17 | #define NV_PMU_RPPG_CTRL_ID_MS (0x0001) | ||
18 | #define NV_PMU_RPPG_CTRL_ID_DI (0x0002) | ||
19 | #define NV_PMU_RPPG_CTRL_ID_MAX (0x0003) | ||
20 | |||
21 | #define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\ | ||
22 | BIT(NV_PMU_RPPG_CTRL_ID_MS) |\ | ||
23 | BIT(NV_PMU_RPPG_CTRL_ID_DI)) | ||
24 | |||
25 | #define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0 | ||
26 | |||
27 | enum { | ||
28 | NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0, | ||
29 | NV_PMU_RPPG_DOMAIN_ID_NON_GFX, | ||
30 | }; | ||
31 | |||
32 | struct nv_pmu_rppg_ctrl_stats { | ||
33 | u32 entry_count; | ||
34 | u32 exit_count; | ||
35 | }; | ||
36 | |||
37 | struct nv_pmu_rppg_cmd_common { | ||
38 | u8 cmd_type; | ||
39 | u8 cmd_id; | ||
40 | }; | ||
41 | |||
42 | struct nv_pmu_rppg_cmd_init { | ||
43 | u8 cmd_type; | ||
44 | u8 cmd_id; | ||
45 | }; | ||
46 | |||
47 | struct nv_pmu_rppg_cmd_init_ctrl { | ||
48 | u8 cmd_type; | ||
49 | u8 cmd_id; | ||
50 | u8 ctrl_id; | ||
51 | u8 domain_id; | ||
52 | }; | ||
53 | |||
54 | struct nv_pmu_rppg_cmd_stats_reset { | ||
55 | u8 cmd_type; | ||
56 | u8 cmd_id; | ||
57 | u8 ctrl_id; | ||
58 | }; | ||
59 | |||
60 | struct nv_pmu_rppg_cmd { | ||
61 | union { | ||
62 | u8 cmd_type; | ||
63 | struct nv_pmu_rppg_cmd_common cmn; | ||
64 | struct nv_pmu_rppg_cmd_init init; | ||
65 | struct nv_pmu_rppg_cmd_init_ctrl init_ctrl; | ||
66 | struct nv_pmu_rppg_cmd_stats_reset stats_reset; | ||
67 | }; | ||
68 | }; | ||
69 | |||
70 | enum { | ||
71 | NV_PMU_RPPG_CMD_ID_INIT = 0x0, | ||
72 | NV_PMU_RPPG_CMD_ID_INIT_CTRL, | ||
73 | NV_PMU_RPPG_CMD_ID_STATS_RESET, | ||
74 | }; | ||
75 | |||
76 | |||
77 | struct nv_pmu_rppg_msg_common { | ||
78 | u8 msg_type; | ||
79 | u8 msg_id; | ||
80 | }; | ||
81 | |||
82 | struct nv_pmu_rppg_msg_init_ctrl_ack { | ||
83 | u8 msg_type; | ||
84 | u8 msg_id; | ||
85 | u8 ctrl_id; | ||
86 | u32 stats_dmem_offset; | ||
87 | }; | ||
88 | |||
89 | struct nv_pmu_rppg_msg { | ||
90 | union { | ||
91 | u8 msg_type; | ||
92 | struct nv_pmu_rppg_msg_common cmn; | ||
93 | struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack; | ||
94 | }; | ||
95 | }; | ||
96 | |||
97 | enum { | ||
98 | NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0, | ||
99 | }; | ||
100 | |||
101 | #endif | ||