diff options
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h')
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h | 426 |
1 files changed, 426 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h new file mode 100644 index 00000000..613dcea6 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h | |||
@@ -0,0 +1,426 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _GPMUIFPMGR_H_ | ||
15 | #define _GPMUIFPMGR_H_ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | #include "gk20a/pmu_gk20a.h" | ||
19 | #include "ctrl/ctrlpmgr.h" | ||
20 | #include "pmuif/gpmuifboardobj.h" | ||
21 | #include "gk20a/pmu_common.h" | ||
22 | |||
23 | struct nv_pmu_pmgr_i2c_device_desc { | ||
24 | struct nv_pmu_boardobj super; | ||
25 | u8 dcb_index; | ||
26 | u16 i2c_address; | ||
27 | u32 i2c_flags; | ||
28 | u8 i2c_port; | ||
29 | }; | ||
30 | |||
31 | #define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32) | ||
32 | |||
33 | struct nv_pmu_pmgr_i2c_device_desc_table { | ||
34 | u32 dev_mask; | ||
35 | struct nv_pmu_pmgr_i2c_device_desc | ||
36 | devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES]; | ||
37 | }; | ||
38 | |||
39 | struct nv_pmu_pmgr_pwr_device_desc { | ||
40 | struct nv_pmu_boardobj super; | ||
41 | u32 power_corr_factor; | ||
42 | }; | ||
43 | |||
44 | #define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03 | ||
45 | |||
46 | struct nv_pmu_pmgr_pwr_device_desc_ina3221 { | ||
47 | struct nv_pmu_pmgr_pwr_device_desc super; | ||
48 | u8 i2c_dev_idx; | ||
49 | struct ctrl_pmgr_pwr_device_info_rshunt | ||
50 | r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM]; | ||
51 | u16 configuration; | ||
52 | u16 mask_enable; | ||
53 | u32 event_mask; | ||
54 | u16 curr_correct_m; | ||
55 | s16 curr_correct_b; | ||
56 | }; | ||
57 | |||
58 | union nv_pmu_pmgr_pwr_device_desc_union { | ||
59 | struct nv_pmu_boardobj board_obj; | ||
60 | struct nv_pmu_pmgr_pwr_device_desc pwr_dev; | ||
61 | struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221; | ||
62 | }; | ||
63 | |||
64 | struct nv_pmu_pmgr_pwr_device_ba_info { | ||
65 | bool b_initialized_and_used; | ||
66 | }; | ||
67 | |||
68 | struct nv_pmu_pmgr_pwr_device_desc_table_header { | ||
69 | struct nv_pmu_boardobjgrp_e32 super; | ||
70 | struct nv_pmu_pmgr_pwr_device_ba_info ba_info; | ||
71 | }; | ||
72 | |||
73 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header, | ||
74 | sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header)); | ||
75 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union, | ||
76 | sizeof(union nv_pmu_pmgr_pwr_device_desc_union)); | ||
77 | |||
78 | struct nv_pmu_pmgr_pwr_device_desc_table { | ||
79 | union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr; | ||
80 | union nv_pmu_pmgr_pwr_device_desc_union_aligned | ||
81 | devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; | ||
82 | }; | ||
83 | |||
84 | union nv_pmu_pmgr_pwr_device_dmem_size { | ||
85 | union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr; | ||
86 | union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device; | ||
87 | }; | ||
88 | |||
89 | struct nv_pmu_pmgr_pwr_channel { | ||
90 | struct nv_pmu_boardobj super; | ||
91 | u8 pwr_rail; | ||
92 | u8 ch_idx; | ||
93 | u32 volt_fixedu_v; | ||
94 | u32 pwr_corr_slope; | ||
95 | s32 pwr_corr_offsetm_w; | ||
96 | u32 curr_corr_slope; | ||
97 | s32 curr_corr_offsetm_a; | ||
98 | u32 dependent_ch_mask; | ||
99 | }; | ||
100 | |||
101 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16 | ||
102 | |||
103 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16 | ||
104 | |||
105 | struct nv_pmu_pmgr_pwr_channel_sensor { | ||
106 | struct nv_pmu_pmgr_pwr_channel super; | ||
107 | u8 pwr_dev_idx; | ||
108 | u8 pwr_dev_prov_idx; | ||
109 | }; | ||
110 | |||
111 | struct nv_pmu_pmgr_pwr_channel_pmu_compactible { | ||
112 | u8 pmu_compactible_data[56]; | ||
113 | }; | ||
114 | |||
115 | union nv_pmu_pmgr_pwr_channel_union { | ||
116 | struct nv_pmu_boardobj board_obj; | ||
117 | struct nv_pmu_pmgr_pwr_channel pwr_channel; | ||
118 | struct nv_pmu_pmgr_pwr_channel_sensor sensor; | ||
119 | struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; | ||
120 | }; | ||
121 | |||
122 | #define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02 | ||
123 | |||
124 | struct nv_pmu_pmgr_pwr_monitor_pstate { | ||
125 | u32 hw_channel_mask; | ||
126 | }; | ||
127 | |||
128 | union nv_pmu_pmgr_pwr_monitor_type_specific { | ||
129 | struct nv_pmu_pmgr_pwr_monitor_pstate pstate; | ||
130 | }; | ||
131 | |||
132 | struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible { | ||
133 | u8 pmu_compactible_data[28]; | ||
134 | }; | ||
135 | |||
136 | union nv_pmu_pmgr_pwr_chrelationship_union { | ||
137 | struct nv_pmu_boardobj board_obj; | ||
138 | struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship; | ||
139 | }; | ||
140 | |||
141 | struct nv_pmu_pmgr_pwr_channel_header { | ||
142 | struct nv_pmu_boardobjgrp_e32 super; | ||
143 | u8 type; | ||
144 | union nv_pmu_pmgr_pwr_monitor_type_specific type_specific; | ||
145 | u8 sample_count; | ||
146 | u16 sampling_periodms; | ||
147 | u16 sampling_period_low_powerms; | ||
148 | u32 total_gpu_power_channel_mask; | ||
149 | u32 physical_channel_mask; | ||
150 | }; | ||
151 | |||
152 | struct nv_pmu_pmgr_pwr_chrelationship_header { | ||
153 | struct nv_pmu_boardobjgrp_e32 super; | ||
154 | }; | ||
155 | |||
156 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header, | ||
157 | sizeof(struct nv_pmu_pmgr_pwr_channel_header)); | ||
158 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header, | ||
159 | sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header)); | ||
160 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union, | ||
161 | sizeof(union nv_pmu_pmgr_pwr_chrelationship_union)); | ||
162 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union, | ||
163 | sizeof(union nv_pmu_pmgr_pwr_channel_union)); | ||
164 | |||
165 | struct nv_pmu_pmgr_pwr_channel_desc { | ||
166 | union nv_pmu_pmgr_pwr_channel_header_aligned hdr; | ||
167 | union nv_pmu_pmgr_pwr_channel_union_aligned | ||
168 | channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS]; | ||
169 | }; | ||
170 | |||
171 | struct nv_pmu_pmgr_pwr_chrelationship_desc { | ||
172 | union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr; | ||
173 | union nv_pmu_pmgr_pwr_chrelationship_union_aligned | ||
174 | ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS]; | ||
175 | }; | ||
176 | |||
177 | union nv_pmu_pmgr_pwr_monitor_dmem_size { | ||
178 | union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr; | ||
179 | union nv_pmu_pmgr_pwr_channel_union_aligned channel; | ||
180 | union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr; | ||
181 | union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels; | ||
182 | }; | ||
183 | |||
184 | struct nv_pmu_pmgr_pwr_monitor_pack { | ||
185 | struct nv_pmu_pmgr_pwr_channel_desc channels; | ||
186 | struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; | ||
187 | }; | ||
188 | |||
189 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32 | ||
190 | |||
191 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32 | ||
192 | |||
193 | struct nv_pmu_pmgr_pwr_policy { | ||
194 | struct nv_pmu_boardobj super; | ||
195 | u8 ch_idx; | ||
196 | u8 num_limit_inputs; | ||
197 | u8 limit_unit; | ||
198 | u8 sample_mult; | ||
199 | u32 limit_curr; | ||
200 | u32 limit_min; | ||
201 | u32 limit_max; | ||
202 | struct ctrl_pmgr_pwr_policy_info_integral integral; | ||
203 | enum ctrl_pmgr_pwr_policy_filter_type filter_type; | ||
204 | union ctrl_pmgr_pwr_policy_filter_param filter_param; | ||
205 | }; | ||
206 | |||
207 | struct nv_pmu_pmgr_pwr_policy_hw_threshold { | ||
208 | struct nv_pmu_pmgr_pwr_policy super; | ||
209 | u8 threshold_idx; | ||
210 | u8 low_threshold_idx; | ||
211 | bool b_use_low_threshold; | ||
212 | u16 low_threshold_value; | ||
213 | }; | ||
214 | |||
215 | struct nv_pmu_pmgr_pwr_policy_pmu_compactible { | ||
216 | u8 pmu_compactible_data[68]; | ||
217 | }; | ||
218 | |||
219 | union nv_pmu_pmgr_pwr_policy_union { | ||
220 | struct nv_pmu_boardobj board_obj; | ||
221 | struct nv_pmu_pmgr_pwr_policy pwr_policy; | ||
222 | struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold; | ||
223 | struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy; | ||
224 | }; | ||
225 | |||
226 | struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible { | ||
227 | u8 pmu_compactible_data[24]; | ||
228 | }; | ||
229 | |||
230 | union nv_pmu_pmgr_pwr_policy_relationship_union { | ||
231 | struct nv_pmu_boardobj board_obj; | ||
232 | struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship; | ||
233 | }; | ||
234 | |||
235 | struct nv_pmu_pmgr_pwr_violation_pmu_compactible { | ||
236 | u8 pmu_compactible_data[16]; | ||
237 | }; | ||
238 | |||
239 | union nv_pmu_pmgr_pwr_violation_union { | ||
240 | struct nv_pmu_boardobj board_obj; | ||
241 | struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; | ||
242 | }; | ||
243 | |||
244 | #define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30 | ||
245 | |||
246 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, | ||
247 | sizeof(union nv_pmu_pmgr_pwr_policy_union)); | ||
248 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, | ||
249 | sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); | ||
250 | |||
251 | #define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2 | ||
252 | |||
253 | struct nv_pmu_perf_domain_group_limits | ||
254 | { | ||
255 | u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; | ||
256 | } ; | ||
257 | |||
258 | #define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6 | ||
259 | |||
260 | struct nv_pmu_pmgr_pwr_policy_desc_header { | ||
261 | struct nv_pmu_boardobjgrp_e32 super; | ||
262 | u8 version; | ||
263 | bool b_enabled; | ||
264 | u8 low_sampling_mult; | ||
265 | u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES]; | ||
266 | u16 base_sample_period; | ||
267 | u16 min_client_sample_period; | ||
268 | u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT]; | ||
269 | struct nv_pmu_perf_domain_group_limits global_ceiling; | ||
270 | }; | ||
271 | |||
272 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header , | ||
273 | sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header )); | ||
274 | |||
275 | struct nv_pmu_pmgr_pwr_policyrel_desc_header { | ||
276 | struct nv_pmu_boardobjgrp_e32 super; | ||
277 | }; | ||
278 | |||
279 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header, | ||
280 | sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header)); | ||
281 | |||
282 | struct nv_pmu_pmgr_pwr_violation_desc_header { | ||
283 | struct nv_pmu_boardobjgrp_e32 super; | ||
284 | }; | ||
285 | |||
286 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header, | ||
287 | sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header)); | ||
288 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union, | ||
289 | sizeof(union nv_pmu_pmgr_pwr_violation_union)); | ||
290 | |||
291 | struct nv_pmu_pmgr_pwr_policy_desc { | ||
292 | union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr; | ||
293 | union nv_pmu_pmgr_pwr_policy_union_aligned | ||
294 | policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES]; | ||
295 | }; | ||
296 | |||
297 | struct nv_pmu_pmgr_pwr_policyrel_desc { | ||
298 | union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr; | ||
299 | union nv_pmu_pmgr_pwr_policy_relationship_union_aligned | ||
300 | policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS]; | ||
301 | }; | ||
302 | |||
303 | struct nv_pmu_pmgr_pwr_violation_desc { | ||
304 | union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr; | ||
305 | union nv_pmu_pmgr_pwr_violation_union_aligned | ||
306 | violations[CTRL_PMGR_PWR_VIOLATION_MAX]; | ||
307 | }; | ||
308 | |||
309 | union nv_pmu_pmgr_pwr_policy_dmem_size { | ||
310 | union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr; | ||
311 | union nv_pmu_pmgr_pwr_policy_union_aligned policy; | ||
312 | union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr; | ||
313 | union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels; | ||
314 | union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr; | ||
315 | union nv_pmu_pmgr_pwr_violation_union_aligned violation; | ||
316 | }; | ||
317 | |||
318 | struct nv_pmu_pmgr_pwr_policy_pack { | ||
319 | struct nv_pmu_pmgr_pwr_policy_desc policies; | ||
320 | struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels; | ||
321 | struct nv_pmu_pmgr_pwr_violation_desc violations; | ||
322 | }; | ||
323 | |||
324 | #define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000) | ||
325 | |||
326 | #define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002) | ||
327 | |||
328 | #define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001) | ||
329 | |||
330 | #define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006) | ||
331 | |||
332 | #define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007) | ||
333 | |||
334 | struct nv_pmu_pmgr_cmd_set_object { | ||
335 | u8 cmd_type; | ||
336 | u8 pad[2]; | ||
337 | u8 object_type; | ||
338 | struct nv_pmu_allocation object; | ||
339 | }; | ||
340 | |||
341 | #define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04) | ||
342 | |||
343 | #define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000) | ||
344 | |||
345 | #define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001) | ||
346 | |||
347 | #define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002) | ||
348 | |||
349 | #define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005) | ||
350 | |||
351 | struct nv_pmu_pmgr_pwr_devices_query_payload { | ||
352 | struct { | ||
353 | u32 powerm_w; | ||
354 | u32 voltageu_v; | ||
355 | u32 currentm_a; | ||
356 | } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; | ||
357 | }; | ||
358 | |||
359 | struct nv_pmu_pmgr_cmd_pwr_devices_query { | ||
360 | u8 cmd_type; | ||
361 | u8 pad[3]; | ||
362 | u32 dev_mask; | ||
363 | struct nv_pmu_allocation payload; | ||
364 | }; | ||
365 | |||
366 | #define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08) | ||
367 | |||
368 | struct nv_pmu_pmgr_cmd_load { | ||
369 | u8 cmd_type; | ||
370 | }; | ||
371 | |||
372 | struct nv_pmu_pmgr_cmd_unload { | ||
373 | u8 cmd_type; | ||
374 | }; | ||
375 | |||
376 | struct nv_pmu_pmgr_cmd { | ||
377 | union { | ||
378 | u8 cmd_type; | ||
379 | struct nv_pmu_pmgr_cmd_set_object set_object; | ||
380 | struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query; | ||
381 | struct nv_pmu_pmgr_cmd_load load; | ||
382 | struct nv_pmu_pmgr_cmd_unload unload; | ||
383 | }; | ||
384 | }; | ||
385 | |||
386 | #define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000) | ||
387 | |||
388 | #define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004) | ||
389 | |||
390 | #define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005) | ||
391 | |||
392 | struct nv_pmu_pmgr_msg_set_object { | ||
393 | u8 msg_type; | ||
394 | bool b_success; | ||
395 | flcn_status flcnstatus; | ||
396 | u8 object_type; | ||
397 | }; | ||
398 | |||
399 | struct nv_pmu_pmgr_msg_query { | ||
400 | u8 msg_type; | ||
401 | bool b_success; | ||
402 | flcn_status flcnstatus; | ||
403 | u8 cmd_type; | ||
404 | }; | ||
405 | |||
406 | struct nv_pmu_pmgr_msg_load { | ||
407 | u8 msg_type; | ||
408 | bool b_success; | ||
409 | flcn_status flcnstatus; | ||
410 | }; | ||
411 | |||
412 | struct nv_pmu_pmgr_msg_unload { | ||
413 | u8 msg_type; | ||
414 | }; | ||
415 | |||
416 | struct nv_pmu_pmgr_msg { | ||
417 | union { | ||
418 | u8 msg_type; | ||
419 | struct nv_pmu_pmgr_msg_set_object set_object; | ||
420 | struct nv_pmu_pmgr_msg_query query; | ||
421 | struct nv_pmu_pmgr_msg_load load; | ||
422 | struct nv_pmu_pmgr_msg_unload unload; | ||
423 | }; | ||
424 | }; | ||
425 | |||
426 | #endif | ||