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path: root/drivers/gpu/nvgpu/pmuif/gpmuifclk.h
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-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuifclk.h414
1 files changed, 414 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h
new file mode 100644
index 00000000..36b9aace
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h
@@ -0,0 +1,414 @@
1/*
2* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify it
5* under the terms and conditions of the GNU General Public License,
6* version 2, as published by the Free Software Foundation.
7*
8* This program is distributed in the hope it will be useful, but WITHOUT
9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11* more details.
12*/
13
14#ifndef _GPMUIFCLK_H_
15#define _GPMUIFCLK_H_
16
17#include "gk20a/gk20a.h"
18#include "gk20a/pmu_gk20a.h"
19#include "ctrl/ctrlboardobj.h"
20#include "ctrl/ctrlvolt.h"
21#include "ctrl/ctrlperf.h"
22#include "ctrl/ctrlclk.h"
23#include "pmuif/gpmuifboardobj.h"
24#include "pmuif/gpmuifvolt.h"
25#include "gk20a/pmu_common.h"
26
27enum nv_pmu_clk_clkwhich {
28 clkwhich_mclk = 5,
29 clkwhich_dispclk = 7,
30 clkwhich_gpc2clk = 17,
31 clkwhich_xbar2clk = 19,
32 clkwhich_sys2clk = 20,
33 clkwhich_hub2clk = 21,
34 clkwhich_pwrclk = 24,
35 clkwhich_nvdclk = 25,
36 clkwhich_pciegenclk = 31,
37};
38
39/*
40 * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId"
41 * argument for communications between Kernel and PMU via the various generic
42 * BOARDOBJGRP interfaces.
43 */
44#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00
45#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01
46#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02
47#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03
48#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04
49
50/*!
51* CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the
52* CLK_DOMAIN feature.
53*/
54struct nv_pmu_clk_clk_domain_boardobjgrp_set_header {
55 struct nv_pmu_boardobjgrp_e32 super;
56 u32 vbios_domains;
57 struct ctrl_boardobjgrp_mask_e32 master_domains_mask;
58 u16 cntr_sampling_periodms;
59 bool b_override_o_v_o_c;
60 bool b_debug_mode;
61 bool b_enforce_vf_monotonicity;
62 u8 volt_rails_max;
63 struct ctrl_clk_clk_delta deltas;
64};
65
66struct nv_pmu_clk_clk_domain_boardobj_set {
67 struct nv_pmu_boardobj super;
68 enum nv_pmu_clk_clkwhich domain;
69 u32 api_domain;
70 u8 perf_domain_grp_idx;
71};
72
73struct nv_pmu_clk_clk_domain_3x_boardobj_set {
74 struct nv_pmu_clk_clk_domain_boardobj_set super;
75 bool b_noise_aware_capable;
76};
77
78struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set {
79 struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
80 u16 freq_mhz;
81};
82
83struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set {
84 struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
85 u8 clk_prog_idx_first;
86 u8 clk_prog_idx_last;
87 u8 noise_unaware_ordering_index;
88 u8 noise_aware_ordering_index;
89 bool b_force_noise_unaware_ordering;
90 int factory_offset_khz;
91 short freq_delta_min_mhz;
92 short freq_delta_max_mhz;
93 struct ctrl_clk_clk_delta deltas;
94};
95
96struct nv_pmu_clk_clk_domain_3x_master_boardobj_set {
97 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
98 u32 slave_idxs_mask;
99};
100
101struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
102 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
103 u8 master_idx;
104};
105
106union nv_pmu_clk_clk_domain_boardobj_set_union {
107 struct nv_pmu_boardobj board_obj;
108 struct nv_pmu_clk_clk_domain_boardobj_set super;
109 struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x;
110 struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed;
111 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog;
112 struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master;
113 struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave;
114};
115
116NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain);
117
118struct nv_pmu_clk_clk_prog_boardobjgrp_set_header {
119 struct nv_pmu_boardobjgrp_e255 super;
120 u8 slave_entry_count;
121 u8 vf_entry_count;
122};
123
124struct nv_pmu_clk_clk_prog_boardobj_set {
125 struct nv_pmu_boardobj super;
126};
127
128struct nv_pmu_clk_clk_prog_1x_boardobj_set {
129 struct nv_pmu_clk_clk_prog_boardobj_set super;
130 u8 source;
131 u16 freq_max_mhz;
132 union ctrl_clk_clk_prog_1x_source_data source_data;
133};
134
135struct nv_pmu_clk_clk_prog_1x_master_boardobj_set {
136 struct nv_pmu_clk_clk_prog_1x_boardobj_set super;
137 bool b_o_c_o_v_enabled;
138 struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[
139 CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES];
140 struct ctrl_clk_clk_delta deltas;
141};
142
143struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set {
144 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super;
145 struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[
146 CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES];
147};
148
149struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set {
150 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super;
151 struct ctrl_clk_clk_prog_1x_master_table_slave_entry
152 slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES];
153};
154
155union nv_pmu_clk_clk_prog_boardobj_set_union {
156 struct nv_pmu_boardobj board_obj;
157 struct nv_pmu_clk_clk_prog_boardobj_set super;
158 struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x;
159 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master;
160 struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio;
161 struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table;
162};
163
164NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog);
165
166struct nv_pmu_clk_lut_device_desc {
167 u8 vselect_mode;
168 u16 hysteresis_threshold;
169};
170
171struct nv_pmu_clk_regime_desc {
172 u8 regime_id;
173 u16 fixed_freq_regime_limit_mhz;
174};
175
176struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header {
177 struct nv_pmu_boardobjgrp_e32 super;
178 struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask;
179 u32 lut_step_size_uv;
180 u32 lut_min_voltage_uv;
181 u8 lut_num_entries;
182 u16 max_min_freq_mhz;
183};
184
185struct nv_pmu_clk_clk_fll_device_boardobj_set {
186 struct nv_pmu_boardobj super;
187 u8 id;
188 u8 mdiv;
189 u8 vin_idx_logic;
190 u8 vin_idx_sram;
191 u8 rail_idx_for_lut;
192 u16 input_freq_mhz;
193 u32 clk_domain;
194 struct nv_pmu_clk_lut_device_desc lut_device;
195 struct nv_pmu_clk_regime_desc regime_desc;
196 u8 min_freq_vfe_idx;
197 u8 freq_ctrl_idx;
198 struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask;
199};
200
201union nv_pmu_clk_clk_fll_device_boardobj_set_union {
202 struct nv_pmu_boardobj board_obj;
203 struct nv_pmu_clk_clk_fll_device_boardobj_set super;
204};
205
206NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device);
207
208struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header {
209 struct nv_pmu_boardobjgrp_e32 super;
210 bool b_vin_is_disable_allowed;
211};
212
213struct nv_pmu_clk_clk_vin_device_boardobj_set {
214 struct nv_pmu_boardobj super;
215 u8 id;
216 u8 volt_domain;
217 u32 slope;
218 u32 intercept;
219 u32 flls_shared_mask;
220};
221
222union nv_pmu_clk_clk_vin_device_boardobj_set_union {
223 struct nv_pmu_boardobj board_obj;
224 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
225};
226
227NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device);
228
229struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header {
230 struct nv_pmu_boardobjgrp_e255 super;
231};
232
233struct nv_pmu_clk_clk_vf_point_boardobj_set {
234 struct nv_pmu_boardobj super;
235 u8 vfe_equ_idx;
236 u8 volt_rail_idx;
237};
238
239struct nv_pmu_clk_clk_vf_point_freq_boardobj_set {
240 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
241 u16 freq_mhz;
242 int volt_delta_uv;
243};
244
245struct nv_pmu_clk_clk_vf_point_volt_boardobj_set {
246 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
247 u32 source_voltage_uv;
248 u8 vf_gain_vfe_equ_idx;
249 u8 clk_domain_idx;
250 int freq_delta_khz;
251};
252
253union nv_pmu_clk_clk_vf_point_boardobj_set_union {
254 struct nv_pmu_boardobj board_obj;
255 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
256 struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq;
257 struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt;
258};
259
260NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point);
261
262struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header {
263 struct nv_pmu_boardobjgrp_e255 super;
264};
265
266struct nv_pmu_clk_clk_vf_point_boardobj_get_status {
267 struct nv_pmu_boardobj super;
268 struct ctrl_clk_vf_pair pair;
269};
270
271struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status {
272 struct nv_pmu_clk_clk_vf_point_boardobj_get_status super;
273 u16 vf_gain_value;
274};
275
276union nv_pmu_clk_clk_vf_point_boardobj_get_status_union {
277 struct nv_pmu_boardobj board_obj;
278 struct nv_pmu_clk_clk_vf_point_boardobj_get_status super;
279 struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt;
280};
281
282NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point);
283
284#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12)
285
286struct nv_pmu_clk_clk_domain_list {
287 u8 num_domains;
288 struct ctrl_clk_clk_domain_list_item clk_domains[
289 NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
290};
291
292struct nv_pmu_clk_vf_change_inject {
293 u8 flags;
294 struct nv_pmu_clk_clk_domain_list clk_list;
295 struct nv_pmu_volt_volt_rail_list volt_list;
296};
297
298#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002)
299#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001)
300
301struct nv_pmu_clk_load_payload_freq_controllers {
302 struct ctrl_boardobjgrp_mask_e32 load_mask;
303};
304
305struct nv_pmu_clk_load {
306 u8 feature;
307 u32 action_mask;
308 union {
309 struct nv_pmu_clk_load_payload_freq_controllers freq_controllers;
310 } payload;
311};
312
313/* CLK CMD ID definitions. */
314#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000)
315#define NV_PMU_CLK_CMD_ID_RPC (0x00000001)
316#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
317
318#define NV_PMU_CLK_RPC_ID_LOAD (0x00000002)
319#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001)
320
321struct nv_pmu_clk_cmd_rpc {
322 u8 cmd_type;
323 u8 pad[3];
324 struct nv_pmu_allocation request;
325};
326
327#define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \
328 (offsetof(struct nv_pmu_clk_cmd_rpc, request))
329
330struct nv_pmu_clk_cmd {
331 union {
332 u8 cmd_type;
333 struct nv_pmu_boardobj_cmd_grp grp_set;
334 struct nv_pmu_clk_cmd_rpc rpc;
335 struct nv_pmu_boardobj_cmd_grp grp_get_status;
336 };
337};
338
339struct nv_pmu_clk_rpc {
340 u8 function;
341 bool b_supported;
342 bool b_success;
343 flcn_status flcn_status;
344 union {
345 struct nv_pmu_clk_vf_change_inject clk_vf_change_inject;
346 struct nv_pmu_clk_load clk_load;
347 } params;
348};
349
350/* CLK MSG ID definitions */
351#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000)
352#define NV_PMU_CLK_MSG_ID_RPC (0x00000001)
353#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
354
355struct nv_pmu_clk_msg_rpc {
356 u8 msg_type;
357 u8 rsvd[3];
358 struct nv_pmu_allocation response;
359};
360
361#define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \
362 offsetof(struct nv_pmu_clk_msg_rpc, response)
363
364struct nv_pmu_clk_msg {
365 union {
366 u8 msg_type;
367 struct nv_pmu_boardobj_msg_grp grp_set;
368 struct nv_pmu_clk_msg_rpc rpc;
369 struct nv_pmu_boardobj_msg_grp grp_get_status;
370 };
371};
372
373struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header {
374 struct nv_pmu_boardobjgrp_e32 super;
375};
376
377struct nv_pmu_clk_clk_vin_device_boardobj_get_status {
378 struct nv_pmu_boardobj_query super;
379 u32 actual_voltage_uv;
380 u32 corrected_voltage_uv;
381 u8 sampled_code;
382 u8 override_code;
383};
384
385union nv_pmu_clk_clk_vin_device_boardobj_get_status_union {
386 struct nv_pmu_boardobj_query board_obj;
387 struct nv_pmu_clk_clk_vin_device_boardobj_get_status super;
388};
389
390NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device);
391
392struct nv_pmu_clk_lut_vf_entry {
393 u32 entry;
394};
395
396struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header {
397 struct nv_pmu_boardobjgrp_e32 super;
398};
399
400struct nv_pmu_clk_clk_fll_device_boardobj_get_status {
401 struct nv_pmu_boardobj_query super;
402 u8 current_regime_id;
403 u16 min_freq_mhz;
404 struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)];
405};
406
407union nv_pmu_clk_clk_fll_device_boardobj_get_status_union {
408 struct nv_pmu_boardobj_query board_obj;
409 struct nv_pmu_clk_clk_fll_device_boardobj_get_status super;
410};
411
412NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device);
413
414#endif /*_GPMUIFCLK_H_*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 01:08:34 -0400