diff options
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif/gpmuifclk.h')
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifclk.h | 455 |
1 files changed, 0 insertions, 455 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h deleted file mode 100644 index 5747b0df..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h +++ /dev/null | |||
@@ -1,455 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _GPMUIFCLK_H_ | ||
15 | #define _GPMUIFCLK_H_ | ||
16 | |||
17 | #include "ctrl/ctrlboardobj.h" | ||
18 | #include "ctrl/ctrlvolt.h" | ||
19 | #include "ctrl/ctrlperf.h" | ||
20 | #include "ctrl/ctrlclk.h" | ||
21 | #include "pmuif/gpmuifboardobj.h" | ||
22 | #include "pmuif/gpmuifvolt.h" | ||
23 | #include <nvgpu/flcnif_cmn.h> | ||
24 | |||
25 | enum nv_pmu_clk_clkwhich { | ||
26 | clkwhich_mclk = 5, | ||
27 | clkwhich_dispclk = 7, | ||
28 | clkwhich_gpc2clk = 17, | ||
29 | clkwhich_xbar2clk = 19, | ||
30 | clkwhich_sys2clk = 20, | ||
31 | clkwhich_hub2clk = 21, | ||
32 | clkwhich_pwrclk = 24, | ||
33 | clkwhich_nvdclk = 25, | ||
34 | clkwhich_pciegenclk = 31, | ||
35 | }; | ||
36 | |||
37 | /* | ||
38 | * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId" | ||
39 | * argument for communications between Kernel and PMU via the various generic | ||
40 | * BOARDOBJGRP interfaces. | ||
41 | */ | ||
42 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00 | ||
43 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01 | ||
44 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 | ||
45 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 | ||
46 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 | ||
47 | #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05 | ||
48 | |||
49 | /*! | ||
50 | * CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the | ||
51 | * CLK_DOMAIN feature. | ||
52 | */ | ||
53 | struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { | ||
54 | struct nv_pmu_boardobjgrp_e32 super; | ||
55 | u32 vbios_domains; | ||
56 | struct ctrl_boardobjgrp_mask_e32 master_domains_mask; | ||
57 | u16 cntr_sampling_periodms; | ||
58 | bool b_override_o_v_o_c; | ||
59 | bool b_debug_mode; | ||
60 | bool b_enforce_vf_monotonicity; | ||
61 | bool b_enforce_vf_smoothening; | ||
62 | u8 volt_rails_max; | ||
63 | struct ctrl_clk_clk_delta deltas; | ||
64 | }; | ||
65 | |||
66 | struct nv_pmu_clk_clk_domain_boardobj_set { | ||
67 | struct nv_pmu_boardobj super; | ||
68 | enum nv_pmu_clk_clkwhich domain; | ||
69 | u32 api_domain; | ||
70 | u8 perf_domain_grp_idx; | ||
71 | }; | ||
72 | |||
73 | struct nv_pmu_clk_clk_domain_3x_boardobj_set { | ||
74 | struct nv_pmu_clk_clk_domain_boardobj_set super; | ||
75 | bool b_noise_aware_capable; | ||
76 | }; | ||
77 | |||
78 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set { | ||
79 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; | ||
80 | u16 freq_mhz; | ||
81 | }; | ||
82 | |||
83 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { | ||
84 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; | ||
85 | u8 clk_prog_idx_first; | ||
86 | u8 clk_prog_idx_last; | ||
87 | u8 noise_unaware_ordering_index; | ||
88 | u8 noise_aware_ordering_index; | ||
89 | bool b_force_noise_unaware_ordering; | ||
90 | int factory_offset_khz; | ||
91 | short freq_delta_min_mhz; | ||
92 | short freq_delta_max_mhz; | ||
93 | struct ctrl_clk_clk_delta deltas; | ||
94 | }; | ||
95 | |||
96 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { | ||
97 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
98 | u32 slave_idxs_mask; | ||
99 | }; | ||
100 | |||
101 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { | ||
102 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
103 | u8 master_idx; | ||
104 | }; | ||
105 | |||
106 | union nv_pmu_clk_clk_domain_boardobj_set_union { | ||
107 | struct nv_pmu_boardobj board_obj; | ||
108 | struct nv_pmu_clk_clk_domain_boardobj_set super; | ||
109 | struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; | ||
110 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; | ||
111 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; | ||
112 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; | ||
113 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; | ||
114 | }; | ||
115 | |||
116 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); | ||
117 | |||
118 | struct nv_pmu_clk_clk_prog_boardobjgrp_set_header { | ||
119 | struct nv_pmu_boardobjgrp_e255 super; | ||
120 | u8 slave_entry_count; | ||
121 | u8 vf_entry_count; | ||
122 | }; | ||
123 | |||
124 | struct nv_pmu_clk_clk_prog_boardobj_set { | ||
125 | struct nv_pmu_boardobj super; | ||
126 | }; | ||
127 | |||
128 | struct nv_pmu_clk_clk_prog_1x_boardobj_set { | ||
129 | struct nv_pmu_clk_clk_prog_boardobj_set super; | ||
130 | u8 source; | ||
131 | u16 freq_max_mhz; | ||
132 | union ctrl_clk_clk_prog_1x_source_data source_data; | ||
133 | }; | ||
134 | |||
135 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { | ||
136 | struct nv_pmu_clk_clk_prog_1x_boardobj_set super; | ||
137 | bool b_o_c_o_v_enabled; | ||
138 | struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ | ||
139 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; | ||
140 | union ctrl_clk_clk_prog_1x_master_source_data source_data; | ||
141 | struct ctrl_clk_clk_delta deltas; | ||
142 | }; | ||
143 | |||
144 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { | ||
145 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | ||
146 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ | ||
147 | CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | ||
148 | }; | ||
149 | |||
150 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { | ||
151 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | ||
152 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry | ||
153 | slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | ||
154 | }; | ||
155 | |||
156 | union nv_pmu_clk_clk_prog_boardobj_set_union { | ||
157 | struct nv_pmu_boardobj board_obj; | ||
158 | struct nv_pmu_clk_clk_prog_boardobj_set super; | ||
159 | struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x; | ||
160 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master; | ||
161 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio; | ||
162 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table; | ||
163 | }; | ||
164 | |||
165 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog); | ||
166 | |||
167 | struct nv_pmu_clk_lut_device_desc { | ||
168 | u8 vselect_mode; | ||
169 | u16 hysteresis_threshold; | ||
170 | }; | ||
171 | |||
172 | struct nv_pmu_clk_regime_desc { | ||
173 | u8 regime_id; | ||
174 | u16 fixed_freq_regime_limit_mhz; | ||
175 | }; | ||
176 | |||
177 | struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header { | ||
178 | struct nv_pmu_boardobjgrp_e32 super; | ||
179 | struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask; | ||
180 | u32 lut_step_size_uv; | ||
181 | u32 lut_min_voltage_uv; | ||
182 | u8 lut_num_entries; | ||
183 | u16 max_min_freq_mhz; | ||
184 | }; | ||
185 | |||
186 | struct nv_pmu_clk_clk_fll_device_boardobj_set { | ||
187 | struct nv_pmu_boardobj super; | ||
188 | u8 id; | ||
189 | u8 mdiv; | ||
190 | u8 vin_idx_logic; | ||
191 | u8 vin_idx_sram; | ||
192 | u8 rail_idx_for_lut; | ||
193 | u16 input_freq_mhz; | ||
194 | u32 clk_domain; | ||
195 | struct nv_pmu_clk_lut_device_desc lut_device; | ||
196 | struct nv_pmu_clk_regime_desc regime_desc; | ||
197 | u8 min_freq_vfe_idx; | ||
198 | u8 freq_ctrl_idx; | ||
199 | struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; | ||
200 | }; | ||
201 | |||
202 | union nv_pmu_clk_clk_fll_device_boardobj_set_union { | ||
203 | struct nv_pmu_boardobj board_obj; | ||
204 | struct nv_pmu_clk_clk_fll_device_boardobj_set super; | ||
205 | }; | ||
206 | |||
207 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device); | ||
208 | |||
209 | struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header { | ||
210 | struct nv_pmu_boardobjgrp_e32 super; | ||
211 | bool b_vin_is_disable_allowed; | ||
212 | }; | ||
213 | |||
214 | struct nv_pmu_clk_clk_vin_device_boardobj_set { | ||
215 | struct nv_pmu_boardobj super; | ||
216 | u8 id; | ||
217 | u8 volt_domain; | ||
218 | u32 slope; | ||
219 | u32 intercept; | ||
220 | u32 flls_shared_mask; | ||
221 | }; | ||
222 | |||
223 | union nv_pmu_clk_clk_vin_device_boardobj_set_union { | ||
224 | struct nv_pmu_boardobj board_obj; | ||
225 | struct nv_pmu_clk_clk_vin_device_boardobj_set super; | ||
226 | }; | ||
227 | |||
228 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device); | ||
229 | |||
230 | struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header { | ||
231 | struct nv_pmu_boardobjgrp_e255 super; | ||
232 | }; | ||
233 | |||
234 | struct nv_pmu_clk_clk_vf_point_boardobj_set { | ||
235 | struct nv_pmu_boardobj super; | ||
236 | u8 vfe_equ_idx; | ||
237 | u8 volt_rail_idx; | ||
238 | }; | ||
239 | |||
240 | struct nv_pmu_clk_clk_vf_point_freq_boardobj_set { | ||
241 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
242 | u16 freq_mhz; | ||
243 | int volt_delta_uv; | ||
244 | }; | ||
245 | |||
246 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_set { | ||
247 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
248 | u32 source_voltage_uv; | ||
249 | int freq_delta_khz; | ||
250 | }; | ||
251 | |||
252 | union nv_pmu_clk_clk_vf_point_boardobj_set_union { | ||
253 | struct nv_pmu_boardobj board_obj; | ||
254 | struct nv_pmu_clk_clk_vf_point_boardobj_set super; | ||
255 | struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq; | ||
256 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt; | ||
257 | }; | ||
258 | |||
259 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point); | ||
260 | |||
261 | struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header { | ||
262 | struct nv_pmu_boardobjgrp_e255 super; | ||
263 | }; | ||
264 | |||
265 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status { | ||
266 | struct nv_pmu_boardobj super; | ||
267 | struct ctrl_clk_vf_pair pair; | ||
268 | }; | ||
269 | |||
270 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status { | ||
271 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; | ||
272 | u16 vf_gain_value; | ||
273 | }; | ||
274 | |||
275 | union nv_pmu_clk_clk_vf_point_boardobj_get_status_union { | ||
276 | struct nv_pmu_boardobj board_obj; | ||
277 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; | ||
278 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt; | ||
279 | }; | ||
280 | |||
281 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point); | ||
282 | |||
283 | #define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12) | ||
284 | |||
285 | struct nv_pmu_clk_clk_domain_list { | ||
286 | u8 num_domains; | ||
287 | struct ctrl_clk_clk_domain_list_item clk_domains[ | ||
288 | NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; | ||
289 | }; | ||
290 | |||
291 | struct nv_pmu_clk_vf_change_inject { | ||
292 | u8 flags; | ||
293 | struct nv_pmu_clk_clk_domain_list clk_list; | ||
294 | struct nv_pmu_volt_volt_rail_list volt_list; | ||
295 | }; | ||
296 | |||
297 | #define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) | ||
298 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) | ||
299 | |||
300 | struct nv_pmu_clk_load_payload_freq_controllers { | ||
301 | struct ctrl_boardobjgrp_mask_e32 load_mask; | ||
302 | }; | ||
303 | |||
304 | struct nv_pmu_clk_load { | ||
305 | u8 feature; | ||
306 | u32 action_mask; | ||
307 | union { | ||
308 | struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; | ||
309 | } payload; | ||
310 | }; | ||
311 | /* CLK_FREQ_CONTROLLER */ | ||
312 | #define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003) | ||
313 | |||
314 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO (0x00000000) | ||
315 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002) | ||
316 | |||
317 | struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header { | ||
318 | struct nv_pmu_boardobjgrp_e32 super; | ||
319 | u32 sampling_period_ms; | ||
320 | u8 volt_policy_idx; | ||
321 | }; | ||
322 | |||
323 | struct nv_pmu_clk_clk_freq_controller_boardobj_set { | ||
324 | struct nv_pmu_boardobj super; | ||
325 | u8 controller_id; | ||
326 | u8 parts_freq_mode; | ||
327 | bool bdisable; | ||
328 | u32 clk_domain; | ||
329 | s16 freq_cap_noise_unaware_vmin_above; | ||
330 | s16 freq_cap_noise_unaware_vmin_below; | ||
331 | s16 freq_hyst_pos_mhz; | ||
332 | s16 freq_hyst_neg_mhz; | ||
333 | }; | ||
334 | |||
335 | struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set { | ||
336 | struct nv_pmu_clk_clk_freq_controller_boardobj_set super; | ||
337 | s32 prop_gain; | ||
338 | s32 integ_gain; | ||
339 | s32 integ_decay; | ||
340 | s32 volt_delta_min; | ||
341 | s32 volt_delta_max; | ||
342 | u8 slowdown_pct_min; | ||
343 | bool bpoison; | ||
344 | }; | ||
345 | |||
346 | union nv_pmu_clk_clk_freq_controller_boardobj_set_union { | ||
347 | struct nv_pmu_boardobj board_obj; | ||
348 | struct nv_pmu_clk_clk_freq_controller_boardobj_set super; | ||
349 | struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi; | ||
350 | }; | ||
351 | |||
352 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); | ||
353 | |||
354 | /* CLK CMD ID definitions. */ | ||
355 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
356 | #define NV_PMU_CLK_CMD_ID_RPC (0x00000001) | ||
357 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
358 | |||
359 | #define NV_PMU_CLK_RPC_ID_LOAD (0x00000002) | ||
360 | #define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001) | ||
361 | |||
362 | struct nv_pmu_clk_cmd_rpc { | ||
363 | u8 cmd_type; | ||
364 | u8 pad[3]; | ||
365 | struct nv_pmu_allocation request; | ||
366 | }; | ||
367 | |||
368 | #define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \ | ||
369 | (offsetof(struct nv_pmu_clk_cmd_rpc, request)) | ||
370 | |||
371 | struct nv_pmu_clk_cmd { | ||
372 | union { | ||
373 | u8 cmd_type; | ||
374 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
375 | struct nv_pmu_clk_cmd_rpc rpc; | ||
376 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
377 | }; | ||
378 | }; | ||
379 | |||
380 | struct nv_pmu_clk_rpc { | ||
381 | u8 function; | ||
382 | bool b_supported; | ||
383 | bool b_success; | ||
384 | flcn_status flcn_status; | ||
385 | union { | ||
386 | struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; | ||
387 | struct nv_pmu_clk_load clk_load; | ||
388 | } params; | ||
389 | }; | ||
390 | |||
391 | /* CLK MSG ID definitions */ | ||
392 | #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
393 | #define NV_PMU_CLK_MSG_ID_RPC (0x00000001) | ||
394 | #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
395 | |||
396 | struct nv_pmu_clk_msg_rpc { | ||
397 | u8 msg_type; | ||
398 | u8 rsvd[3]; | ||
399 | struct nv_pmu_allocation response; | ||
400 | }; | ||
401 | |||
402 | #define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \ | ||
403 | offsetof(struct nv_pmu_clk_msg_rpc, response) | ||
404 | |||
405 | struct nv_pmu_clk_msg { | ||
406 | union { | ||
407 | u8 msg_type; | ||
408 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
409 | struct nv_pmu_clk_msg_rpc rpc; | ||
410 | struct nv_pmu_boardobj_msg_grp grp_get_status; | ||
411 | }; | ||
412 | }; | ||
413 | |||
414 | struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header { | ||
415 | struct nv_pmu_boardobjgrp_e32 super; | ||
416 | }; | ||
417 | |||
418 | struct nv_pmu_clk_clk_vin_device_boardobj_get_status { | ||
419 | struct nv_pmu_boardobj_query super; | ||
420 | u32 actual_voltage_uv; | ||
421 | u32 corrected_voltage_uv; | ||
422 | u8 sampled_code; | ||
423 | u8 override_code; | ||
424 | }; | ||
425 | |||
426 | union nv_pmu_clk_clk_vin_device_boardobj_get_status_union { | ||
427 | struct nv_pmu_boardobj_query board_obj; | ||
428 | struct nv_pmu_clk_clk_vin_device_boardobj_get_status super; | ||
429 | }; | ||
430 | |||
431 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device); | ||
432 | |||
433 | struct nv_pmu_clk_lut_vf_entry { | ||
434 | u32 entry; | ||
435 | }; | ||
436 | |||
437 | struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header { | ||
438 | struct nv_pmu_boardobjgrp_e32 super; | ||
439 | }; | ||
440 | |||
441 | struct nv_pmu_clk_clk_fll_device_boardobj_get_status { | ||
442 | struct nv_pmu_boardobj_query super; | ||
443 | u8 current_regime_id; | ||
444 | u16 min_freq_mhz; | ||
445 | struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)]; | ||
446 | }; | ||
447 | |||
448 | union nv_pmu_clk_clk_fll_device_boardobj_get_status_union { | ||
449 | struct nv_pmu_boardobj_query board_obj; | ||
450 | struct nv_pmu_clk_clk_fll_device_boardobj_get_status super; | ||
451 | }; | ||
452 | |||
453 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device); | ||
454 | |||
455 | #endif /*_GPMUIFCLK_H_*/ | ||