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Diffstat (limited to 'drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h')
-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h215
1 files changed, 215 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h
new file mode 100644
index 00000000..f9ffb4b1
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h
@@ -0,0 +1,215 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef _GPMUIFPMU_H_
14#define _GPMUIFPMU_H_
15
16#include "gk20a/pmu_common.h"
17#include "gpmuif_cmn.h"
18
19/* Make sure size of this structure is a multiple of 4 bytes */
20struct pmu_cmdline_args_v0 {
21 u32 cpu_freq_hz;
22 u32 falc_trace_size;
23 u32 falc_trace_dma_base;
24 u32 falc_trace_dma_idx;
25 struct pmu_mem_v0 gc6_ctx;
26};
27
28struct pmu_cmdline_args_v1 {
29 u32 cpu_freq_hz;
30 u32 falc_trace_size;
31 u32 falc_trace_dma_base;
32 u32 falc_trace_dma_idx;
33 u8 secure_mode;
34 struct pmu_mem_v1 gc6_ctx;
35};
36
37struct pmu_cmdline_args_v2 {
38 u32 cpu_freq_hz;
39 u32 falc_trace_size;
40 u32 falc_trace_dma_base;
41 u32 falc_trace_dma_idx;
42 u8 secure_mode;
43 u8 raise_priv_sec;
44 struct pmu_mem_v1 gc6_ctx;
45};
46
47struct pmu_cmdline_args_v3 {
48 u32 reserved;
49 u32 cpu_freq_hz;
50 u32 falc_trace_size;
51 u32 falc_trace_dma_base;
52 u32 falc_trace_dma_idx;
53 u8 secure_mode;
54 u8 raise_priv_sec;
55 struct pmu_mem_v1 gc6_ctx;
56};
57
58struct pmu_cmdline_args_v4 {
59 u32 reserved;
60 u32 cpu_freq_hz;
61 u32 falc_trace_size;
62 struct falc_dma_addr dma_addr;
63 u32 falc_trace_dma_idx;
64 u8 secure_mode;
65 u8 raise_priv_sec;
66 struct pmu_mem_desc_v0 gc6_ctx;
67 u8 pad;
68};
69
70struct pmu_cmdline_args_v5 {
71 u32 cpu_freq_hz;
72 struct flcn_mem_desc_v0 trace_buf;
73 u8 secure_mode;
74 u8 raise_priv_sec;
75 struct flcn_mem_desc_v0 gc6_ctx;
76 struct flcn_mem_desc_v0 init_data_dma_info;
77 u32 dummy;
78};
79
80/* GPU ID */
81#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2
82#define PMU_SHA1_GID_SIGNATURE_SIZE 4
83
84#define PMU_SHA1_GID_SIZE 16
85
86struct pmu_sha1_gid {
87 bool valid;
88 u8 gid[PMU_SHA1_GID_SIZE];
89};
90
91struct pmu_sha1_gid_data {
92 u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE];
93 u8 gid[PMU_SHA1_GID_SIZE];
94};
95
96/* PMU INIT MSG */
97enum {
98 PMU_INIT_MSG_TYPE_PMU_INIT = 0,
99};
100
101struct pmu_init_msg_pmu_v0 {
102 u8 msg_type;
103 u8 pad;
104
105 struct {
106 u16 size;
107 u16 offset;
108 u8 index;
109 u8 pad;
110 } queue_info[PMU_QUEUE_COUNT];
111
112 u16 sw_managed_area_offset;
113 u16 sw_managed_area_size;
114};
115
116struct pmu_init_msg_pmu_v1 {
117 u8 msg_type;
118 u8 pad;
119 u16 os_debug_entry_point;
120
121 struct {
122 u16 size;
123 u16 offset;
124 u8 index;
125 u8 pad;
126 } queue_info[PMU_QUEUE_COUNT];
127
128 u16 sw_managed_area_offset;
129 u16 sw_managed_area_size;
130};
131struct pmu_init_msg_pmu_v2 {
132 u8 msg_type;
133 u8 pad;
134 u16 os_debug_entry_point;
135
136 struct {
137 u16 size;
138 u16 offset;
139 u8 index;
140 u8 pad;
141 } queue_info[PMU_QUEUE_COUNT];
142
143 u16 sw_managed_area_offset;
144 u16 sw_managed_area_size;
145 u8 dummy[18];
146};
147
148#define PMU_QUEUE_COUNT_FOR_V4 5
149#define PMU_QUEUE_COUNT_FOR_V3 3
150#define PMU_QUEUE_HPQ_IDX_FOR_V3 0
151#define PMU_QUEUE_LPQ_IDX_FOR_V3 1
152#define PMU_QUEUE_MSG_IDX_FOR_V3 2
153struct pmu_init_msg_pmu_v3 {
154 u8 msg_type;
155 u8 queue_index[PMU_QUEUE_COUNT_FOR_V3];
156 u16 queue_size[PMU_QUEUE_COUNT_FOR_V3];
157 u16 queue_offset;
158
159 u16 sw_managed_area_offset;
160 u16 sw_managed_area_size;
161
162 u16 os_debug_entry_point;
163
164 u8 dummy[18];
165};
166
167struct pmu_init_msg_pmu_v4 {
168 u8 msg_type;
169 u8 queue_index[PMU_QUEUE_COUNT_FOR_V4];
170 u16 queue_size[PMU_QUEUE_COUNT_FOR_V4];
171 u16 queue_offset;
172
173 u16 sw_managed_area_offset;
174 u16 sw_managed_area_size;
175
176 u16 os_debug_entry_point;
177
178 u8 dummy[18];
179};
180
181union pmu_init_msg_pmu {
182 struct pmu_init_msg_pmu_v0 v0;
183 struct pmu_init_msg_pmu_v1 v1;
184 struct pmu_init_msg_pmu_v2 v2;
185 struct pmu_init_msg_pmu_v3 v3;
186 struct pmu_init_msg_pmu_v4 v4;
187};
188
189struct pmu_init_msg {
190 union {
191 u8 msg_type;
192 struct pmu_init_msg_pmu_v1 pmu_init_v1;
193 struct pmu_init_msg_pmu_v0 pmu_init_v0;
194 struct pmu_init_msg_pmu_v2 pmu_init_v2;
195 struct pmu_init_msg_pmu_v3 pmu_init_v3;
196 struct pmu_init_msg_pmu_v4 pmu_init_v4;
197 };
198};
199
200/* robust channel (RC) messages */
201enum {
202 PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0,
203};
204
205struct pmu_rc_msg_unhandled_cmd {
206 u8 msg_type;
207 u8 unit_id;
208};
209
210struct pmu_rc_msg {
211 u8 msg_type;
212 struct pmu_rc_msg_unhandled_cmd unhandled_cmd;
213};
214
215#endif /* _GPMUIFPMU_H_*/
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