diff options
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif/gpmuif_pg.h')
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuif_pg.h | 311 |
1 files changed, 0 insertions, 311 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h deleted file mode 100644 index 8c71e2a2..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h +++ /dev/null | |||
@@ -1,311 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPG_H_ | ||
14 | #define _GPMUIFPG_H_ | ||
15 | |||
16 | #include "gpmuif_ap.h" | ||
17 | #include "gpmuif_pg_rppg.h" | ||
18 | |||
19 | /*PG defines*/ | ||
20 | |||
21 | /* Identifier for each PG */ | ||
22 | #define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000) | ||
23 | #define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004) | ||
24 | #define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005) | ||
25 | #define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE | ||
26 | |||
27 | /* PG message */ | ||
28 | enum { | ||
29 | PMU_PG_ELPG_MSG_INIT_ACK, | ||
30 | PMU_PG_ELPG_MSG_DISALLOW_ACK, | ||
31 | PMU_PG_ELPG_MSG_ALLOW_ACK, | ||
32 | PMU_PG_ELPG_MSG_FREEZE_ACK, | ||
33 | PMU_PG_ELPG_MSG_FREEZE_ABORT, | ||
34 | PMU_PG_ELPG_MSG_UNFREEZE_ACK, | ||
35 | }; | ||
36 | |||
37 | struct pmu_pg_msg_elpg_msg { | ||
38 | u8 msg_type; | ||
39 | u8 engine_id; | ||
40 | u16 msg; | ||
41 | }; | ||
42 | |||
43 | enum { | ||
44 | PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, | ||
45 | }; | ||
46 | |||
47 | struct pmu_pg_msg_stat { | ||
48 | u8 msg_type; | ||
49 | u8 engine_id; | ||
50 | u16 sub_msg_id; | ||
51 | u32 data; | ||
52 | }; | ||
53 | |||
54 | enum { | ||
55 | PMU_PG_MSG_ENG_BUF_LOADED, | ||
56 | PMU_PG_MSG_ENG_BUF_UNLOADED, | ||
57 | PMU_PG_MSG_ENG_BUF_FAILED, | ||
58 | }; | ||
59 | |||
60 | struct pmu_pg_msg_eng_buf_stat { | ||
61 | u8 msg_type; | ||
62 | u8 engine_id; | ||
63 | u8 buf_idx; | ||
64 | u8 status; | ||
65 | }; | ||
66 | |||
67 | struct pmu_pg_msg { | ||
68 | union { | ||
69 | u8 msg_type; | ||
70 | struct pmu_pg_msg_elpg_msg elpg_msg; | ||
71 | struct pmu_pg_msg_stat stat; | ||
72 | struct pmu_pg_msg_eng_buf_stat eng_buf_stat; | ||
73 | /* TBD: other pg messages */ | ||
74 | union pmu_ap_msg ap_msg; | ||
75 | struct nv_pmu_rppg_msg rppg_msg; | ||
76 | }; | ||
77 | }; | ||
78 | |||
79 | /* PG commands */ | ||
80 | enum { | ||
81 | PMU_PG_ELPG_CMD_INIT, | ||
82 | PMU_PG_ELPG_CMD_DISALLOW, | ||
83 | PMU_PG_ELPG_CMD_ALLOW, | ||
84 | PMU_PG_ELPG_CMD_FREEZE, | ||
85 | PMU_PG_ELPG_CMD_UNFREEZE, | ||
86 | }; | ||
87 | |||
88 | enum { | ||
89 | PMU_PG_CMD_ID_ELPG_CMD = 0, | ||
90 | PMU_PG_CMD_ID_ENG_BUF_LOAD, | ||
91 | PMU_PG_CMD_ID_ENG_BUF_UNLOAD, | ||
92 | PMU_PG_CMD_ID_PG_STAT, | ||
93 | PMU_PG_CMD_ID_PG_LOG_INIT, | ||
94 | PMU_PG_CMD_ID_PG_LOG_FLUSH, | ||
95 | PMU_PG_CMD_ID_PG_PARAM, | ||
96 | PMU_PG_CMD_ID_ELPG_INIT, | ||
97 | PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, | ||
98 | PMU_PG_CMD_ID_ELPG_ABORT_POLL, | ||
99 | PMU_PG_CMD_ID_ELPG_PWR_UP, | ||
100 | PMU_PG_CMD_ID_ELPG_DISALLOW, | ||
101 | PMU_PG_CMD_ID_ELPG_ALLOW, | ||
102 | PMU_PG_CMD_ID_AP, | ||
103 | RM_PMU_PG_CMD_ID_PSI, | ||
104 | RM_PMU_PG_CMD_ID_CG, | ||
105 | PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, | ||
106 | PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, | ||
107 | PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, | ||
108 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, | ||
109 | PMU_PMU_PG_CMD_ID_RPPG = 0x24, | ||
110 | }; | ||
111 | |||
112 | enum { | ||
113 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, | ||
114 | }; | ||
115 | |||
116 | #define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 | ||
117 | #define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 | ||
118 | #define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 | ||
119 | #define PMU_PG_PARAM_CMD_POST_INIT 0x06 | ||
120 | |||
121 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) | ||
122 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) | ||
123 | #define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) | ||
124 | |||
125 | #define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) | ||
126 | #define NVGPU_PMU_GR_FEATURE_MASK_ALL \ | ||
127 | ( \ | ||
128 | NVGPU_PMU_GR_FEATURE_MASK_RPPG \ | ||
129 | ) | ||
130 | |||
131 | #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) | ||
132 | #define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1) | ||
133 | #define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8) | ||
134 | #define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5) | ||
135 | |||
136 | #define NVGPU_PMU_MS_FEATURE_MASK_ALL \ | ||
137 | ( \ | ||
138 | NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\ | ||
139 | NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\ | ||
140 | NVGPU_PMU_MS_FEATURE_MASK_RPPG |\ | ||
141 | NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \ | ||
142 | ) | ||
143 | |||
144 | |||
145 | struct pmu_pg_cmd_elpg_cmd { | ||
146 | u8 cmd_type; | ||
147 | u8 engine_id; | ||
148 | u16 cmd; | ||
149 | }; | ||
150 | |||
151 | struct pmu_pg_cmd_eng_buf_load_v0 { | ||
152 | u8 cmd_type; | ||
153 | u8 engine_id; | ||
154 | u8 buf_idx; | ||
155 | u8 pad; | ||
156 | u16 buf_size; | ||
157 | u32 dma_base; | ||
158 | u8 dma_offset; | ||
159 | u8 dma_idx; | ||
160 | }; | ||
161 | |||
162 | struct pmu_pg_cmd_eng_buf_load_v1 { | ||
163 | u8 cmd_type; | ||
164 | u8 engine_id; | ||
165 | u8 buf_idx; | ||
166 | u8 pad; | ||
167 | struct flcn_mem_desc { | ||
168 | struct falc_u64 dma_addr; | ||
169 | u16 dma_size; | ||
170 | u8 dma_idx; | ||
171 | } dma_desc; | ||
172 | }; | ||
173 | |||
174 | struct pmu_pg_cmd_eng_buf_load_v2 { | ||
175 | u8 cmd_type; | ||
176 | u8 engine_id; | ||
177 | u8 buf_idx; | ||
178 | u8 pad; | ||
179 | struct flcn_mem_desc_v0 dma_desc; | ||
180 | }; | ||
181 | |||
182 | struct pmu_pg_cmd_gr_init_param { | ||
183 | u8 cmd_type; | ||
184 | u16 sub_cmd_id; | ||
185 | u8 featuremask; | ||
186 | }; | ||
187 | |||
188 | struct pmu_pg_cmd_ms_init_param { | ||
189 | u8 cmd_type; | ||
190 | u16 cmd_id; | ||
191 | u8 psi; | ||
192 | u8 idle_flipped_test_enabled; | ||
193 | u16 psiSettleTimeUs; | ||
194 | u8 rsvd[2]; | ||
195 | u32 support_mask; | ||
196 | u32 abort_timeout_us; | ||
197 | }; | ||
198 | |||
199 | struct pmu_pg_cmd_mclk_change { | ||
200 | u8 cmd_type; | ||
201 | u16 cmd_id; | ||
202 | u8 rsvd; | ||
203 | u32 data; | ||
204 | }; | ||
205 | |||
206 | #define PG_VOLT_RAIL_IDX_MAX 2 | ||
207 | |||
208 | struct pmu_pg_volt_rail { | ||
209 | u8 volt_rail_idx; | ||
210 | u8 sleep_volt_dev_idx; | ||
211 | u8 sleep_vfe_idx; | ||
212 | u32 sleep_voltage_uv; | ||
213 | u32 therm_vid0_cache; | ||
214 | u32 therm_vid1_cache; | ||
215 | }; | ||
216 | |||
217 | struct pmu_pg_cmd_post_init_param { | ||
218 | u8 cmd_type; | ||
219 | u16 cmd_id; | ||
220 | struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; | ||
221 | }; | ||
222 | |||
223 | struct pmu_pg_cmd_stat { | ||
224 | u8 cmd_type; | ||
225 | u8 engine_id; | ||
226 | u16 sub_cmd_id; | ||
227 | u32 data; | ||
228 | }; | ||
229 | |||
230 | struct pmu_pg_cmd { | ||
231 | union { | ||
232 | u8 cmd_type; | ||
233 | struct pmu_pg_cmd_elpg_cmd elpg_cmd; | ||
234 | struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; | ||
235 | struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; | ||
236 | struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; | ||
237 | struct pmu_pg_cmd_stat stat; | ||
238 | struct pmu_pg_cmd_gr_init_param gr_init_param; | ||
239 | struct pmu_pg_cmd_ms_init_param ms_init_param; | ||
240 | struct pmu_pg_cmd_mclk_change mclk_change; | ||
241 | struct pmu_pg_cmd_post_init_param post_init; | ||
242 | /* TBD: other pg commands */ | ||
243 | union pmu_ap_cmd ap_cmd; | ||
244 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
245 | }; | ||
246 | }; | ||
247 | |||
248 | /* Statistics structure for PG features */ | ||
249 | struct pmu_pg_stats_v2 { | ||
250 | u32 entry_count; | ||
251 | u32 exit_count; | ||
252 | u32 abort_count; | ||
253 | u32 detection_count; | ||
254 | u32 prevention_activate_count; | ||
255 | u32 prevention_deactivate_count; | ||
256 | u32 powered_up_time_us; | ||
257 | u32 entry_latency_us; | ||
258 | u32 exit_latency_us; | ||
259 | u32 resident_time_us; | ||
260 | u32 entry_latency_avg_us; | ||
261 | u32 exit_latency_avg_us; | ||
262 | u32 entry_latency_max_us; | ||
263 | u32 exit_latency_max_us; | ||
264 | u32 total_sleep_time_us; | ||
265 | u32 total_non_sleep_time_us; | ||
266 | }; | ||
267 | |||
268 | struct pmu_pg_stats_v1 { | ||
269 | /* Number of time PMU successfully engaged sleep state */ | ||
270 | u32 entry_count; | ||
271 | /* Number of time PMU exit sleep state */ | ||
272 | u32 exit_count; | ||
273 | /* Number of time PMU aborted in entry sequence */ | ||
274 | u32 abort_count; | ||
275 | /* | ||
276 | * Time for which GPU was neither in Sleep state not | ||
277 | * executing sleep sequence. | ||
278 | */ | ||
279 | u32 poweredup_timeus; | ||
280 | /* Entry and exit latency of current sleep cycle */ | ||
281 | u32 entry_latency_us; | ||
282 | u32 exitlatencyus; | ||
283 | /* Resident time for current sleep cycle. */ | ||
284 | u32 resident_timeus; | ||
285 | /* Rolling average entry and exit latencies */ | ||
286 | u32 entrylatency_avgus; | ||
287 | u32 exitlatency_avgus; | ||
288 | /* Max entry and exit latencies */ | ||
289 | u32 entrylatency_maxus; | ||
290 | u32 exitlatency_maxus; | ||
291 | /* Total time spent in sleep and non-sleep state */ | ||
292 | u32 total_sleep_timeus; | ||
293 | u32 total_nonsleep_timeus; | ||
294 | }; | ||
295 | |||
296 | struct pmu_pg_stats { | ||
297 | u64 pg_entry_start_timestamp; | ||
298 | u64 pg_ingating_start_timestamp; | ||
299 | u64 pg_exit_start_timestamp; | ||
300 | u64 pg_ungating_start_timestamp; | ||
301 | u32 pg_avg_entry_time_us; | ||
302 | u32 pg_ingating_cnt; | ||
303 | u32 pg_ingating_time_us; | ||
304 | u32 pg_avg_exit_time_us; | ||
305 | u32 pg_ungating_count; | ||
306 | u32 pg_ungating_time_us; | ||
307 | u32 pg_gating_cnt; | ||
308 | u32 pg_gating_deny_cnt; | ||
309 | }; | ||
310 | |||
311 | #endif /* _GPMUIFPG_H_*/ | ||