diff options
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr')
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrdev.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrmonitor.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrpolicy.c | 12 |
3 files changed, 22 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c index 7f4ab716..da51ac4b 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -36,7 +36,7 @@ static u32 _pwr_device_pmudata_instget(struct gk20a *g, | |||
36 | struct nv_pmu_pmgr_pwr_device_desc_table *ppmgrdevice = | 36 | struct nv_pmu_pmgr_pwr_device_desc_table *ppmgrdevice = |
37 | (struct nv_pmu_pmgr_pwr_device_desc_table *)pmuboardobjgrp; | 37 | (struct nv_pmu_pmgr_pwr_device_desc_table *)pmuboardobjgrp; |
38 | 38 | ||
39 | gk20a_dbg_info(""); | 39 | nvgpu_log_info(g, " "); |
40 | 40 | ||
41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
42 | if (((u32)BIT(idx) & | 42 | if (((u32)BIT(idx) & |
@@ -46,7 +46,7 @@ static u32 _pwr_device_pmudata_instget(struct gk20a *g, | |||
46 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 46 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
47 | &ppmgrdevice->devices[idx].data.board_obj; | 47 | &ppmgrdevice->devices[idx].data.board_obj; |
48 | 48 | ||
49 | gk20a_dbg_info(" Done"); | 49 | nvgpu_log_info(g, " Done"); |
50 | 50 | ||
51 | return 0; | 51 | return 0; |
52 | } | 52 | } |
@@ -122,7 +122,7 @@ static struct boardobj *construct_pwr_device(struct gk20a *g, | |||
122 | pwrdev->r_shuntm_ohm[indx] = ina3221->r_shuntm_ohm[indx]; | 122 | pwrdev->r_shuntm_ohm[indx] = ina3221->r_shuntm_ohm[indx]; |
123 | } | 123 | } |
124 | 124 | ||
125 | gk20a_dbg_info(" Done"); | 125 | nvgpu_log_info(g, " Done"); |
126 | 126 | ||
127 | return board_obj_ptr; | 127 | return board_obj_ptr; |
128 | } | 128 | } |
@@ -145,7 +145,7 @@ static u32 devinit_get_pwr_device_table(struct gk20a *g, | |||
145 | struct pwr_device_ina3221 ina3221; | 145 | struct pwr_device_ina3221 ina3221; |
146 | } pwr_device_data; | 146 | } pwr_device_data; |
147 | 147 | ||
148 | gk20a_dbg_info(""); | 148 | nvgpu_log_info(g, " "); |
149 | 149 | ||
150 | pwr_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | 150 | pwr_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, |
151 | g->bios.perf_token, POWER_SENSORS_TABLE); | 151 | g->bios.perf_token, POWER_SENSORS_TABLE); |
@@ -280,7 +280,7 @@ static u32 devinit_get_pwr_device_table(struct gk20a *g, | |||
280 | } | 280 | } |
281 | 281 | ||
282 | done: | 282 | done: |
283 | gk20a_dbg_info(" done status %x", status); | 283 | nvgpu_log_info(g, " done status %x", status); |
284 | return status; | 284 | return status; |
285 | } | 285 | } |
286 | 286 | ||
@@ -310,6 +310,6 @@ u32 pmgr_device_sw_setup(struct gk20a *g) | |||
310 | goto done; | 310 | goto done; |
311 | 311 | ||
312 | done: | 312 | done: |
313 | gk20a_dbg_info(" done status %x", status); | 313 | nvgpu_log_info(g, " done status %x", status); |
314 | return status; | 314 | return status; |
315 | } | 315 | } |
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c index 00c930a6..5e0cc966 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -36,7 +36,7 @@ static u32 _pwr_channel_pmudata_instget(struct gk20a *g, | |||
36 | struct nv_pmu_pmgr_pwr_channel_desc *ppmgrchannel = | 36 | struct nv_pmu_pmgr_pwr_channel_desc *ppmgrchannel = |
37 | (struct nv_pmu_pmgr_pwr_channel_desc *)pmuboardobjgrp; | 37 | (struct nv_pmu_pmgr_pwr_channel_desc *)pmuboardobjgrp; |
38 | 38 | ||
39 | gk20a_dbg_info(""); | 39 | nvgpu_log_info(g, " "); |
40 | 40 | ||
41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
42 | if (((u32)BIT(idx) & | 42 | if (((u32)BIT(idx) & |
@@ -49,7 +49,7 @@ static u32 _pwr_channel_pmudata_instget(struct gk20a *g, | |||
49 | /* handle Global/common data here as we need index */ | 49 | /* handle Global/common data here as we need index */ |
50 | ppmgrchannel->channels[idx].data.pwr_channel.ch_idx = idx; | 50 | ppmgrchannel->channels[idx].data.pwr_channel.ch_idx = idx; |
51 | 51 | ||
52 | gk20a_dbg_info(" Done"); | 52 | nvgpu_log_info(g, " Done"); |
53 | 53 | ||
54 | return 0; | 54 | return 0; |
55 | } | 55 | } |
@@ -62,7 +62,7 @@ static u32 _pwr_channel_rels_pmudata_instget(struct gk20a *g, | |||
62 | struct nv_pmu_pmgr_pwr_chrelationship_desc *ppmgrchrels = | 62 | struct nv_pmu_pmgr_pwr_chrelationship_desc *ppmgrchrels = |
63 | (struct nv_pmu_pmgr_pwr_chrelationship_desc *)pmuboardobjgrp; | 63 | (struct nv_pmu_pmgr_pwr_chrelationship_desc *)pmuboardobjgrp; |
64 | 64 | ||
65 | gk20a_dbg_info(""); | 65 | nvgpu_log_info(g, " "); |
66 | 66 | ||
67 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 67 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
68 | if (((u32)BIT(idx) & | 68 | if (((u32)BIT(idx) & |
@@ -72,7 +72,7 @@ static u32 _pwr_channel_rels_pmudata_instget(struct gk20a *g, | |||
72 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 72 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
73 | &ppmgrchrels->ch_rels[idx].data.board_obj; | 73 | &ppmgrchrels->ch_rels[idx].data.board_obj; |
74 | 74 | ||
75 | gk20a_dbg_info(" Done"); | 75 | nvgpu_log_info(g, " Done"); |
76 | 76 | ||
77 | return 0; | 77 | return 0; |
78 | } | 78 | } |
@@ -169,7 +169,7 @@ static struct boardobj *construct_pwr_topology(struct gk20a *g, | |||
169 | pwrchannel->pwr_dev_idx = sensor->pwr_dev_idx; | 169 | pwrchannel->pwr_dev_idx = sensor->pwr_dev_idx; |
170 | pwrchannel->pwr_dev_prov_idx = sensor->pwr_dev_prov_idx; | 170 | pwrchannel->pwr_dev_prov_idx = sensor->pwr_dev_prov_idx; |
171 | 171 | ||
172 | gk20a_dbg_info(" Done"); | 172 | nvgpu_log_info(g, " Done"); |
173 | 173 | ||
174 | return board_obj_ptr; | 174 | return board_obj_ptr; |
175 | } | 175 | } |
@@ -192,7 +192,7 @@ static u32 devinit_get_pwr_topology_table(struct gk20a *g, | |||
192 | struct pwr_channel_sensor sensor; | 192 | struct pwr_channel_sensor sensor; |
193 | } pwr_topology_data; | 193 | } pwr_topology_data; |
194 | 194 | ||
195 | gk20a_dbg_info(""); | 195 | nvgpu_log_info(g, " "); |
196 | 196 | ||
197 | pwr_topology_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | 197 | pwr_topology_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, |
198 | g->bios.perf_token, POWER_TOPOLOGY_TABLE); | 198 | g->bios.perf_token, POWER_TOPOLOGY_TABLE); |
@@ -292,7 +292,7 @@ static u32 devinit_get_pwr_topology_table(struct gk20a *g, | |||
292 | } | 292 | } |
293 | 293 | ||
294 | done: | 294 | done: |
295 | gk20a_dbg_info(" done status %x", status); | 295 | nvgpu_log_info(g, " done status %x", status); |
296 | return status; | 296 | return status; |
297 | } | 297 | } |
298 | 298 | ||
@@ -365,6 +365,6 @@ u32 pmgr_monitor_sw_setup(struct gk20a *g) | |||
365 | } | 365 | } |
366 | 366 | ||
367 | done: | 367 | done: |
368 | gk20a_dbg_info(" done status %x", status); | 368 | nvgpu_log_info(g, " done status %x", status); |
369 | return status; | 369 | return status; |
370 | } | 370 | } |
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c index 2942268f..0d617f6a 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -270,7 +270,7 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g, | |||
270 | pwrpolicyhwthreshold = (struct pwr_policy_hw_threshold*)board_obj_ptr; | 270 | pwrpolicyhwthreshold = (struct pwr_policy_hw_threshold*)board_obj_ptr; |
271 | pwrpolicy = (struct pwr_policy *)board_obj_ptr; | 271 | pwrpolicy = (struct pwr_policy *)board_obj_ptr; |
272 | 272 | ||
273 | gk20a_dbg_fn("min=%u rated=%u max=%u", | 273 | nvgpu_log_fn(g, "min=%u rated=%u max=%u", |
274 | pwrpolicyparams->limit_min, | 274 | pwrpolicyparams->limit_min, |
275 | pwrpolicyparams->limit_rated, | 275 | pwrpolicyparams->limit_rated, |
276 | pwrpolicyparams->limit_max); | 276 | pwrpolicyparams->limit_max); |
@@ -358,7 +358,7 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g, | |||
358 | pwrpolicyswthreshold->event_id = swthreshold->event_id; | 358 | pwrpolicyswthreshold->event_id = swthreshold->event_id; |
359 | } | 359 | } |
360 | 360 | ||
361 | gk20a_dbg_info(" Done"); | 361 | nvgpu_log_info(g, " Done"); |
362 | 362 | ||
363 | return board_obj_ptr; | 363 | return board_obj_ptr; |
364 | } | 364 | } |
@@ -527,7 +527,7 @@ static u32 devinit_get_pwr_policy_table(struct gk20a *g, | |||
527 | u32 hw_threshold_policy_index = 0; | 527 | u32 hw_threshold_policy_index = 0; |
528 | union pwr_policy_data_union pwr_policy_data; | 528 | union pwr_policy_data_union pwr_policy_data; |
529 | 529 | ||
530 | gk20a_dbg_info(""); | 530 | nvgpu_log_info(g, " "); |
531 | 531 | ||
532 | ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | 532 | ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, |
533 | g->bios.perf_token, POWER_CAPPING_TABLE); | 533 | g->bios.perf_token, POWER_CAPPING_TABLE); |
@@ -702,7 +702,7 @@ static u32 devinit_get_pwr_policy_table(struct gk20a *g, | |||
702 | } | 702 | } |
703 | 703 | ||
704 | done: | 704 | done: |
705 | gk20a_dbg_info(" done status %x", status); | 705 | nvgpu_log_info(g, " done status %x", status); |
706 | return status; | 706 | return status; |
707 | } | 707 | } |
708 | 708 | ||
@@ -773,6 +773,6 @@ u32 pmgr_policy_sw_setup(struct gk20a *g) | |||
773 | g->pmgr_pmu.pmgr_policyobjs.client_work_item.b_pending = false; | 773 | g->pmgr_pmu.pmgr_policyobjs.client_work_item.b_pending = false; |
774 | 774 | ||
775 | done: | 775 | done: |
776 | gk20a_dbg_info(" done status %x", status); | 776 | nvgpu_log_info(g, " done status %x", status); |
777 | return status; | 777 | return status; |
778 | } | 778 | } |