10 files changed, 47 insertions, 47 deletions

diff --git a/drivers/gpu/nvgpu/pmgr/pmgr.c b/drivers/gpu/nvgpu/pmgr/pmgr.c
index 3d6a96af..6be0f82f 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgr.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -101,7 +101,7 @@ exit:
         return status;
 }
 
-u32 pmgr_domain_pmu_setup(struct gk20a *g)
+int pmgr_domain_pmu_setup(struct gk20a *g)
 {
         return pmgr_send_pmgr_tables_to_pmu(g);
 }
diff --git a/drivers/gpu/nvgpu/pmgr/pmgr.h b/drivers/gpu/nvgpu/pmgr/pmgr.h
index 85b1bbd1..33daf8a9 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgr.h
+++ b/drivers/gpu/nvgpu/pmgr/pmgr.h
@@ -1,7 +1,7 @@
 /*
  * general power device structures & definitions
  *
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -35,7 +35,7 @@ struct pmgr_pmupstate {
 };
 
 u32 pmgr_domain_sw_setup(struct gk20a *g);
-u32 pmgr_domain_pmu_setup(struct gk20a *g);
+int pmgr_domain_pmu_setup(struct gk20a *g);
 int pmgr_pwr_devices_get_current(struct gk20a *g, u32 *val);
 int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val);
 int pmgr_pwr_devices_get_power(struct gk20a *g, u32 *val);
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
index 3398e8df..69c43a01 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -175,11 +175,11 @@ static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g)
         return status;
 }
 
-static u32 pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g)
+static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g)
 {
         struct nv_pmu_pmgr_pwr_device_desc_table *pwr_desc_table;
         struct nv_pmu_pmgr_pwr_device_desc_table_header *ppwr_desc_header;
-        u32 status = 0;
+        int status = 0;
 
         /* Set the BA-device-independent HW information */
         pwr_desc_table = nvgpu_kzalloc(g, sizeof(*pwr_desc_table));
@@ -221,13 +221,13 @@ exit:
         return status;
 }
 
-static u32 pmgr_send_pwr_mointer_to_pmu(struct gk20a *g)
+static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g)
 {
         struct nv_pmu_pmgr_pwr_monitor_pack *pwr_monitor_pack = NULL;
         struct nv_pmu_pmgr_pwr_channel_header *pwr_channel_hdr;
         struct nv_pmu_pmgr_pwr_chrelationship_header *pwr_chrelationship_header;
         u32 max_dmem_size;
-        u32 status = 0;
+        int status = 0;
 
         pwr_monitor_pack = nvgpu_kzalloc(g, sizeof(*pwr_monitor_pack));
         if (!pwr_monitor_pack)
@@ -290,11 +290,11 @@ exit:
         return status;
 }
 
-static u32 pmgr_send_pwr_policy_to_pmu(struct gk20a *g)
+static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g)
 {
         struct nv_pmu_pmgr_pwr_policy_pack *ppwrpack = NULL;
         struct pwr_policy *ppolicy = NULL;
-        u32 status = 0;
+        int status = 0;
         u8 indx;
         u32 max_dmem_size;
 
@@ -479,9 +479,9 @@ exit:
         return status;
 }
 
-u32 pmgr_send_pmgr_tables_to_pmu(struct gk20a *g)
+int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g)
 {
-        u32 status = 0;
+        int status = 0;
 
         status = pmgr_send_i2c_device_topology_to_pmu(g);
 
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.h b/drivers/gpu/nvgpu/pmgr/pmgrpmu.h
index 3cb9eecb..a576f384 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.h
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.h
@@ -1,7 +1,7 @@
 /*
  * general power device control structures & definitions
  *
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,7 +28,7 @@
 #include "pwrdev.h"
 #include "pwrmonitor.h"
 
-u32 pmgr_send_pmgr_tables_to_pmu(struct gk20a *g);
+int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g);
 
 u32 pmgr_pmu_pwr_devices_query_blocking(
                 struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c
index da51ac4b..235629d6 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrdev.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c
@@ -28,7 +28,7 @@
 #include "boardobj/boardobjgrp_e32.h"
 #include "gp106/bios_gp106.h"
 
-static u32 _pwr_device_pmudata_instget(struct gk20a *g,
+static int _pwr_device_pmudata_instget(struct gk20a *g,
                         struct nv_pmu_boardobjgrp *pmuboardobjgrp,
                         struct nv_pmu_boardobj **ppboardobjpmudata,
                         u8 idx)
@@ -51,13 +51,13 @@ static u32 _pwr_device_pmudata_instget(struct gk20a *g,
         return 0;
 }
 
-static u32 _pwr_domains_pmudatainit_ina3221(struct gk20a *g,
+static int _pwr_domains_pmudatainit_ina3221(struct gk20a *g,
                         struct boardobj *board_obj_ptr,
                         struct nv_pmu_boardobj *ppmudata)
 {
         struct nv_pmu_pmgr_pwr_device_desc_ina3221 *ina3221_desc;
         struct pwr_device_ina3221 *ina3221;
-        u32 status = 0;
+        int status = 0;
         u32 indx;
 
         status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
@@ -92,7 +92,7 @@ static struct boardobj *construct_pwr_device(struct gk20a *g,
                         void *pargs, u16 pargs_size, u8 type)
 {
         struct boardobj *board_obj_ptr = NULL;
-        u32 status;
+        int status;
         u32 indx;
         struct pwr_device_ina3221 *pwrdev;
         struct pwr_device_ina3221 *ina3221 = (struct pwr_device_ina3221*)pargs;
@@ -127,10 +127,10 @@ static struct boardobj *construct_pwr_device(struct gk20a *g,
         return board_obj_ptr;
 }
 
-static u32 devinit_get_pwr_device_table(struct gk20a *g,
+static int devinit_get_pwr_device_table(struct gk20a *g,
                         struct pwr_devices *ppwrdeviceobjs)
 {
-        u32 status = 0;
+        int status = 0;
         u8 *pwr_device_table_ptr = NULL;
         u8 *curr_pwr_device_table_ptr = NULL;
         struct boardobj *boardobj;
@@ -284,9 +284,9 @@ done:
         return status;
 }
 
-u32 pmgr_device_sw_setup(struct gk20a *g)
+int pmgr_device_sw_setup(struct gk20a *g)
 {
-        u32 status;
+        int status;
         struct boardobjgrp *pboardobjgrp = NULL;
         struct pwr_devices *ppwrdeviceobjs;
 
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.h b/drivers/gpu/nvgpu/pmgr/pwrdev.h
index 1d9acb89..72cca1fb 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrdev.h
+++ b/drivers/gpu/nvgpu/pmgr/pwrdev.h
@@ -1,7 +1,7 @@
 /*
  * general power device structures & definitions
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -55,6 +55,6 @@ struct pwr_device_ina3221 {
         s16 curr_correct_b;
 } ;
 
-u32 pmgr_device_sw_setup(struct gk20a *g);
+int pmgr_device_sw_setup(struct gk20a *g);
 
 #endif
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
index 5e0cc966..53c7a1c4 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
@@ -28,7 +28,7 @@
 #include "boardobj/boardobjgrp_e32.h"
 #include "gp106/bios_gp106.h"
 
-static u32 _pwr_channel_pmudata_instget(struct gk20a *g,
+static int _pwr_channel_pmudata_instget(struct gk20a *g,
                         struct nv_pmu_boardobjgrp *pmuboardobjgrp,
                         struct nv_pmu_boardobj **ppboardobjpmudata,
                         u8 idx)
@@ -54,7 +54,7 @@ static u32 _pwr_channel_pmudata_instget(struct gk20a *g,
         return 0;
 }
 
-static u32 _pwr_channel_rels_pmudata_instget(struct gk20a *g,
+static int _pwr_channel_rels_pmudata_instget(struct gk20a *g,
                         struct nv_pmu_boardobjgrp *pmuboardobjgrp,
                         struct nv_pmu_boardobj **ppboardobjpmudata,
                         u8 idx)
@@ -105,13 +105,13 @@ static bool _pwr_channel_implements(struct pwr_channel *pchannel,
         return (type == BOARDOBJ_GET_TYPE(pchannel));
 }
 
-static u32 _pwr_domains_pmudatainit_sensor(struct gk20a *g,
+static int _pwr_domains_pmudatainit_sensor(struct gk20a *g,
                                         struct boardobj *board_obj_ptr,
                                         struct nv_pmu_boardobj *ppmudata)
 {
         struct nv_pmu_pmgr_pwr_channel_sensor *pmu_sensor_data;
         struct pwr_channel_sensor *sensor;
-        u32 status = 0;
+        int status = 0;
 
         status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
         if (status) {
@@ -144,7 +144,7 @@ static struct boardobj *construct_pwr_topology(struct gk20a *g,
                                 void *pargs, u16 pargs_size, u8 type)
 {
         struct boardobj *board_obj_ptr = NULL;
-        u32 status;
+        int status;
         struct pwr_channel_sensor *pwrchannel;
         struct pwr_channel_sensor *sensor = (struct pwr_channel_sensor*)pargs;
 
@@ -174,10 +174,10 @@ static struct boardobj *construct_pwr_topology(struct gk20a *g,
         return board_obj_ptr;
 }
 
-static u32 devinit_get_pwr_topology_table(struct gk20a *g,
+static int devinit_get_pwr_topology_table(struct gk20a *g,
                                 struct pmgr_pwr_monitor *ppwrmonitorobjs)
 {
-        u32 status = 0;
+        int status = 0;
         u8 *pwr_topology_table_ptr = NULL;
         u8 *curr_pwr_topology_table_ptr = NULL;
         struct boardobj *boardobj;
@@ -296,9 +296,9 @@ done:
         return status;
 }
 
-u32 pmgr_monitor_sw_setup(struct gk20a *g)
+int pmgr_monitor_sw_setup(struct gk20a *g)
 {
-        u32 status;
+        int status;
         struct boardobjgrp *pboardobjgrp = NULL;
         struct pwr_channel *pchannel;
         struct pmgr_pwr_monitor *ppwrmonitorobjs;
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
index 4f094c3e..da52b08a 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
+++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
@@ -1,7 +1,7 @@
 /*
  * general power channel structures & definitions
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -64,6 +64,6 @@ struct pmgr_pwr_monitor {
         ((struct pwr_channel *)BOARDOBJGRP_OBJ_GET_BY_IDX(                                 \
                 &(g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super), (channel_idx)))
 
-u32 pmgr_monitor_sw_setup(struct gk20a *g);
+int pmgr_monitor_sw_setup(struct gk20a *g);
 
 #endif
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
index 38575f74..13a94e4f 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
@@ -182,7 +182,7 @@ static u32 _pwr_policy_limitarboutputget(struct gk20a *g,
         return _pwr_policy_limitarboutputget_helper(p_limit_arb);
 }
 
-static u32 _pwr_domains_pmudatainit_hw_threshold(struct gk20a *g,
+static int _pwr_domains_pmudatainit_hw_threshold(struct gk20a *g,
                                 struct boardobj *board_obj_ptr,
                                 struct nv_pmu_boardobj *ppmudata)
 {
@@ -190,7 +190,7 @@ static u32 _pwr_domains_pmudatainit_hw_threshold(struct gk20a *g,
         struct pwr_policy_hw_threshold *p_hw_threshold;
         struct pwr_policy *p_pwr_policy;
         struct nv_pmu_pmgr_pwr_policy *pmu_pwr_policy;
-        u32 status = 0;
+        int status = 0;
 
         status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
         if (status) {
@@ -256,7 +256,7 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g,
                         void *pargs, u16 pargs_size, u8 type)
 {
         struct boardobj *board_obj_ptr = NULL;
-        u32 status;
+        int status;
         struct pwr_policy_hw_threshold *pwrpolicyhwthreshold;
         struct pwr_policy *pwrpolicy;
         struct pwr_policy *pwrpolicyparams = (struct pwr_policy*)pargs;
@@ -363,13 +363,13 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g,
         return board_obj_ptr;
 }
 
-static u32 _pwr_policy_construct_WAR_SW_Threshold_policy(struct gk20a *g,
+static int _pwr_policy_construct_WAR_SW_Threshold_policy(struct gk20a *g,
                         struct pmgr_pwr_policy *ppwrpolicyobjs,
                         union pwr_policy_data_union *ppwrpolicydata,
                         u16 pwr_policy_size,
                         u32 obj_index)
 {
-        u32 status = 0;
+        int status = 0;
         struct boardobj *boardobj;
 
         /* WARN policy */
@@ -512,10 +512,10 @@ static inline void devinit_unpack_pwr_policy_entry(
         __UNPACK_FIELD(unpacked, packed, filter_param);
 }
 
-static u32 devinit_get_pwr_policy_table(struct gk20a *g,
+static int devinit_get_pwr_policy_table(struct gk20a *g,
                         struct pmgr_pwr_policy *ppwrpolicyobjs)
 {
-        u32 status = 0;
+        int status = 0;
         u8 *ptr = NULL;
         struct boardobj *boardobj;
         struct pwr_policy_3x_header_struct *packed_hdr;
@@ -707,9 +707,9 @@ done:
         return status;
 }
 
-u32 pmgr_policy_sw_setup(struct gk20a *g)
+int pmgr_policy_sw_setup(struct gk20a *g)
 {
-        u32 status;
+        int status;
         struct boardobjgrp *pboardobjgrp = NULL;
         struct pwr_policy *ppolicy;
         struct pmgr_pwr_policy *ppwrpolicyobjs;
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
index 9bc99bb7..12936a3e 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
@@ -1,7 +1,7 @@
 /*
  * general power channel structures & definitions
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -131,6 +131,6 @@ union pwr_policy_data_union {
 #define PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy)                 \
         ((ppolicy)->num_limit_inputs++)
 
-u32 pmgr_policy_sw_setup(struct gk20a *g);
+int pmgr_policy_sw_setup(struct gk20a *g);
 
 #endif