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Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrpolicy.c')
-rw-r--r--drivers/gpu/nvgpu/pmgr/pwrpolicy.c781
1 files changed, 781 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
new file mode 100644
index 00000000..420eda4f
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
@@ -0,0 +1,781 @@
1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bios.h>
24#include <nvgpu/bug.h>
25
26#include "gk20a/gk20a.h"
27#include "pwrpolicy.h"
28#include "boardobj/boardobjgrp.h"
29#include "boardobj/boardobjgrp_e32.h"
30#include "gp106/bios_gp106.h"
31#include "common/linux/os_linux.h"
32#include "common/linux/platform_gk20a.h"
33
34#define _pwr_policy_limitarboutputget_helper(p_limit_arb) (p_limit_arb)->output
35#define _pwr_policy_limitdeltaapply(limit, delta) ((u32)max(((s32)limit) + (delta), 0))
36
37static u32 _pwr_policy_limitarbinputset_helper(struct gk20a *g,
38 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb,
39 u8 client_idx,
40 u32 limit_value)
41{
42 u8 indx;
43 bool b_found = false;
44 u32 status = 0;
45 u32 output = limit_value;
46
47 for (indx = 0; indx< p_limit_arb->num_inputs; indx++) {
48 if (p_limit_arb->inputs[indx].pwr_policy_idx == client_idx) {
49 p_limit_arb->inputs[indx].limit_value = limit_value;
50 b_found = true;
51 } else if (p_limit_arb->b_arb_max) {
52 output = max(output, p_limit_arb->inputs[indx].limit_value);
53 } else {
54 output = min(output, p_limit_arb->inputs[indx].limit_value);
55 }
56 }
57
58 if (!b_found) {
59 if (p_limit_arb->num_inputs <
60 CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS) {
61 p_limit_arb->inputs[
62 p_limit_arb->num_inputs].pwr_policy_idx = client_idx;
63 p_limit_arb->inputs[
64 p_limit_arb->num_inputs].limit_value = limit_value;
65 p_limit_arb->num_inputs++;
66 } else {
67 nvgpu_err(g, "No entries remaining for clientIdx=%d",
68 client_idx);
69 status = -EINVAL;
70 }
71 }
72
73 if (!status) {
74 p_limit_arb->output = output;
75 }
76
77 return status;
78}
79
80static u32 _pwr_policy_limitid_translate(struct gk20a *g,
81 struct pwr_policy *ppolicy,
82 enum pwr_policy_limit_id limit_id,
83 struct ctrl_pmgr_pwr_policy_limit_arbitration **p_limit_arb,
84 struct ctrl_pmgr_pwr_policy_limit_arbitration **p_limit_arb_sec)
85{
86 u32 status = 0;
87
88 switch (limit_id) {
89 case PWR_POLICY_LIMIT_ID_MIN:
90 *p_limit_arb = &ppolicy->limit_arb_min;
91 break;
92
93 case PWR_POLICY_LIMIT_ID_RATED:
94 *p_limit_arb = &ppolicy->limit_arb_rated;
95
96 if (p_limit_arb_sec != NULL) {
97 *p_limit_arb_sec = &ppolicy->limit_arb_curr;
98 }
99 break;
100
101 case PWR_POLICY_LIMIT_ID_MAX:
102 *p_limit_arb = &ppolicy->limit_arb_max;
103 break;
104
105 case PWR_POLICY_LIMIT_ID_CURR:
106 *p_limit_arb = &ppolicy->limit_arb_curr;
107 break;
108
109 case PWR_POLICY_LIMIT_ID_BATT:
110 *p_limit_arb = &ppolicy->limit_arb_batt;
111 break;
112
113 default:
114 nvgpu_err(g, "Unsupported limitId=%d",
115 limit_id);
116 status = -EINVAL;
117 break;
118 }
119
120 return status;
121}
122
123static u32 _pwr_policy_limitarbinputset(struct gk20a *g,
124 struct pwr_policy *ppolicy,
125 enum pwr_policy_limit_id limit_id,
126 u8 client_idx,
127 u32 limit)
128{
129 u32 status = 0;
130 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb = NULL;
131 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb_sec = NULL;
132
133 status = _pwr_policy_limitid_translate(g,
134 ppolicy,
135 limit_id,
136 &p_limit_arb,
137 &p_limit_arb_sec);
138 if (status) {
139 goto exit;
140 }
141
142 status = _pwr_policy_limitarbinputset_helper(g, p_limit_arb, client_idx, limit);
143 if (status) {
144 nvgpu_err(g,
145 "Error setting client limit value: status=0x%08x, limitId=0x%x, clientIdx=0x%x, limit=%d",
146 status, limit_id, client_idx, limit);
147 goto exit;
148 }
149
150 if (NULL != p_limit_arb_sec) {
151 status = _pwr_policy_limitarbinputset_helper(g, p_limit_arb_sec,
152 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
153 _pwr_policy_limitarboutputget_helper(p_limit_arb));
154 }
155
156exit:
157 return status;
158}
159
160static inline void _pwr_policy_limitarbconstruct(
161 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb,
162 bool b_arb_max)
163{
164 p_limit_arb->num_inputs = 0;
165 p_limit_arb->b_arb_max = b_arb_max;
166}
167
168static u32 _pwr_policy_limitarboutputget(struct gk20a *g,
169 struct pwr_policy *ppolicy,
170 enum pwr_policy_limit_id limit_id)
171{
172 u32 status = 0;
173 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb = NULL;
174
175 status = _pwr_policy_limitid_translate(g,
176 ppolicy,
177 limit_id,
178 &p_limit_arb,
179 NULL);
180 if (status) {
181 return 0;
182 }
183
184 return _pwr_policy_limitarboutputget_helper(p_limit_arb);
185}
186
187static u32 _pwr_domains_pmudatainit_hw_threshold(struct gk20a *g,
188 struct boardobj *board_obj_ptr,
189 struct nv_pmu_boardobj *ppmudata)
190{
191 struct nv_pmu_pmgr_pwr_policy_hw_threshold *pmu_hw_threshold_data;
192 struct pwr_policy_hw_threshold *p_hw_threshold;
193 struct pwr_policy *p_pwr_policy;
194 struct nv_pmu_pmgr_pwr_policy *pmu_pwr_policy;
195 u32 status = 0;
196
197 status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
198 if (status) {
199 nvgpu_err(g,
200 "error updating pmu boardobjgrp for pwr sensor 0x%x",
201 status);
202 status = -ENOMEM;
203 goto done;
204 }
205
206 p_hw_threshold = (struct pwr_policy_hw_threshold *)board_obj_ptr;
207 pmu_hw_threshold_data = (struct nv_pmu_pmgr_pwr_policy_hw_threshold *) ppmudata;
208 pmu_pwr_policy = (struct nv_pmu_pmgr_pwr_policy *) ppmudata;
209 p_pwr_policy = (struct pwr_policy *)&(p_hw_threshold->super.super);
210
211 pmu_pwr_policy->ch_idx = 0;
212 pmu_pwr_policy->limit_unit = p_pwr_policy->limit_unit;
213 pmu_pwr_policy->num_limit_inputs = p_pwr_policy->num_limit_inputs;
214
215 pmu_pwr_policy->limit_min = _pwr_policy_limitdeltaapply(
216 _pwr_policy_limitarboutputget(g, p_pwr_policy,
217 PWR_POLICY_LIMIT_ID_MIN),
218 p_pwr_policy->limit_delta);
219
220 pmu_pwr_policy->limit_max = _pwr_policy_limitdeltaapply(
221 _pwr_policy_limitarboutputget(g, p_pwr_policy,
222 PWR_POLICY_LIMIT_ID_MAX),
223 p_pwr_policy->limit_delta);
224
225 pmu_pwr_policy->limit_curr = _pwr_policy_limitdeltaapply(
226 _pwr_policy_limitarboutputget(g, p_pwr_policy,
227 PWR_POLICY_LIMIT_ID_CURR),
228 p_pwr_policy->limit_delta);
229
230 memcpy(&pmu_pwr_policy->integral, &p_pwr_policy->integral,
231 sizeof(struct ctrl_pmgr_pwr_policy_info_integral));
232
233 pmu_pwr_policy->sample_mult = p_pwr_policy->sample_mult;
234 pmu_pwr_policy->filter_type = p_pwr_policy->filter_type;
235 pmu_pwr_policy->filter_param = p_pwr_policy->filter_param;
236
237 pmu_hw_threshold_data->threshold_idx = p_hw_threshold->threshold_idx;
238 pmu_hw_threshold_data->low_threshold_idx = p_hw_threshold->low_threshold_idx;
239 pmu_hw_threshold_data->b_use_low_threshold = p_hw_threshold->b_use_low_threshold;
240 pmu_hw_threshold_data->low_threshold_value = p_hw_threshold->low_threshold_value;
241
242 if (BOARDOBJ_GET_TYPE(board_obj_ptr) ==
243 CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD) {
244 struct nv_pmu_pmgr_pwr_policy_sw_threshold *pmu_sw_threshold_data;
245 struct pwr_policy_sw_threshold *p_sw_threshold;
246
247 p_sw_threshold = (struct pwr_policy_sw_threshold *)board_obj_ptr;
248 pmu_sw_threshold_data =
249 (struct nv_pmu_pmgr_pwr_policy_sw_threshold *) ppmudata;
250 pmu_sw_threshold_data->event_id =
251 p_sw_threshold->event_id;
252 }
253done:
254 return status;
255}
256
257static struct boardobj *construct_pwr_policy(struct gk20a *g,
258 void *pargs, u16 pargs_size, u8 type)
259{
260 struct boardobj *board_obj_ptr = NULL;
261 u32 status;
262 struct pwr_policy_hw_threshold *pwrpolicyhwthreshold;
263 struct pwr_policy *pwrpolicy;
264 struct pwr_policy *pwrpolicyparams = (struct pwr_policy*)pargs;
265 struct pwr_policy_hw_threshold *hwthreshold = (struct pwr_policy_hw_threshold*)pargs;
266
267 status = boardobj_construct_super(g, &board_obj_ptr,
268 pargs_size, pargs);
269 if (status)
270 return NULL;
271
272 pwrpolicyhwthreshold = (struct pwr_policy_hw_threshold*)board_obj_ptr;
273 pwrpolicy = (struct pwr_policy *)board_obj_ptr;
274
275 gk20a_dbg_fn("min=%u rated=%u max=%u",
276 pwrpolicyparams->limit_min,
277 pwrpolicyparams->limit_rated,
278 pwrpolicyparams->limit_max);
279
280 /* Set Super class interfaces */
281 board_obj_ptr->pmudatainit = _pwr_domains_pmudatainit_hw_threshold;
282
283 pwrpolicy->ch_idx = pwrpolicyparams->ch_idx;
284 pwrpolicy->num_limit_inputs = 0;
285 pwrpolicy->limit_unit = pwrpolicyparams->limit_unit;
286 pwrpolicy->filter_type = (enum ctrl_pmgr_pwr_policy_filter_type)(pwrpolicyparams->filter_type);
287 pwrpolicy->sample_mult = pwrpolicyparams->sample_mult;
288 switch (pwrpolicy->filter_type)
289 {
290 case CTRL_PMGR_PWR_POLICY_FILTER_TYPE_NONE:
291 break;
292
293 case CTRL_PMGR_PWR_POLICY_FILTER_TYPE_BLOCK:
294 pwrpolicy->filter_param.block.block_size =
295 pwrpolicyparams->filter_param.block.block_size;
296 break;
297
298 case CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE:
299 pwrpolicy->filter_param.moving_avg.window_size =
300 pwrpolicyparams->filter_param.moving_avg.window_size;
301 break;
302
303 case CTRL_PMGR_PWR_POLICY_FILTER_TYPE_IIR:
304 pwrpolicy->filter_param.iir.divisor = pwrpolicyparams->filter_param.iir.divisor;
305 break;
306
307 default:
308 nvgpu_err(g, "Error: unrecognized Power Policy filter type: %d",
309 pwrpolicy->filter_type);
310 }
311
312 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_curr, false);
313
314 pwrpolicy->limit_delta = 0;
315
316 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_min, true);
317 status = _pwr_policy_limitarbinputset(g,
318 pwrpolicy,
319 PWR_POLICY_LIMIT_ID_MIN,
320 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
321 pwrpolicyparams->limit_min);
322
323 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_max, false);
324 status = _pwr_policy_limitarbinputset(g,
325 pwrpolicy,
326 PWR_POLICY_LIMIT_ID_MAX,
327 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
328 pwrpolicyparams->limit_max);
329
330 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_rated, false);
331 status = _pwr_policy_limitarbinputset(g,
332 pwrpolicy,
333 PWR_POLICY_LIMIT_ID_RATED,
334 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
335 pwrpolicyparams->limit_rated);
336
337 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_batt, false);
338 status = _pwr_policy_limitarbinputset(g,
339 pwrpolicy,
340 PWR_POLICY_LIMIT_ID_BATT,
341 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
342 ((pwrpolicyparams->limit_batt != 0) ?
343 pwrpolicyparams->limit_batt:
344 CTRL_PMGR_PWR_POLICY_LIMIT_MAX));
345
346 memcpy(&pwrpolicy->integral, &pwrpolicyparams->integral,
347 sizeof(struct ctrl_pmgr_pwr_policy_info_integral));
348
349 pwrpolicyhwthreshold->threshold_idx = hwthreshold->threshold_idx;
350 pwrpolicyhwthreshold->b_use_low_threshold = hwthreshold->b_use_low_threshold;
351 pwrpolicyhwthreshold->low_threshold_idx = hwthreshold->low_threshold_idx;
352 pwrpolicyhwthreshold->low_threshold_value = hwthreshold->low_threshold_value;
353
354 if (type == CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD) {
355 struct pwr_policy_sw_threshold *pwrpolicyswthreshold;
356 struct pwr_policy_sw_threshold *swthreshold =
357 (struct pwr_policy_sw_threshold*)pargs;
358
359 pwrpolicyswthreshold = (struct pwr_policy_sw_threshold*)board_obj_ptr;
360 pwrpolicyswthreshold->event_id = swthreshold->event_id;
361 }
362
363 gk20a_dbg_info(" Done");
364
365 return board_obj_ptr;
366}
367
368static u32 _pwr_policy_construct_WAR_SW_Threshold_policy(struct gk20a *g,
369 struct pmgr_pwr_policy *ppwrpolicyobjs,
370 union pwr_policy_data_union *ppwrpolicydata,
371 u16 pwr_policy_size,
372 u32 obj_index)
373{
374 u32 status = 0;
375 struct boardobj *boardobj;
376
377 /* WARN policy */
378 ppwrpolicydata->pwrpolicy.limit_unit = 0;
379 ppwrpolicydata->pwrpolicy.limit_min = 10000;
380 ppwrpolicydata->pwrpolicy.limit_rated = 100000;
381 ppwrpolicydata->pwrpolicy.limit_max = 100000;
382 ppwrpolicydata->sw_threshold.threshold_idx = 1;
383 ppwrpolicydata->pwrpolicy.filter_type =
384 CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE;
385 ppwrpolicydata->pwrpolicy.sample_mult = 5;
386
387 /* Filled the entry.filterParam value in the filterParam */
388 ppwrpolicydata->pwrpolicy.filter_param.moving_avg.window_size = 10;
389
390 ppwrpolicydata->sw_threshold.event_id = 0x01;
391
392 ppwrpolicydata->boardobj.type = CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD;
393
394 boardobj = construct_pwr_policy(g, ppwrpolicydata,
395 pwr_policy_size, ppwrpolicydata->boardobj.type);
396
397 if (!boardobj) {
398 nvgpu_err(g,
399 "unable to create pwr policy for type %d", ppwrpolicydata->boardobj.type);
400 status = -EINVAL;
401 goto done;
402 }
403
404 status = boardobjgrp_objinsert(&ppwrpolicyobjs->pwr_policies.super,
405 boardobj, obj_index);
406
407 if (status) {
408 nvgpu_err(g,
409 "unable to insert pwr policy boardobj for %d", obj_index);
410 status = -EINVAL;
411 goto done;
412 }
413done:
414 return status;
415}
416
417struct pwr_policy_3x_header_unpacked {
418 u8 version;
419 u8 header_size;
420 u8 table_entry_size;
421 u8 num_table_entries;
422 u16 base_sample_period;
423 u16 min_client_sample_period;
424 u8 table_rel_entry_size;
425 u8 num_table_rel_entries;
426 u8 tgp_policy_idx;
427 u8 rtp_policy_idx;
428 u8 mxm_policy_idx;
429 u8 dnotifier_policy_idx;
430 u32 d2_limit;
431 u32 d3_limit;
432 u32 d4_limit;
433 u32 d5_limit;
434 u8 low_sampling_mult;
435 u8 pwr_tgt_policy_idx;
436 u8 pwr_tgt_floor_policy_idx;
437 u8 sm_bus_policy_idx;
438 u8 table_viol_entry_size;
439 u8 num_table_viol_entries;
440};
441
442#define __UNPACK_FIELD(unpacked, packed, field) \
443 __builtin_memcpy(&unpacked->field, &packed->field, \
444 sizeof(unpacked->field))
445
446static inline void devinit_unpack_pwr_policy_header(
447 struct pwr_policy_3x_header_unpacked *unpacked,
448 struct pwr_policy_3x_header_struct *packed)
449{
450 __UNPACK_FIELD(unpacked, packed, version);
451 __UNPACK_FIELD(unpacked, packed, header_size);
452 __UNPACK_FIELD(unpacked, packed, table_entry_size);
453 __UNPACK_FIELD(unpacked, packed, num_table_entries);
454 __UNPACK_FIELD(unpacked, packed, base_sample_period);
455 __UNPACK_FIELD(unpacked, packed, min_client_sample_period);
456 __UNPACK_FIELD(unpacked, packed, table_rel_entry_size);
457 __UNPACK_FIELD(unpacked, packed, num_table_rel_entries);
458 __UNPACK_FIELD(unpacked, packed, tgp_policy_idx);
459 __UNPACK_FIELD(unpacked, packed, rtp_policy_idx);
460 __UNPACK_FIELD(unpacked, packed, mxm_policy_idx);
461 __UNPACK_FIELD(unpacked, packed, dnotifier_policy_idx);
462 __UNPACK_FIELD(unpacked, packed, d2_limit);
463 __UNPACK_FIELD(unpacked, packed, d3_limit);
464 __UNPACK_FIELD(unpacked, packed, d4_limit);
465 __UNPACK_FIELD(unpacked, packed, d5_limit);
466 __UNPACK_FIELD(unpacked, packed, low_sampling_mult);
467 __UNPACK_FIELD(unpacked, packed, pwr_tgt_policy_idx);
468 __UNPACK_FIELD(unpacked, packed, pwr_tgt_floor_policy_idx);
469 __UNPACK_FIELD(unpacked, packed, sm_bus_policy_idx);
470 __UNPACK_FIELD(unpacked, packed, table_viol_entry_size);
471 __UNPACK_FIELD(unpacked, packed, num_table_viol_entries);
472}
473
474struct pwr_policy_3x_entry_unpacked {
475 u8 flags0;
476 u8 ch_idx;
477 u32 limit_min;
478 u32 limit_rated;
479 u32 limit_max;
480 u32 param0;
481 u32 param1;
482 u32 param2;
483 u32 param3;
484 u32 limit_batt;
485 u8 flags1;
486 u8 past_length;
487 u8 next_length;
488 u16 ratio_min;
489 u16 ratio_max;
490 u8 sample_mult;
491 u32 filter_param;
492};
493
494static inline void devinit_unpack_pwr_policy_entry(
495 struct pwr_policy_3x_entry_unpacked *unpacked,
496 struct pwr_policy_3x_entry_struct *packed)
497{
498 __UNPACK_FIELD(unpacked, packed, flags0);
499 __UNPACK_FIELD(unpacked, packed, ch_idx);
500 __UNPACK_FIELD(unpacked, packed, limit_min);
501 __UNPACK_FIELD(unpacked, packed, limit_rated);
502 __UNPACK_FIELD(unpacked, packed, limit_max);
503 __UNPACK_FIELD(unpacked, packed, param0);
504 __UNPACK_FIELD(unpacked, packed, param1);
505 __UNPACK_FIELD(unpacked, packed, param2);
506 __UNPACK_FIELD(unpacked, packed, param3);
507 __UNPACK_FIELD(unpacked, packed, limit_batt);
508 __UNPACK_FIELD(unpacked, packed, flags1);
509 __UNPACK_FIELD(unpacked, packed, past_length);
510 __UNPACK_FIELD(unpacked, packed, next_length);
511 __UNPACK_FIELD(unpacked, packed, ratio_min);
512 __UNPACK_FIELD(unpacked, packed, ratio_max);
513 __UNPACK_FIELD(unpacked, packed, sample_mult);
514 __UNPACK_FIELD(unpacked, packed, filter_param);
515}
516
517static u32 devinit_get_pwr_policy_table(struct gk20a *g,
518 struct pmgr_pwr_policy *ppwrpolicyobjs)
519{
520 struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
521 u32 status = 0;
522 u8 *ptr = NULL;
523 struct boardobj *boardobj;
524 struct pwr_policy_3x_header_struct *packed_hdr;
525 struct pwr_policy_3x_header_unpacked hdr;
526 u32 index;
527 u32 obj_index = 0;
528 u16 pwr_policy_size;
529 bool integral_control = false;
530 u32 hw_threshold_policy_index = 0;
531 union pwr_policy_data_union pwr_policy_data;
532
533 gk20a_dbg_info("");
534
535 ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
536 g->bios.perf_token, POWER_CAPPING_TABLE);
537 if (ptr == NULL) {
538 status = -EINVAL;
539 goto done;
540 }
541
542 packed_hdr = (struct pwr_policy_3x_header_struct *)ptr;
543
544 if (packed_hdr->version !=
545 VBIOS_POWER_POLICY_VERSION_3X) {
546 status = -EINVAL;
547 goto done;
548 }
549
550 if (packed_hdr->header_size <
551 VBIOS_POWER_POLICY_3X_HEADER_SIZE_25) {
552 status = -EINVAL;
553 goto done;
554 }
555
556 if (packed_hdr->table_entry_size <
557 VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E) {
558 status = -EINVAL;
559 goto done;
560 }
561
562 /* unpack power policy table header */
563 devinit_unpack_pwr_policy_header(&hdr, packed_hdr);
564
565 ptr += (u32)hdr.header_size;
566
567 for (index = 0; index < hdr.num_table_entries;
568 index++, ptr += (u32)hdr.table_entry_size) {
569
570 struct pwr_policy_3x_entry_struct *packed_entry;
571 struct pwr_policy_3x_entry_unpacked entry;
572
573 u8 class_type;
574
575 packed_entry = (struct pwr_policy_3x_entry_struct *)ptr;
576
577 class_type = (u8)BIOS_GET_FIELD(
578 packed_entry->flags0,
579 NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS);
580
581 if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD)
582 continue;
583
584 /* unpack power policy table entry */
585 devinit_unpack_pwr_policy_entry(&entry, packed_entry);
586
587 ppwrpolicyobjs->version =
588 CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X;
589 ppwrpolicyobjs->base_sample_period = hdr.base_sample_period;
590 ppwrpolicyobjs->min_client_sample_period =
591 hdr.min_client_sample_period;
592 ppwrpolicyobjs->low_sampling_mult = hdr.low_sampling_mult;
593
594 ppwrpolicyobjs->policy_idxs[1] = hdr.tgp_policy_idx;
595 ppwrpolicyobjs->policy_idxs[0] = hdr.rtp_policy_idx;
596 ppwrpolicyobjs->policy_idxs[2] = hdr.mxm_policy_idx;
597 ppwrpolicyobjs->policy_idxs[3] = hdr.dnotifier_policy_idx;
598 ppwrpolicyobjs->ext_limits[0].limit = hdr.d2_limit;
599 ppwrpolicyobjs->ext_limits[1].limit = hdr.d3_limit;
600 ppwrpolicyobjs->ext_limits[2].limit = hdr.d4_limit;
601 ppwrpolicyobjs->ext_limits[3].limit = hdr.d5_limit;
602 ppwrpolicyobjs->policy_idxs[4] = hdr.pwr_tgt_policy_idx;
603 ppwrpolicyobjs->policy_idxs[5] = hdr.pwr_tgt_floor_policy_idx;
604 ppwrpolicyobjs->policy_idxs[6] = hdr.sm_bus_policy_idx;
605
606 integral_control = (bool)BIOS_GET_FIELD(entry.flags1,
607 NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL);
608
609 if (integral_control == 0x01) {
610 pwr_policy_data.pwrpolicy.integral.past_sample_count =
611 entry.past_length;
612 pwr_policy_data.pwrpolicy.integral.next_sample_count =
613 entry.next_length;
614 pwr_policy_data.pwrpolicy.integral.ratio_limit_max =
615 entry.ratio_max;
616 pwr_policy_data.pwrpolicy.integral.ratio_limit_min =
617 entry.ratio_min;
618 } else {
619 memset(&(pwr_policy_data.pwrpolicy.integral), 0x0,
620 sizeof(struct ctrl_pmgr_pwr_policy_info_integral));
621 }
622 pwr_policy_data.hw_threshold.threshold_idx = (u8)
623 BIOS_GET_FIELD(entry.param0,
624 NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX);
625
626 pwr_policy_data.hw_threshold.b_use_low_threshold =
627 BIOS_GET_FIELD(entry.param0,
628 NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE);
629
630 if (pwr_policy_data.hw_threshold.b_use_low_threshold) {
631 pwr_policy_data.hw_threshold.low_threshold_idx = (u8)
632 BIOS_GET_FIELD(entry.param0,
633 NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX);
634
635 pwr_policy_data.hw_threshold.low_threshold_value = (u16)
636 BIOS_GET_FIELD(entry.param1,
637 NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL);
638 }
639
640 pwr_policy_size = sizeof(struct pwr_policy_hw_threshold);
641
642 /* Initialize data for the parent class */
643 pwr_policy_data.boardobj.type =
644 CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD;
645 pwr_policy_data.pwrpolicy.ch_idx = entry.ch_idx;
646 pwr_policy_data.pwrpolicy.limit_unit = (u8)
647 BIOS_GET_FIELD(entry.flags0,
648 NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT);
649 pwr_policy_data.pwrpolicy.filter_type = (u8)
650 BIOS_GET_FIELD(entry.flags1,
651 NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE);
652
653 pwr_policy_data.pwrpolicy.limit_min = entry.limit_min;
654 pwr_policy_data.pwrpolicy.limit_rated = entry.limit_rated;
655 pwr_policy_data.pwrpolicy.limit_max = entry.limit_max;
656 pwr_policy_data.pwrpolicy.limit_batt = entry.limit_batt;
657
658 pwr_policy_data.pwrpolicy.sample_mult = (u8)entry.sample_mult;
659
660 /* Filled the entry.filterParam value in the filterParam */
661 pwr_policy_data.pwrpolicy.filter_param.block.block_size = 0;
662 pwr_policy_data.pwrpolicy.filter_param.moving_avg.window_size = 0;
663 pwr_policy_data.pwrpolicy.filter_param.iir.divisor = 0;
664
665 hw_threshold_policy_index |=
666 BIT(pwr_policy_data.hw_threshold.threshold_idx);
667
668 boardobj = construct_pwr_policy(g, &pwr_policy_data,
669 pwr_policy_size, pwr_policy_data.boardobj.type);
670
671 if (!boardobj) {
672 nvgpu_err(g,
673 "unable to create pwr policy for %d type %d",
674 index, pwr_policy_data.boardobj.type);
675 status = -EINVAL;
676 goto done;
677 }
678
679 status = boardobjgrp_objinsert(&ppwrpolicyobjs->pwr_policies.super,
680 boardobj, obj_index);
681
682 if (status) {
683 nvgpu_err(g,
684 "unable to insert pwr policy boardobj for %d",
685 index);
686 status = -EINVAL;
687 goto done;
688 }
689
690 ++obj_index;
691 }
692
693 if (platform->hardcode_sw_threshold) {
694 status = _pwr_policy_construct_WAR_SW_Threshold_policy(g,
695 ppwrpolicyobjs,
696 &pwr_policy_data,
697 sizeof(struct pwr_policy_sw_threshold),
698 obj_index);
699 if (status) {
700 nvgpu_err(g, "unable to construct_WAR_policy");
701 status = -EINVAL;
702 goto done;
703 }
704 ++obj_index;
705 }
706
707done:
708 gk20a_dbg_info(" done status %x", status);
709 return status;
710}
711
712u32 pmgr_policy_sw_setup(struct gk20a *g)
713{
714 u32 status;
715 struct boardobjgrp *pboardobjgrp = NULL;
716 struct pwr_policy *ppolicy;
717 struct pmgr_pwr_policy *ppwrpolicyobjs;
718 u8 indx = 0;
719
720 /* Construct the Super Class and override the Interfaces */
721 status = boardobjgrpconstruct_e32(g,
722 &g->pmgr_pmu.pmgr_policyobjs.pwr_policies);
723 if (status) {
724 nvgpu_err(g,
725 "error creating boardobjgrp for pmgr policy, status - 0x%x",
726 status);
727 goto done;
728 }
729
730 status = boardobjgrpconstruct_e32(g,
731 &g->pmgr_pmu.pmgr_policyobjs.pwr_policy_rels);
732 if (status) {
733 nvgpu_err(g,
734 "error creating boardobjgrp for pmgr policy rels, status - 0x%x",
735 status);
736 goto done;
737 }
738
739 status = boardobjgrpconstruct_e32(g,
740 &g->pmgr_pmu.pmgr_policyobjs.pwr_violations);
741 if (status) {
742 nvgpu_err(g,
743 "error creating boardobjgrp for pmgr violations, status - 0x%x",
744 status);
745 goto done;
746 }
747
748 memset(g->pmgr_pmu.pmgr_policyobjs.policy_idxs, CTRL_PMGR_PWR_POLICY_INDEX_INVALID,
749 sizeof(u8) * CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES);
750
751 /* Initialize external power limit policy indexes to _INVALID/0xFF */
752 for (indx = 0; indx < PWR_POLICY_EXT_POWER_STATE_ID_COUNT; indx++) {
753 g->pmgr_pmu.pmgr_policyobjs.ext_limits[indx].policy_table_idx =
754 CTRL_PMGR_PWR_POLICY_INDEX_INVALID;
755 }
756
757 /* Initialize external power state to _D1 */
758 g->pmgr_pmu.pmgr_policyobjs.ext_power_state = 0xFFFFFFFF;
759
760 ppwrpolicyobjs = &(g->pmgr_pmu.pmgr_policyobjs);
761 pboardobjgrp = &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super);
762
763 status = devinit_get_pwr_policy_table(g, ppwrpolicyobjs);
764 if (status)
765 goto done;
766
767 g->pmgr_pmu.pmgr_policyobjs.b_enabled = true;
768
769 BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct pwr_policy *, ppolicy, indx) {
770 PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy);
771 }
772
773 g->pmgr_pmu.pmgr_policyobjs.global_ceiling.values[0] =
774 0xFF;
775
776 g->pmgr_pmu.pmgr_policyobjs.client_work_item.b_pending = false;
777
778done:
779 gk20a_dbg_info(" done status %x", status);
780 return status;
781}
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 14:09:32 -0400