diff options
Diffstat (limited to 'drivers/gpu/nvgpu/os')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 56 |
2 files changed, 58 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index dfa9edf3..8ad304bd 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2011-2020, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -224,6 +224,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = { | |||
224 | NVGPU_SUPPORT_SCG}, | 224 | NVGPU_SUPPORT_SCG}, |
225 | {NVGPU_GPU_FLAGS_SUPPORT_VPR, | 225 | {NVGPU_GPU_FLAGS_SUPPORT_VPR, |
226 | NVGPU_SUPPORT_VPR}, | 226 | NVGPU_SUPPORT_VPR}, |
227 | {NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE, | ||
228 | NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE}, | ||
227 | }; | 229 | }; |
228 | 230 | ||
229 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) | 231 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index adf40d5d..f7a65f2b 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger/Profiler Driver | 2 | * Tegra GK20A GPU Debugger/Profiler Driver |
3 | * | 3 | * |
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -117,6 +117,10 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
117 | static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | 117 | static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, |
118 | struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args); | 118 | struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args); |
119 | 119 | ||
120 | static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( | ||
121 | struct dbg_session_gk20a *dbg_s, | ||
122 | struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *args); | ||
123 | |||
120 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | 124 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( |
121 | struct dbg_session_gk20a *dbg_s, | 125 | struct dbg_session_gk20a *dbg_s, |
122 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args); | 126 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args); |
@@ -1072,6 +1076,51 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
1072 | return err; | 1076 | return err; |
1073 | } | 1077 | } |
1074 | 1078 | ||
1079 | static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( | ||
1080 | struct dbg_session_gk20a *dbg_s, | ||
1081 | struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *args) | ||
1082 | { | ||
1083 | int err; | ||
1084 | struct gk20a *g = dbg_s->g; | ||
1085 | struct channel_gk20a *ch; | ||
1086 | bool enable = (args->mode == NVGPU_DBG_GPU_CTX_MMU_DEBUG_MODE_ENABLED); | ||
1087 | |||
1088 | nvgpu_log_fn(g, "mode=%u", args->mode); | ||
1089 | |||
1090 | if (args->reserved != 0U) { | ||
1091 | return -EINVAL; | ||
1092 | } | ||
1093 | |||
1094 | if (g->ops.gr.set_mmu_debug_mode == NULL) { | ||
1095 | return -ENOSYS; | ||
1096 | } | ||
1097 | |||
1098 | err = gk20a_busy(g); | ||
1099 | if (err) { | ||
1100 | nvgpu_err(g, "failed to poweron"); | ||
1101 | return err; | ||
1102 | } | ||
1103 | |||
1104 | /* Take the global lock, since we'll be doing global regops */ | ||
1105 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
1106 | |||
1107 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | ||
1108 | if (!ch) { | ||
1109 | nvgpu_err(g, "no bound channel for mmu debug mode"); | ||
1110 | goto clean_up; | ||
1111 | } | ||
1112 | |||
1113 | err = g->ops.gr.set_mmu_debug_mode(g, ch, enable); | ||
1114 | if (err) { | ||
1115 | nvgpu_err(g, "set mmu debug mode failed, err=%d", err); | ||
1116 | } | ||
1117 | |||
1118 | clean_up: | ||
1119 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
1120 | gk20a_idle(g); | ||
1121 | return err; | ||
1122 | } | ||
1123 | |||
1075 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | 1124 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( |
1076 | struct dbg_session_gk20a *dbg_s, | 1125 | struct dbg_session_gk20a *dbg_s, |
1077 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args) | 1126 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args) |
@@ -2030,6 +2079,11 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
2030 | (struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *)buf); | 2079 | (struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *)buf); |
2031 | break; | 2080 | break; |
2032 | 2081 | ||
2082 | case NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE: | ||
2083 | err = nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode(dbg_s, | ||
2084 | (struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *)buf); | ||
2085 | break; | ||
2086 | |||
2033 | default: | 2087 | default: |
2034 | nvgpu_err(g, | 2088 | nvgpu_err(g, |
2035 | "unrecognized dbg gpu ioctl cmd: 0x%x", | 2089 | "unrecognized dbg gpu ioctl cmd: 0x%x", |