diff options
Diffstat (limited to 'drivers/gpu/nvgpu/os')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 55 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_tsg.c | 58 |
3 files changed, 96 insertions, 67 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index fc1f7011..2f013029 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | |||
@@ -1567,56 +1567,6 @@ out: | |||
1567 | return err; | 1567 | return err; |
1568 | } | 1568 | } |
1569 | 1569 | ||
1570 | static int nvgpu_gpu_read_single_sm_error_state(struct gk20a *g, | ||
1571 | struct nvgpu_gpu_read_single_sm_error_state_args *args) | ||
1572 | { | ||
1573 | struct gr_gk20a *gr = &g->gr; | ||
1574 | struct nvgpu_gr_sm_error_state *sm_error_state; | ||
1575 | struct nvgpu_gpu_sm_error_state_record sm_error_state_record; | ||
1576 | u32 sm_id; | ||
1577 | int err = 0; | ||
1578 | |||
1579 | sm_id = args->sm_id; | ||
1580 | if (sm_id >= gr->no_of_sm) | ||
1581 | return -EINVAL; | ||
1582 | |||
1583 | nvgpu_speculation_barrier(); | ||
1584 | |||
1585 | sm_error_state = gr->sm_error_states + sm_id; | ||
1586 | sm_error_state_record.global_esr = | ||
1587 | sm_error_state->hww_global_esr; | ||
1588 | sm_error_state_record.warp_esr = | ||
1589 | sm_error_state->hww_warp_esr; | ||
1590 | sm_error_state_record.warp_esr_pc = | ||
1591 | sm_error_state->hww_warp_esr_pc; | ||
1592 | sm_error_state_record.global_esr_report_mask = | ||
1593 | sm_error_state->hww_global_esr_report_mask; | ||
1594 | sm_error_state_record.warp_esr_report_mask = | ||
1595 | sm_error_state->hww_warp_esr_report_mask; | ||
1596 | |||
1597 | if (args->record_size > 0) { | ||
1598 | size_t write_size = sizeof(*sm_error_state); | ||
1599 | |||
1600 | if (write_size > args->record_size) | ||
1601 | write_size = args->record_size; | ||
1602 | |||
1603 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
1604 | err = copy_to_user((void __user *)(uintptr_t) | ||
1605 | args->record_mem, | ||
1606 | &sm_error_state_record, | ||
1607 | write_size); | ||
1608 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
1609 | if (err) { | ||
1610 | nvgpu_err(g, "copy_to_user failed!"); | ||
1611 | return err; | ||
1612 | } | ||
1613 | |||
1614 | args->record_size = write_size; | ||
1615 | } | ||
1616 | |||
1617 | return 0; | ||
1618 | } | ||
1619 | |||
1620 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | 1570 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) |
1621 | { | 1571 | { |
1622 | struct gk20a_ctrl_priv *priv = filp->private_data; | 1572 | struct gk20a_ctrl_priv *priv = filp->private_data; |
@@ -1925,11 +1875,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
1925 | (struct nvgpu_gpu_set_deterministic_opts_args *)buf); | 1875 | (struct nvgpu_gpu_set_deterministic_opts_args *)buf); |
1926 | break; | 1876 | break; |
1927 | 1877 | ||
1928 | case NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE: | ||
1929 | err = nvgpu_gpu_read_single_sm_error_state(g, | ||
1930 | (struct nvgpu_gpu_read_single_sm_error_state_args *)buf); | ||
1931 | break; | ||
1932 | |||
1933 | default: | 1878 | default: |
1934 | nvgpu_log_info(g, "unrecognized gpu ioctl cmd: 0x%x", cmd); | 1879 | nvgpu_log_info(g, "unrecognized gpu ioctl cmd: 0x%x", cmd); |
1935 | err = -ENOTTY; | 1880 | err = -ENOTTY; |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index ff4fcdca..4ac4fb62 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -35,6 +35,7 @@ | |||
35 | 35 | ||
36 | #include "gk20a/gk20a.h" | 36 | #include "gk20a/gk20a.h" |
37 | #include "gk20a/gr_gk20a.h" | 37 | #include "gk20a/gr_gk20a.h" |
38 | #include "gk20a/tsg_gk20a.h" | ||
38 | #include "gk20a/regops_gk20a.h" | 39 | #include "gk20a/regops_gk20a.h" |
39 | #include "gk20a/dbg_gpu_gk20a.h" | 40 | #include "gk20a/dbg_gpu_gk20a.h" |
40 | #include "os_linux.h" | 41 | #include "os_linux.h" |
@@ -271,20 +272,23 @@ static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state( | |||
271 | u32 sm_id; | 272 | u32 sm_id; |
272 | struct channel_gk20a *ch; | 273 | struct channel_gk20a *ch; |
273 | struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record; | 274 | struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record; |
274 | struct nvgpu_gr_sm_error_state sm_error_state; | 275 | struct nvgpu_tsg_sm_error_state sm_error_state; |
275 | int err = 0; | 276 | int err = 0; |
276 | 277 | ||
277 | /* Not currently supported in the virtual case */ | 278 | /* Not currently supported in the virtual case */ |
278 | if (g->is_virtual) | 279 | if (g->is_virtual) { |
279 | return -ENOSYS; | 280 | return -ENOSYS; |
281 | } | ||
280 | 282 | ||
281 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | 283 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); |
282 | if (!ch) | 284 | if (ch == NULL) { |
283 | return -EINVAL; | 285 | return -EINVAL; |
286 | } | ||
284 | 287 | ||
285 | sm_id = args->sm_id; | 288 | sm_id = args->sm_id; |
286 | if (sm_id >= gr->no_of_sm) | 289 | if (sm_id >= gr->no_of_sm) { |
287 | return -EINVAL; | 290 | return -EINVAL; |
291 | } | ||
288 | 292 | ||
289 | nvgpu_speculation_barrier(); | 293 | nvgpu_speculation_barrier(); |
290 | 294 | ||
@@ -300,13 +304,15 @@ static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state( | |||
300 | args->sm_error_state_record_mem, | 304 | args->sm_error_state_record_mem, |
301 | read_size); | 305 | read_size); |
302 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 306 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
303 | if (err) | 307 | if (err != 0) { |
304 | return -ENOMEM; | 308 | return -ENOMEM; |
309 | } | ||
305 | } | 310 | } |
306 | 311 | ||
307 | err = gk20a_busy(g); | 312 | err = gk20a_busy(g); |
308 | if (err) | 313 | if (err != 0) { |
309 | return err; | 314 | return err; |
315 | } | ||
310 | 316 | ||
311 | sm_error_state.hww_global_esr = | 317 | sm_error_state.hww_global_esr = |
312 | sm_error_state_record.hww_global_esr; | 318 | sm_error_state_record.hww_global_esr; |
@@ -335,18 +341,36 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state( | |||
335 | { | 341 | { |
336 | struct gk20a *g = dbg_s->g; | 342 | struct gk20a *g = dbg_s->g; |
337 | struct gr_gk20a *gr = &g->gr; | 343 | struct gr_gk20a *gr = &g->gr; |
338 | struct nvgpu_gr_sm_error_state *sm_error_state; | 344 | struct nvgpu_tsg_sm_error_state *sm_error_state; |
339 | struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record; | 345 | struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record; |
346 | struct channel_gk20a *ch; | ||
347 | struct tsg_gk20a *tsg; | ||
340 | u32 sm_id; | 348 | u32 sm_id; |
341 | int err = 0; | 349 | int err = 0; |
342 | 350 | ||
351 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | ||
352 | if (ch == NULL) { | ||
353 | return -EINVAL; | ||
354 | } | ||
355 | |||
356 | tsg = tsg_gk20a_from_ch(ch); | ||
357 | if (tsg == NULL) { | ||
358 | nvgpu_err(g, "no valid tsg from ch"); | ||
359 | return -EINVAL; | ||
360 | } | ||
361 | |||
343 | sm_id = args->sm_id; | 362 | sm_id = args->sm_id; |
344 | if (sm_id >= gr->no_of_sm) | 363 | if (sm_id >= gr->no_of_sm) { |
345 | return -EINVAL; | 364 | return -EINVAL; |
365 | } | ||
366 | |||
367 | if (tsg->sm_error_states == NULL) { | ||
368 | return -EINVAL; | ||
369 | } | ||
346 | 370 | ||
347 | nvgpu_speculation_barrier(); | 371 | nvgpu_speculation_barrier(); |
348 | 372 | ||
349 | sm_error_state = gr->sm_error_states + sm_id; | 373 | sm_error_state = tsg->sm_error_states + sm_id; |
350 | sm_error_state_record.hww_global_esr = | 374 | sm_error_state_record.hww_global_esr = |
351 | sm_error_state->hww_global_esr; | 375 | sm_error_state->hww_global_esr; |
352 | sm_error_state_record.hww_warp_esr = | 376 | sm_error_state_record.hww_warp_esr = |
@@ -370,7 +394,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state( | |||
370 | &sm_error_state_record, | 394 | &sm_error_state_record, |
371 | write_size); | 395 | write_size); |
372 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 396 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
373 | if (err) { | 397 | if (err != 0) { |
374 | nvgpu_err(g, "copy_to_user failed!"); | 398 | nvgpu_err(g, "copy_to_user failed!"); |
375 | return err; | 399 | return err; |
376 | } | 400 | } |
@@ -1500,8 +1524,9 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state( | |||
1500 | int err = 0; | 1524 | int err = 0; |
1501 | 1525 | ||
1502 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | 1526 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); |
1503 | if (!ch) | 1527 | if (ch == NULL) { |
1504 | return -EINVAL; | 1528 | return -EINVAL; |
1529 | } | ||
1505 | 1530 | ||
1506 | sm_id = args->sm_id; | 1531 | sm_id = args->sm_id; |
1507 | if (sm_id >= gr->no_of_sm) | 1532 | if (sm_id >= gr->no_of_sm) |
@@ -1510,8 +1535,9 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state( | |||
1510 | nvgpu_speculation_barrier(); | 1535 | nvgpu_speculation_barrier(); |
1511 | 1536 | ||
1512 | err = gk20a_busy(g); | 1537 | err = gk20a_busy(g); |
1513 | if (err) | 1538 | if (err != 0) { |
1514 | return err; | 1539 | return err; |
1540 | } | ||
1515 | 1541 | ||
1516 | err = gr_gk20a_elpg_protected_call(g, | 1542 | err = gr_gk20a_elpg_protected_call(g, |
1517 | g->ops.gr.clear_sm_error_state(g, ch, sm_id)); | 1543 | g->ops.gr.clear_sm_error_state(g, ch, sm_id)); |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c index f7d20f34..6c68ca58 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c | |||
@@ -536,6 +536,57 @@ static int gk20a_tsg_ioctl_get_timeslice(struct gk20a *g, | |||
536 | return 0; | 536 | return 0; |
537 | } | 537 | } |
538 | 538 | ||
539 | static int gk20a_tsg_ioctl_read_single_sm_error_state(struct gk20a *g, | ||
540 | struct tsg_gk20a *tsg, | ||
541 | struct nvgpu_tsg_read_single_sm_error_state_args *args) | ||
542 | { | ||
543 | struct gr_gk20a *gr = &g->gr; | ||
544 | struct nvgpu_tsg_sm_error_state *sm_error_state; | ||
545 | struct nvgpu_tsg_sm_error_state_record sm_error_state_record; | ||
546 | u32 sm_id; | ||
547 | int err = 0; | ||
548 | |||
549 | sm_id = args->sm_id; | ||
550 | if (sm_id >= gr->no_of_sm) | ||
551 | return -EINVAL; | ||
552 | |||
553 | nvgpu_speculation_barrier(); | ||
554 | |||
555 | sm_error_state = tsg->sm_error_states + sm_id; | ||
556 | sm_error_state_record.global_esr = | ||
557 | sm_error_state->hww_global_esr; | ||
558 | sm_error_state_record.warp_esr = | ||
559 | sm_error_state->hww_warp_esr; | ||
560 | sm_error_state_record.warp_esr_pc = | ||
561 | sm_error_state->hww_warp_esr_pc; | ||
562 | sm_error_state_record.global_esr_report_mask = | ||
563 | sm_error_state->hww_global_esr_report_mask; | ||
564 | sm_error_state_record.warp_esr_report_mask = | ||
565 | sm_error_state->hww_warp_esr_report_mask; | ||
566 | |||
567 | if (args->record_size > 0) { | ||
568 | size_t write_size = sizeof(*sm_error_state); | ||
569 | |||
570 | if (write_size > args->record_size) | ||
571 | write_size = args->record_size; | ||
572 | |||
573 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
574 | err = copy_to_user((void __user *)(uintptr_t) | ||
575 | args->record_mem, | ||
576 | &sm_error_state_record, | ||
577 | write_size); | ||
578 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
579 | if (err) { | ||
580 | nvgpu_err(g, "copy_to_user failed!"); | ||
581 | return err; | ||
582 | } | ||
583 | |||
584 | args->record_size = write_size; | ||
585 | } | ||
586 | |||
587 | return 0; | ||
588 | } | ||
589 | |||
539 | long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | 590 | long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, |
540 | unsigned long arg) | 591 | unsigned long arg) |
541 | { | 592 | { |
@@ -670,6 +721,13 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | |||
670 | break; | 721 | break; |
671 | } | 722 | } |
672 | 723 | ||
724 | case NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE: | ||
725 | { | ||
726 | err = gk20a_tsg_ioctl_read_single_sm_error_state(g, tsg, | ||
727 | (struct nvgpu_tsg_read_single_sm_error_state_args *)buf); | ||
728 | break; | ||
729 | } | ||
730 | |||
673 | default: | 731 | default: |
674 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", | 732 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", |
675 | cmd); | 733 | cmd); |