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-rw-r--r--drivers/gpu/nvgpu/os/linux/module.c3
-rw-r--r--drivers/gpu/nvgpu/os/linux/platform_gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c25
-rw-r--r--drivers/gpu/nvgpu/os/linux/sysfs.c28
4 files changed, 35 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c
index 964fc651..a81d837b 100644
--- a/drivers/gpu/nvgpu/os/linux/module.c
+++ b/drivers/gpu/nvgpu/os/linux/module.c
@@ -1200,7 +1200,8 @@ static int nvgpu_read_fuse_overrides(struct gk20a *g)
1200 break; 1200 break;
1201 case GV11B_FUSE_OPT_TPC_DISABLE: 1201 case GV11B_FUSE_OPT_TPC_DISABLE:
1202 if (platform->set_tpc_pg_mask != NULL) 1202 if (platform->set_tpc_pg_mask != NULL)
1203 platform->set_tpc_pg_mask(dev_from_gk20a(g), value); 1203 platform->set_tpc_pg_mask(dev_from_gk20a(g),
1204 value);
1204 break; 1205 break;
1205 default: 1206 default:
1206 nvgpu_err(g, "ignore unknown fuse override %08x", fuse); 1207 nvgpu_err(g, "ignore unknown fuse override %08x", fuse);
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gk20a.h b/drivers/gpu/nvgpu/os/linux/platform_gk20a.h
index 2ddadd2e..adec8607 100644
--- a/drivers/gpu/nvgpu/os/linux/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/os/linux/platform_gk20a.h
@@ -196,8 +196,8 @@ struct gk20a_platform {
196 /* Pre callback is called before frequency change */ 196 /* Pre callback is called before frequency change */
197 void (*prescale)(struct device *dev); 197 void (*prescale)(struct device *dev);
198 198
199 /* Set TPC_PG during probe */ 199 /* Set TPC_PG_MASK during probe */
200 void (*set_tpc_pg_mask)(struct device *dev, u32 tpc_mask); 200 void (*set_tpc_pg_mask)(struct device *dev, u32 tpc_pg_mask);
201 201
202 /* Devfreq governor name. If scaling is enabled, we request 202 /* Devfreq governor name. If scaling is enabled, we request
203 * this governor to be used in scaling */ 203 * this governor to be used in scaling */
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
index 4a94c1cd..ac1958a2 100644
--- a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
@@ -218,26 +218,29 @@ static int gv11b_tegra_suspend(struct device *dev)
218 return 0; 218 return 0;
219} 219}
220 220
221static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_mask) 221static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_pg_mask)
222{ 222{
223 u32 i; 223 u32 i;
224 bool valid = false; 224 bool valid = false;
225 225
226 for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) { 226 for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) {
227 if (tpc_mask == platform->valid_tpc_mask[i]) 227 if (tpc_pg_mask == platform->valid_tpc_mask[i]) {
228 valid = true; 228 valid = true;
229 break;
230 }
229 } 231 }
230 return valid; 232 return valid;
231} 233}
232 234
233static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_mask) 235static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_pg_mask)
234{ 236{
235 struct gk20a_platform *platform = gk20a_get_platform(dev); 237 struct gk20a_platform *platform = gk20a_get_platform(dev);
236 struct gk20a *g = get_gk20a(dev); 238 struct gk20a *g = get_gk20a(dev);
237 239
238 if (is_tpc_mask_valid(platform, tpc_mask)) { 240 if (is_tpc_mask_valid(platform, tpc_pg_mask)) {
239 g->tpc_pg_mask = tpc_mask; 241 g->tpc_pg_mask = tpc_pg_mask;
240 } 242 }
243
241} 244}
242 245
243struct gk20a_platform gv11b_tegra_platform = { 246struct gk20a_platform gv11b_tegra_platform = {
@@ -257,9 +260,15 @@ struct gk20a_platform gv11b_tegra_platform = {
257 .can_tpc_powergate = true, 260 .can_tpc_powergate = true,
258 .valid_tpc_mask[0] = 0x0, 261 .valid_tpc_mask[0] = 0x0,
259 .valid_tpc_mask[1] = 0x1, 262 .valid_tpc_mask[1] = 0x1,
260 .valid_tpc_mask[2] = 0x5, 263 .valid_tpc_mask[2] = 0x2,
261 264 .valid_tpc_mask[3] = 0x4,
262 .set_tpc_pg_mask = gv11b_tegra_set_tpc_pg_mask, 265 .valid_tpc_mask[4] = 0x8,
266 .valid_tpc_mask[5] = 0x5,
267 .valid_tpc_mask[6] = 0x6,
268 .valid_tpc_mask[7] = 0x9,
269 .valid_tpc_mask[8] = 0xa,
270
271 .set_tpc_pg_mask = gv11b_tegra_set_tpc_pg_mask,
263 272
264 .can_slcg = true, 273 .can_slcg = true,
265 .can_blcg = true, 274 .can_blcg = true,
diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c
index 759c12e8..2ab29649 100644
--- a/drivers/gpu/nvgpu/os/linux/sysfs.c
+++ b/drivers/gpu/nvgpu/os/linux/sysfs.c
@@ -788,26 +788,28 @@ static ssize_t force_idle_read(struct device *dev,
788static DEVICE_ATTR(force_idle, ROOTRW, force_idle_read, force_idle_store); 788static DEVICE_ATTR(force_idle, ROOTRW, force_idle_read, force_idle_store);
789#endif 789#endif
790 790
791static ssize_t tpc_pg_mask_read(struct device *dev,
792 struct device_attribute *attr, char *buf)
793{
794 struct gk20a *g = get_gk20a(dev);
795
796 return snprintf(buf, PAGE_SIZE, "%d\n", g->tpc_pg_mask);
797}
798
799static bool is_tpc_mask_valid(struct gk20a *g, u32 tpc_mask) 791static bool is_tpc_mask_valid(struct gk20a *g, u32 tpc_mask)
800{ 792{
801 u32 i; 793 u32 i;
802 bool valid = false; 794 bool valid = false;
803 795
804 for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) { 796 for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) {
805 if (tpc_mask == g->valid_tpc_mask[i]) 797 if (tpc_mask == g->valid_tpc_mask[i]) {
806 valid = true; 798 valid = true;
799 break;
800 }
807 } 801 }
808 return valid; 802 return valid;
809} 803}
810 804
805static ssize_t tpc_pg_mask_read(struct device *dev,
806 struct device_attribute *attr, char *buf)
807{
808 struct gk20a *g = get_gk20a(dev);
809
810 return snprintf(buf, PAGE_SIZE, "%d\n", g->tpc_pg_mask);
811}
812
811static ssize_t tpc_pg_mask_store(struct device *dev, 813static ssize_t tpc_pg_mask_store(struct device *dev,
812 struct device_attribute *attr, const char *buf, size_t count) 814 struct device_attribute *attr, const char *buf, size_t count)
813{ 815{
@@ -817,11 +819,6 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
817 819
818 nvgpu_mutex_acquire(&g->tpc_pg_lock); 820 nvgpu_mutex_acquire(&g->tpc_pg_lock);
819 821
820 if (!g->can_tpc_powergate) {
821 nvgpu_info(g, "TPC-PG not enabled for the platform");
822 goto exit;
823 }
824
825 if (kstrtoul(buf, 10, &val) < 0) { 822 if (kstrtoul(buf, 10, &val) < 0) {
826 nvgpu_err(g, "invalid value"); 823 nvgpu_err(g, "invalid value");
827 nvgpu_mutex_release(&g->tpc_pg_lock); 824 nvgpu_mutex_release(&g->tpc_pg_lock);
@@ -839,6 +836,9 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
839 return -ENODEV; 836 return -ENODEV;
840 } 837 }
841 838
839 /* checking that the value from userspace is within
840 * the possible valid TPC configurations.
841 */
842 if (is_tpc_mask_valid(g, (u32)val)) { 842 if (is_tpc_mask_valid(g, (u32)val)) {
843 g->tpc_pg_mask = val; 843 g->tpc_pg_mask = val;
844 } else { 844 } else {