diff options
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index eadf1f93..ad4dfc0e 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -151,6 +151,10 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s); | |||
151 | static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, | 151 | static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, |
152 | struct file *filp, bool is_profiler); | 152 | struct file *filp, bool is_profiler); |
153 | 153 | ||
154 | static int nvgpu_set_sm_exception_type_mask_locked( | ||
155 | struct dbg_session_gk20a *dbg_s, | ||
156 | u32 exception_mask); | ||
157 | |||
154 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) | 158 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) |
155 | { | 159 | { |
156 | unsigned int mask = 0; | 160 | unsigned int mask = 0; |
@@ -217,6 +221,10 @@ int gk20a_dbg_gpu_dev_release(struct inode *inode, struct file *filp) | |||
217 | nvgpu_kfree(g, prof_obj); | 221 | nvgpu_kfree(g, prof_obj); |
218 | } | 222 | } |
219 | } | 223 | } |
224 | |||
225 | nvgpu_set_sm_exception_type_mask_locked(dbg_s, | ||
226 | NVGPU_SM_EXCEPTION_TYPE_MASK_NONE); | ||
227 | |||
220 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 228 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
221 | 229 | ||
222 | nvgpu_mutex_destroy(&dbg_s->ch_list_lock); | 230 | nvgpu_mutex_destroy(&dbg_s->ch_list_lock); |
@@ -466,6 +474,7 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, | |||
466 | dbg_s->is_profiler = is_profiler; | 474 | dbg_s->is_profiler = is_profiler; |
467 | dbg_s->is_pg_disabled = false; | 475 | dbg_s->is_pg_disabled = false; |
468 | dbg_s->is_timeout_disabled = false; | 476 | dbg_s->is_timeout_disabled = false; |
477 | dbg_s->is_sm_exception_type_mask_set = false; | ||
469 | 478 | ||
470 | nvgpu_cond_init(&dbg_s->dbg_events.wait_queue); | 479 | nvgpu_cond_init(&dbg_s->dbg_events.wait_queue); |
471 | nvgpu_init_list_node(&dbg_s->ch_list); | 480 | nvgpu_init_list_node(&dbg_s->ch_list); |
@@ -478,6 +487,9 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, | |||
478 | dbg_s->dbg_events.events_enabled = false; | 487 | dbg_s->dbg_events.events_enabled = false; |
479 | dbg_s->dbg_events.num_pending_events = 0; | 488 | dbg_s->dbg_events.num_pending_events = 0; |
480 | 489 | ||
490 | nvgpu_set_sm_exception_type_mask_locked(dbg_s, | ||
491 | NVGPU_SM_EXCEPTION_TYPE_MASK_NONE); | ||
492 | |||
481 | return 0; | 493 | return 0; |
482 | 494 | ||
483 | err_destroy_lock: | 495 | err_destroy_lock: |
@@ -1839,6 +1851,57 @@ out: | |||
1839 | return err; | 1851 | return err; |
1840 | } | 1852 | } |
1841 | 1853 | ||
1854 | static int nvgpu_set_sm_exception_type_mask_locked( | ||
1855 | struct dbg_session_gk20a *dbg_s, | ||
1856 | u32 exception_mask) | ||
1857 | { | ||
1858 | struct gk20a *g = dbg_s->g; | ||
1859 | struct gr_gk20a *gr = &g->gr; | ||
1860 | int err = 0; | ||
1861 | |||
1862 | switch (exception_mask) { | ||
1863 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: | ||
1864 | gr->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL; | ||
1865 | if (dbg_s->is_sm_exception_type_mask_set == false) { | ||
1866 | gr->sm_exception_mask_refcount++; | ||
1867 | dbg_s->is_sm_exception_type_mask_set = true; | ||
1868 | } | ||
1869 | break; | ||
1870 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_NONE: | ||
1871 | if (dbg_s->is_sm_exception_type_mask_set) { | ||
1872 | gr->sm_exception_mask_refcount--; | ||
1873 | dbg_s->is_sm_exception_type_mask_set = false; | ||
1874 | } | ||
1875 | if (gr->sm_exception_mask_refcount == 0) | ||
1876 | gr->sm_exception_mask_type = | ||
1877 | NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | ||
1878 | break; | ||
1879 | default: | ||
1880 | nvgpu_err(g, | ||
1881 | "unrecognized dbg sm exception type mask: 0x%x", | ||
1882 | exception_mask); | ||
1883 | err = -EINVAL; | ||
1884 | break; | ||
1885 | } | ||
1886 | |||
1887 | return err; | ||
1888 | } | ||
1889 | |||
1890 | static int nvgpu_dbg_gpu_set_sm_exception_type_mask( | ||
1891 | struct dbg_session_gk20a *dbg_s, | ||
1892 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args) | ||
1893 | { | ||
1894 | int err = 0; | ||
1895 | struct gk20a *g = dbg_s->g; | ||
1896 | |||
1897 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
1898 | err = nvgpu_set_sm_exception_type_mask_locked(dbg_s, | ||
1899 | args->exception_type_mask); | ||
1900 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
1901 | |||
1902 | return err; | ||
1903 | } | ||
1904 | |||
1842 | int gk20a_dbg_gpu_dev_open(struct inode *inode, struct file *filp) | 1905 | int gk20a_dbg_gpu_dev_open(struct inode *inode, struct file *filp) |
1843 | { | 1906 | { |
1844 | struct nvgpu_os_linux *l = container_of(inode->i_cdev, | 1907 | struct nvgpu_os_linux *l = container_of(inode->i_cdev, |
@@ -1994,6 +2057,11 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
1994 | (struct nvgpu_dbg_gpu_profiler_reserve_args *)buf); | 2057 | (struct nvgpu_dbg_gpu_profiler_reserve_args *)buf); |
1995 | break; | 2058 | break; |
1996 | 2059 | ||
2060 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK: | ||
2061 | err = nvgpu_dbg_gpu_set_sm_exception_type_mask(dbg_s, | ||
2062 | (struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *)buf); | ||
2063 | break; | ||
2064 | |||
1997 | default: | 2065 | default: |
1998 | nvgpu_err(g, | 2066 | nvgpu_err(g, |
1999 | "unrecognized dbg gpu ioctl cmd: 0x%x", | 2067 | "unrecognized dbg gpu ioctl cmd: 0x%x", |