summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c')
-rw-r--r--drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c25
1 files changed, 17 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
index 4a94c1cd..ac1958a2 100644
--- a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
@@ -218,26 +218,29 @@ static int gv11b_tegra_suspend(struct device *dev)
218 return 0; 218 return 0;
219} 219}
220 220
221static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_mask) 221static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_pg_mask)
222{ 222{
223 u32 i; 223 u32 i;
224 bool valid = false; 224 bool valid = false;
225 225
226 for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) { 226 for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) {
227 if (tpc_mask == platform->valid_tpc_mask[i]) 227 if (tpc_pg_mask == platform->valid_tpc_mask[i]) {
228 valid = true; 228 valid = true;
229 break;
230 }
229 } 231 }
230 return valid; 232 return valid;
231} 233}
232 234
233static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_mask) 235static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_pg_mask)
234{ 236{
235 struct gk20a_platform *platform = gk20a_get_platform(dev); 237 struct gk20a_platform *platform = gk20a_get_platform(dev);
236 struct gk20a *g = get_gk20a(dev); 238 struct gk20a *g = get_gk20a(dev);
237 239
238 if (is_tpc_mask_valid(platform, tpc_mask)) { 240 if (is_tpc_mask_valid(platform, tpc_pg_mask)) {
239 g->tpc_pg_mask = tpc_mask; 241 g->tpc_pg_mask = tpc_pg_mask;
240 } 242 }
243
241} 244}
242 245
243struct gk20a_platform gv11b_tegra_platform = { 246struct gk20a_platform gv11b_tegra_platform = {
@@ -257,9 +260,15 @@ struct gk20a_platform gv11b_tegra_platform = {
257 .can_tpc_powergate = true, 260 .can_tpc_powergate = true,
258 .valid_tpc_mask[0] = 0x0, 261 .valid_tpc_mask[0] = 0x0,
259 .valid_tpc_mask[1] = 0x1, 262 .valid_tpc_mask[1] = 0x1,
260 .valid_tpc_mask[2] = 0x5, 263 .valid_tpc_mask[2] = 0x2,
261 264 .valid_tpc_mask[3] = 0x4,
262 .set_tpc_pg_mask = gv11b_tegra_set_tpc_pg_mask, 265 .valid_tpc_mask[4] = 0x8,
266 .valid_tpc_mask[5] = 0x5,
267 .valid_tpc_mask[6] = 0x6,
268 .valid_tpc_mask[7] = 0x9,
269 .valid_tpc_mask[8] = 0xa,
270
271 .set_tpc_pg_mask = gv11b_tegra_set_tpc_pg_mask,
263 272
264 .can_slcg = true, 273 .can_slcg = true,
265 .can_blcg = true, 274 .can_blcg = true,