diff options
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/platform_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/platform_gk20a.h | 317 |
1 files changed, 317 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gk20a.h b/drivers/gpu/nvgpu/os/linux/platform_gk20a.h new file mode 100644 index 00000000..9a99b7fe --- /dev/null +++ b/drivers/gpu/nvgpu/os/linux/platform_gk20a.h | |||
@@ -0,0 +1,317 @@ | |||
1 | /* | ||
2 | * GK20A Platform (SoC) Interface | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _GK20A_PLATFORM_H_ | ||
17 | #define _GK20A_PLATFORM_H_ | ||
18 | |||
19 | #include <linux/device.h> | ||
20 | |||
21 | #include <nvgpu/lock.h> | ||
22 | |||
23 | #include "gk20a/gk20a.h" | ||
24 | |||
25 | #define GK20A_CLKS_MAX 4 | ||
26 | |||
27 | struct gk20a; | ||
28 | struct channel_gk20a; | ||
29 | struct gr_ctx_buffer_desc; | ||
30 | struct gk20a_scale_profile; | ||
31 | |||
32 | struct secure_page_buffer { | ||
33 | void (*destroy)(struct gk20a *, struct secure_page_buffer *); | ||
34 | size_t size; | ||
35 | dma_addr_t phys; | ||
36 | size_t used; | ||
37 | }; | ||
38 | |||
39 | struct gk20a_platform { | ||
40 | /* Populated by the gk20a driver before probing the platform. */ | ||
41 | struct gk20a *g; | ||
42 | |||
43 | /* Should be populated at probe. */ | ||
44 | bool can_railgate_init; | ||
45 | |||
46 | /* Should be populated at probe. */ | ||
47 | bool can_elpg_init; | ||
48 | |||
49 | /* Should be populated at probe. */ | ||
50 | bool has_syncpoints; | ||
51 | |||
52 | /* channel limit after which to start aggressive sync destroy */ | ||
53 | unsigned int aggressive_sync_destroy_thresh; | ||
54 | |||
55 | /* flag to set sync destroy aggressiveness */ | ||
56 | bool aggressive_sync_destroy; | ||
57 | |||
58 | /* set if ASPM should be disabled on boot; only makes sense for PCI */ | ||
59 | bool disable_aspm; | ||
60 | |||
61 | /* Set if the platform can unify the small/large address spaces. */ | ||
62 | bool unify_address_spaces; | ||
63 | |||
64 | /* Clock configuration is stored here. Platform probe is responsible | ||
65 | * for filling this data. */ | ||
66 | struct clk *clk[GK20A_CLKS_MAX]; | ||
67 | int num_clks; | ||
68 | int maxmin_clk_id; | ||
69 | |||
70 | #ifdef CONFIG_RESET_CONTROLLER | ||
71 | /* Reset control for device */ | ||
72 | struct reset_control *reset_control; | ||
73 | #endif | ||
74 | |||
75 | /* Delay before rail gated */ | ||
76 | int railgate_delay_init; | ||
77 | |||
78 | /* init value for slowdown factor */ | ||
79 | u8 ldiv_slowdown_factor_init; | ||
80 | |||
81 | /* Second Level Clock Gating: true = enable false = disable */ | ||
82 | bool enable_slcg; | ||
83 | |||
84 | /* Block Level Clock Gating: true = enable flase = disable */ | ||
85 | bool enable_blcg; | ||
86 | |||
87 | /* Engine Level Clock Gating: true = enable flase = disable */ | ||
88 | bool enable_elcg; | ||
89 | |||
90 | /* Should be populated at probe. */ | ||
91 | bool can_slcg; | ||
92 | |||
93 | /* Should be populated at probe. */ | ||
94 | bool can_blcg; | ||
95 | |||
96 | /* Should be populated at probe. */ | ||
97 | bool can_elcg; | ||
98 | |||
99 | /* Engine Level Power Gating: true = enable flase = disable */ | ||
100 | bool enable_elpg; | ||
101 | |||
102 | /* Adaptative ELPG: true = enable flase = disable */ | ||
103 | bool enable_aelpg; | ||
104 | |||
105 | /* PMU Perfmon: true = enable false = disable */ | ||
106 | bool enable_perfmon; | ||
107 | |||
108 | /* Memory System Clock Gating: true = enable flase = disable*/ | ||
109 | bool enable_mscg; | ||
110 | |||
111 | /* Timeout for per-channel watchdog (in mS) */ | ||
112 | u32 ch_wdt_timeout_ms; | ||
113 | |||
114 | /* Disable big page support */ | ||
115 | bool disable_bigpage; | ||
116 | |||
117 | /* | ||
118 | * gk20a_do_idle() API can take GPU either into rail gate or CAR reset | ||
119 | * This flag can be used to force CAR reset case instead of rail gate | ||
120 | */ | ||
121 | bool force_reset_in_do_idle; | ||
122 | |||
123 | /* guest/vm id, needed for IPA to PA transation */ | ||
124 | int vmid; | ||
125 | |||
126 | /* Initialize the platform interface of the gk20a driver. | ||
127 | * | ||
128 | * The platform implementation of this function must | ||
129 | * - set the power and clocks of the gk20a device to a known | ||
130 | * state, and | ||
131 | * - populate the gk20a_platform structure (a pointer to the | ||
132 | * structure can be obtained by calling gk20a_get_platform). | ||
133 | * | ||
134 | * After this function is finished, the driver will initialise | ||
135 | * pm runtime and genpd based on the platform configuration. | ||
136 | */ | ||
137 | int (*probe)(struct device *dev); | ||
138 | |||
139 | /* Second stage initialisation - called once all power management | ||
140 | * initialisations are done. | ||
141 | */ | ||
142 | int (*late_probe)(struct device *dev); | ||
143 | |||
144 | /* Remove device after power management has been done | ||
145 | */ | ||
146 | int (*remove)(struct device *dev); | ||
147 | |||
148 | /* Poweron platform dependencies */ | ||
149 | int (*busy)(struct device *dev); | ||
150 | |||
151 | /* Powerdown platform dependencies */ | ||
152 | void (*idle)(struct device *dev); | ||
153 | |||
154 | /* Preallocated VPR buffer for kernel */ | ||
155 | size_t secure_buffer_size; | ||
156 | struct secure_page_buffer secure_buffer; | ||
157 | |||
158 | /* Device is going to be suspended */ | ||
159 | int (*suspend)(struct device *); | ||
160 | |||
161 | /* Called to turn off the device */ | ||
162 | int (*railgate)(struct device *dev); | ||
163 | |||
164 | /* Called to turn on the device */ | ||
165 | int (*unrailgate)(struct device *dev); | ||
166 | struct nvgpu_mutex railgate_lock; | ||
167 | |||
168 | /* Called to check state of device */ | ||
169 | bool (*is_railgated)(struct device *dev); | ||
170 | |||
171 | /* get supported frequency list */ | ||
172 | int (*get_clk_freqs)(struct device *pdev, | ||
173 | unsigned long **freqs, int *num_freqs); | ||
174 | |||
175 | /* clk related supported functions */ | ||
176 | long (*clk_round_rate)(struct device *dev, | ||
177 | unsigned long rate); | ||
178 | |||
179 | /* Called to register GPCPLL with common clk framework */ | ||
180 | int (*clk_register)(struct gk20a *g); | ||
181 | |||
182 | /* platform specific scale init quirks */ | ||
183 | void (*initscale)(struct device *dev); | ||
184 | |||
185 | /* Postscale callback is called after frequency change */ | ||
186 | void (*postscale)(struct device *dev, | ||
187 | unsigned long freq); | ||
188 | |||
189 | /* Pre callback is called before frequency change */ | ||
190 | void (*prescale)(struct device *dev); | ||
191 | |||
192 | /* Devfreq governor name. If scaling is enabled, we request | ||
193 | * this governor to be used in scaling */ | ||
194 | const char *devfreq_governor; | ||
195 | |||
196 | /* Quality of service notifier callback. If this is set, the scaling | ||
197 | * routines will register a callback to Qos. Each time we receive | ||
198 | * a new value, this callback gets called. */ | ||
199 | int (*qos_notify)(struct notifier_block *nb, | ||
200 | unsigned long n, void *p); | ||
201 | |||
202 | /* Called as part of debug dump. If the gpu gets hung, this function | ||
203 | * is responsible for delivering all necessary debug data of other | ||
204 | * hw units which may interact with the gpu without direct supervision | ||
205 | * of the CPU. | ||
206 | */ | ||
207 | void (*dump_platform_dependencies)(struct device *dev); | ||
208 | |||
209 | /* Defined when SMMU stage-2 is enabled, and we need to use physical | ||
210 | * addresses (not IPA). This is the case for GV100 nvlink in HV+L | ||
211 | * configuration, when dGPU is in pass-through mode. | ||
212 | */ | ||
213 | u64 (*phys_addr)(struct gk20a *g, u64 ipa); | ||
214 | |||
215 | /* Callbacks to assert/deassert GPU reset */ | ||
216 | int (*reset_assert)(struct device *dev); | ||
217 | int (*reset_deassert)(struct device *dev); | ||
218 | struct clk *clk_reset; | ||
219 | struct dvfs_rail *gpu_rail; | ||
220 | |||
221 | bool virtual_dev; | ||
222 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | ||
223 | void *vgpu_priv; | ||
224 | #endif | ||
225 | /* source frequency for ptimer in hz */ | ||
226 | u32 ptimer_src_freq; | ||
227 | |||
228 | #ifdef CONFIG_NVGPU_SUPPORT_CDE | ||
229 | bool has_cde; | ||
230 | #endif | ||
231 | |||
232 | /* soc name for finding firmware files */ | ||
233 | const char *soc_name; | ||
234 | |||
235 | /* false if vidmem aperture actually points to sysmem */ | ||
236 | bool honors_aperture; | ||
237 | /* unified or split memory with separate vidmem? */ | ||
238 | bool unified_memory; | ||
239 | |||
240 | /* | ||
241 | * DMA mask for Linux (both coh and non-coh). If not set defaults to | ||
242 | * 0x3ffffffff (i.e a 34 bit mask). | ||
243 | */ | ||
244 | u64 dma_mask; | ||
245 | |||
246 | /* minimum supported VBIOS version */ | ||
247 | u32 vbios_min_version; | ||
248 | |||
249 | /* true if we run preos microcode on this board */ | ||
250 | bool run_preos; | ||
251 | |||
252 | /* true if we need to program sw threshold for | ||
253 | * power limits | ||
254 | */ | ||
255 | bool hardcode_sw_threshold; | ||
256 | |||
257 | /* i2c device index, port and address for INA3221 */ | ||
258 | u32 ina3221_dcb_index; | ||
259 | u32 ina3221_i2c_address; | ||
260 | u32 ina3221_i2c_port; | ||
261 | |||
262 | /* stream id to use */ | ||
263 | u32 ltc_streamid; | ||
264 | |||
265 | /* scaling rate */ | ||
266 | unsigned long cached_rate; | ||
267 | }; | ||
268 | |||
269 | static inline struct gk20a_platform *gk20a_get_platform( | ||
270 | struct device *dev) | ||
271 | { | ||
272 | return (struct gk20a_platform *)dev_get_drvdata(dev); | ||
273 | } | ||
274 | |||
275 | #ifdef CONFIG_TEGRA_GK20A | ||
276 | extern struct gk20a_platform gm20b_tegra_platform; | ||
277 | extern struct gk20a_platform gp10b_tegra_platform; | ||
278 | extern struct gk20a_platform gv11b_tegra_platform; | ||
279 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | ||
280 | extern struct gk20a_platform vgpu_tegra_platform; | ||
281 | extern struct gk20a_platform gv11b_vgpu_tegra_platform; | ||
282 | #endif | ||
283 | #endif | ||
284 | |||
285 | int gk20a_tegra_busy(struct device *dev); | ||
286 | void gk20a_tegra_idle(struct device *dev); | ||
287 | void gk20a_tegra_debug_dump(struct device *pdev); | ||
288 | |||
289 | static inline struct gk20a *get_gk20a(struct device *dev) | ||
290 | { | ||
291 | return gk20a_get_platform(dev)->g; | ||
292 | } | ||
293 | static inline struct gk20a *gk20a_from_dev(struct device *dev) | ||
294 | { | ||
295 | if (!dev) | ||
296 | return NULL; | ||
297 | |||
298 | return ((struct gk20a_platform *)dev_get_drvdata(dev))->g; | ||
299 | } | ||
300 | static inline bool gk20a_gpu_is_virtual(struct device *dev) | ||
301 | { | ||
302 | struct gk20a_platform *platform = dev_get_drvdata(dev); | ||
303 | |||
304 | return platform->virtual_dev; | ||
305 | } | ||
306 | |||
307 | static inline int support_gk20a_pmu(struct device *dev) | ||
308 | { | ||
309 | if (IS_ENABLED(CONFIG_GK20A_PMU)) { | ||
310 | /* gPMU is not supported for vgpu */ | ||
311 | return !gk20a_gpu_is_virtual(dev); | ||
312 | } | ||
313 | |||
314 | return 0; | ||
315 | } | ||
316 | |||
317 | #endif | ||