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path: root/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
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Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/ioctl_dbg.c')
-rw-r--r--drivers/gpu/nvgpu/os/linux/ioctl_dbg.c50
1 files changed, 38 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index ff4fcdca..4ac4fb62 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -35,6 +35,7 @@
35 35
36#include "gk20a/gk20a.h" 36#include "gk20a/gk20a.h"
37#include "gk20a/gr_gk20a.h" 37#include "gk20a/gr_gk20a.h"
38#include "gk20a/tsg_gk20a.h"
38#include "gk20a/regops_gk20a.h" 39#include "gk20a/regops_gk20a.h"
39#include "gk20a/dbg_gpu_gk20a.h" 40#include "gk20a/dbg_gpu_gk20a.h"
40#include "os_linux.h" 41#include "os_linux.h"
@@ -271,20 +272,23 @@ static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state(
271 u32 sm_id; 272 u32 sm_id;
272 struct channel_gk20a *ch; 273 struct channel_gk20a *ch;
273 struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record; 274 struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record;
274 struct nvgpu_gr_sm_error_state sm_error_state; 275 struct nvgpu_tsg_sm_error_state sm_error_state;
275 int err = 0; 276 int err = 0;
276 277
277 /* Not currently supported in the virtual case */ 278 /* Not currently supported in the virtual case */
278 if (g->is_virtual) 279 if (g->is_virtual) {
279 return -ENOSYS; 280 return -ENOSYS;
281 }
280 282
281 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); 283 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
282 if (!ch) 284 if (ch == NULL) {
283 return -EINVAL; 285 return -EINVAL;
286 }
284 287
285 sm_id = args->sm_id; 288 sm_id = args->sm_id;
286 if (sm_id >= gr->no_of_sm) 289 if (sm_id >= gr->no_of_sm) {
287 return -EINVAL; 290 return -EINVAL;
291 }
288 292
289 nvgpu_speculation_barrier(); 293 nvgpu_speculation_barrier();
290 294
@@ -300,13 +304,15 @@ static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state(
300 args->sm_error_state_record_mem, 304 args->sm_error_state_record_mem,
301 read_size); 305 read_size);
302 nvgpu_mutex_release(&g->dbg_sessions_lock); 306 nvgpu_mutex_release(&g->dbg_sessions_lock);
303 if (err) 307 if (err != 0) {
304 return -ENOMEM; 308 return -ENOMEM;
309 }
305 } 310 }
306 311
307 err = gk20a_busy(g); 312 err = gk20a_busy(g);
308 if (err) 313 if (err != 0) {
309 return err; 314 return err;
315 }
310 316
311 sm_error_state.hww_global_esr = 317 sm_error_state.hww_global_esr =
312 sm_error_state_record.hww_global_esr; 318 sm_error_state_record.hww_global_esr;
@@ -335,18 +341,36 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
335{ 341{
336 struct gk20a *g = dbg_s->g; 342 struct gk20a *g = dbg_s->g;
337 struct gr_gk20a *gr = &g->gr; 343 struct gr_gk20a *gr = &g->gr;
338 struct nvgpu_gr_sm_error_state *sm_error_state; 344 struct nvgpu_tsg_sm_error_state *sm_error_state;
339 struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record; 345 struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record;
346 struct channel_gk20a *ch;
347 struct tsg_gk20a *tsg;
340 u32 sm_id; 348 u32 sm_id;
341 int err = 0; 349 int err = 0;
342 350
351 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
352 if (ch == NULL) {
353 return -EINVAL;
354 }
355
356 tsg = tsg_gk20a_from_ch(ch);
357 if (tsg == NULL) {
358 nvgpu_err(g, "no valid tsg from ch");
359 return -EINVAL;
360 }
361
343 sm_id = args->sm_id; 362 sm_id = args->sm_id;
344 if (sm_id >= gr->no_of_sm) 363 if (sm_id >= gr->no_of_sm) {
345 return -EINVAL; 364 return -EINVAL;
365 }
366
367 if (tsg->sm_error_states == NULL) {
368 return -EINVAL;
369 }
346 370
347 nvgpu_speculation_barrier(); 371 nvgpu_speculation_barrier();
348 372
349 sm_error_state = gr->sm_error_states + sm_id; 373 sm_error_state = tsg->sm_error_states + sm_id;
350 sm_error_state_record.hww_global_esr = 374 sm_error_state_record.hww_global_esr =
351 sm_error_state->hww_global_esr; 375 sm_error_state->hww_global_esr;
352 sm_error_state_record.hww_warp_esr = 376 sm_error_state_record.hww_warp_esr =
@@ -370,7 +394,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state(
370 &sm_error_state_record, 394 &sm_error_state_record,
371 write_size); 395 write_size);
372 nvgpu_mutex_release(&g->dbg_sessions_lock); 396 nvgpu_mutex_release(&g->dbg_sessions_lock);
373 if (err) { 397 if (err != 0) {
374 nvgpu_err(g, "copy_to_user failed!"); 398 nvgpu_err(g, "copy_to_user failed!");
375 return err; 399 return err;
376 } 400 }
@@ -1500,8 +1524,9 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state(
1500 int err = 0; 1524 int err = 0;
1501 1525
1502 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); 1526 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
1503 if (!ch) 1527 if (ch == NULL) {
1504 return -EINVAL; 1528 return -EINVAL;
1529 }
1505 1530
1506 sm_id = args->sm_id; 1531 sm_id = args->sm_id;
1507 if (sm_id >= gr->no_of_sm) 1532 if (sm_id >= gr->no_of_sm)
@@ -1510,8 +1535,9 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state(
1510 nvgpu_speculation_barrier(); 1535 nvgpu_speculation_barrier();
1511 1536
1512 err = gk20a_busy(g); 1537 err = gk20a_busy(g);
1513 if (err) 1538 if (err != 0) {
1514 return err; 1539 return err;
1540 }
1515 1541
1516 err = gr_gk20a_elpg_protected_call(g, 1542 err = gr_gk20a_elpg_protected_call(g,
1517 g->ops.gr.clear_sm_error_state(g, ch, sm_id)); 1543 g->ops.gr.clear_sm_error_state(g, ch, sm_id));