diff options
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/debug_clk.c')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/debug_clk.c | 271 |
1 files changed, 271 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk.c b/drivers/gpu/nvgpu/os/linux/debug_clk.c new file mode 100644 index 00000000..2484d44b --- /dev/null +++ b/drivers/gpu/nvgpu/os/linux/debug_clk.c | |||
@@ -0,0 +1,271 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2017 NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * This software is licensed under the terms of the GNU General Public | ||
5 | * License version 2, as published by the Free Software Foundation, and | ||
6 | * may be copied, distributed, and modified under those terms. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, | ||
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
11 | * GNU General Public License for more details. | ||
12 | * | ||
13 | */ | ||
14 | |||
15 | #include <linux/uaccess.h> | ||
16 | #include <linux/debugfs.h> | ||
17 | #include <linux/seq_file.h> | ||
18 | |||
19 | #include "gm20b/clk_gm20b.h" | ||
20 | #include "os_linux.h" | ||
21 | #include "platform_gk20a.h" | ||
22 | |||
23 | static int rate_get(void *data, u64 *val) | ||
24 | { | ||
25 | struct gk20a *g = (struct gk20a *)data; | ||
26 | struct clk_gk20a *clk = &g->clk; | ||
27 | |||
28 | *val = (u64)rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
29 | return 0; | ||
30 | } | ||
31 | static int rate_set(void *data, u64 val) | ||
32 | { | ||
33 | struct gk20a *g = (struct gk20a *)data; | ||
34 | return g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, (u32)val); | ||
35 | } | ||
36 | DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n"); | ||
37 | |||
38 | static int pll_reg_show(struct seq_file *s, void *data) | ||
39 | { | ||
40 | struct gk20a *g = s->private; | ||
41 | struct nvgpu_clk_pll_debug_data d; | ||
42 | u32 reg, m, n, pl, f; | ||
43 | int err = 0; | ||
44 | |||
45 | if (g->ops.clk.get_pll_debug_data) { | ||
46 | err = g->ops.clk.get_pll_debug_data(g, &d); | ||
47 | if (err) | ||
48 | return err; | ||
49 | } else { | ||
50 | return -EINVAL; | ||
51 | } | ||
52 | |||
53 | seq_printf(s, "bypassctrl = %s, ", | ||
54 | d.trim_sys_bypassctrl_val ? "bypass" : "vco"); | ||
55 | seq_printf(s, "sel_vco = %s, ", | ||
56 | d.trim_sys_sel_vco_val ? "vco" : "bypass"); | ||
57 | |||
58 | seq_printf(s, "cfg = 0x%x : %s : %s : %s\n", d.trim_sys_gpcpll_cfg_val, | ||
59 | d.trim_sys_gpcpll_cfg_enabled ? "enabled" : "disabled", | ||
60 | d.trim_sys_gpcpll_cfg_locked ? "locked" : "unlocked", | ||
61 | d.trim_sys_gpcpll_cfg_sync_on ? "sync_on" : "sync_off"); | ||
62 | |||
63 | reg = d.trim_sys_gpcpll_coeff_val; | ||
64 | m = d.trim_sys_gpcpll_coeff_mdiv; | ||
65 | n = d.trim_sys_gpcpll_coeff_ndiv; | ||
66 | pl = d.trim_sys_gpcpll_coeff_pldiv; | ||
67 | f = g->clk.gpc_pll.clk_in * n / (m * nvgpu_pl_to_div(pl)); | ||
68 | seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl); | ||
69 | seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2); | ||
70 | |||
71 | seq_printf(s, "dvfs0 = 0x%x : d = %u : dmax = %u : doffs = %u\n", | ||
72 | d.trim_sys_gpcpll_dvfs0_val, | ||
73 | d.trim_sys_gpcpll_dvfs0_dfs_coeff, | ||
74 | d.trim_sys_gpcpll_dvfs0_dfs_det_max, | ||
75 | d.trim_sys_gpcpll_dvfs0_dfs_dc_offset); | ||
76 | |||
77 | return 0; | ||
78 | } | ||
79 | |||
80 | static int pll_reg_open(struct inode *inode, struct file *file) | ||
81 | { | ||
82 | return single_open(file, pll_reg_show, inode->i_private); | ||
83 | } | ||
84 | |||
85 | static const struct file_operations pll_reg_fops = { | ||
86 | .open = pll_reg_open, | ||
87 | .read = seq_read, | ||
88 | .llseek = seq_lseek, | ||
89 | .release = single_release, | ||
90 | }; | ||
91 | |||
92 | static int pll_reg_raw_show(struct seq_file *s, void *data) | ||
93 | { | ||
94 | struct gk20a *g = s->private; | ||
95 | struct nvgpu_clk_pll_debug_data d; | ||
96 | u32 reg; | ||
97 | int err = 0; | ||
98 | |||
99 | if (g->ops.clk.get_pll_debug_data) { | ||
100 | err = g->ops.clk.get_pll_debug_data(g, &d); | ||
101 | if (err) | ||
102 | return err; | ||
103 | } else { | ||
104 | return -EINVAL; | ||
105 | } | ||
106 | |||
107 | seq_puts(s, "GPCPLL REGISTERS:\n"); | ||
108 | for (reg = d.trim_sys_gpcpll_cfg_reg; | ||
109 | reg <= d.trim_sys_gpcpll_dvfs2_reg; | ||
110 | reg += sizeof(u32)) | ||
111 | seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); | ||
112 | |||
113 | seq_puts(s, "\nGPC CLK OUT REGISTERS:\n"); | ||
114 | |||
115 | seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_sel_vco_reg, | ||
116 | d.trim_sys_sel_vco_val); | ||
117 | seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_gpc2clk_out_reg, | ||
118 | d.trim_sys_gpc2clk_out_val); | ||
119 | seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_bypassctrl_reg, | ||
120 | d.trim_sys_bypassctrl_val); | ||
121 | |||
122 | return 0; | ||
123 | } | ||
124 | |||
125 | static int pll_reg_raw_open(struct inode *inode, struct file *file) | ||
126 | { | ||
127 | return single_open(file, pll_reg_raw_show, inode->i_private); | ||
128 | } | ||
129 | |||
130 | static ssize_t pll_reg_raw_write(struct file *file, | ||
131 | const char __user *userbuf, size_t count, loff_t *ppos) | ||
132 | { | ||
133 | struct gk20a *g = file->f_path.dentry->d_inode->i_private; | ||
134 | char buf[80]; | ||
135 | u32 reg, val; | ||
136 | int err = 0; | ||
137 | |||
138 | if (sizeof(buf) <= count) | ||
139 | return -EINVAL; | ||
140 | |||
141 | if (copy_from_user(buf, userbuf, count)) | ||
142 | return -EFAULT; | ||
143 | |||
144 | /* terminate buffer and trim - white spaces may be appended | ||
145 | * at the end when invoked from shell command line */ | ||
146 | buf[count] = '\0'; | ||
147 | strim(buf); | ||
148 | |||
149 | if (sscanf(buf, "[0x%x] = 0x%x", ®, &val) != 2) | ||
150 | return -EINVAL; | ||
151 | |||
152 | if (g->ops.clk.pll_reg_write(g, reg, val)) | ||
153 | err = g->ops.clk.pll_reg_write(g, reg, val); | ||
154 | else | ||
155 | err = -EINVAL; | ||
156 | |||
157 | return err; | ||
158 | } | ||
159 | |||
160 | static const struct file_operations pll_reg_raw_fops = { | ||
161 | .open = pll_reg_raw_open, | ||
162 | .read = seq_read, | ||
163 | .write = pll_reg_raw_write, | ||
164 | .llseek = seq_lseek, | ||
165 | .release = single_release, | ||
166 | }; | ||
167 | |||
168 | static int monitor_get(void *data, u64 *val) | ||
169 | { | ||
170 | struct gk20a *g = (struct gk20a *)data; | ||
171 | int err = 0; | ||
172 | |||
173 | if (g->ops.clk.get_gpcclk_clock_counter) | ||
174 | err = g->ops.clk.get_gpcclk_clock_counter(&g->clk, val); | ||
175 | else | ||
176 | err = -EINVAL; | ||
177 | |||
178 | return err; | ||
179 | } | ||
180 | DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n"); | ||
181 | |||
182 | static int voltage_get(void *data, u64 *val) | ||
183 | { | ||
184 | struct gk20a *g = (struct gk20a *)data; | ||
185 | int err = 0; | ||
186 | |||
187 | if (g->ops.clk.get_voltage) | ||
188 | err = g->ops.clk.get_voltage(&g->clk, val); | ||
189 | else | ||
190 | err = -EINVAL; | ||
191 | |||
192 | return err; | ||
193 | } | ||
194 | DEFINE_SIMPLE_ATTRIBUTE(voltage_fops, voltage_get, NULL, "%llu\n"); | ||
195 | |||
196 | static int pll_param_show(struct seq_file *s, void *data) | ||
197 | { | ||
198 | struct pll_parms *gpc_pll_params = gm20b_get_gpc_pll_parms(); | ||
199 | |||
200 | seq_printf(s, "ADC offs = %d uV, ADC slope = %d uV, VCO ctrl = 0x%x\n", | ||
201 | gpc_pll_params->uvdet_offs, gpc_pll_params->uvdet_slope, | ||
202 | gpc_pll_params->vco_ctrl); | ||
203 | return 0; | ||
204 | } | ||
205 | |||
206 | static int pll_param_open(struct inode *inode, struct file *file) | ||
207 | { | ||
208 | return single_open(file, pll_param_show, inode->i_private); | ||
209 | } | ||
210 | |||
211 | static const struct file_operations pll_param_fops = { | ||
212 | .open = pll_param_open, | ||
213 | .read = seq_read, | ||
214 | .llseek = seq_lseek, | ||
215 | .release = single_release, | ||
216 | }; | ||
217 | |||
218 | int gm20b_clk_init_debugfs(struct gk20a *g) | ||
219 | { | ||
220 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
221 | struct dentry *d; | ||
222 | |||
223 | if (!l->debugfs) | ||
224 | return -EINVAL; | ||
225 | |||
226 | d = debugfs_create_file( | ||
227 | "rate", S_IRUGO|S_IWUSR, l->debugfs, g, &rate_fops); | ||
228 | if (!d) | ||
229 | goto err_out; | ||
230 | |||
231 | d = debugfs_create_file( | ||
232 | "pll_reg", S_IRUGO, l->debugfs, g, &pll_reg_fops); | ||
233 | if (!d) | ||
234 | goto err_out; | ||
235 | |||
236 | d = debugfs_create_file("pll_reg_raw", | ||
237 | S_IRUGO, l->debugfs, g, &pll_reg_raw_fops); | ||
238 | if (!d) | ||
239 | goto err_out; | ||
240 | |||
241 | d = debugfs_create_file( | ||
242 | "monitor", S_IRUGO, l->debugfs, g, &monitor_fops); | ||
243 | if (!d) | ||
244 | goto err_out; | ||
245 | |||
246 | d = debugfs_create_file( | ||
247 | "voltage", S_IRUGO, l->debugfs, g, &voltage_fops); | ||
248 | if (!d) | ||
249 | goto err_out; | ||
250 | |||
251 | d = debugfs_create_file( | ||
252 | "pll_param", S_IRUGO, l->debugfs, g, &pll_param_fops); | ||
253 | if (!d) | ||
254 | goto err_out; | ||
255 | |||
256 | d = debugfs_create_u32("pll_na_mode", S_IRUGO, l->debugfs, | ||
257 | (u32 *)&g->clk.gpc_pll.mode); | ||
258 | if (!d) | ||
259 | goto err_out; | ||
260 | |||
261 | d = debugfs_create_u32("fmax2x_at_vmin_safe_t", S_IRUGO, | ||
262 | l->debugfs, (u32 *)&g->clk.dvfs_safe_max_freq); | ||
263 | if (!d) | ||
264 | goto err_out; | ||
265 | |||
266 | return 0; | ||
267 | |||
268 | err_out: | ||
269 | pr_err("%s: Failed to make debugfs node\n", __func__); | ||
270 | return -ENOMEM; | ||
271 | } | ||