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path: root/drivers/gpu/nvgpu/os/linux/ctxsw_trace.c
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Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/ctxsw_trace.c')
-rw-r--r--drivers/gpu/nvgpu/os/linux/ctxsw_trace.c37
1 files changed, 26 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ctxsw_trace.c b/drivers/gpu/nvgpu/os/linux/ctxsw_trace.c
index a335988a..a8f5f815 100644
--- a/drivers/gpu/nvgpu/os/linux/ctxsw_trace.c
+++ b/drivers/gpu/nvgpu/os/linux/ctxsw_trace.c
@@ -20,9 +20,11 @@
20#include <linux/poll.h> 20#include <linux/poll.h>
21#include <trace/events/gk20a.h> 21#include <trace/events/gk20a.h>
22#include <uapi/linux/nvgpu.h> 22#include <uapi/linux/nvgpu.h>
23#include <nvgpu/ctxsw_trace.h>
23 24
24#include "gk20a/gk20a.h" 25#include "gk20a/gk20a.h"
25#include "gk20a/gr_gk20a.h" 26#include "gk20a/gr_gk20a.h"
27#include "gk20a/fecs_trace_gk20a.h"
26 28
27#include <nvgpu/kmem.h> 29#include <nvgpu/kmem.h>
28#include <nvgpu/log.h> 30#include <nvgpu/log.h>
@@ -43,7 +45,7 @@ struct gk20a_ctxsw_dev {
43 struct gk20a *g; 45 struct gk20a *g;
44 46
45 struct nvgpu_ctxsw_ring_header *hdr; 47 struct nvgpu_ctxsw_ring_header *hdr;
46 struct nvgpu_ctxsw_trace_entry *ents; 48 struct nvgpu_gpu_ctxsw_trace_entry *ents;
47 struct nvgpu_ctxsw_trace_filter filter; 49 struct nvgpu_ctxsw_trace_filter filter;
48 bool write_enabled; 50 bool write_enabled;
49 struct nvgpu_cond readout_wq; 51 struct nvgpu_cond readout_wq;
@@ -75,6 +77,17 @@ static inline int ring_len(struct nvgpu_ctxsw_ring_header *hdr)
75 return (hdr->write_idx - hdr->read_idx) % hdr->num_ents; 77 return (hdr->write_idx - hdr->read_idx) % hdr->num_ents;
76} 78}
77 79
80static void nvgpu_set_ctxsw_trace_entry(struct nvgpu_ctxsw_trace_entry *entry_dst,
81 struct nvgpu_gpu_ctxsw_trace_entry *entry_src)
82{
83 entry_dst->tag = entry_src->tag;
84 entry_dst->vmid = entry_src->vmid;
85 entry_dst->seqno = entry_src->seqno;
86 entry_dst->context_id = entry_src->context_id;
87 entry_dst->pid = entry_src->pid;
88 entry_dst->timestamp = entry_src->timestamp;
89}
90
78ssize_t gk20a_ctxsw_dev_read(struct file *filp, char __user *buf, size_t size, 91ssize_t gk20a_ctxsw_dev_read(struct file *filp, char __user *buf, size_t size,
79 loff_t *off) 92 loff_t *off)
80{ 93{
@@ -83,6 +96,7 @@ ssize_t gk20a_ctxsw_dev_read(struct file *filp, char __user *buf, size_t size,
83 struct nvgpu_ctxsw_ring_header *hdr = dev->hdr; 96 struct nvgpu_ctxsw_ring_header *hdr = dev->hdr;
84 struct nvgpu_ctxsw_trace_entry __user *entry = 97 struct nvgpu_ctxsw_trace_entry __user *entry =
85 (struct nvgpu_ctxsw_trace_entry *) buf; 98 (struct nvgpu_ctxsw_trace_entry *) buf;
99 struct nvgpu_ctxsw_trace_entry user_entry;
86 size_t copied = 0; 100 size_t copied = 0;
87 int err; 101 int err;
88 102
@@ -101,11 +115,12 @@ ssize_t gk20a_ctxsw_dev_read(struct file *filp, char __user *buf, size_t size,
101 nvgpu_mutex_acquire(&dev->write_lock); 115 nvgpu_mutex_acquire(&dev->write_lock);
102 } 116 }
103 117
104 while (size >= sizeof(struct nvgpu_ctxsw_trace_entry)) { 118 while (size >= sizeof(struct nvgpu_gpu_ctxsw_trace_entry)) {
105 if (ring_is_empty(hdr)) 119 if (ring_is_empty(hdr))
106 break; 120 break;
107 121
108 if (copy_to_user(entry, &dev->ents[hdr->read_idx], 122 nvgpu_set_ctxsw_trace_entry(&user_entry, &dev->ents[hdr->read_idx]);
123 if (copy_to_user(entry, &user_entry,
109 sizeof(*entry))) { 124 sizeof(*entry))) {
110 nvgpu_mutex_release(&dev->write_lock); 125 nvgpu_mutex_release(&dev->write_lock);
111 return -EFAULT; 126 return -EFAULT;
@@ -169,7 +184,7 @@ static int gk20a_ctxsw_dev_alloc_buffer(struct gk20a_ctxsw_dev *dev,
169 184
170 185
171 dev->hdr = buf; 186 dev->hdr = buf;
172 dev->ents = (struct nvgpu_ctxsw_trace_entry *) (dev->hdr + 1); 187 dev->ents = (struct nvgpu_gpu_ctxsw_trace_entry *) (dev->hdr + 1);
173 dev->size = size; 188 dev->size = size;
174 dev->num_ents = dev->hdr->num_ents; 189 dev->num_ents = dev->hdr->num_ents;
175 190
@@ -191,8 +206,8 @@ int gk20a_ctxsw_dev_ring_alloc(struct gk20a *g,
191 hdr->magic = NVGPU_CTXSW_RING_HEADER_MAGIC; 206 hdr->magic = NVGPU_CTXSW_RING_HEADER_MAGIC;
192 hdr->version = NVGPU_CTXSW_RING_HEADER_VERSION; 207 hdr->version = NVGPU_CTXSW_RING_HEADER_VERSION;
193 hdr->num_ents = (*size - sizeof(struct nvgpu_ctxsw_ring_header)) 208 hdr->num_ents = (*size - sizeof(struct nvgpu_ctxsw_ring_header))
194 / sizeof(struct nvgpu_ctxsw_trace_entry); 209 / sizeof(struct nvgpu_gpu_ctxsw_trace_entry);
195 hdr->ent_size = sizeof(struct nvgpu_ctxsw_trace_entry); 210 hdr->ent_size = sizeof(struct nvgpu_gpu_ctxsw_trace_entry);
196 hdr->drop_count = 0; 211 hdr->drop_count = 0;
197 hdr->read_idx = 0; 212 hdr->read_idx = 0;
198 hdr->write_idx = 0; 213 hdr->write_idx = 0;
@@ -327,9 +342,9 @@ int gk20a_ctxsw_dev_open(struct inode *inode, struct file *filp)
327 n = g->ops.fecs_trace.max_entries(g, &dev->filter); 342 n = g->ops.fecs_trace.max_entries(g, &dev->filter);
328 343
329 size = sizeof(struct nvgpu_ctxsw_ring_header) + 344 size = sizeof(struct nvgpu_ctxsw_ring_header) +
330 n * sizeof(struct nvgpu_ctxsw_trace_entry); 345 n * sizeof(struct nvgpu_gpu_ctxsw_trace_entry);
331 nvgpu_log(g, gpu_dbg_ctxsw, "size=%zu entries=%d ent_size=%zu", 346 nvgpu_log(g, gpu_dbg_ctxsw, "size=%zu entries=%d ent_size=%zu",
332 size, n, sizeof(struct nvgpu_ctxsw_trace_entry)); 347 size, n, sizeof(struct nvgpu_gpu_ctxsw_trace_entry));
333 348
334 err = gk20a_ctxsw_dev_alloc_buffer(dev, size); 349 err = gk20a_ctxsw_dev_alloc_buffer(dev, size);
335 if (!err) { 350 if (!err) {
@@ -583,7 +598,7 @@ void gk20a_ctxsw_trace_cleanup(struct gk20a *g)
583} 598}
584 599
585int gk20a_ctxsw_trace_write(struct gk20a *g, 600int gk20a_ctxsw_trace_write(struct gk20a *g,
586 struct nvgpu_ctxsw_trace_entry *entry) 601 struct nvgpu_gpu_ctxsw_trace_entry *entry)
587{ 602{
588 struct nvgpu_ctxsw_ring_header *hdr; 603 struct nvgpu_ctxsw_ring_header *hdr;
589 struct gk20a_ctxsw_dev *dev; 604 struct gk20a_ctxsw_dev *dev;
@@ -692,7 +707,7 @@ void gk20a_ctxsw_trace_wake_up(struct gk20a *g, int vmid)
692void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch) 707void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch)
693{ 708{
694#ifdef CONFIG_GK20A_CTXSW_TRACE 709#ifdef CONFIG_GK20A_CTXSW_TRACE
695 struct nvgpu_ctxsw_trace_entry entry = { 710 struct nvgpu_gpu_ctxsw_trace_entry entry = {
696 .vmid = 0, 711 .vmid = 0,
697 .tag = NVGPU_CTXSW_TAG_ENGINE_RESET, 712 .tag = NVGPU_CTXSW_TAG_ENGINE_RESET,
698 .context_id = 0, 713 .context_id = 0,
@@ -712,7 +727,7 @@ void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch)
712void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) 727void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg)
713{ 728{
714#ifdef CONFIG_GK20A_CTXSW_TRACE 729#ifdef CONFIG_GK20A_CTXSW_TRACE
715 struct nvgpu_ctxsw_trace_entry entry = { 730 struct nvgpu_gpu_ctxsw_trace_entry entry = {
716 .vmid = 0, 731 .vmid = 0,
717 .tag = NVGPU_CTXSW_TAG_ENGINE_RESET, 732 .tag = NVGPU_CTXSW_TAG_ENGINE_RESET,
718 .context_id = 0, 733 .context_id = 0,