diff options
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/ce2.c')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ce2.c | 155 |
1 files changed, 155 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ce2.c b/drivers/gpu/nvgpu/os/linux/ce2.c new file mode 100644 index 00000000..165f33db --- /dev/null +++ b/drivers/gpu/nvgpu/os/linux/ce2.c | |||
@@ -0,0 +1,155 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <nvgpu/types.h> | ||
18 | |||
19 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> | ||
20 | |||
21 | #include "gk20a/ce2_gk20a.h" | ||
22 | #include "gk20a/gk20a.h" | ||
23 | #include "channel.h" | ||
24 | |||
25 | static inline int gk20a_get_valid_launch_flags(struct gk20a *g, int launch_flags) | ||
26 | { | ||
27 | /* there is no local memory available, | ||
28 | don't allow local memory related CE flags */ | ||
29 | if (!g->mm.vidmem.size) { | ||
30 | launch_flags &= ~(NVGPU_CE_SRC_LOCATION_LOCAL_FB | | ||
31 | NVGPU_CE_DST_LOCATION_LOCAL_FB); | ||
32 | } | ||
33 | return launch_flags; | ||
34 | } | ||
35 | |||
36 | int gk20a_ce_execute_ops(struct gk20a *g, | ||
37 | u32 ce_ctx_id, | ||
38 | u64 src_buf, | ||
39 | u64 dst_buf, | ||
40 | u64 size, | ||
41 | unsigned int payload, | ||
42 | int launch_flags, | ||
43 | int request_operation, | ||
44 | u32 submit_flags, | ||
45 | struct gk20a_fence **gk20a_fence_out) | ||
46 | { | ||
47 | int ret = -EPERM; | ||
48 | struct gk20a_ce_app *ce_app = &g->ce_app; | ||
49 | struct gk20a_gpu_ctx *ce_ctx, *ce_ctx_save; | ||
50 | bool found = false; | ||
51 | u32 *cmd_buf_cpu_va; | ||
52 | u64 cmd_buf_gpu_va = 0; | ||
53 | u32 methodSize; | ||
54 | u32 cmd_buf_read_offset; | ||
55 | u32 dma_copy_class; | ||
56 | struct nvgpu_gpfifo_entry gpfifo; | ||
57 | struct nvgpu_channel_fence fence = {0, 0}; | ||
58 | struct gk20a_fence *ce_cmd_buf_fence_out = NULL; | ||
59 | |||
60 | if (!ce_app->initialised ||ce_app->app_state != NVGPU_CE_ACTIVE) | ||
61 | goto end; | ||
62 | |||
63 | nvgpu_mutex_acquire(&ce_app->app_mutex); | ||
64 | |||
65 | nvgpu_list_for_each_entry_safe(ce_ctx, ce_ctx_save, | ||
66 | &ce_app->allocated_contexts, gk20a_gpu_ctx, list) { | ||
67 | if (ce_ctx->ctx_id == ce_ctx_id) { | ||
68 | found = true; | ||
69 | break; | ||
70 | } | ||
71 | } | ||
72 | |||
73 | nvgpu_mutex_release(&ce_app->app_mutex); | ||
74 | |||
75 | if (!found) { | ||
76 | ret = -EINVAL; | ||
77 | goto end; | ||
78 | } | ||
79 | |||
80 | if (ce_ctx->gpu_ctx_state != NVGPU_CE_GPU_CTX_ALLOCATED) { | ||
81 | ret = -ENODEV; | ||
82 | goto end; | ||
83 | } | ||
84 | |||
85 | nvgpu_mutex_acquire(&ce_ctx->gpu_ctx_mutex); | ||
86 | |||
87 | ce_ctx->cmd_buf_read_queue_offset %= NVGPU_CE_MAX_INFLIGHT_JOBS; | ||
88 | |||
89 | cmd_buf_read_offset = (ce_ctx->cmd_buf_read_queue_offset * | ||
90 | (NVGPU_CE_MAX_COMMAND_BUFF_BYTES_PER_KICKOFF / sizeof(u32))); | ||
91 | |||
92 | cmd_buf_cpu_va = (u32 *)ce_ctx->cmd_buf_mem.cpu_va; | ||
93 | |||
94 | if (ce_ctx->postfences[ce_ctx->cmd_buf_read_queue_offset]) { | ||
95 | struct gk20a_fence **prev_post_fence = | ||
96 | &ce_ctx->postfences[ce_ctx->cmd_buf_read_queue_offset]; | ||
97 | |||
98 | ret = gk20a_fence_wait(g, *prev_post_fence, | ||
99 | gk20a_get_gr_idle_timeout(g)); | ||
100 | |||
101 | gk20a_fence_put(*prev_post_fence); | ||
102 | *prev_post_fence = NULL; | ||
103 | if (ret) | ||
104 | goto noop; | ||
105 | } | ||
106 | |||
107 | cmd_buf_gpu_va = (ce_ctx->cmd_buf_mem.gpu_va + (u64)(cmd_buf_read_offset *sizeof(u32))); | ||
108 | |||
109 | dma_copy_class = g->ops.get_litter_value(g, GPU_LIT_DMA_COPY_CLASS); | ||
110 | methodSize = gk20a_ce_prepare_submit(src_buf, | ||
111 | dst_buf, | ||
112 | size, | ||
113 | &cmd_buf_cpu_va[cmd_buf_read_offset], | ||
114 | NVGPU_CE_MAX_COMMAND_BUFF_BYTES_PER_KICKOFF, | ||
115 | payload, | ||
116 | gk20a_get_valid_launch_flags(g, launch_flags), | ||
117 | request_operation, | ||
118 | dma_copy_class); | ||
119 | |||
120 | if (methodSize) { | ||
121 | /* store the element into gpfifo */ | ||
122 | gpfifo.entry0 = | ||
123 | u64_lo32(cmd_buf_gpu_va); | ||
124 | gpfifo.entry1 = | ||
125 | (u64_hi32(cmd_buf_gpu_va) | | ||
126 | pbdma_gp_entry1_length_f(methodSize)); | ||
127 | |||
128 | /* take always the postfence as it is needed for protecting the ce context */ | ||
129 | submit_flags |= NVGPU_SUBMIT_FLAGS_FENCE_GET; | ||
130 | |||
131 | nvgpu_smp_wmb(); | ||
132 | |||
133 | ret = gk20a_submit_channel_gpfifo(ce_ctx->ch, &gpfifo, NULL, | ||
134 | 1, submit_flags, &fence, | ||
135 | &ce_cmd_buf_fence_out, NULL); | ||
136 | |||
137 | if (!ret) { | ||
138 | ce_ctx->postfences[ce_ctx->cmd_buf_read_queue_offset] = | ||
139 | ce_cmd_buf_fence_out; | ||
140 | if (gk20a_fence_out) { | ||
141 | gk20a_fence_get(ce_cmd_buf_fence_out); | ||
142 | *gk20a_fence_out = ce_cmd_buf_fence_out; | ||
143 | } | ||
144 | |||
145 | /* Next available command buffer queue Index */ | ||
146 | ++ce_ctx->cmd_buf_read_queue_offset; | ||
147 | } | ||
148 | } else { | ||
149 | ret = -ENOMEM; | ||
150 | } | ||
151 | noop: | ||
152 | nvgpu_mutex_release(&ce_ctx->gpu_ctx_mutex); | ||
153 | end: | ||
154 | return ret; | ||
155 | } | ||