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Diffstat (limited to 'drivers/gpu/nvgpu/lpwr')
-rw-r--r--drivers/gpu/nvgpu/lpwr/lpwr.c4
-rw-r--r--drivers/gpu/nvgpu/lpwr/rppg.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index 95eea2e3..c80ddee0 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -243,7 +243,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
243 cmd.cmd.pg.mclk_change.data = payload; 243 cmd.cmd.pg.mclk_change.data = payload;
244 244
245 nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE"); 245 nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE");
246 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, 246 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
247 PMU_COMMAND_QUEUE_HPQ, 247 PMU_COMMAND_QUEUE_HPQ,
248 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); 248 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
249 249
@@ -276,7 +276,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g)
276 PMU_PG_PARAM_CMD_POST_INIT; 276 PMU_PG_PARAM_CMD_POST_INIT;
277 277
278 nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT"); 278 nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT");
279 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, 279 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
280 PMU_COMMAND_QUEUE_LPQ, 280 PMU_COMMAND_QUEUE_LPQ,
281 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); 281 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
282 282
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c
index 553457f7..64046040 100644
--- a/drivers/gpu/nvgpu/lpwr/rppg.c
+++ b/drivers/gpu/nvgpu/lpwr/rppg.c
@@ -73,7 +73,7 @@ static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
73 return -1; 73 return -1;
74 } 74 }
75 75
76 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, 76 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
77 pmu_handle_rppg_init_msg, &success, &seq, ~0); 77 pmu_handle_rppg_init_msg, &success, &seq, ~0);
78 if (status) { 78 if (status) {
79 nvgpu_err(g, "Unable to submit parameter command %d", 79 nvgpu_err(g, "Unable to submit parameter command %d",