diff options
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr')
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/lpwr.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/rppg.h | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.h b/drivers/gpu/nvgpu/lpwr/lpwr.h index 98b9769e..c38ba629 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.h +++ b/drivers/gpu/nvgpu/lpwr/lpwr.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -19,8 +19,8 @@ | |||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | #ifndef _MSCG_H_ | 22 | #ifndef NVGPU_LPWR_H |
23 | #define _MSCG_H_ | 23 | #define NVGPU_LPWR_H |
24 | 24 | ||
25 | #define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540 | 25 | #define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540 |
26 | 26 | ||
@@ -98,4 +98,4 @@ u32 nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num); | |||
98 | u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num); | 98 | u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num); |
99 | u32 nvgpu_lpwr_post_init(struct gk20a *g); | 99 | u32 nvgpu_lpwr_post_init(struct gk20a *g); |
100 | 100 | ||
101 | #endif | 101 | #endif /* NVGPU_LPWR_H */ |
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.h b/drivers/gpu/nvgpu/lpwr/rppg.h index a9966cbf..d66600a0 100644 --- a/drivers/gpu/nvgpu/lpwr/rppg.h +++ b/drivers/gpu/nvgpu/lpwr/rppg.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -19,8 +19,8 @@ | |||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | #ifndef _RPPG_H_ | 22 | #ifndef NVGPU_LPWR_RPPG_H |
23 | #define _RPPG_H_ | 23 | #define NVGPU_LPWR_RPPG_H |
24 | 24 | ||
25 | u32 init_rppg(struct gk20a *g); | 25 | u32 init_rppg(struct gk20a *g); |
26 | #endif | 26 | #endif /* NVGPU_LPWR_RPPG_H */ |