diff options
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr/rppg.c')
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/rppg.c | 164 |
1 files changed, 164 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c new file mode 100644 index 00000000..b1c72a4a --- /dev/null +++ b/drivers/gpu/nvgpu/lpwr/rppg.c | |||
@@ -0,0 +1,164 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/pmu.h> | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include "gp106/bios_gp106.h" | ||
27 | #include "pstate/pstate.h" | ||
28 | |||
29 | static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg, | ||
30 | void *param, u32 handle, u32 status) | ||
31 | { | ||
32 | |||
33 | u8 ctrlId = NV_PMU_RPPG_CTRL_ID_MAX; | ||
34 | u32 *success = param; | ||
35 | |||
36 | if (status == 0) { | ||
37 | switch (msg->msg.pg.rppg_msg.cmn.msg_id) { | ||
38 | case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK: | ||
39 | ctrlId = msg->msg.pg.rppg_msg.init_ctrl_ack.ctrl_id; | ||
40 | *success = 1; | ||
41 | nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x", | ||
42 | msg->msg.pg.msg_type); | ||
43 | break; | ||
44 | } | ||
45 | } | ||
46 | |||
47 | nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x", | ||
48 | msg->msg.pg.msg_type); | ||
49 | } | ||
50 | |||
51 | static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd) | ||
52 | { | ||
53 | struct pmu_cmd cmd; | ||
54 | u32 seq; | ||
55 | u32 status = 0; | ||
56 | u32 success = 0; | ||
57 | |||
58 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
59 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
60 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
61 | sizeof(struct nv_pmu_rppg_cmd); | ||
62 | |||
63 | cmd.cmd.pg.rppg_cmd.cmn.cmd_type = PMU_PMU_PG_CMD_ID_RPPG; | ||
64 | cmd.cmd.pg.rppg_cmd.cmn.cmd_id = prppg_cmd->cmn.cmd_id; | ||
65 | |||
66 | switch (prppg_cmd->cmn.cmd_id) { | ||
67 | case NV_PMU_RPPG_CMD_ID_INIT: | ||
68 | break; | ||
69 | case NV_PMU_RPPG_CMD_ID_INIT_CTRL: | ||
70 | cmd.cmd.pg.rppg_cmd.init_ctrl.ctrl_id = | ||
71 | prppg_cmd->init_ctrl.ctrl_id; | ||
72 | cmd.cmd.pg.rppg_cmd.init_ctrl.domain_id = | ||
73 | prppg_cmd->init_ctrl.domain_id; | ||
74 | break; | ||
75 | case NV_PMU_RPPG_CMD_ID_STATS_RESET: | ||
76 | cmd.cmd.pg.rppg_cmd.stats_reset.ctrl_id = | ||
77 | prppg_cmd->stats_reset.ctrl_id; | ||
78 | break; | ||
79 | default: | ||
80 | nvgpu_err(g, "Inivalid RPPG command %d", | ||
81 | prppg_cmd->cmn.cmd_id); | ||
82 | return -1; | ||
83 | } | ||
84 | |||
85 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
86 | pmu_handle_rppg_init_msg, &success, &seq, ~0); | ||
87 | if (status) { | ||
88 | nvgpu_err(g, "Unable to submit parameter command %d", | ||
89 | prppg_cmd->cmn.cmd_id); | ||
90 | goto exit; | ||
91 | } | ||
92 | |||
93 | if (prppg_cmd->cmn.cmd_id == NV_PMU_RPPG_CMD_ID_INIT_CTRL) { | ||
94 | pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g), | ||
95 | &success, 1); | ||
96 | if (success == 0) { | ||
97 | status = -EINVAL; | ||
98 | nvgpu_err(g, "Ack for the parameter command %x", | ||
99 | prppg_cmd->cmn.cmd_id); | ||
100 | } | ||
101 | } | ||
102 | |||
103 | exit: | ||
104 | return status; | ||
105 | } | ||
106 | |||
107 | static u32 rppg_init(struct gk20a *g) | ||
108 | { | ||
109 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
110 | |||
111 | rppg_cmd.init.cmd_id = NV_PMU_RPPG_CMD_ID_INIT; | ||
112 | |||
113 | return rppg_send_cmd(g, &rppg_cmd); | ||
114 | } | ||
115 | |||
116 | static u32 rppg_ctrl_init(struct gk20a *g, u8 ctrl_id) | ||
117 | { | ||
118 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
119 | |||
120 | rppg_cmd.init_ctrl.cmd_id = NV_PMU_RPPG_CMD_ID_INIT_CTRL; | ||
121 | rppg_cmd.init_ctrl.ctrl_id = ctrl_id; | ||
122 | |||
123 | switch (ctrl_id) { | ||
124 | case NV_PMU_RPPG_CTRL_ID_GR: | ||
125 | case NV_PMU_RPPG_CTRL_ID_MS: | ||
126 | rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX; | ||
127 | break; | ||
128 | } | ||
129 | |||
130 | return rppg_send_cmd(g, &rppg_cmd); | ||
131 | } | ||
132 | |||
133 | u32 init_rppg(struct gk20a *g) | ||
134 | { | ||
135 | u32 status; | ||
136 | |||
137 | status = rppg_init(g); | ||
138 | if (status != 0) { | ||
139 | nvgpu_err(g, | ||
140 | "Failed to initialize RPPG in PMU: 0x%08x", status); | ||
141 | return status; | ||
142 | } | ||
143 | |||
144 | |||
145 | status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_GR); | ||
146 | if (status != 0) { | ||
147 | nvgpu_err(g, | ||
148 | "Failed to initialize RPPG_CTRL: GR in PMU: 0x%08x", | ||
149 | status); | ||
150 | return status; | ||
151 | } | ||
152 | |||
153 | status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_MS); | ||
154 | if (status != 0) { | ||
155 | nvgpu_err(g, | ||
156 | "Failed to initialize RPPG_CTRL: MS in PMU: 0x%08x", | ||
157 | status); | ||
158 | return status; | ||
159 | } | ||
160 | |||
161 | return status; | ||
162 | } | ||
163 | |||
164 | |||