diff options
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr/rppg.c')
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/rppg.c | 158 |
1 files changed, 158 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c new file mode 100644 index 00000000..40e857ee --- /dev/null +++ b/drivers/gpu/nvgpu/lpwr/rppg.c | |||
@@ -0,0 +1,158 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include "gk20a/gk20a.h" | ||
15 | #include "gk20a/pmu_gk20a.h" | ||
16 | #include "gp106/pmu_gp106.h" | ||
17 | #include "gk20a/pmu_api.h" | ||
18 | #include "gm206/bios_gm206.h" | ||
19 | #include "pstate/pstate.h" | ||
20 | #include "include/bios.h" | ||
21 | #include "pmuif/gpmuif_pg_rppg.h" | ||
22 | |||
23 | static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg, | ||
24 | void *param, u32 handle, u32 status) | ||
25 | { | ||
26 | |||
27 | u8 ctrlId = NV_PMU_RPPG_CTRL_ID_MAX; | ||
28 | u32 *success = param; | ||
29 | |||
30 | if (status == 0) { | ||
31 | switch (msg->msg.pg.rppg_msg.cmn.msg_id) { | ||
32 | case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK: | ||
33 | ctrlId = msg->msg.pg.rppg_msg.init_ctrl_ack.ctrl_id; | ||
34 | *success = 1; | ||
35 | gp106_dbg_pmu("RPPG is acknowledged from PMU %x", | ||
36 | msg->msg.pg.msg_type); | ||
37 | break; | ||
38 | } | ||
39 | } | ||
40 | |||
41 | gp106_dbg_pmu("RPPG is acknowledged from PMU %x", | ||
42 | msg->msg.pg.msg_type); | ||
43 | } | ||
44 | |||
45 | static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd) | ||
46 | { | ||
47 | struct pmu_cmd cmd; | ||
48 | u32 seq; | ||
49 | u32 status = 0; | ||
50 | u32 success = 0; | ||
51 | |||
52 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
53 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
54 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
55 | sizeof(struct nv_pmu_rppg_cmd); | ||
56 | |||
57 | cmd.cmd.pg.rppg_cmd.cmn.cmd_type = PMU_PMU_PG_CMD_ID_RPPG; | ||
58 | cmd.cmd.pg.rppg_cmd.cmn.cmd_id = prppg_cmd->cmn.cmd_id; | ||
59 | |||
60 | switch (prppg_cmd->cmn.cmd_id) { | ||
61 | case NV_PMU_RPPG_CMD_ID_INIT: | ||
62 | break; | ||
63 | case NV_PMU_RPPG_CMD_ID_INIT_CTRL: | ||
64 | cmd.cmd.pg.rppg_cmd.init_ctrl.ctrl_id = | ||
65 | prppg_cmd->init_ctrl.ctrl_id; | ||
66 | cmd.cmd.pg.rppg_cmd.init_ctrl.domain_id = | ||
67 | prppg_cmd->init_ctrl.domain_id; | ||
68 | break; | ||
69 | case NV_PMU_RPPG_CMD_ID_STATS_RESET: | ||
70 | cmd.cmd.pg.rppg_cmd.stats_reset.ctrl_id = | ||
71 | prppg_cmd->stats_reset.ctrl_id; | ||
72 | break; | ||
73 | default: | ||
74 | gk20a_err(dev_from_gk20a(g), "Inivalid RPPG command %d", | ||
75 | prppg_cmd->cmn.cmd_id); | ||
76 | return -1; | ||
77 | } | ||
78 | |||
79 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
80 | pmu_handle_rppg_init_msg, &success, &seq, ~0); | ||
81 | if (status) { | ||
82 | gk20a_err(dev_from_gk20a(g), "Unable to submit parameter command %d", | ||
83 | prppg_cmd->cmn.cmd_id); | ||
84 | goto exit; | ||
85 | } | ||
86 | |||
87 | if (prppg_cmd->cmn.cmd_id == NV_PMU_RPPG_CMD_ID_INIT_CTRL) { | ||
88 | pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g), | ||
89 | &success, 1); | ||
90 | if (success == 0) { | ||
91 | status = -EINVAL; | ||
92 | gk20a_err(dev_from_gk20a(g), "Ack for the parameter command %x", | ||
93 | prppg_cmd->cmn.cmd_id); | ||
94 | } | ||
95 | } | ||
96 | |||
97 | exit: | ||
98 | return status; | ||
99 | } | ||
100 | |||
101 | static u32 rppg_init(struct gk20a *g) | ||
102 | { | ||
103 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
104 | |||
105 | rppg_cmd.init.cmd_id = NV_PMU_RPPG_CMD_ID_INIT; | ||
106 | |||
107 | return rppg_send_cmd(g, &rppg_cmd); | ||
108 | } | ||
109 | |||
110 | static u32 rppg_ctrl_init(struct gk20a *g, u8 ctrl_id) | ||
111 | { | ||
112 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
113 | |||
114 | rppg_cmd.init_ctrl.cmd_id = NV_PMU_RPPG_CMD_ID_INIT_CTRL; | ||
115 | rppg_cmd.init_ctrl.ctrl_id = ctrl_id; | ||
116 | |||
117 | switch (ctrl_id) { | ||
118 | case NV_PMU_RPPG_CTRL_ID_GR: | ||
119 | case NV_PMU_RPPG_CTRL_ID_MS: | ||
120 | rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX; | ||
121 | break; | ||
122 | } | ||
123 | |||
124 | return rppg_send_cmd(g, &rppg_cmd); | ||
125 | } | ||
126 | |||
127 | u32 init_rppg(struct gk20a *g) | ||
128 | { | ||
129 | u32 status; | ||
130 | |||
131 | status = rppg_init(g); | ||
132 | if (status != 0) { | ||
133 | gk20a_err(dev_from_gk20a(g), | ||
134 | "Failed to initialize RPPG in PMU: 0x%08x", status); | ||
135 | return status; | ||
136 | } | ||
137 | |||
138 | |||
139 | status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_GR); | ||
140 | if (status != 0) { | ||
141 | gk20a_err(dev_from_gk20a(g), | ||
142 | "Failed to initialize RPPG_CTRL: GR in PMU: 0x%08x", | ||
143 | status); | ||
144 | return status; | ||
145 | } | ||
146 | |||
147 | status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_MS); | ||
148 | if (status != 0) { | ||
149 | gk20a_err(dev_from_gk20a(g), | ||
150 | "Failed to initialize RPPG_CTRL: MS in PMU: 0x%08x", | ||
151 | status); | ||
152 | return status; | ||
153 | } | ||
154 | |||
155 | return status; | ||
156 | } | ||
157 | |||
158 | |||