5 files changed, 219 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index a4823caa..fb0a313f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1051,5 +1051,5 @@ u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset);
 void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
                 struct bit_token *ptoken, u8 table_id);
 int nvgpu_bios_execute_script(struct gk20a *g, u32 offset);
-
+u32 nvgpu_bios_get_nvlink_config_data(struct gk20a *g);
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index c614ce4d..4d8dbb08 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -77,7 +77,8 @@ struct gk20a;
 #define NVGPU_SUPPORT_MAP_BUFFER_BATCH          25
 /* Support DMA coherence */
 #define NVGPU_DMA_COHERENT                      26
-
+/* Use physical scatter tables instead of IOMMU */
+#define NVGPU_MM_USE_PHYSICAL_SG                27
 
 /*
  * Host flags
@@ -114,6 +115,11 @@ struct gk20a;
 #define NVGPU_SEC_PRIVSECURITY                  42
 
 /*
+ * Nvlink flags
+ */
+
+#define NVGPU_SUPPORT_NVLINK                    45
+/*
  * PMU flags.
  */
 /* perfmon enabled or disabled for PMU */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
index 1f104fa1..31587ee7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -34,6 +34,7 @@
 #define FALCON_ID_GPCCS     (3)
 #define FALCON_ID_NVDEC     (4)
 #define FALCON_ID_SEC2      (7)
+#define FALCON_ID_MINION    (10)
 
 /*
  * Falcon Base address Defines
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log.h b/drivers/gpu/nvgpu/include/nvgpu/log.h
index 65f86198..7d7a41e3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/log.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/log.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -79,6 +79,7 @@ enum nvgpu_log_categories {
         gpu_dbg_dma        = BIT(22),   /* DMA allocation prints. */
         gpu_dbg_sgl        = BIT(23),   /* SGL related traces. */
         gpu_dbg_vidmem     = BIT(24),   /* VIDMEM tracing. */
+        gpu_dbg_nvlink     = BIT(25),   /* nvlink Operation tracing. */
         gpu_dbg_mem        = BIT(31),   /* memory accesses; very verbose. */
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h
new file mode 100644
index 00000000..48851ff1
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_NVLINK_H__
+#define __NVGPU_NVLINK_H__
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+struct nvgpu_nvlink_ioctrl_list {
+        bool valid;
+        u32 pri_base_addr;
+        u8 intr_enum;
+        u8 reset_enum;
+};
+
+struct nvgpu_nvlink_device_list {
+        bool valid;
+        u8 device_type;
+        u8 device_id;
+        u8 device_version;
+        u32 pri_base_addr;
+        u8 intr_enum;
+        u8 reset_enum;
+        u8 num_tx;
+        u8 num_rx;
+        u8 pll_master;
+        u8 pll_master_id;
+};
+
+enum nvgpu_nvlink_endp {
+        nvgpu_nvlink_endp_gpu,
+        nvgpu_nvlink_endp_tegra,
+        nvgpu_nvlink_endp__last,
+};
+
+enum nvgpu_nvlink_link_mode {
+        nvgpu_nvlink_link_off,
+        nvgpu_nvlink_link_hs,
+        nvgpu_nvlink_link_safe,
+        nvgpu_nvlink_link_fault,
+        nvgpu_nvlink_link_recovery,
+        nvgpu_nvlink_link_detect,
+        nvgpu_nvlink_link_reset,
+        nvgpu_nvlink_link_enable_pm,
+        nvgpu_nvlink_link_disable_pm,
+        nvgpu_nvlink_link_disable_err_detect,
+        nvgpu_nvlink_link_lane_disable,
+        nvgpu_nvlink_link_lane_shutdown,
+        nvgpu_nvlink_link__last,
+};
+
+enum nvgpu_nvlink_sublink_mode {
+        nvgpu_nvlink_sublink_tx_hs,
+        nvgpu_nvlink_sublink_tx_enable_pm,
+        nvgpu_nvlink_sublink_tx_disable_pm,
+        nvgpu_nvlink_sublink_tx_single_lane,
+        nvgpu_nvlink_sublink_tx_safe,
+        nvgpu_nvlink_sublink_tx_off,
+        nvgpu_nvlink_sublink_tx_common,
+        nvgpu_nvlink_sublink_tx_common_disable,
+        nvgpu_nvlink_sublink_tx_data_ready,
+        nvgpu_nvlink_sublink_tx_prbs_en,
+        nvgpu_nvlink_sublink_tx__last,
+        /* RX */
+        nvgpu_nvlink_sublink_rx_hs,
+        nvgpu_nvlink_sublink_rx_enable_pm,
+        nvgpu_nvlink_sublink_rx_disable_pm,
+        nvgpu_nvlink_sublink_rx_single_lane,
+        nvgpu_nvlink_sublink_rx_safe,
+        nvgpu_nvlink_sublink_rx_off,
+        nvgpu_nvlink_sublink_rx_rxcal,
+        nvgpu_nvlink_sublink_rx__last,
+};
+
+struct nvgpu_nvlink_conn_info {
+        enum nvgpu_nvlink_endp device_type;
+        u32 link_number;
+        bool is_connected;
+};
+
+struct nvgpu_nvlink_link {
+        bool valid;
+        struct gk20a *g;
+        u8 link_id;
+
+        u32 dlpl_base;
+        u8 dlpl_version;
+
+        u32 tl_base;
+        u8 tl_version;
+
+        u32 mif_base;
+        u8 mif_version;
+
+        u8 intr_enum;
+        u8 reset_enum;
+
+        bool dl_init_done;
+
+        u8 pll_master_link_id;
+        u8 pll_slave_link_id;
+
+        struct nvgpu_nvlink_conn_info remote_info;
+        void *priv;
+};
+
+#define NVLINK_MAX_LINKS_SW 6
+
+enum nvgpu_nvlink_speed {
+        nvgpu_nvlink_speed_default,
+        nvgpu_nvlink_speed__last,
+};
+
+struct nvgpu_nvlink_dev {
+        struct nvgpu_nvlink_ioctrl_list *ioctrl_table;
+        u32 io_num_entries;
+
+        struct nvgpu_nvlink_device_list *device_table;
+        u32 num_devices;
+
+        struct nvgpu_nvlink_link links[NVLINK_MAX_LINKS_SW];
+
+        u8 dlpl_type;
+        u32 dlpl_base[NVLINK_MAX_LINKS_SW];
+
+        u8 tl_type;
+        u32 tl_base[NVLINK_MAX_LINKS_SW];
+
+        u8 mif_type;
+        u32 mif_base[NVLINK_MAX_LINKS_SW];
+
+        u8 ipt_type;
+        u32 ipt_base;
+        u8 ipt_version;
+
+        u8 dlpl_multicast_type;
+        u8 dlpl_multicast_version;
+        u32 dlpl_multicast_base;
+
+        u8 tl_multicast_type;
+        u8 tl_multicast_version;
+        u32 tl_multicast_base;
+
+        u8 mif_multicast_type;
+        u8 mif_multicast_version;
+        u32 mif_multicast_base;
+
+        u8 ioctrl_type;
+        u32 ioctrl_base;
+
+        u8 minion_type;
+        u32 minion_base;
+        u8 minion_version;
+
+        u32 discovered_links;
+
+        /* VBIOS settings */
+        u32 link_disable_mask;
+        u32 link_mode_mask;
+        u32 link_refclk_mask;
+        u8 train_at_boot;
+        u32 ac_coupling_mask;
+
+        u32 init_disabled_links;
+        u32 connected_links;
+        u32 initialized_links;
+        u32 enabled_links;
+        u32 topology_connected_links;
+
+        enum nvgpu_nvlink_speed speed;
+
+        /* hshub settings */
+        u32 hshub_config0;
+        u32 hshub_config1;
+        u32 hshub_config2;
+        u32 hshub_config6;
+        /* priv struct */
+        void *priv;
+};
+
+
+u32 nvgpu_nvlink_enumerate(struct gk20a *g);
+u32 nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off);
+u32 nvgpu_nvlink_probe(struct gk20a *g);
+#endif