diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/log.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/nvlink.h | 206 |
5 files changed, 219 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index a4823caa..fb0a313f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -1051,5 +1051,5 @@ u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset); | |||
1051 | void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g, | 1051 | void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g, |
1052 | struct bit_token *ptoken, u8 table_id); | 1052 | struct bit_token *ptoken, u8 table_id); |
1053 | int nvgpu_bios_execute_script(struct gk20a *g, u32 offset); | 1053 | int nvgpu_bios_execute_script(struct gk20a *g, u32 offset); |
1054 | 1054 | u32 nvgpu_bios_get_nvlink_config_data(struct gk20a *g); | |
1055 | #endif | 1055 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index c614ce4d..4d8dbb08 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -77,7 +77,8 @@ struct gk20a; | |||
77 | #define NVGPU_SUPPORT_MAP_BUFFER_BATCH 25 | 77 | #define NVGPU_SUPPORT_MAP_BUFFER_BATCH 25 |
78 | /* Support DMA coherence */ | 78 | /* Support DMA coherence */ |
79 | #define NVGPU_DMA_COHERENT 26 | 79 | #define NVGPU_DMA_COHERENT 26 |
80 | 80 | /* Use physical scatter tables instead of IOMMU */ | |
81 | #define NVGPU_MM_USE_PHYSICAL_SG 27 | ||
81 | 82 | ||
82 | /* | 83 | /* |
83 | * Host flags | 84 | * Host flags |
@@ -114,6 +115,11 @@ struct gk20a; | |||
114 | #define NVGPU_SEC_PRIVSECURITY 42 | 115 | #define NVGPU_SEC_PRIVSECURITY 42 |
115 | 116 | ||
116 | /* | 117 | /* |
118 | * Nvlink flags | ||
119 | */ | ||
120 | |||
121 | #define NVGPU_SUPPORT_NVLINK 45 | ||
122 | /* | ||
117 | * PMU flags. | 123 | * PMU flags. |
118 | */ | 124 | */ |
119 | /* perfmon enabled or disabled for PMU */ | 125 | /* perfmon enabled or disabled for PMU */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 1f104fa1..31587ee7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -34,6 +34,7 @@ | |||
34 | #define FALCON_ID_GPCCS (3) | 34 | #define FALCON_ID_GPCCS (3) |
35 | #define FALCON_ID_NVDEC (4) | 35 | #define FALCON_ID_NVDEC (4) |
36 | #define FALCON_ID_SEC2 (7) | 36 | #define FALCON_ID_SEC2 (7) |
37 | #define FALCON_ID_MINION (10) | ||
37 | 38 | ||
38 | /* | 39 | /* |
39 | * Falcon Base address Defines | 40 | * Falcon Base address Defines |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log.h b/drivers/gpu/nvgpu/include/nvgpu/log.h index 65f86198..7d7a41e3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/log.h +++ b/drivers/gpu/nvgpu/include/nvgpu/log.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -79,6 +79,7 @@ enum nvgpu_log_categories { | |||
79 | gpu_dbg_dma = BIT(22), /* DMA allocation prints. */ | 79 | gpu_dbg_dma = BIT(22), /* DMA allocation prints. */ |
80 | gpu_dbg_sgl = BIT(23), /* SGL related traces. */ | 80 | gpu_dbg_sgl = BIT(23), /* SGL related traces. */ |
81 | gpu_dbg_vidmem = BIT(24), /* VIDMEM tracing. */ | 81 | gpu_dbg_vidmem = BIT(24), /* VIDMEM tracing. */ |
82 | gpu_dbg_nvlink = BIT(25), /* nvlink Operation tracing. */ | ||
82 | gpu_dbg_mem = BIT(31), /* memory accesses; very verbose. */ | 83 | gpu_dbg_mem = BIT(31), /* memory accesses; very verbose. */ |
83 | }; | 84 | }; |
84 | 85 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h new file mode 100644 index 00000000..48851ff1 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h | |||
@@ -0,0 +1,206 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __NVGPU_NVLINK_H__ | ||
24 | #define __NVGPU_NVLINK_H__ | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | struct nvgpu_nvlink_ioctrl_list { | ||
31 | bool valid; | ||
32 | u32 pri_base_addr; | ||
33 | u8 intr_enum; | ||
34 | u8 reset_enum; | ||
35 | }; | ||
36 | |||
37 | struct nvgpu_nvlink_device_list { | ||
38 | bool valid; | ||
39 | u8 device_type; | ||
40 | u8 device_id; | ||
41 | u8 device_version; | ||
42 | u32 pri_base_addr; | ||
43 | u8 intr_enum; | ||
44 | u8 reset_enum; | ||
45 | u8 num_tx; | ||
46 | u8 num_rx; | ||
47 | u8 pll_master; | ||
48 | u8 pll_master_id; | ||
49 | }; | ||
50 | |||
51 | enum nvgpu_nvlink_endp { | ||
52 | nvgpu_nvlink_endp_gpu, | ||
53 | nvgpu_nvlink_endp_tegra, | ||
54 | nvgpu_nvlink_endp__last, | ||
55 | }; | ||
56 | |||
57 | enum nvgpu_nvlink_link_mode { | ||
58 | nvgpu_nvlink_link_off, | ||
59 | nvgpu_nvlink_link_hs, | ||
60 | nvgpu_nvlink_link_safe, | ||
61 | nvgpu_nvlink_link_fault, | ||
62 | nvgpu_nvlink_link_recovery, | ||
63 | nvgpu_nvlink_link_detect, | ||
64 | nvgpu_nvlink_link_reset, | ||
65 | nvgpu_nvlink_link_enable_pm, | ||
66 | nvgpu_nvlink_link_disable_pm, | ||
67 | nvgpu_nvlink_link_disable_err_detect, | ||
68 | nvgpu_nvlink_link_lane_disable, | ||
69 | nvgpu_nvlink_link_lane_shutdown, | ||
70 | nvgpu_nvlink_link__last, | ||
71 | }; | ||
72 | |||
73 | enum nvgpu_nvlink_sublink_mode { | ||
74 | nvgpu_nvlink_sublink_tx_hs, | ||
75 | nvgpu_nvlink_sublink_tx_enable_pm, | ||
76 | nvgpu_nvlink_sublink_tx_disable_pm, | ||
77 | nvgpu_nvlink_sublink_tx_single_lane, | ||
78 | nvgpu_nvlink_sublink_tx_safe, | ||
79 | nvgpu_nvlink_sublink_tx_off, | ||
80 | nvgpu_nvlink_sublink_tx_common, | ||
81 | nvgpu_nvlink_sublink_tx_common_disable, | ||
82 | nvgpu_nvlink_sublink_tx_data_ready, | ||
83 | nvgpu_nvlink_sublink_tx_prbs_en, | ||
84 | nvgpu_nvlink_sublink_tx__last, | ||
85 | /* RX */ | ||
86 | nvgpu_nvlink_sublink_rx_hs, | ||
87 | nvgpu_nvlink_sublink_rx_enable_pm, | ||
88 | nvgpu_nvlink_sublink_rx_disable_pm, | ||
89 | nvgpu_nvlink_sublink_rx_single_lane, | ||
90 | nvgpu_nvlink_sublink_rx_safe, | ||
91 | nvgpu_nvlink_sublink_rx_off, | ||
92 | nvgpu_nvlink_sublink_rx_rxcal, | ||
93 | nvgpu_nvlink_sublink_rx__last, | ||
94 | }; | ||
95 | |||
96 | struct nvgpu_nvlink_conn_info { | ||
97 | enum nvgpu_nvlink_endp device_type; | ||
98 | u32 link_number; | ||
99 | bool is_connected; | ||
100 | }; | ||
101 | |||
102 | struct nvgpu_nvlink_link { | ||
103 | bool valid; | ||
104 | struct gk20a *g; | ||
105 | u8 link_id; | ||
106 | |||
107 | u32 dlpl_base; | ||
108 | u8 dlpl_version; | ||
109 | |||
110 | u32 tl_base; | ||
111 | u8 tl_version; | ||
112 | |||
113 | u32 mif_base; | ||
114 | u8 mif_version; | ||
115 | |||
116 | u8 intr_enum; | ||
117 | u8 reset_enum; | ||
118 | |||
119 | bool dl_init_done; | ||
120 | |||
121 | u8 pll_master_link_id; | ||
122 | u8 pll_slave_link_id; | ||
123 | |||
124 | struct nvgpu_nvlink_conn_info remote_info; | ||
125 | void *priv; | ||
126 | }; | ||
127 | |||
128 | #define NVLINK_MAX_LINKS_SW 6 | ||
129 | |||
130 | enum nvgpu_nvlink_speed { | ||
131 | nvgpu_nvlink_speed_default, | ||
132 | nvgpu_nvlink_speed__last, | ||
133 | }; | ||
134 | |||
135 | struct nvgpu_nvlink_dev { | ||
136 | struct nvgpu_nvlink_ioctrl_list *ioctrl_table; | ||
137 | u32 io_num_entries; | ||
138 | |||
139 | struct nvgpu_nvlink_device_list *device_table; | ||
140 | u32 num_devices; | ||
141 | |||
142 | struct nvgpu_nvlink_link links[NVLINK_MAX_LINKS_SW]; | ||
143 | |||
144 | u8 dlpl_type; | ||
145 | u32 dlpl_base[NVLINK_MAX_LINKS_SW]; | ||
146 | |||
147 | u8 tl_type; | ||
148 | u32 tl_base[NVLINK_MAX_LINKS_SW]; | ||
149 | |||
150 | u8 mif_type; | ||
151 | u32 mif_base[NVLINK_MAX_LINKS_SW]; | ||
152 | |||
153 | u8 ipt_type; | ||
154 | u32 ipt_base; | ||
155 | u8 ipt_version; | ||
156 | |||
157 | u8 dlpl_multicast_type; | ||
158 | u8 dlpl_multicast_version; | ||
159 | u32 dlpl_multicast_base; | ||
160 | |||
161 | u8 tl_multicast_type; | ||
162 | u8 tl_multicast_version; | ||
163 | u32 tl_multicast_base; | ||
164 | |||
165 | u8 mif_multicast_type; | ||
166 | u8 mif_multicast_version; | ||
167 | u32 mif_multicast_base; | ||
168 | |||
169 | u8 ioctrl_type; | ||
170 | u32 ioctrl_base; | ||
171 | |||
172 | u8 minion_type; | ||
173 | u32 minion_base; | ||
174 | u8 minion_version; | ||
175 | |||
176 | u32 discovered_links; | ||
177 | |||
178 | /* VBIOS settings */ | ||
179 | u32 link_disable_mask; | ||
180 | u32 link_mode_mask; | ||
181 | u32 link_refclk_mask; | ||
182 | u8 train_at_boot; | ||
183 | u32 ac_coupling_mask; | ||
184 | |||
185 | u32 init_disabled_links; | ||
186 | u32 connected_links; | ||
187 | u32 initialized_links; | ||
188 | u32 enabled_links; | ||
189 | u32 topology_connected_links; | ||
190 | |||
191 | enum nvgpu_nvlink_speed speed; | ||
192 | |||
193 | /* hshub settings */ | ||
194 | u32 hshub_config0; | ||
195 | u32 hshub_config1; | ||
196 | u32 hshub_config2; | ||
197 | u32 hshub_config6; | ||
198 | /* priv struct */ | ||
199 | void *priv; | ||
200 | }; | ||
201 | |||
202 | |||
203 | u32 nvgpu_nvlink_enumerate(struct gk20a *g); | ||
204 | u32 nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off); | ||
205 | u32 nvgpu_nvlink_probe(struct gk20a *g); | ||
206 | #endif | ||