diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 64 |
1 files changed, 61 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 8c0bb9d3..87449ccc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -34,6 +34,18 @@ struct gk20a; | |||
34 | #define NVGPU_IS_FMODEL 1 | 34 | #define NVGPU_IS_FMODEL 1 |
35 | #define NVGPU_DRIVER_IS_DYING 2 | 35 | #define NVGPU_DRIVER_IS_DYING 2 |
36 | #define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3 | 36 | #define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3 |
37 | |||
38 | /* | ||
39 | * ECC flags | ||
40 | */ | ||
41 | /* SM LRF ECC is enabled */ | ||
42 | #define NVGPU_ECC_ENABLED_SM_LRF 8 | ||
43 | /* SM SHM ECC is enabled */ | ||
44 | #define NVGPU_ECC_ENABLED_SM_SHM 9 | ||
45 | /* TEX ECC is enabled */ | ||
46 | #define NVGPU_ECC_ENABLED_TEX 10 | ||
47 | /* L2 ECC is enabled */ | ||
48 | #define NVGPU_ECC_ENABLED_LTC 11 | ||
37 | /* | 49 | /* |
38 | * MM flags. | 50 | * MM flags. |
39 | */ | 51 | */ |
@@ -44,13 +56,47 @@ struct gk20a; | |||
44 | #define NVGPU_MM_UNIFIED_MEMORY 18 | 56 | #define NVGPU_MM_UNIFIED_MEMORY 18 |
45 | /* kernel mode ce vidmem clearing channels need to be in a tsg */ | 57 | /* kernel mode ce vidmem clearing channels need to be in a tsg */ |
46 | #define NVGPU_MM_CE_TSG_REQUIRED 19 | 58 | #define NVGPU_MM_CE_TSG_REQUIRED 19 |
59 | /* User-space managed address spaces support */ | ||
60 | #define NVGPU_SUPPORT_USERSPACE_MANAGED_AS 20 | ||
61 | /* IO coherence support is available */ | ||
62 | #define NVGPU_SUPPORT_IO_COHERENCE 21 | ||
63 | /* MAP_BUFFER_EX with partial mappings */ | ||
64 | #define NVGPU_SUPPORT_PARTIAL_MAPPINGS 22 | ||
65 | /* MAP_BUFFER_EX with sparse allocations */ | ||
66 | #define NVGPU_SUPPORT_SPARSE_ALLOCS 23 | ||
67 | /* Direct PTE kind control is supported (map_buffer_ex) */ | ||
68 | #define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL 24 | ||
69 | |||
70 | /* | ||
71 | * Host flags | ||
72 | */ | ||
73 | #define NVGPU_HAS_SYNCPOINTS 30 | ||
74 | /* sync fence FDs are available in, e.g., submit_gpfifo */ | ||
75 | #define NVGPU_SUPPORT_SYNC_FENCE_FDS 31 | ||
76 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ | ||
77 | #define NVGPU_SUPPORT_CYCLE_STATS 32 | ||
78 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */ | ||
79 | #define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33 | ||
80 | /* Both gpu driver and device support TSG */ | ||
81 | #define NVGPU_SUPPORT_TSG 33 | ||
82 | /* Fast deterministic submits with no job tracking are supported */ | ||
83 | #define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING 34 | ||
84 | /* Deterministic submits are supported even with job tracking */ | ||
85 | #define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL 35 | ||
86 | /* NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is available */ | ||
87 | #define NVGPU_SUPPORT_RESCHEDULE_RUNLIST 36 | ||
88 | |||
89 | /* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */ | ||
90 | #define NVGPU_SUPPORT_DEVICE_EVENTS 37 | ||
91 | /* FECS context switch tracing is available */ | ||
92 | #define NVGPU_SUPPORT_FECS_CTXSW_TRACE 38 | ||
47 | 93 | ||
48 | /* | 94 | /* |
49 | * Security flags | 95 | * Security flags |
50 | */ | 96 | */ |
51 | 97 | ||
52 | #define NVGPU_SEC_SECUREGPCCS 32 | 98 | #define NVGPU_SEC_SECUREGPCCS 40 |
53 | #define NVGPU_SEC_PRIVSECURITY 33 | 99 | #define NVGPU_SEC_PRIVSECURITY 41 |
54 | 100 | ||
55 | /* | 101 | /* |
56 | * PMU flags. | 102 | * PMU flags. |
@@ -63,9 +109,21 @@ struct gk20a; | |||
63 | #define NVGPU_GPU_CAN_BLCG 52 | 109 | #define NVGPU_GPU_CAN_BLCG 52 |
64 | #define NVGPU_GPU_CAN_SLCG 53 | 110 | #define NVGPU_GPU_CAN_SLCG 53 |
65 | #define NVGPU_GPU_CAN_ELCG 54 | 111 | #define NVGPU_GPU_CAN_ELCG 54 |
112 | /* Clock control support */ | ||
113 | #define NVGPU_SUPPORT_CLOCK_CONTROLS 55 | ||
114 | /* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */ | ||
115 | #define NVGPU_SUPPORT_GET_VOLTAGE 56 | ||
116 | /* NVGPU_GPU_IOCTL_GET_CURRENT is available */ | ||
117 | #define NVGPU_SUPPORT_GET_CURRENT 57 | ||
118 | /* NVGPU_GPU_IOCTL_GET_POWER is available */ | ||
119 | #define NVGPU_SUPPORT_GET_POWER 58 | ||
120 | /* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */ | ||
121 | #define NVGPU_SUPPORT_GET_TEMPERATURE 59 | ||
122 | /* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */ | ||
123 | #define NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT 60 | ||
66 | 124 | ||
67 | /* whether to run PREOS binary on dGPUs */ | 125 | /* whether to run PREOS binary on dGPUs */ |
68 | #define NVGPU_PMU_RUN_PREOS 52 | 126 | #define NVGPU_PMU_RUN_PREOS 61 |
69 | 127 | ||
70 | /* | 128 | /* |
71 | * Must be greater than the largest bit offset in the above list. | 129 | * Must be greater than the largest bit offset in the above list. |