diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmu.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h | 84 |
2 files changed, 91 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index cd7e1879..5e9983b0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -329,6 +329,8 @@ struct nvgpu_pmu { | |||
329 | u32 *ucode_image; | 329 | u32 *ucode_image; |
330 | bool pmu_ready; | 330 | bool pmu_ready; |
331 | 331 | ||
332 | u32 perfmon_query; | ||
333 | |||
332 | u32 zbc_save_done; | 334 | u32 zbc_save_done; |
333 | 335 | ||
334 | u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; | 336 | u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; |
@@ -362,6 +364,7 @@ struct nvgpu_pmu { | |||
362 | u32 sample_buffer; | 364 | u32 sample_buffer; |
363 | u32 load_shadow; | 365 | u32 load_shadow; |
364 | u32 load_avg; | 366 | u32 load_avg; |
367 | u32 load; | ||
365 | 368 | ||
366 | struct nvgpu_mutex isr_mutex; | 369 | struct nvgpu_mutex isr_mutex; |
367 | bool isr_enabled; | 370 | bool isr_enabled; |
@@ -432,8 +435,12 @@ int nvgpu_pmu_process_message(struct nvgpu_pmu *pmu); | |||
432 | int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu); | 435 | int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu); |
433 | int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu); | 436 | int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu); |
434 | int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu); | 437 | int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu); |
438 | int nvgpu_pmu_perfmon_start_sampling_rpc(struct nvgpu_pmu *pmu); | ||
439 | int nvgpu_pmu_perfmon_stop_sampling_rpc(struct nvgpu_pmu *pmu); | ||
440 | int nvgpu_pmu_perfmon_get_samples_rpc(struct nvgpu_pmu *pmu); | ||
435 | int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu, | 441 | int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu, |
436 | struct pmu_perfmon_msg *msg); | 442 | struct pmu_perfmon_msg *msg); |
443 | int nvgpu_pmu_init_perfmon_rpc(struct nvgpu_pmu *pmu); | ||
437 | int nvgpu_pmu_load_norm(struct gk20a *g, u32 *load); | 444 | int nvgpu_pmu_load_norm(struct gk20a *g, u32 *load); |
438 | int nvgpu_pmu_load_update(struct gk20a *g); | 445 | int nvgpu_pmu_load_update(struct gk20a *g); |
439 | void nvgpu_pmu_reset_load_counters(struct gk20a *g); | 446 | void nvgpu_pmu_reset_load_counters(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h index f8c15324..bcf4c8b6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h | |||
@@ -32,6 +32,8 @@ | |||
32 | #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) | 32 | #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) |
33 | #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) | 33 | #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) |
34 | 34 | ||
35 | #define NV_PMU_PERFMON_MAX_COUNTERS 10 | ||
36 | |||
35 | enum pmu_perfmon_cmd_start_fields { | 37 | enum pmu_perfmon_cmd_start_fields { |
36 | COUNTER_ALLOC | 38 | COUNTER_ALLOC |
37 | }; | 39 | }; |
@@ -61,6 +63,15 @@ struct pmu_perfmon_counter_v2 { | |||
61 | u32 scale; | 63 | u32 scale; |
62 | }; | 64 | }; |
63 | 65 | ||
66 | struct pmu_perfmon_counter_v3 { | ||
67 | u8 index; | ||
68 | u8 group_id; | ||
69 | u16 flags; | ||
70 | u16 upper_threshold; /* units of 0.01% */ | ||
71 | u16 lower_threshold; /* units of 0.01% */ | ||
72 | u32 scale; | ||
73 | }; | ||
74 | |||
64 | struct pmu_perfmon_cmd_start_v3 { | 75 | struct pmu_perfmon_cmd_start_v3 { |
65 | u8 cmd_type; | 76 | u8 cmd_type; |
66 | u8 group_id; | 77 | u8 group_id; |
@@ -184,4 +195,77 @@ struct pmu_perfmon_msg { | |||
184 | }; | 195 | }; |
185 | }; | 196 | }; |
186 | 197 | ||
198 | /* PFERMON RPC interface*/ | ||
199 | /* | ||
200 | * RPC calls serviced by PERFMON unit. | ||
201 | */ | ||
202 | #define NV_PMU_RPC_ID_PERFMON_T18X_INIT 0x00 | ||
203 | #define NV_PMU_RPC_ID_PERFMON_T18X_DEINIT 0x01 | ||
204 | #define NV_PMU_RPC_ID_PERFMON_T18X_START 0x02 | ||
205 | #define NV_PMU_RPC_ID_PERFMON_T18X_STOP 0x03 | ||
206 | #define NV_PMU_RPC_ID_PERFMON_T18X_QUERY 0x04 | ||
207 | #define NV_PMU_RPC_ID_PERFMON_T18X__COUNT 0x05 | ||
208 | |||
209 | /* | ||
210 | * structure that holds data used to | ||
211 | * execute Perfmon INIT RPC. | ||
212 | * hdr - RPC header | ||
213 | * sample_periodus - Desired period in between samples. | ||
214 | * to_decrease_count - Consecutive samples before decrease event. | ||
215 | * base_counter_id - Index of the base counter. | ||
216 | * samples_in_moving_avg - Number of values in moving average. | ||
217 | * num_counters - Num of counters PMU should use. | ||
218 | * counter - Counters. | ||
219 | */ | ||
220 | struct nv_pmu_rpc_struct_perfmon_init { | ||
221 | struct nv_pmu_rpc_header hdr; | ||
222 | u32 sample_periodus; | ||
223 | u8 to_decrease_count; | ||
224 | u8 base_counter_id; | ||
225 | u8 samples_in_moving_avg; | ||
226 | u8 num_counters; | ||
227 | struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS]; | ||
228 | u32 scratch[1]; | ||
229 | }; | ||
230 | |||
231 | /* | ||
232 | * structure that holds data used to | ||
233 | * execute Perfmon START RPC. | ||
234 | * hdr - RPC header | ||
235 | * group_id - NV group ID | ||
236 | * state_id - NV state ID | ||
237 | * flags - PMU_PERFON flags | ||
238 | * counters - Counters. | ||
239 | */ | ||
240 | struct nv_pmu_rpc_struct_perfmon_start { | ||
241 | struct nv_pmu_rpc_header hdr; | ||
242 | u8 group_id; | ||
243 | u8 state_id; | ||
244 | u8 flags; | ||
245 | struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS]; | ||
246 | u32 scratch[1]; | ||
247 | }; | ||
248 | |||
249 | /* | ||
250 | * structure that holds data used to | ||
251 | * execute Perfmon STOP RPC. | ||
252 | * hdr - RPC header | ||
253 | */ | ||
254 | struct nv_pmu_rpc_struct_perfmon_stop { | ||
255 | struct nv_pmu_rpc_header hdr; | ||
256 | u32 scratch[1]; | ||
257 | }; | ||
258 | |||
259 | /* | ||
260 | * structure that holds data used to | ||
261 | * execute QUERY RPC. | ||
262 | * hdr - RPC header | ||
263 | * sample_buffer - Output buffer from pmu containing utilization samples. | ||
264 | */ | ||
265 | struct nv_pmu_rpc_struct_perfmon_query { | ||
266 | struct nv_pmu_rpc_header hdr; | ||
267 | u16 sample_buffer[NV_PMU_PERFMON_MAX_COUNTERS]; | ||
268 | u32 scratch[1]; | ||
269 | }; | ||
270 | |||
187 | #endif /* _GPMUIFPERFMON_H_ */ | 271 | #endif /* _GPMUIFPERFMON_H_ */ |