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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h14
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm206/hw_gr_gm206.h14
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h12
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h12
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h12
5 files changed, 62 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
index 1a888b53..7f6f58f3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -3178,14 +3178,26 @@ static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3178{ 3178{
3179 return 0x00504614; 3179 return 0x00504614;
3180} 3180}
3181static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
3182{
3183 return 0x00504618;
3184}
3181static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) 3185static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3182{ 3186{
3183 return 0x00504624; 3187 return 0x00504624;
3184} 3188}
3189static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
3190{
3191 return 0x00504628;
3192}
3185static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) 3193static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3186{ 3194{
3187 return 0x00504634; 3195 return 0x00504634;
3188} 3196}
3197static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
3198{
3199 return 0x00504638;
3200}
3189static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) 3201static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3190{ 3202{
3191 return 0x00419e24; 3203 return 0x00419e24;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm206/hw_gr_gm206.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm206/hw_gr_gm206.h
index ff677844..f0dea40a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm206/hw_gr_gm206.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm206/hw_gr_gm206.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -3174,14 +3174,26 @@ static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3174{ 3174{
3175 return 0x00504614; 3175 return 0x00504614;
3176} 3176}
3177static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
3178{
3179 return 0x00504618;
3180}
3177static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) 3181static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3178{ 3182{
3179 return 0x00504624; 3183 return 0x00504624;
3180} 3184}
3185static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
3186{
3187 return 0x00504628;
3188}
3181static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) 3189static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3182{ 3190{
3183 return 0x00504634; 3191 return 0x00504634;
3184} 3192}
3193static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
3194{
3195 return 0x00504638;
3196}
3185static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) 3197static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3186{ 3198{
3187 return 0x00419e24; 3199 return 0x00419e24;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
index 30436fb1..bc966416 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -3250,6 +3250,10 @@ static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3250{ 3250{
3251 return 0x00504614; 3251 return 0x00504614;
3252} 3252}
3253static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
3254{
3255 return 0x00504618;
3256}
3253static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void) 3257static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void)
3254{ 3258{
3255 return 0x0050461c; 3259 return 0x0050461c;
@@ -3258,6 +3262,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3258{ 3262{
3259 return 0x00504624; 3263 return 0x00504624;
3260} 3264}
3265static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
3266{
3267 return 0x00504628;
3268}
3261static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void) 3269static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void)
3262{ 3270{
3263 return 0x00504750; 3271 return 0x00504750;
@@ -3266,6 +3274,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3266{ 3274{
3267 return 0x00504634; 3275 return 0x00504634;
3268} 3276}
3277static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
3278{
3279 return 0x00504638;
3280}
3269static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void) 3281static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void)
3270{ 3282{
3271 return 0x00504758; 3283 return 0x00504758;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
index c20da067..c6490f7a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
@@ -3478,14 +3478,26 @@ static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3478{ 3478{
3479 return 0x00504614; 3479 return 0x00504614;
3480} 3480}
3481static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
3482{
3483 return 0x00504618;
3484}
3481static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) 3485static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3482{ 3486{
3483 return 0x00504624; 3487 return 0x00504624;
3484} 3488}
3489static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
3490{
3491 return 0x00504628;
3492}
3485static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) 3493static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3486{ 3494{
3487 return 0x00504634; 3495 return 0x00504634;
3488} 3496}
3497static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
3498{
3499 return 0x00504638;
3500}
3489static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) 3501static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3490{ 3502{
3491 return 0x00419e24; 3503 return 0x00419e24;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index 7989337c..12ba42a9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -3606,14 +3606,26 @@ static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3606{ 3606{
3607 return 0x00504614; 3607 return 0x00504614;
3608} 3608}
3609static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
3610{
3611 return 0x00504618;
3612}
3609static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) 3613static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3610{ 3614{
3611 return 0x00504624; 3615 return 0x00504624;
3612} 3616}
3617static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
3618{
3619 return 0x00504628;
3620}
3613static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) 3621static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3614{ 3622{
3615 return 0x00504634; 3623 return 0x00504634;
3616} 3624}
3625static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
3626{
3627 return 0x00504638;
3628}
3617static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) 3629static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3618{ 3630{
3619 return 0x00419e24; 3631 return 0x00419e24;