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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/bios.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h61
2 files changed, 61 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index fb0a313f..75f8da35 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -725,6 +725,7 @@ struct vbios_voltage_rail_table_1x_header {
725#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 725#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009
726#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A 726#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A
727#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B 727#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B
728#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000C
728 729
729struct vbios_voltage_rail_table_1x_entry { 730struct vbios_voltage_rail_table_1x_entry {
730 u32 boot_voltage_uv; 731 u32 boot_voltage_uv;
@@ -735,6 +736,7 @@ struct vbios_voltage_rail_table_1x_entry {
735 u8 boot_volt_vfe_equ_idx; 736 u8 boot_volt_vfe_equ_idx;
736 u8 vmin_limit_vfe_equ_idx; 737 u8 vmin_limit_vfe_equ_idx;
737 u8 volt_margin_limit_vfe_equ_idx; 738 u8 volt_margin_limit_vfe_equ_idx;
739 u8 volt_scale_exp_pwr_equ_idx;
738} __packed; 740} __packed;
739 741
740/* Voltage Device Table */ 742/* Voltage Device Table */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h
index c3d540cc..3b286139 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h
@@ -1,5 +1,5 @@
1/* 1/*
2* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3* 3*
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -49,6 +49,8 @@ struct nv_pmu_volt_volt_rail_boardobj_set {
49 u8 volt_margin_limit_vfe_equ_idx; 49 u8 volt_margin_limit_vfe_equ_idx;
50 u8 pwr_equ_idx; 50 u8 pwr_equ_idx;
51 u8 volt_dev_idx_default; 51 u8 volt_dev_idx_default;
52 u8 volt_dev_idx_ipc_vmin;
53 u8 volt_scale_exp_pwr_equ_idx;
52 struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; 54 struct ctrl_boardobjgrp_mask_e32 volt_dev_mask;
53 s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; 55 s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
54}; 56};
@@ -101,7 +103,6 @@ NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device);
101 103
102/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ 104/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */
103struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { 105struct nv_pmu_volt_volt_policy_boardobjgrp_set_header {
104
105 struct nv_pmu_boardobjgrp_e32 super; 106 struct nv_pmu_boardobjgrp_e32 super;
106}; 107};
107 108
@@ -332,4 +333,60 @@ struct nv_pmu_volt_volt_rail_list {
332 rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; 333 rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
333}; 334};
334 335
336struct nv_pmu_volt_volt_rail_list_V1 {
337 u8 num_rails;
338 struct ctrl_volt_volt_rail_list_item_v1
339 rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
340};
341
342/* VOLT RPC */
343#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00
344#define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01
345#define NV_PMU_RPC_ID_VOLT_LOAD 0x02
346#define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03
347#define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04
348#define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05
349#define NV_PMU_RPC_ID_VOLT__COUNT 0x06
350
351/*
352 * Defines the structure that holds data
353 * used to execute LOAD RPC.
354 */
355struct nv_pmu_rpc_struct_volt_load {
356 /*[IN/OUT] Must be first field in RPC structure */
357 struct nv_pmu_rpc_header hdr;
358 u32 scratch[1];
359};
360
361/*
362 * Defines the structure that holds data
363 * used to execute VOLT_SET_VOLTAGE RPC.
364 */
365struct nv_pmu_rpc_struct_volt_volt_set_voltage {
366 /*[IN/OUT] Must be first field in RPC structure */
367 struct nv_pmu_rpc_header hdr;
368 /*[IN] ID of the client that wants to set the voltage */
369 u8 client_id;
370 /*
371 * [IN] The list containing target voltage and
372 * noise-unaware Vmin value for the VOLT_RAILs.
373 */
374 struct ctrl_volt_volt_rail_list_v1 rail_list;
375 u32 scratch[1];
376};
377
378/*
379 * Defines the structure that holds data
380 * used to execute VOLT_RAIL_GET_VOLTAGE RPC.
381 */
382struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage {
383 /*[IN/OUT] Must be first field in RPC structure */
384 struct nv_pmu_rpc_header hdr;
385 /* [OUT] Current voltage in uv */
386 u32 voltage_uv;
387 /* [IN] Voltage Rail Table Index */
388 u8 rail_idx;
389 u32 scratch[1];
390};
391
335#endif /* _GPMUIFVOLT_H_*/ 392#endif /* _GPMUIFVOLT_H_*/