diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/semaphore.h | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h index 373c5745..9ab6cc67 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h +++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h | |||
@@ -276,28 +276,36 @@ static inline bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s) | |||
276 | } | 276 | } |
277 | 277 | ||
278 | /* | 278 | /* |
279 | * Fast-forward the hw sema to the threshold represented by sema_thresh. | 279 | * Fast-forward the hw sema to its tracked max value. |
280 | * | ||
281 | * Return true if the sema wasn't at the max value and needed updating, false | ||
282 | * otherwise. | ||
280 | */ | 283 | */ |
281 | static inline void nvgpu_semaphore_reset(struct nvgpu_semaphore *sema_thresh, | 284 | static inline bool nvgpu_semaphore_reset(struct nvgpu_semaphore_int *hw_sema) |
282 | struct nvgpu_semaphore_int *hw_sema) | ||
283 | { | 285 | { |
284 | u32 current_val; | 286 | u32 threshold = (u32)nvgpu_atomic_read(&hw_sema->next_value); |
285 | u32 threshold = nvgpu_semaphore_get_value(sema_thresh); | 287 | u32 current_val = __nvgpu_semaphore_read(hw_sema); |
286 | |||
287 | current_val = nvgpu_semaphore_read(sema_thresh); | ||
288 | 288 | ||
289 | /* | 289 | /* |
290 | * If the semaphore has already reached the value we would write then | 290 | * If the semaphore has already reached the value we would write then |
291 | * this is really just a NO-OP. | 291 | * this is really just a NO-OP. However, the sema value shouldn't be |
292 | * more than what we expect to be the max. | ||
292 | */ | 293 | */ |
293 | if (__nvgpu_semaphore_value_released(threshold, current_val)) | 294 | |
294 | return; | 295 | if (WARN_ON(__nvgpu_semaphore_value_released(threshold + 1, |
296 | current_val))) | ||
297 | return false; | ||
298 | |||
299 | if (current_val == threshold) | ||
300 | return false; | ||
295 | 301 | ||
296 | nvgpu_mem_wr(hw_sema->ch->g, &hw_sema->location.pool->rw_mem, | 302 | nvgpu_mem_wr(hw_sema->ch->g, &hw_sema->location.pool->rw_mem, |
297 | hw_sema->location.offset, threshold); | 303 | hw_sema->location.offset, threshold); |
298 | 304 | ||
299 | gpu_sema_verbose_dbg(hw_sema->ch->g, "(c=%d) RESET %u -> %u", | 305 | gpu_sema_verbose_dbg(hw_sema->ch->g, "(c=%d) RESET %u -> %u", |
300 | hw_sema->ch->chid, current_val, threshold); | 306 | hw_sema->ch->chid, current_val, threshold); |
307 | |||
308 | return true; | ||
301 | } | 309 | } |
302 | 310 | ||
303 | /* | 311 | /* |