4 files changed, 26 insertions, 25 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
index f207c9ab..6991a0ba 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
@@ -67,8 +67,8 @@ struct wpr_carveout_info {
 };
 
 struct acr_desc {
-        struct mem_desc ucode_blob;
-        struct mem_desc wpr_dummy;
+        struct nvgpu_mem ucode_blob;
+        struct nvgpu_mem wpr_dummy;
         struct bin_hdr *bl_bin_hdr;
         struct hsflcn_bl_desc *pmu_hsbl_desc;
         struct bin_hdr *hsbin_hdr;
@@ -79,9 +79,9 @@ struct acr_desc {
                 struct flcn_acr_desc *acr_dmem_desc;
                 struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
         };
-        struct mem_desc acr_ucode;
+        struct nvgpu_mem acr_ucode;
         const struct firmware *hsbl_fw;
-        struct mem_desc hsbl_ucode;
+        struct nvgpu_mem hsbl_ucode;
         union {
                 struct flcn_bl_dmem_desc bl_dmem_desc;
                 struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
index 42d8854a..ae5dcc6e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -14,8 +14,8 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef __NVGPU_MEM_DESC_H__
-#define __NVGPU_MEM_DESC_H__
+#ifndef __NVGPU_NVGPU_MEM_H__
+#define __NVGPU_NVGPU_MEM_H__
 
 #include <linux/types.h>
 
@@ -38,7 +38,7 @@ enum nvgpu_aperture {
         APERTURE_VIDMEM
 };
 
-struct mem_desc {
+struct nvgpu_mem {
         void *cpu_va; /* sysmem only */
         struct page **pages; /* sysmem only */
         struct sg_table *sgt;
@@ -53,14 +53,15 @@ struct mem_desc {
         unsigned long flags;
 };
 
-static inline struct mem_desc *
-mem_desc_from_clear_list_entry(struct nvgpu_list_node *node)
+static inline struct nvgpu_mem *
+nvgpu_mem_from_clear_list_entry(struct nvgpu_list_node *node)
 {
-        return (struct mem_desc *)
-                ((uintptr_t)node - offsetof(struct mem_desc, clear_list_entry));
+        return (struct nvgpu_mem *)
+                ((uintptr_t)node - offsetof(struct nvgpu_mem,
+                                            clear_list_entry));
 };
 
-struct mem_desc_sub {
+struct nvgpu_mem_sub {
         u32 offset;
         u32 size;
 };
@@ -80,32 +81,32 @@ static inline const char *nvgpu_aperture_str(enum nvgpu_aperture aperture)
  * kernel mapping for this buffer.
  */
 
-int nvgpu_mem_begin(struct gk20a *g, struct mem_desc *mem);
+int nvgpu_mem_begin(struct gk20a *g, struct nvgpu_mem *mem);
 /* nop for null mem, like with free() or vunmap() */
-void nvgpu_mem_end(struct gk20a *g, struct mem_desc *mem);
+void nvgpu_mem_end(struct gk20a *g, struct nvgpu_mem *mem);
 
 /* word-indexed offset */
-u32 nvgpu_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w);
+u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w);
 /* byte offset (32b-aligned) */
-u32 nvgpu_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset);
+u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset);
 /* memcpy to cpu, offset and size in bytes (32b-aligned) */
-void nvgpu_mem_rd_n(struct gk20a *g, struct mem_desc *mem, u32 offset,
+void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
                 void *dest, u32 size);
 
 /* word-indexed offset */
-void nvgpu_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data);
+void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data);
 /* byte offset (32b-aligned) */
-void nvgpu_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data);
+void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data);
 /* memcpy from cpu, offset and size in bytes (32b-aligned) */
-void nvgpu_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset,
+void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
                 void *src, u32 size);
 /* size and offset in bytes (32b-aligned), filled with the constant byte c */
-void nvgpu_memset(struct gk20a *g, struct mem_desc *mem, u32 offset,
+void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
                 u32 c, u32 size);
 
 u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture,
                 u32 sysmem_mask, u32 vidmem_mask);
-u32 nvgpu_aperture_mask(struct gk20a *g, struct mem_desc *mem,
+u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem,
                 u32 sysmem_mask, u32 vidmem_mask);
 
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pramin.h b/drivers/gpu/nvgpu/include/nvgpu/pramin.h
index 7e0df06b..50367a6c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pramin.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pramin.h
@@ -21,7 +21,7 @@
 
 struct gk20a;
 struct mm_gk20a;
-struct mem_desc;
+struct nvgpu_mem;
 
 /*
  * This typedef is for functions that get called during the access_batched()
@@ -37,7 +37,7 @@ void pramin_access_batch_rd_n(struct gk20a *g, u32 start, u32 words, u32 **arg);
 void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg);
 void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg);
 
-void nvgpu_pramin_access_batched(struct gk20a *g, struct mem_desc *mem,
+void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem,
                                  u32 offset, u32 size,
                                  pramin_access_batch_fn loop, u32 **arg);
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h
index ade48178..d9120b65 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h
@@ -136,7 +136,7 @@ struct nvgpu_semaphore_sea {
         struct page *pages[SEMAPHORE_POOL_COUNT];
         */
 
-        struct mem_desc sea_mem;
+        struct nvgpu_mem sea_mem;
 
         /*
          * Can't use a regular allocator here since the full range of pools are