diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h | 6 |
2 files changed, 0 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 4e6f2cd1..1e2f516f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -667,9 +667,6 @@ enum { | |||
667 | TEGRA_VGPU_FIFO_INTR_PBDMA = 10, | 667 | TEGRA_VGPU_FIFO_INTR_PBDMA = 10, |
668 | TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT = 11, | 668 | TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT = 11, |
669 | TEGRA_VGPU_FIFO_INTR_MMU_FAULT = 12, | 669 | TEGRA_VGPU_FIFO_INTR_MMU_FAULT = 12, |
670 | TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE = 13, | ||
671 | TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL = 14, | ||
672 | TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE = 15, | ||
673 | TEGRA_VGPU_GR_INTR_SM_EXCEPTION = 16, | 670 | TEGRA_VGPU_GR_INTR_SM_EXCEPTION = 16, |
674 | }; | 671 | }; |
675 | 672 | ||
@@ -737,9 +734,6 @@ enum { | |||
737 | TEGRA_VGPU_INTR_GR = 0, | 734 | TEGRA_VGPU_INTR_GR = 0, |
738 | TEGRA_VGPU_INTR_FIFO = 1, | 735 | TEGRA_VGPU_INTR_FIFO = 1, |
739 | TEGRA_VGPU_INTR_CE2 = 2, | 736 | TEGRA_VGPU_INTR_CE2 = 2, |
740 | TEGRA_VGPU_NONSTALL_INTR_GR = 3, | ||
741 | TEGRA_VGPU_NONSTALL_INTR_FIFO = 4, | ||
742 | TEGRA_VGPU_NONSTALL_INTR_CE2 = 5, | ||
743 | }; | 737 | }; |
744 | 738 | ||
745 | enum { | 739 | enum { |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h index 046763dd..1e851b8e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h | |||
@@ -76,8 +76,6 @@ int vgpu_init_hal(struct gk20a *g); | |||
76 | int vgpu_get_constants(struct gk20a *g); | 76 | int vgpu_get_constants(struct gk20a *g); |
77 | u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem); | 77 | u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem); |
78 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | 78 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); |
79 | int vgpu_gr_nonstall_isr(struct gk20a *g, | ||
80 | struct tegra_vgpu_gr_nonstall_intr_info *info); | ||
81 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | 79 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, |
82 | struct nvgpu_gr_ctx *gr_ctx, | 80 | struct nvgpu_gr_ctx *gr_ctx, |
83 | struct vm_gk20a *vm, | 81 | struct vm_gk20a *vm, |
@@ -89,10 +87,6 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | |||
89 | struct tegra_vgpu_sm_esr_info *info); | 87 | struct tegra_vgpu_sm_esr_info *info); |
90 | int vgpu_gr_init_ctx_state(struct gk20a *g); | 88 | int vgpu_gr_init_ctx_state(struct gk20a *g); |
91 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); | 89 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); |
92 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | ||
93 | struct tegra_vgpu_fifo_nonstall_intr_info *info); | ||
94 | int vgpu_ce2_nonstall_isr(struct gk20a *g, | ||
95 | struct tegra_vgpu_ce2_nonstall_intr_info *info); | ||
96 | u32 vgpu_ce_get_num_pce(struct gk20a *g); | 90 | u32 vgpu_ce_get_num_pce(struct gk20a *g); |
97 | int vgpu_init_mm_support(struct gk20a *g); | 91 | int vgpu_init_mm_support(struct gk20a *g); |
98 | int vgpu_init_gr_support(struct gk20a *g); | 92 | int vgpu_init_gr_support(struct gk20a *g); |