196 files changed, 65800 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h
new file mode 100644
index 00000000..52dc3f24
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __ACR_FLCNBL_H__
+#define __ACR_FLCNBL_H__
+
+#include <nvgpu/flcnif_cmn.h>
+
+#ifndef __NVGPU_ACR_H__
+#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \
+        "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
+#endif
+
+/*
+ * Structure used by the boot-loader to load the rest of the code. This has
+ * to be filled by NVGPU and copied into DMEM at offset provided in the
+ * hsflcn_bl_desc.bl_desc_dmem_load_off.
+ */
+struct flcn_bl_dmem_desc {
+        u32    reserved[4];        /*Should be the first element..*/
+        u32    signature[4];        /*Should be the first element..*/
+        u32    ctx_dma;
+        u32    code_dma_base;
+        u32    non_sec_code_off;
+        u32    non_sec_code_size;
+        u32    sec_code_off;
+        u32    sec_code_size;
+        u32    code_entry_point;
+        u32    data_dma_base;
+        u32    data_size;
+        u32    code_dma_base1;
+        u32    data_dma_base1;
+};
+
+struct flcn_bl_dmem_desc_v1 {
+        u32    reserved[4];        /*Should be the first element..*/
+        u32    signature[4];        /*Should be the first element..*/
+        u32    ctx_dma;
+        struct falc_u64 code_dma_base;
+        u32    non_sec_code_off;
+        u32    non_sec_code_size;
+        u32    sec_code_off;
+        u32    sec_code_size;
+        u32    code_entry_point;
+        struct falc_u64 data_dma_base;
+        u32    data_size;
+        u32 argc;
+        u32 argv;
+};
+
+/*
+ * The header used by NVGPU to figure out code and data sections of bootloader
+ *
+ * bl_code_off        - Offset of code section in the image
+ * bl_code_size          - Size of code section in the image
+ * bl_data_off        - Offset of data section in the image
+ * bl_data_size          - Size of data section in the image
+ */
+struct flcn_bl_img_hdr {
+        u32 bl_code_off;
+        u32 bl_code_size;
+        u32 bl_data_off;
+        u32 bl_data_size;
+};
+
+/*
+ * The descriptor used by NVGPU to figure out the requirements of bootloader
+ *
+ * bl_start_tag - Starting tag of bootloader
+ * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
+ * to be loaded
+ * bl_img_hdr - Description of the image
+ */
+struct hsflcn_bl_desc {
+        u32 bl_start_tag;
+        u32 bl_desc_dmem_load_off;
+        struct flcn_bl_img_hdr bl_img_hdr;
+};
+
+/*
+ * Legacy structure used by the current PMU/DPU bootloader.
+ */
+struct loader_config {
+        u32 dma_idx;
+        u32 code_dma_base;     /* upper 32-bits of 40-bit dma address */
+        u32 code_size_total;
+        u32 code_size_to_load;
+        u32 code_entry_point;
+        u32 data_dma_base;     /* upper 32-bits of 40-bit dma address */
+        u32 data_size;         /* initialized data of the application  */
+        u32 overlay_dma_base;  /* upper 32-bits of the 40-bit dma address */
+        u32 argc;
+        u32 argv;
+        u16 code_dma_base1;    /* upper 7 bits of 47-bit dma address */
+        u16 data_dma_base1;    /* upper 7 bits of 47-bit dma address */
+        u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */
+};
+
+struct loader_config_v1 {
+        u32 reserved;
+        u32 dma_idx;
+        struct falc_u64 code_dma_base;
+        u32 code_size_total;
+        u32 code_size_to_load;
+        u32 code_entry_point;
+        struct falc_u64 data_dma_base;
+        u32 data_size;
+        struct falc_u64 overlay_dma_base;
+        u32 argc;
+        u32 argv;
+};
+
+/*
+ * Union of all supported structures used by bootloaders.
+ */
+union flcn_bl_generic_desc {
+        struct flcn_bl_dmem_desc bl_dmem_desc;
+        struct loader_config loader_cfg;
+};
+
+union flcn_bl_generic_desc_v1 {
+        struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
+        struct loader_config_v1 loader_cfg_v1;
+};
+
+#endif /* __ACR_FLCNBL_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
new file mode 100644
index 00000000..70184934
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __ACR_LSFM_H__
+#define __ACR_LSFM_H__
+
+#ifndef __NVGPU_ACR_H__
+#warning "acr_lsfm.h not included from nvgpu_acr.h!" \
+        "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
+#endif
+
+/*
+ * Falcon Id Defines
+ * Defines a common Light Secure Falcon identifier.
+ */
+#define LSF_FALCON_ID_PMU       (0)
+#define LSF_FALCON_ID_RESERVED  (1)
+#define LSF_FALCON_ID_FECS      (2)
+#define LSF_FALCON_ID_GPCCS     (3)
+#define LSF_FALCON_ID_SEC2      (7)
+#define LSF_FALCON_ID_END       (11)
+#define LSF_FALCON_ID_INVALID   (0xFFFFFFFF)
+
+/*
+ * Light Secure Falcon Ucode Description Defines
+ * This structure is prelim and may change as the ucode signing flow evolves.
+ */
+struct lsf_ucode_desc {
+        u8  prd_keys[2][16];
+        u8  dbg_keys[2][16];
+        u32 b_prd_present;
+        u32 b_dbg_present;
+        u32 falcon_id;
+};
+
+struct lsf_ucode_desc_v1 {
+        u8  prd_keys[2][16];
+        u8  dbg_keys[2][16];
+        u32 b_prd_present;
+        u32 b_dbg_present;
+        u32 falcon_id;
+        u32 bsupports_versioning;
+        u32 version;
+        u32 dep_map_count;
+        u8  dep_map[LSF_FALCON_ID_END * 2 * 4];
+        u8  kdf[16];
+};
+
+/*
+ * Light Secure WPR Header
+ * Defines state allowing Light Secure Falcon bootstrapping.
+ */
+struct lsf_wpr_header {
+        u32 falcon_id;
+        u32 lsb_offset;
+        u32 bootstrap_owner;
+        u32 lazy_bootstrap;
+        u32 status;
+};
+
+struct lsf_wpr_header_v1 {
+        u32 falcon_id;
+        u32 lsb_offset;
+        u32 bootstrap_owner;
+        u32 lazy_bootstrap;
+        u32 bin_version;
+        u32 status;
+};
+/*
+ * Bootstrap Owner Defines
+ */
+#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU)
+
+/*
+ * Image Status Defines
+ */
+#define LSF_IMAGE_STATUS_NONE                           (0)
+#define LSF_IMAGE_STATUS_COPY                           (1)
+#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED         (2)
+#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED         (3)
+#define LSF_IMAGE_STATUS_VALIDATION_DONE                (4)
+#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED             (5)
+#define LSF_IMAGE_STATUS_BOOTSTRAP_READY                (6)
+
+/*Light Secure Bootstrap header related defines*/
+#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE       0
+#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE        1
+#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE       0
+#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE        4
+#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE       8
+#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE      0
+
+/*
+ * Light Secure Bootstrap Header
+ * Defines state allowing Light Secure Falcon bootstrapping.
+ */
+struct lsf_lsb_header {
+        struct lsf_ucode_desc signature;
+        u32 ucode_off;
+        u32 ucode_size;
+        u32 data_size;
+        u32 bl_code_size;
+        u32 bl_imem_off;
+        u32 bl_data_off;
+        u32 bl_data_size;
+        u32 app_code_off;
+        u32 app_code_size;
+        u32 app_data_off;
+        u32 app_data_size;
+        u32 flags;
+};
+
+struct lsf_lsb_header_v1 {
+        struct lsf_ucode_desc_v1 signature;
+        u32 ucode_off;
+        u32 ucode_size;
+        u32 data_size;
+        u32 bl_code_size;
+        u32 bl_imem_off;
+        u32 bl_data_off;
+        u32 bl_data_size;
+        u32 app_code_off;
+        u32 app_code_size;
+        u32 app_data_off;
+        u32 app_data_size;
+        u32 flags;
+};
+
+/*
+ * Light Secure WPR Content Alignments
+ */
+#define LSF_LSB_HEADER_ALIGNMENT    256
+#define LSF_BL_DATA_ALIGNMENT       256
+#define LSF_BL_DATA_SIZE_ALIGNMENT  256
+#define LSF_BL_CODE_SIZE_ALIGNMENT  256
+
+#define LSF_UCODE_DATA_ALIGNMENT 4096
+
+/*
+ * Supporting maximum of 2 regions.
+ * This is needed to pre-allocate space in DMEM
+ */
+#define NVGPU_FLCN_ACR_MAX_REGIONS                (2)
+#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE    (0x200)
+
+/*
+ * start_addr     - Starting address of region
+ * end_addr       - Ending address of region
+ * region_id      - Region ID
+ * read_mask      - Read Mask
+ * write_mask     - WriteMask
+ * client_mask    - Bit map of all clients currently using this region
+ */
+struct flcn_acr_region_prop {
+        u32 start_addr;
+        u32 end_addr;
+        u32 region_id;
+        u32 read_mask;
+        u32 write_mask;
+        u32 client_mask;
+};
+
+struct flcn_acr_region_prop_v1 {
+        u32 start_addr;
+        u32 end_addr;
+        u32 region_id;
+        u32 read_mask;
+        u32 write_mask;
+        u32 client_mask;
+        u32 shadowmMem_startaddress;
+};
+
+/*
+ * no_regions   - Number of regions used.
+ * region_props   - Region properties
+ */
+struct flcn_acr_regions {
+        u32 no_regions;
+        struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
+};
+
+struct flcn_acr_regions_v1 {
+        u32 no_regions;
+        struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
+};
+/*
+ * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons,
+ *                and need to switch into LS mode, it needs to have its own
+ *                actual DMEM image copied into DMEM as part of LS setup. If
+ *                ACR desc is at location 0, it will definitely get overwritten
+ *                causing data corruption. Hence we are reserving 0x200 bytes
+ *                to give room for any loading data. NOTE: This has to be the
+ *                first member always
+ * signature    - Signature of ACR ucode.
+ * wpr_region_id - Region ID holding the WPR header and its details
+ * wpr_offset    - Offset from the WPR region holding the wpr header
+ * regions       - Region descriptors
+ * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
+ * nonwpr_ucode_blob_end   -stores non-WPR end where kernel stores ucode blob
+ */
+struct flcn_acr_desc {
+        union {
+                u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
+                u32 signatures[4];
+        } ucode_reserved_space;
+        /*Always 1st*/
+        u32 wpr_region_id;
+        u32 wpr_offset;
+        u32 mmu_mem_range;
+        struct flcn_acr_regions regions;
+        u32 nonwpr_ucode_blob_size;
+        u64 nonwpr_ucode_blob_start;
+};
+
+struct flcn_acr_desc_v1 {
+        union {
+                u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
+        } ucode_reserved_space;
+        u32 signatures[4];
+        /*Always 1st*/
+        u32 wpr_region_id;
+        u32 wpr_offset;
+        u32 mmu_mem_range;
+        struct flcn_acr_regions_v1 regions;
+        u32 nonwpr_ucode_blob_size;
+        u64 nonwpr_ucode_blob_start;
+        u32 dummy[4];  /* ACR_BSI_VPR_DESC */
+};
+
+
+#endif /* __ACR_LSFM_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h
new file mode 100644
index 00000000..951eb3c6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __ACR_OBJFLCN_H__
+#define __ACR_OBJFLCN_H__
+
+#ifndef __NVGPU_ACR_H__
+#warning "acr_objflcn.h not included from nvgpu_acr.h!" \
+        "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
+#endif
+
+struct flcn_ucode_img {
+        u32 *header; /* only some falcons have header */
+        u32 *data;
+        struct pmu_ucode_desc *desc; /* only some falcons have descriptor */
+        u32 data_size;
+        void *fw_ver; /* CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct */
+        u8 load_entire_os_data; /* load the whole osData section at boot time.*/
+        /* NULL if not a light secure falcon.*/
+        struct lsf_ucode_desc *lsf_desc;
+        /* True if there a resources to freed by the client. */
+        u8 free_res_allocs;
+        u32 flcn_inst;
+};
+
+struct flcn_ucode_img_v1 {
+        u32 *header;
+        u32 *data;
+        struct pmu_ucode_desc_v1 *desc;
+        u32 data_size;
+        void *fw_ver;
+        u8 load_entire_os_data;
+        struct lsf_ucode_desc_v1 *lsf_desc;
+        u8 free_res_allocs;
+        u32 flcn_inst;
+};
+
+/*
+ * Falcon UCODE header index.
+ */
+#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND              (0)
+#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND             (1)
+#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND              (2)
+#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND             (3)
+#define FLCN_NL_UCODE_HDR_NUM_APPS_IND                 (4)
+
+/*
+ * There are total N number of Apps with code and offset defined in UCODE header
+ * This macro provides the CODE and DATA offset and size of Ath application.
+ */
+#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND           (5)
+#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \
+        (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2))
+#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \
+        (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1)
+#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \
+        (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1)
+
+#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \
+        (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1)
+#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \
+        (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2))
+#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \
+        (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1)
+#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \
+        (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1)
+
+#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \
+        (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1)
+#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \
+        (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2)
+
+#endif /* __ACR_OBJFLCN_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h
new file mode 100644
index 00000000..cde8707a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __ACR_OBJLSFM_H__
+#define __ACR_OBJLSFM_H__
+
+#ifndef __NVGPU_ACR_H__
+#warning "acr_objlsfm.h not included from nvgpu_acr.h!" \
+        "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
+#endif
+
+#include "acr_flcnbl.h"
+#include "acr_objflcn.h"
+
+/*
+ * LSFM Managed Ucode Image
+ * next             : Next image the list, NULL if last.
+ * wpr_header         : WPR header for this ucode image
+ * lsb_header         : LSB header for this ucode image
+ * bl_gen_desc     : Bootloader generic desc structure for this ucode image
+ * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image
+ * full_ucode_size  : Surface size required for final ucode image
+ * ucode_img        : Ucode image info
+ */
+struct lsfm_managed_ucode_img {
+        struct lsfm_managed_ucode_img *next;
+        struct lsf_wpr_header wpr_header;
+        struct lsf_lsb_header lsb_header;
+        union flcn_bl_generic_desc bl_gen_desc;
+        u32 bl_gen_desc_size;
+        u32 full_ucode_size;
+        struct flcn_ucode_img ucode_img;
+};
+
+struct lsfm_managed_ucode_img_v2 {
+        struct lsfm_managed_ucode_img_v2 *next;
+        struct lsf_wpr_header_v1 wpr_header;
+        struct lsf_lsb_header_v1 lsb_header;
+        union flcn_bl_generic_desc_v1 bl_gen_desc;
+        u32 bl_gen_desc_size;
+        u32 full_ucode_size;
+        struct flcn_ucode_img_v1 ucode_img;
+};
+
+/*
+ * Defines the structure used to contain all generic information related to
+ * the LSFM.
+ * Contains the Light Secure Falcon Manager (LSFM) feature related data.
+ */
+struct ls_flcn_mgr {
+        u16 managed_flcn_cnt;
+        u32 wpr_size;
+        u32 disable_mask;
+        struct lsfm_managed_ucode_img *ucode_img_list;
+        void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
+};
+
+struct ls_flcn_mgr_v1 {
+        u16 managed_flcn_cnt;
+        u32 wpr_size;
+        u32 disable_mask;
+        struct lsfm_managed_ucode_img_v2 *ucode_img_list;
+        void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
+};
+
+
+#endif /* __ACR_OBJLSFM_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
new file mode 100644
index 00000000..a9ed6e68
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_ACR_H__
+#define __NVGPU_ACR_H__
+
+#include "gk20a/mm_gk20a.h"
+
+#include "acr_lsfm.h"
+#include "acr_flcnbl.h"
+#include "acr_objlsfm.h"
+#include "acr_objflcn.h"
+
+struct nvgpu_firmware;
+
+#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
+
+#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */
+
+#define PMU_SECURE_MODE (0x1)
+#define PMU_LSFM_MANAGED (0x2)
+
+struct bin_hdr {
+        /* 0x10de */
+        u32 bin_magic;
+        /* versioning of bin format */
+        u32 bin_ver;
+        /* Entire image size including this header */
+        u32 bin_size;
+        /*
+         * Header offset of executable binary metadata,
+         * start @ offset- 0x100 *
+         */
+        u32 header_offset;
+        /*
+         * Start of executable binary data, start @
+         * offset- 0x200
+         */
+        u32 data_offset;
+        /* Size of executable binary */
+        u32 data_size;
+};
+
+struct acr_fw_header {
+        u32 sig_dbg_offset;
+        u32 sig_dbg_size;
+        u32 sig_prod_offset;
+        u32 sig_prod_size;
+        u32 patch_loc;
+        u32 patch_sig;
+        u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */
+        u32 hdr_size; /* Size of above header */
+};
+
+struct wpr_carveout_info {
+        u64 wpr_base;
+        u64 nonwpr_base;
+        u64 size;
+};
+
+struct acr_desc {
+        struct nvgpu_mem ucode_blob;
+        struct nvgpu_mem wpr_dummy;
+        struct bin_hdr *bl_bin_hdr;
+        struct hsflcn_bl_desc *pmu_hsbl_desc;
+        struct bin_hdr *hsbin_hdr;
+        struct acr_fw_header *fw_hdr;
+        u32 pmu_args;
+        struct nvgpu_firmware *acr_fw;
+        union{
+                struct flcn_acr_desc *acr_dmem_desc;
+                struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
+        };
+        struct nvgpu_mem acr_ucode;
+        struct nvgpu_firmware *hsbl_fw;
+        struct nvgpu_mem hsbl_ucode;
+        union {
+                struct flcn_bl_dmem_desc bl_dmem_desc;
+                struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
+        };
+        struct nvgpu_firmware *pmu_fw;
+        struct nvgpu_firmware *pmu_desc;
+        u32 capabilities;
+};
+
+#endif /*__NVGPU_ACR_H__*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/allocator.h b/drivers/gpu/nvgpu/include/nvgpu/allocator.h
new file mode 100644
index 00000000..1e7ab38f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/allocator.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_ALLOCATOR_H__
+#define __NVGPU_ALLOCATOR_H__
+
+#ifdef __KERNEL__
+/*
+ * The Linux kernel has this notion of seq_files for printing info to userspace.
+ * One of the allocator function pointers takes advantage of this and allows the
+ * debug output to be directed either to nvgpu_log() or a seq_file.
+ */
+#include <linux/seq_file.h>
+#endif
+
+#include <nvgpu/log.h>
+#include <nvgpu/lock.h>
+#include <nvgpu/list.h>
+#include <nvgpu/types.h>
+
+/* #define ALLOCATOR_DEBUG */
+
+struct nvgpu_allocator;
+struct nvgpu_alloc_carveout;
+struct vm_gk20a;
+struct gk20a;
+
+/*
+ * Operations for an allocator to implement.
+ */
+struct nvgpu_allocator_ops {
+        u64  (*alloc)(struct nvgpu_allocator *allocator, u64 len);
+        void (*free)(struct nvgpu_allocator *allocator, u64 addr);
+
+        /*
+         * Special interface to allocate a memory region with a specific
+         * starting address. Yikes. Note: if free() works for freeing both
+         * regular and fixed allocations then free_fixed() does not need to
+         * be implemented. This behavior exists for legacy reasons and should
+         * not be propagated to new allocators.
+         *
+         * For allocators where the @page_size field is not applicable it can
+         * be left as 0. Otherwise a valid page size should be passed (4k or
+         * what the large page size is).
+         */
+        u64  (*alloc_fixed)(struct nvgpu_allocator *allocator,
+                            u64 base, u64 len, u32 page_size);
+        void (*free_fixed)(struct nvgpu_allocator *allocator,
+                           u64 base, u64 len);
+
+        /*
+         * Allow allocators to reserve space for carveouts.
+         */
+        int  (*reserve_carveout)(struct nvgpu_allocator *allocator,
+                                 struct nvgpu_alloc_carveout *co);
+        void (*release_carveout)(struct nvgpu_allocator *allocator,
+                                 struct nvgpu_alloc_carveout *co);
+
+        /*
+         * Returns info about the allocator.
+         */
+        u64  (*base)(struct nvgpu_allocator *allocator);
+        u64  (*length)(struct nvgpu_allocator *allocator);
+        u64  (*end)(struct nvgpu_allocator *allocator);
+        int  (*inited)(struct nvgpu_allocator *allocator);
+        u64  (*space)(struct nvgpu_allocator *allocator);
+
+        /* Destructor. */
+        void (*fini)(struct nvgpu_allocator *allocator);
+
+#ifdef __KERNEL__
+        /* Debugging. */
+        void (*print_stats)(struct nvgpu_allocator *allocator,
+                            struct seq_file *s, int lock);
+#endif
+};
+
+struct nvgpu_allocator {
+        struct gk20a *g;
+
+        char name[32];
+        struct nvgpu_mutex lock;
+
+        void *priv;
+        const struct nvgpu_allocator_ops *ops;
+
+        struct dentry *debugfs_entry;
+        bool debug;                             /* Control for debug msgs. */
+};
+
+struct nvgpu_alloc_carveout {
+        const char *name;
+        u64 base;
+        u64 length;
+
+        struct nvgpu_allocator *allocator;
+
+        /*
+         * For usage by the allocator implementation.
+         */
+        struct nvgpu_list_node co_entry;
+};
+
+static inline struct nvgpu_alloc_carveout *
+nvgpu_alloc_carveout_from_co_entry(struct nvgpu_list_node *node)
+{
+        return (struct nvgpu_alloc_carveout *)
+        ((uintptr_t)node - offsetof(struct nvgpu_alloc_carveout, co_entry));
+};
+
+#define NVGPU_CARVEOUT(__name, __base, __length)        \
+        {                                               \
+                .name = (__name),                       \
+                .base = (__base),                       \
+                .length = (__length)                    \
+        }
+
+/*
+ * These are the available allocator flags.
+ *
+ *   GPU_ALLOC_GVA_SPACE
+ *
+ *     This flag makes sense for the buddy allocator only. It specifies that the
+ *     allocator will be used for managing a GVA space. When managing GVA spaces
+ *     special care has to be taken to ensure that allocations of similar PTE
+ *     sizes are placed in the same PDE block. This allows the higher level
+ *     code to skip defining both small and large PTE tables for every PDE. That
+ *     can save considerable memory for address spaces that have a lot of
+ *     allocations.
+ *
+ *   GPU_ALLOC_NO_ALLOC_PAGE
+ *
+ *     For any allocator that needs to manage a resource in a latency critical
+ *     path this flag specifies that the allocator should not use any kmalloc()
+ *     or similar functions during normal operation. Initialization routines
+ *     may still use kmalloc(). This prevents the possibility of long waits for
+ *     pages when using alloc_page(). Currently only the bitmap allocator
+ *     implements this functionality.
+ *
+ *     Also note that if you accept this flag then you must also define the
+ *     free_fixed() function. Since no meta-data is allocated to help free
+ *     allocations you need to keep track of the meta-data yourself (in this
+ *     case the base and length of the allocation as opposed to just the base
+ *     of the allocation).
+ *
+ *   GPU_ALLOC_4K_VIDMEM_PAGES
+ *
+ *     We manage vidmem pages at a large page granularity for performance
+ *     reasons; however, this can lead to wasting memory. For page allocators
+ *     setting this flag will tell the allocator to manage pools of 4K pages
+ *     inside internally allocated large pages.
+ *
+ *     Currently this flag is ignored since the only usage of the page allocator
+ *     uses a 4K block size already. However, this flag has been reserved since
+ *     it will be necessary in the future.
+ *
+ *   GPU_ALLOC_FORCE_CONTIG
+ *
+ *     Force allocations to be contiguous. Currently only relevant for page
+ *     allocators since all other allocators are naturally contiguous.
+ *
+ *   GPU_ALLOC_NO_SCATTER_GATHER
+ *
+ *     The page allocator normally returns a scatter gather data structure for
+ *     allocations (to handle discontiguous pages). However, at times that can
+ *     be annoying so this flag forces the page allocator to return a u64
+ *     pointing to the allocation base (requires GPU_ALLOC_FORCE_CONTIG to be
+ *     set as well).
+ */
+#define GPU_ALLOC_GVA_SPACE             0x1
+#define GPU_ALLOC_NO_ALLOC_PAGE         0x2
+#define GPU_ALLOC_4K_VIDMEM_PAGES       0x4
+#define GPU_ALLOC_FORCE_CONTIG          0x8
+#define GPU_ALLOC_NO_SCATTER_GATHER     0x10
+
+static inline void alloc_lock(struct nvgpu_allocator *a)
+{
+        nvgpu_mutex_acquire(&a->lock);
+}
+
+static inline void alloc_unlock(struct nvgpu_allocator *a)
+{
+        nvgpu_mutex_release(&a->lock);
+}
+
+/*
+ * Buddy allocator specific initializers.
+ */
+int  __nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *a,
+                                  struct vm_gk20a *vm, const char *name,
+                                  u64 base, u64 size, u64 blk_size,
+                                  u64 max_order, u64 flags);
+int  nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *a,
+                                const char *name, u64 base, u64 size,
+                                u64 blk_size, u64 flags);
+
+/*
+ * Bitmap initializers.
+ */
+int nvgpu_bitmap_allocator_init(struct gk20a *g, struct nvgpu_allocator *a,
+                                const char *name, u64 base, u64 length,
+                                u64 blk_size, u64 flags);
+
+/*
+ * Page allocator initializers.
+ */
+int nvgpu_page_allocator_init(struct gk20a *g, struct nvgpu_allocator *a,
+                              const char *name, u64 base, u64 length,
+                              u64 blk_size, u64 flags);
+
+/*
+ * Lockless allocatior initializers.
+ * Note: This allocator can only allocate fixed-size structures of a
+ * pre-defined size.
+ */
+int nvgpu_lockless_allocator_init(struct gk20a *g, struct nvgpu_allocator *a,
+                                  const char *name, u64 base, u64 length,
+                                  u64 struct_size, u64 flags);
+
+#define GPU_BALLOC_MAX_ORDER            31
+
+/*
+ * Allocator APIs.
+ */
+u64  nvgpu_alloc(struct nvgpu_allocator *allocator, u64 len);
+void nvgpu_free(struct nvgpu_allocator *allocator, u64 addr);
+
+u64  nvgpu_alloc_fixed(struct nvgpu_allocator *allocator, u64 base, u64 len,
+                       u32 page_size);
+void nvgpu_free_fixed(struct nvgpu_allocator *allocator, u64 base, u64 len);
+
+int  nvgpu_alloc_reserve_carveout(struct nvgpu_allocator *a,
+                                  struct nvgpu_alloc_carveout *co);
+void nvgpu_alloc_release_carveout(struct nvgpu_allocator *a,
+                                  struct nvgpu_alloc_carveout *co);
+
+u64  nvgpu_alloc_base(struct nvgpu_allocator *a);
+u64  nvgpu_alloc_length(struct nvgpu_allocator *a);
+u64  nvgpu_alloc_end(struct nvgpu_allocator *a);
+u64  nvgpu_alloc_initialized(struct nvgpu_allocator *a);
+u64  nvgpu_alloc_space(struct nvgpu_allocator *a);
+
+void nvgpu_alloc_destroy(struct nvgpu_allocator *allocator);
+
+#ifdef __KERNEL__
+void nvgpu_alloc_print_stats(struct nvgpu_allocator *a,
+                             struct seq_file *s, int lock);
+#endif
+
+static inline struct gk20a *nvgpu_alloc_to_gpu(struct nvgpu_allocator *a)
+{
+        return a->g;
+}
+
+#ifdef CONFIG_DEBUG_FS
+/*
+ * Common functionality for the internals of the allocators.
+ */
+void nvgpu_init_alloc_debug(struct gk20a *g, struct nvgpu_allocator *a);
+void nvgpu_fini_alloc_debug(struct nvgpu_allocator *a);
+#endif
+
+int  __nvgpu_alloc_common_init(struct nvgpu_allocator *a, struct gk20a *g,
+                               const char *name, void *priv, bool dbg,
+                               const struct nvgpu_allocator_ops *ops);
+
+static inline void nvgpu_alloc_enable_dbg(struct nvgpu_allocator *a)
+{
+        a->debug = true;
+}
+
+static inline void nvgpu_alloc_disable_dbg(struct nvgpu_allocator *a)
+{
+        a->debug = false;
+}
+
+/*
+ * Debug stuff.
+ */
+#ifdef __KERNEL__
+#define __alloc_pstat(seq, allocator, fmt, arg...)              \
+        do {                                                    \
+                if (seq)                                        \
+                        seq_printf(seq, fmt, ##arg);            \
+                else                                            \
+                        alloc_dbg(allocator, fmt, ##arg);       \
+        } while (0)
+#endif
+
+#define __alloc_dbg(a, fmt, arg...)                             \
+        nvgpu_log((a)->g, gpu_dbg_alloc, "%25s " fmt, (a)->name, ##arg)
+
+/*
+ * This gives finer control over debugging messages. By defining the
+ * ALLOCATOR_DEBUG macro prints for an allocator will only get made if
+ * that allocator's debug flag is set.
+ *
+ * Otherwise debugging is as normal: debug statements for all allocators
+ * if the GPU debugging mask bit is set. Note: even when ALLOCATOR_DEBUG
+ * is set gpu_dbg_alloc must still also be set to true.
+ */
+#if defined(ALLOCATOR_DEBUG)
+#define alloc_dbg(a, fmt, arg...)                               \
+        do {                                                    \
+                if ((a)->debug)                                 \
+                        __alloc_dbg((a), fmt, ##arg);           \
+        } while (0)
+#else
+#define alloc_dbg(a, fmt, arg...) __alloc_dbg(a, fmt, ##arg)
+#endif
+
+#endif /* NVGPU_ALLOCATOR_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/as.h b/drivers/gpu/nvgpu/include/nvgpu/as.h
new file mode 100644
index 00000000..03799717
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/as.h
@@ -0,0 +1,45 @@
+/*
+ * GK20A Address Spaces
+ *
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_AS_H__
+#define __NVGPU_AS_H__
+
+struct vm_gk20a;
+
+struct gk20a_as {
+        int last_share_id; /* dummy allocator for now */
+};
+
+struct gk20a_as_share {
+        struct gk20a_as *as;
+        struct vm_gk20a *vm;
+        int id;
+};
+
+int gk20a_as_release_share(struct gk20a_as_share *as_share);
+
+/* if big_page_size == 0, the default big page size is used */
+int gk20a_as_alloc_share(struct gk20a *g, u32 big_page_size,
+                         u32 flags, struct gk20a_as_share **out);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/atomic.h
new file mode 100644
index 00000000..0f319f71
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/atomic.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_ATOMIC_H__
+#define __NVGPU_ATOMIC_H__
+
+#ifdef __KERNEL__
+#include <nvgpu/linux/atomic.h>
+#else
+#include <nvgpu_rmos/include/atomic.h>
+#endif
+
+#define NVGPU_ATOMIC_INIT(i)    __nvgpu_atomic_init(i)
+#define NVGPU_ATOMIC64_INIT(i)  __nvgpu_atomic64_init(i)
+
+static inline void nvgpu_atomic_set(nvgpu_atomic_t *v, int i)
+{
+        __nvgpu_atomic_set(v, i);
+}
+static inline int nvgpu_atomic_read(nvgpu_atomic_t *v)
+{
+        return __nvgpu_atomic_read(v);
+}
+static inline void nvgpu_atomic_inc(nvgpu_atomic_t *v)
+{
+        __nvgpu_atomic_inc(v);
+}
+static inline int nvgpu_atomic_inc_return(nvgpu_atomic_t *v)
+{
+        return __nvgpu_atomic_inc_return(v);
+}
+static inline void nvgpu_atomic_dec(nvgpu_atomic_t *v)
+{
+         __nvgpu_atomic_dec(v);
+}
+static inline int nvgpu_atomic_dec_return(nvgpu_atomic_t *v)
+{
+        return __nvgpu_atomic_dec_return(v);
+}
+static inline int nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new)
+{
+        return __nvgpu_atomic_cmpxchg(v, old, new);
+}
+static inline int nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new)
+{
+        return __nvgpu_atomic_xchg(v, new);
+}
+static inline bool nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v)
+{
+        return __nvgpu_atomic_inc_and_test(v);
+}
+static inline bool nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v)
+{
+        return __nvgpu_atomic_dec_and_test(v);
+}
+static inline bool nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v)
+{
+        return __nvgpu_atomic_sub_and_test(i, v);
+}
+static inline int nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v)
+{
+        return __nvgpu_atomic_add_return(i, v);
+}
+static inline int nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u)
+{
+        return __nvgpu_atomic_add_unless(v, a, u);
+}
+static inline void nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i)
+{
+        return  __nvgpu_atomic64_set(v, i);
+}
+static inline long nvgpu_atomic64_read(nvgpu_atomic64_t *v)
+{
+        return  __nvgpu_atomic64_read(v);
+}
+static inline void nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v)
+{
+        __nvgpu_atomic64_add(x, v);
+}
+static inline void nvgpu_atomic64_inc(nvgpu_atomic64_t *v)
+{
+        __nvgpu_atomic64_inc(v);
+}
+static inline long nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v)
+{
+        return __nvgpu_atomic64_inc_return(v);
+}
+static inline void nvgpu_atomic64_dec(nvgpu_atomic64_t *v)
+{
+        __nvgpu_atomic64_dec(v);
+}
+static inline void nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v)
+{
+        __nvgpu_atomic64_dec_return(v);
+}
+static inline long nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, long old,
+                                        long new)
+{
+        return __nvgpu_atomic64_cmpxchg(v, old, new);
+}
+static inline void nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v)
+{
+        __nvgpu_atomic64_sub(x, v);
+}
+static inline long nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v)
+{
+        return __nvgpu_atomic64_sub_return(x, v);
+}
+
+#endif /* __NVGPU_ATOMIC_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/barrier.h b/drivers/gpu/nvgpu/include/nvgpu/barrier.h
new file mode 100644
index 00000000..01bd3023
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/barrier.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/* This file contains NVGPU_* high-level abstractions for various
+ * memor-barrier operations available in linux/kernel. Every OS
+ * should provide their own OS specific calls under this common API
+ */
+
+#ifndef __NVGPU_BARRIER_H__
+#define __NVGPU_BARRIER_H__
+
+#ifdef __KERNEL__
+#include <nvgpu/linux/barrier.h>
+#else
+#include <nvgpu_rmos/include/barrier.h>
+#endif
+
+#define nvgpu_mb()      __nvgpu_mb()
+#define nvgpu_rmb()     __nvgpu_rmb()
+#define nvgpu_wmb()     __nvgpu_wmb()
+
+#define nvgpu_smp_mb()  __nvgpu_smp_mb()
+#define nvgpu_smp_rmb() __nvgpu_smp_rmb()
+#define nvgpu_smp_wmb() __nvgpu_smp_wmb()
+
+#define nvgpu_read_barrier_depends() __nvgpu_read_barrier_depends()
+#define nvgpu_smp_read_barrier_depends() __nvgpu_smp_read_barrier_depends()
+
+#define NV_ACCESS_ONCE(x)       __NV_ACCESS_ONCE(x)
+
+#endif /* __NVGPU_BARRIER_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
new file mode 100644
index 00000000..a4823caa
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -0,0 +1,1055 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_BIOS_H
+#define NVGPU_BIOS_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+#define PERF_PTRS_WIDTH 0x4
+#define PERF_PTRS_WIDTH_16 0x2
+
+enum {
+        CLOCKS_TABLE = 2,
+        CLOCK_PROGRAMMING_TABLE,
+        FLL_TABLE,
+        VIN_TABLE,
+        FREQUENCY_CONTROLLER_TABLE
+};
+
+enum {
+        PERFORMANCE_TABLE = 0,
+        MEMORY_CLOCK_TABLE,
+        MEMORY_TWEAK_TABLE,
+        POWER_CONTROL_TABLE,
+        THERMAL_CONTROL_TABLE,
+        THERMAL_DEVICE_TABLE,
+        THERMAL_COOLERS_TABLE,
+        PERFORMANCE_SETTINGS_SCRIPT,
+        CONTINUOUS_VIRTUAL_BINNING_TABLE,
+        POWER_SENSORS_TABLE = 0xA,
+        POWER_CAPPING_TABLE = 0xB,
+        POWER_TOPOLOGY_TABLE = 0xF,
+        THERMAL_CHANNEL_TABLE = 0x12,
+        VOLTAGE_RAIL_TABLE = 26,
+        VOLTAGE_DEVICE_TABLE,
+        VOLTAGE_POLICY_TABLE,
+        LOWPOWER_TABLE,
+        LOWPOWER_GR_TABLE = 32,
+        LOWPOWER_MS_TABLE = 33,
+};
+
+enum {
+        VP_FIELD_TABLE = 0,
+        VP_FIELD_REGISTER,
+        VP_TRANSLATION_TABLE,
+};
+
+struct bit_token {
+        u8 token_id;
+        u8 data_version;
+        u16 data_size;
+        u16 data_ptr;
+} __packed;
+
+#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT)
+
+struct fll_descriptor_header {
+        u8 version;
+        u8 size;
+} __packed;
+
+#define FLL_DESCRIPTOR_HEADER_10_SIZE_4     4
+#define FLL_DESCRIPTOR_HEADER_10_SIZE_6     6
+
+struct fll_descriptor_header_10 {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u16 max_min_freq_mhz;
+} __packed;
+
+#define FLL_DESCRIPTOR_ENTRY_10_SIZE     15
+
+struct fll_descriptor_entry_10 {
+        u8 fll_device_type;
+        u8 clk_domain;
+        u8 fll_device_id;
+        u16 lut_params;
+        u8 vin_idx_logic;
+        u8 vin_idx_sram;
+        u16 fll_params;
+        u8 min_freq_vfe_idx;
+        u8 freq_ctrl_idx;
+        u16 ref_freq_mhz;
+        u16 ffr_cutoff_freq_mhz;
+} __packed;
+
+#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F
+#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0
+
+#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3
+#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0
+
+#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C
+#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2
+
+struct vin_descriptor_header_10 {
+        u8 version;
+        u8 header_sizee;
+        u8 entry_size;
+        u8 entry_count;
+        u8 flags0;
+        u32 vin_cal;
+} __packed;
+
+struct vin_descriptor_entry_10 {
+        u8 vin_device_type;
+        u8 volt_domain_vbios;
+        u8 vin_device_id;
+} __packed;
+
+#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7
+#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0
+
+#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8
+#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3
+
+#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF
+#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0
+
+#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00
+#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT  10
+
+#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000
+#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14
+
+#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000
+#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18
+
+#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07
+struct vbios_clocks_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u8 clocks_hal;
+        u16 cntr_sampling_periodms;
+} __packed;
+
+#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09                                 0x09
+struct vbios_clocks_table_1x_entry {
+        u8 flags0;
+        u16 param0;
+        u32 param1;
+        u16 param2;
+} __packed;
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK                    0x1F
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT                   0
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED                   0x00
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER                  0x01
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE                   0x02
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK  0xFF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT  0
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK  0xFF00
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK        0xFFFF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT       0
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK         0xF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT       0
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK     0xF0
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT   4
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE   0x00
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE    0x01
+
+#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08                              0x08
+struct vbios_clock_programming_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u8 slave_entry_size;
+        u8 slave_entry_count;
+        u8 vf_entry_size;
+        u8 vf_entry_count;
+} __packed;
+
+#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05                      0x05
+#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D                      0x0D
+struct vbios_clock_programming_table_1x_entry {
+        u8 flags0;
+        u16 freq_max_mhz;
+        u8 param0;
+        u8 param1;
+        u32 rsvd;
+        u32 rsvd1;
+} __packed;
+
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK          0xF
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT         0
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO   0x00
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE   0x01
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE          0x02
+
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK          0x70
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT         4
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL          0x00
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE   0x01
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL        0x02
+
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK    0x80
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT   7
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE  0x00
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE   0x01
+
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK   0xFF
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT  0
+
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK   0xFF
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT  0
+
+#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03              0x03
+struct vbios_clock_programming_table_1x_slave_entry {
+        u8 clk_dom_idx;
+        u16 param0;
+} __packed;
+
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0
+
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK  0x3FFF
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT  0
+
+#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02                   0x02
+struct vbios_clock_programming_table_1x_vf_entry {
+        u8 vfe_idx;
+        u8 param0;
+} __packed;
+
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF
+#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0
+
+struct vbios_vfe_3x_header_struct {
+        u8 version;
+        u8 header_size;
+        u8 vfe_var_entry_size;
+        u8 vfe_var_entry_count;
+        u8 vfe_equ_entry_size;
+        u8 vfe_equ_entry_count;
+        u8 polling_periodms;
+} __packed;
+
+#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11                                      0x11
+#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19                                      0x19
+struct vbios_vfe_3x_var_entry_struct {
+        u8 type;
+        u32 out_range_min;
+        u32 out_range_max;
+        u32 param0;
+        u32 param1;
+        u32 param2;
+        u32 param3;
+} __packed;
+
+#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED                                0x00
+#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY                        0x01
+#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE                          0x02
+#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP                      0x03
+#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE                      0x04
+#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT                         0x05
+#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM                             0x06
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0
+
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF
+#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0
+
+#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17                                      0x17
+#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18                                      0x18
+
+struct vbios_vfe_3x_equ_entry_struct {
+        u8 type;
+        u8 var_idx;
+        u8 equ_idx_next;
+        u32 out_range_min;
+        u32 out_range_max;
+        u32 param0;
+        u32 param1;
+        u32 param2;
+        u8 param3;
+} __packed;
+
+
+#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED                                0x00
+#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC                               0x01
+#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX                                  0x02
+#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE                                 0x03
+#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP                           0x04
+#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP                              0x05
+
+#define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID                                  0xFF
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002
+
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS                     0x0
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ                     0x1
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV                      0x2
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN                      0x3
+#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV                0x4
+
+#define NV_VFIELD_DESC_SIZE_BYTE            0x00000000
+#define NV_VFIELD_DESC_SIZE_WORD            0x00000001
+#define NV_VFIELD_DESC_SIZE_DWORD           0x00000002
+#define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18) >> 3)
+
+#define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID         0x00000000
+#define NV_PMU_BIOS_VFIELD_DESC_CODE_REG             0x00000001
+#define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG       0x00000002
+
+#define NV_VFIELD_DESC_CODE_INVALID         NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID
+#define NV_VFIELD_DESC_CODE_REG             NV_PMU_BIOS_VFIELD_DESC_CODE_REG
+#define NV_VFIELD_DESC_CODE_INDEX_REG       NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG
+
+#define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0) >> 5)
+
+#define VFIELD_ID_STRAP_IDDQ                    0x09
+#define VFIELD_ID_STRAP_IDDQ_1                  0x0B
+
+#define VFIELD_REG_HEADER_SIZE 3
+struct vfield_reg_header {
+        u8 version;
+        u8 entry_size;
+        u8 count;
+} __packed;
+
+#define VBIOS_VFIELD_REG_TABLE_VERSION_1_0  0x10
+
+
+#define VFIELD_REG_ENTRY_SIZE 13
+struct vfield_reg_entry {
+        u8 strap_reg_desc;
+        u32 reg;
+        u32 reg_index;
+        u32 index;
+} __packed;
+
+#define VFIELD_HEADER_SIZE 3
+
+struct vfield_header {
+        u8 version;
+        u8 entry_size;
+        u8 count;
+} __packed;
+
+#define VBIOS_VFIELD_TABLE_VERSION_1_0  0x10
+
+#define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1F)
+#define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0) >> 5)
+#define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00) >> 10)
+
+#define VFIELD_ENTRY_SIZE 3
+
+struct vfield_entry {
+        u8 strap_id;
+        u16 strap_desc;
+} __packed;
+
+#define PERF_CLK_DOMAINS_IDX_MAX                (32)
+#define PERF_CLK_DOMAINS_IDX_INVALID            PERF_CLK_DOMAINS_IDX_MAX
+
+#define VBIOS_PSTATE_TABLE_VERSION_5X           0x50
+#define VBIOS_PSTATE_HEADER_5X_SIZE_10          (10)
+
+struct vbios_pstate_header_5x {
+        u8 version;
+        u8 header_size;
+        u8 base_entry_size;
+        u8 base_entry_count;
+        u8 clock_entry_size;
+        u8 clock_entry_count;
+        u8 flags0;
+        u8 initial_pstate;
+        u8 cpi_support_level;
+u8 cpi_features;
+} __packed;
+
+#define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6      6
+
+#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2       0x2
+#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3       0x3
+
+struct vbios_pstate_entry_clock_5x {
+        u16 param0;
+        u32 param1;
+} __packed;
+
+struct vbios_pstate_entry_5x {
+        u8 pstate_level;
+        u8 flags0;
+        u8 lpwr_entry_idx;
+        struct vbios_pstate_entry_clock_5x clockEntry[PERF_CLK_DOMAINS_IDX_MAX];
+} __packed;
+
+#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_SHIFT    0
+#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_MASK     0x00003FFF
+
+#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_SHIFT    0
+#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_MASK     0x00003FFF
+
+#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT    14
+#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK     0x0FFFC000
+
+#define VBIOS_PERFLEVEL_SKIP_ENTRY                              0xFF
+
+#define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION                            0x11
+
+#define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE                             16
+#define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE                             21
+#define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE                             26
+
+struct vbios_memory_clock_header_1x {
+        u8 version;
+        u8 header_size;
+        u8 base_entry_size;
+        u8 strap_entry_size;
+        u8 strap_entry_count;
+        u8 entry_count;
+        u8 flags;
+        u8 fbvdd_settle_time;
+        u32 cfg_pwrd_val;
+        u16 fbvddq_high;
+        u16 fbvddq_low;
+        u32 script_list_ptr;
+        u8 script_list_count;
+        u32 cmd_script_list_ptr;
+        u8 cmd_script_list_count;
+} __packed;
+
+#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE                         20
+
+struct vbios_memory_clock_base_entry_11 {
+        u16 minimum;
+        u16 maximum;
+        u32 script_pointer;
+        u8 flags0;
+        u32 fbpa_config;
+        u32 fbpa_config1;
+        u8 flags1;
+        u8 ref_mpllssf_freq_delta;
+        u8 flags2;
+} __packed;
+
+/* Script Pointer Index */
+/* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX         3:2*/
+#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK       0xc
+#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT      2
+/* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX     1:0*/
+#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK   0x3
+#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT  0
+
+#define VBIOS_POWER_SENSORS_VERSION_2X                                      0x20
+#define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08                         0x00000008
+
+struct pwr_sensors_2x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+        u32 ba_script_pointer;
+} __packed;
+
+#define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15                          0x00000015
+
+struct pwr_sensors_2x_entry {
+        u8 flags0;
+        u32 class_param0;
+        u32 sensor_param0;
+        u32 sensor_param1;
+        u32 sensor_param2;
+        u32 sensor_param3;
+} __packed;
+
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK                   0xF
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT                    0
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C              0x00000001
+
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK        0xFF
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT          0
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK  0x100
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT  8
+
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK  0xFFFF
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT  0
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK  0xFFFF0000
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT  16
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK   0xFFFF
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT   0
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK  0xFFFF0000
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT  16
+
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK    0xFFFF
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT    0
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK   0xFF0000
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT   16
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK  0xFFFF
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT  0
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK  0xFFFF0000
+#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT  16
+
+#define VBIOS_POWER_TOPOLOGY_VERSION_2X                                      0x20
+#define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06                         0x00000006
+
+struct pwr_topology_2x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+        u8 rel_entry_size;
+        u8 num_rel_entries;
+} __packed;
+
+#define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16                          0x00000016
+
+struct pwr_topology_2x_entry {
+        u8 flags0;
+        u8 pwr_rail;
+        u32 param0;
+        u32 curr_corr_slope;
+        u32 curr_corr_offset;
+        u32 param1;
+        u32 param2;
+} __packed;
+
+#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK                  0xF
+#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT                   0
+#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR                0x00000001
+
+#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK          0xFF
+#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT            0
+#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00
+#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT   8
+
+#define VBIOS_POWER_POLICY_VERSION_3X                                       0x30
+#define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25                          0x00000025
+
+struct pwr_policy_3x_header_struct {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+        u16 base_sample_period;
+        u16 min_client_sample_period;
+        u8 table_rel_entry_size;
+        u8 num_table_rel_entries;
+        u8 tgp_policy_idx;
+        u8 rtp_policy_idx;
+        u8 mxm_policy_idx;
+        u8 dnotifier_policy_idx;
+        u32 d2_limit;
+        u32 d3_limit;
+        u32 d4_limit;
+        u32 d5_limit;
+        u8 low_sampling_mult;
+        u8 pwr_tgt_policy_idx;
+        u8 pwr_tgt_floor_policy_idx;
+        u8 sm_bus_policy_idx;
+        u8 table_viol_entry_size;
+        u8 num_table_viol_entries;
+} __packed;
+
+#define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E                           0x0000002E
+
+struct pwr_policy_3x_entry_struct {
+        u8 flags0;
+        u8 ch_idx;
+        u32 limit_min;
+        u32 limit_rated;
+        u32 limit_max;
+        u32 param0;
+        u32 param1;
+        u32 param2;
+        u32 param3;
+        u32 limit_batt;
+        u8 flags1;
+        u8 past_length;
+        u8 next_length;
+        u16 ratio_min;
+        u16 ratio_max;
+        u8 sample_mult;
+        u32 filter_param;
+} __packed;
+
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK                    0xF
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT                    0
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD        0x00000005
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK              0x10
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT                4
+
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK    0x1
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT     0
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK         0x2
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT          1
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK             0x3C
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT               2
+
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK  0xFF
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT    0
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16
+
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF
+#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0
+
+/* Voltage Rail Table */
+struct vbios_voltage_rail_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+        u8 volt_domain_hal;
+} __packed;
+
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07          0X00000007
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08          0X00000008
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09          0X00000009
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A          0X0000000A
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B          0X0000000B
+
+struct vbios_voltage_rail_table_1x_entry {
+        u32 boot_voltage_uv;
+        u8 rel_limit_vfe_equ_idx;
+        u8 alt_rel_limit_vfe_equidx;
+        u8 ov_limit_vfe_equ_idx;
+        u8 pwr_equ_idx;
+        u8 boot_volt_vfe_equ_idx;
+        u8 vmin_limit_vfe_equ_idx;
+        u8 volt_margin_limit_vfe_equ_idx;
+} __packed;
+
+/* Voltage Device Table */
+struct vbios_voltage_device_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+} __packed;
+
+struct vbios_voltage_device_table_1x_entry {
+        u8 type;
+        u8 volt_domain;
+        u16 settle_time_us;
+        u32 param0;
+        u32 param1;
+        u32 param2;
+        u32 param3;
+        u32 param4;
+} __packed;
+
+#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID   0x00
+#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV               0x02
+
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK   \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT  0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK  \
+        GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24
+
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK   \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT  0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK    \
+        GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT           24
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \
+                0x01
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \
+                0x02
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK   \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT  0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK              \
+                GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT             24
+
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK      \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT     0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK     \
+                GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT    24
+
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT     0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK              \
+                GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT     24
+
+/* Voltage Policy Table */
+struct vbios_voltage_policy_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+        u8 perf_core_vf_seq_policy_idx;
+} __packed;
+
+struct vbios_voltage_policy_table_1x_entry {
+        u8 type;
+        u32 param0;
+        u32 param1;
+} __packed;
+
+#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID           0x00
+#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL       0x01
+#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP     0x02
+#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP    0x03
+
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \
+                GENMASK(7, 0)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0
+#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK     GENMASK(8, 31)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT    8
+
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \
+                GENMASK(7, 0)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \
+                GENMASK(15, 8)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \
+                GENMASK(23, 16)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \
+                GENMASK(31, 24)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24
+
+/* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */
+#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \
+                GENMASK(15, 0)
+#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \
+                0
+
+#define VBIOS_THERM_DEVICE_VERSION_1X                                      0x10
+
+#define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04                         0x00000004
+
+struct therm_device_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+} ;
+
+struct therm_device_1x_entry {
+        u8 class_id;
+        u8 param0;
+        u8 flags;
+} ;
+
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU                               0x01
+
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK        0xFF
+#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT          0
+
+#define VBIOS_THERM_CHANNEL_VERSION_1X                                     0x10
+
+#define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09                        0x00000009
+
+struct therm_channel_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+        u8 gpu_avg_pri_ch_idx;
+        u8 gpu_max_pri_ch_idx;
+        u8 board_pri_ch_idx;
+        u8 mem_pri_ch_idx;
+        u8 pwr_supply_pri_ch_idx;
+} __packed;
+
+struct therm_channel_1x_entry {
+        u8 class_id;
+        u8 param0;
+        u8 param1;
+        u8 param2;
+        u8 flags;
+} __packed;
+
+#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE                       0x01
+
+#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK           0xFF
+#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT             0
+
+#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK  0xFF
+#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT    0
+
+/* Frequency Controller Table */
+struct vbios_fct_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u16 sampling_period_ms;
+} __packed;
+
+struct vbios_fct_1x_entry {
+        u8 flags0;
+        u8 clk_domain_idx;
+        u16 param0;
+        u16 param1;
+        u32 param2;
+        u32 param3;
+        u32 param4;
+        u32 param5;
+        u32 param6;
+        u32 param7;
+        u32 param8;
+} __packed;
+
+#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0
+#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0
+#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI       0x1
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS   0x00
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC   0x01
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR  0x02
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0  0x03
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1  0x04
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2  0x05
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3  0x06
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4  0x07
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5  0x08
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS  0x09
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN   0x1
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX   0x2
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG   0x3
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO  0x0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0
+
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0
+
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16
+
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16)
+#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16
+
+/* LPWR Index Table */
+struct nvgpu_bios_lpwr_idx_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u16 base_sampling_period;
+} __packed;
+
+struct nvgpu_bios_lpwr_idx_table_1x_entry {
+        u8 pcie_idx;
+        u8 gr_idx;
+        u8 ms_idx;
+        u8 di_idx;
+        u8 gc6_idx;
+} __packed;
+
+/* LPWR MS Table*/
+struct nvgpu_bios_lpwr_ms_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u8 default_entry_idx;
+        u16 idle_threshold_us;
+} __packed;
+
+struct nvgpu_bios_lpwr_ms_table_1x_entry {
+        u32 feautre_mask;
+        u16 dynamic_current_logic;
+        u16 dynamic_current_sram;
+} __packed;
+
+#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK    GENMASK(0, 0)
+#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT    0
+#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK    GENMASK(2, 2)
+#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT    2
+#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_MASK    \
+                        GENMASK(3, 3)
+#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT    3
+#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK    GENMASK(5, 5)
+#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT    5
+
+/* LPWR GR Table */
+struct nvgpu_bios_lpwr_gr_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u8 default_entry_idx;
+        u16 idle_threshold_us;
+        u8 adaptive_gr_multiplier;
+} __packed;
+
+struct nvgpu_bios_lpwr_gr_table_1x_entry {
+        u32 feautre_mask;
+} __packed;
+
+#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK GENMASK(0, 0)
+#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0
+
+#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4)
+#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4
+int nvgpu_bios_parse_rom(struct gk20a *g);
+u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset);
+s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset);
+u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset);
+u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset);
+void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
+                struct bit_token *ptoken, u8 table_id);
+int nvgpu_bios_execute_script(struct gk20a *g, u32 offset);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/bitops.h
new file mode 100644
index 00000000..d3bac60e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/bitops.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_BITOPS_H__
+#define __NVGPU_BITOPS_H__
+
+#ifdef __KERNEL__
+#include <linux/bitops.h>
+#include <linux/bitmap.h>
+#else
+#include <nvgpu_rmos/include/bitops.h>
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bsearch.h b/drivers/gpu/nvgpu/include/nvgpu/bsearch.h
new file mode 100644
index 00000000..b02cc85c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/bsearch.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_BSEARCH_H__
+#define __NVGPU_BSEARCH_H__
+
+#ifdef __KERNEL__
+#include <linux/bsearch.h>
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bug.h b/drivers/gpu/nvgpu/include/nvgpu/bug.h
new file mode 100644
index 00000000..ea62c6d8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/bug.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_BUG_H__
+#define __NVGPU_BUG_H__
+
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#else
+#include <nvgpu_rmos/include/bug.h>
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bus.h b/drivers/gpu/nvgpu/include/nvgpu/bus.h
new file mode 100644
index 00000000..6957bfbd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/bus.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_BUS_H__
+#define __NVGPU_BUS_H__
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+struct nvgpu_cpu_time_correlation_sample {
+        u64 cpu_timestamp;
+        u64 gpu_timestamp;
+};
+
+int nvgpu_get_timestamps_zipper(struct gk20a *g,
+                u32 source_id, u32 count,
+                struct nvgpu_cpu_time_correlation_sample *samples);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h b/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h
new file mode 100644
index 00000000..c6620663
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_CIRC_BUF_H__
+#define __NVGPU_CIRC_BUF_H__
+
+#ifdef __KERNEL__
+#include <linux/circ_buf.h>
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
new file mode 100644
index 00000000..09f0b0d3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_CLK_ARB_H__
+#define __NVGPU_CLK_ARB_H__
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_clk_session;
+
+int nvgpu_clk_arb_init_arbiter(struct gk20a *g);
+
+int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+                u16 *min_mhz, u16 *max_mhz);
+
+int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
+                u32 api_domain, u16 *actual_mhz);
+
+int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
+                u32 api_domain, u16 *effective_mhz);
+
+int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
+        u32 api_domain, u32 *max_points, u16 *fpoints);
+
+u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g);
+bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain);
+
+void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g);
+
+int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
+                struct nvgpu_clk_session *session);
+
+int nvgpu_clk_arb_init_session(struct gk20a *g,
+                struct nvgpu_clk_session **_session);
+
+void nvgpu_clk_arb_release_session(struct gk20a *g,
+                struct nvgpu_clk_session *session);
+
+int nvgpu_clk_arb_commit_request_fd(struct gk20a *g,
+        struct nvgpu_clk_session *session, int request_fd);
+
+int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
+                int fd, u32 api_domain, u16 target_mhz);
+
+int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
+                u32 api_domain, u16 *target_mhz);
+
+int nvgpu_clk_arb_install_event_fd(struct gk20a *g,
+        struct nvgpu_clk_session *session, int *event_fd, u32 alarm_mask);
+
+int nvgpu_clk_arb_install_request_fd(struct gk20a *g,
+        struct nvgpu_clk_session *session, int *event_fd);
+
+void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g);
+
+int nvgpu_clk_arb_get_current_pstate(struct gk20a *g);
+
+void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
+
+void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm);
+#endif /* __NVGPU_CLK_ARB_H__ */
+
diff --git a/drivers/gpu/nvgpu/include/nvgpu/comptags.h b/drivers/gpu/nvgpu/include/nvgpu/comptags.h
new file mode 100644
index 00000000..679a0f9e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/comptags.h
@@ -0,0 +1,97 @@
+/*
+* Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_COMPTAGS__
+#define __NVGPU_COMPTAGS__
+
+#include <nvgpu/lock.h>
+
+struct gk20a;
+struct nvgpu_os_buffer;
+
+struct gk20a_comptags {
+        u32 offset;
+        u32 lines;
+
+        /*
+         * This signals whether allocation has been attempted. Observe 'lines'
+         * to see whether the comptags were actually allocated. We try alloc
+         * only once per buffer in order not to break multiple compressible-kind
+         * mappings.
+         */
+        bool allocated;
+
+        /*
+         * Do comptags need to be cleared before mapping?
+         */
+        bool needs_clear;
+};
+
+struct gk20a_comptag_allocator {
+        struct gk20a *g;
+
+        struct nvgpu_mutex lock;
+
+        /* This bitmap starts at ctag 1. 0th cannot be taken. */
+        unsigned long *bitmap;
+
+        /* Size of bitmap, not max ctags, so one less. */
+        unsigned long size;
+};
+
+/* real size here, but first (ctag 0) isn't used */
+int gk20a_comptag_allocator_init(struct gk20a *g,
+                                 struct gk20a_comptag_allocator *allocator,
+                                 unsigned long size);
+void gk20a_comptag_allocator_destroy(struct gk20a *g,
+                                     struct gk20a_comptag_allocator *allocator);
+
+int gk20a_comptaglines_alloc(struct gk20a_comptag_allocator *allocator,
+                             u32 *offset, u32 len);
+void gk20a_comptaglines_free(struct gk20a_comptag_allocator *allocator,
+                             u32 offset, u32 len);
+
+/*
+ * Defined by OS specific code since comptags are stored in a highly OS specific
+ * way.
+ */
+int gk20a_alloc_or_get_comptags(struct gk20a *g,
+                                struct nvgpu_os_buffer *buf,
+                                struct gk20a_comptag_allocator *allocator,
+                                struct gk20a_comptags *comptags);
+void gk20a_get_comptags(struct nvgpu_os_buffer *buf,
+                        struct gk20a_comptags *comptags);
+
+/*
+ * These functions must be used to synchronize comptags clear. The usage:
+ *
+ *   if (gk20a_comptags_start_clear(os_buf)) {
+ *           // we now hold the buffer lock for clearing
+ *
+ *           bool successful = hw_clear_comptags();
+ *
+ *           // mark the buf cleared (or not) and release the buffer lock
+ *           gk20a_comptags_finish_clear(os_buf, successful);
+ *   }
+ *
+ *  If gk20a_start_comptags_clear() returns false, another caller has
+ *  already cleared the comptags.
+ */
+bool gk20a_comptags_start_clear(struct nvgpu_os_buffer *buf);
+void gk20a_comptags_finish_clear(struct nvgpu_os_buffer *buf,
+                                 bool clear_successful);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/cond.h b/drivers/gpu/nvgpu/include/nvgpu/cond.h
new file mode 100644
index 00000000..b6f2598e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/cond.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_COND_H__
+#define __NVGPU_COND_H__
+
+#ifdef __KERNEL__
+#include <nvgpu/linux/cond.h>
+#else
+#include <nvgpu_rmos/include/cond.h>
+#endif
+
+/*
+ * struct nvgpu_cond
+ *
+ * Should be implemented per-OS in a separate library
+ */
+struct nvgpu_cond;
+
+/**
+ * nvgpu_cond_init - Initialize a condition variable
+ *
+ * @cond - The condition variable to initialize
+ *
+ * Initialize a condition variable before using it.
+ */
+int nvgpu_cond_init(struct nvgpu_cond *cond);
+
+/**
+ * nvgpu_cond_signal - Signal a condition variable
+ *
+ * @cond - The condition variable to signal
+ *
+ * Wake up a waiter for a condition variable to check if its condition has been
+ * satisfied.
+ *
+ * The waiter is using an uninterruptible wait.
+ */
+int nvgpu_cond_signal(struct nvgpu_cond *cond);
+
+/**
+ * nvgpu_cond_signal_interruptible - Signal a condition variable
+ *
+ * @cond - The condition variable to signal
+ *
+ * Wake up a waiter for a condition variable to check if its condition has been
+ * satisfied.
+ *
+ * The waiter is using an interruptible wait.
+ */
+int nvgpu_cond_signal_interruptible(struct nvgpu_cond *cond);
+
+/**
+ * nvgpu_cond_broadcast - Signal all waiters of a condition variable
+ *
+ * @cond - The condition variable to signal
+ *
+ * Wake up all waiters for a condition variable to check if their conditions
+ * have been satisfied.
+ *
+ * The waiters are using an uninterruptible wait.
+ */
+int nvgpu_cond_broadcast(struct nvgpu_cond *cond);
+
+/**
+ * nvgpu_cond_broadcast_interruptible - Signal all waiters of a condition
+ * variable
+ *
+ * @cond - The condition variable to signal
+ *
+ * Wake up all waiters for a condition variable to check if their conditions
+ * have been satisfied.
+ *
+ * The waiters are using an interruptible wait.
+ */
+int nvgpu_cond_broadcast_interruptible(struct nvgpu_cond *cond);
+
+/**
+ * nvgpu_cond_destroy - Destroy a condition variable
+ *
+ * @cond - The condition variable to destroy
+ */
+void nvgpu_cond_destroy(struct nvgpu_cond *cond);
+
+#endif /* __NVGPU_COND_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h b/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h
new file mode 100644
index 00000000..cc6edb49
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_CTXSW_TRACE_H__
+#define __NVGPU_CTXSW_TRACE_H__
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct tsg_gk20a;
+struct channel_gk20a;
+struct nvgpu_ctxsw_trace_entry;
+
+int gk20a_ctxsw_trace_init(struct gk20a *g);
+
+void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch);
+void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg);
+
+void gk20a_ctxsw_trace_cleanup(struct gk20a *g);
+int gk20a_ctxsw_trace_write(struct gk20a *g,
+                            struct nvgpu_ctxsw_trace_entry *entry);
+void gk20a_ctxsw_trace_wake_up(struct gk20a *g, int vmid);
+
+#ifdef CONFIG_GK20A_CTXSW_TRACE
+struct file;
+struct vm_area_struct;
+
+int gk20a_ctxsw_dev_mmap(struct file *filp, struct vm_area_struct *vma);
+int gk20a_ctxsw_dev_ring_alloc(struct gk20a *g, void **buf, size_t *size);
+int gk20a_ctxsw_dev_ring_free(struct gk20a *g);
+int gk20a_ctxsw_dev_mmap_buffer(struct gk20a *g, struct vm_area_struct *vma);
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/debug.h b/drivers/gpu/nvgpu/include/nvgpu/debug.h
new file mode 100644
index 00000000..c2811319
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/debug.h
@@ -0,0 +1,59 @@
+/*
+ * GK20A Debug functionality
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_DEBUG_H__
+#define __NVGPU_DEBUG_H__
+
+struct gk20a;
+struct gpu_ops;
+
+struct gk20a_debug_output {
+        void (*fn)(void *ctx, const char *str, size_t len);
+        void *ctx;
+        char buf[256];
+};
+
+#ifdef CONFIG_DEBUG_FS
+extern unsigned int gk20a_debug_trace_cmdbuf;
+
+void gk20a_debug_output(struct gk20a_debug_output *o,
+                                        const char *fmt, ...);
+
+void gk20a_debug_dump(struct gk20a *g);
+void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o);
+int gk20a_gr_debug_dump(struct gk20a *g);
+void gk20a_init_debug_ops(struct gpu_ops *gops);
+
+void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink);
+void gk20a_debug_deinit(struct gk20a *g);
+#else
+static inline void gk20a_debug_output(struct gk20a_debug_output *o,
+                                        const char *fmt, ...) {}
+
+static inline void gk20a_debug_dump(struct gk20a *g) {}
+static inline void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o) {}
+static inline int gk20a_gr_debug_dump(struct gk20a *g) { return 0;}
+static inline void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink) {}
+static inline void gk20a_debug_deinit(struct gk20a *g) {}
+#endif
+
+#endif /* __NVGPU_DEBUG_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/dma.h b/drivers/gpu/nvgpu/include/nvgpu/dma.h
new file mode 100644
index 00000000..c0397b58
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/dma.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_DMA_H__
+#define __NVGPU_DMA_H__
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct vm_gk20a;
+struct nvgpu_mem;
+
+/*
+ * Flags for the below nvgpu_dma_{alloc,alloc_map}_flags*
+ */
+
+/*
+ * Don't create a virtual kernel mapping for the buffer but only allocate it;
+ * this may save some resources. The buffer can be mapped later explicitly.
+ */
+#define NVGPU_DMA_NO_KERNEL_MAPPING     (1 << 0)
+
+/*
+ * Don't allow building the buffer from individual pages but require a
+ * physically contiguous block.
+ */
+#define NVGPU_DMA_FORCE_CONTIGUOUS      (1 << 1)
+
+/*
+ * Make the mapping read-only.
+ */
+#define NVGPU_DMA_READ_ONLY             (1 << 2)
+
+/**
+ * nvgpu_iommuable - Check if GPU is behind IOMMU
+ *
+ * @g - The GPU.
+ *
+ * Returns true if the passed GPU is behind an IOMMU; false otherwise. If the
+ * GPU is iommuable then the DMA address in nvgpu_mem_sgl is valid.
+ *
+ * Note that even if a GPU is behind an IOMMU that does not necessarily mean the
+ * GPU _must_ use DMA addresses. GPUs may still use physical addresses if it
+ * makes sense.
+ */
+bool nvgpu_iommuable(struct gk20a *g);
+
+/**
+ * nvgpu_dma_alloc - Allocate DMA memory
+ *
+ * @g    - The GPU.
+ * @size - Size of the allocation in bytes.
+ * @mem  - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA. Store the allocation info in @mem.
+ * Returns 0 on success and a suitable error code when there's an error. This
+ * memory can be either placed in VIDMEM or SYSMEM, which ever is more
+ * convenient for the driver.
+ */
+int nvgpu_dma_alloc(struct gk20a *g, size_t size, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_flags - Allocate DMA memory
+ *
+ * @g     - The GPU.
+ * @flags - Flags modifying the operation of the DMA allocation.
+ * @size  - Size of the allocation in bytes.
+ * @mem   - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA. Store the allocation info in @mem.
+ * Returns 0 on success and a suitable error code when there's an error. This
+ * memory can be either placed in VIDMEM or SYSMEM, which ever is more
+ * convenient for the driver.
+ *
+ * The following flags are accepted:
+ *
+ *   %NVGPU_DMA_NO_KERNEL_MAPPING
+ *   %NVGPU_DMA_FORCE_CONTIGUOUS
+ *   %NVGPU_DMA_READ_ONLY
+ */
+int nvgpu_dma_alloc_flags(struct gk20a *g, unsigned long flags, size_t size,
+                struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_sys - Allocate DMA memory
+ *
+ * @g    - The GPU.
+ * @size - Size of the allocation in bytes.
+ * @mem  - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA. Store the allocation info in @mem.
+ * Returns 0 on success and a suitable error code when there's an error. This
+ * allocates memory specifically in SYSMEM.
+ */
+int nvgpu_dma_alloc_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_flags_sys - Allocate DMA memory
+ *
+ * @g     - The GPU.
+ * @flags - Flags modifying the operation of the DMA allocation.
+ * @size  - Size of the allocation in bytes.
+ * @mem   - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA. Store the allocation info in @mem.
+ * Returns 0 on success and a suitable error code when there's an error. This
+ * allocates memory specifically in SYSMEM.
+ *
+ * The following flags are accepted:
+ *
+ *   %NVGPU_DMA_NO_KERNEL_MAPPING
+ *   %NVGPU_DMA_FORCE_CONTIGUOUS
+ *   %NVGPU_DMA_READ_ONLY
+ */
+int nvgpu_dma_alloc_flags_sys(struct gk20a *g, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_vid - Allocate DMA memory
+ *
+ * @g    - The GPU.
+ * @size - Size of the allocation in bytes.
+ * @mem  - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA. Store the allocation info in @mem.
+ * Returns 0 on success and a suitable error code when there's an error. This
+ * allocates memory specifically in VIDMEM.
+ */
+int nvgpu_dma_alloc_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_flags_vid - Allocate DMA memory
+ *
+ * @g     - The GPU.
+ * @flags - Flags modifying the operation of the DMA allocation.
+ * @size  - Size of the allocation in bytes.
+ * @mem   - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA. Store the allocation info in @mem.
+ * Returns 0 on success and a suitable error code when there's an error. This
+ * allocates memory specifically in VIDMEM.
+ *
+ * Only the following flags are accepted:
+ *
+ *   %NVGPU_DMA_NO_KERNEL_MAPPING
+ *
+ */
+int nvgpu_dma_alloc_flags_vid(struct gk20a *g, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_flags_vid_at - Allocate DMA memory
+ *
+ * @g     - The GPU.
+ * @flags - Flags modifying the operation of the DMA allocation.
+ * @size  - Size of the allocation in bytes.
+ * @mem   - Struct for storing the allocation information.
+ * @at    - A specific location to attempt to allocate memory from or 0 if the
+ *          caller does not care what the address is.
+ *
+ * Allocate memory suitable for doing DMA. Store the allocation info in @mem.
+ * Returns 0 on success and a suitable error code when there's an error. This
+ * allocates memory specifically in VIDMEM.
+ *
+ * Only the following flags are accepted:
+ *
+ *   %NVGPU_DMA_NO_KERNEL_MAPPING
+ */
+int nvgpu_dma_alloc_flags_vid_at(struct gk20a *g, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem, u64 at);
+
+/**
+ * nvgpu_dma_free - Free a DMA allocation
+ *
+ * @g   - The GPU.
+ * @mem - An allocation to free.
+ *
+ * Free memory created with any of:
+ *
+ *   nvgpu_dma_alloc()
+ *   nvgpu_dma_alloc_flags()
+ *   nvgpu_dma_alloc_sys()
+ *   nvgpu_dma_alloc_flags_sys()
+ *   nvgpu_dma_alloc_vid()
+ *   nvgpu_dma_alloc_flags_vid()
+ *   nvgpu_dma_alloc_flags_vid_at()
+ */
+void nvgpu_dma_free(struct gk20a *g, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_map - Allocate DMA memory and map into GMMU.
+ *
+ * @vm   - VM context for GMMU mapping.
+ * @size - Size of the allocation in bytes.
+ * @mem  - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA and map that memory into the GMMU.
+ * Note this is different than mapping it into the CPU. This memory can be
+ * either placed in VIDMEM or SYSMEM, which ever is more convenient for the
+ * driver.
+ *
+ * Note: currently a bug exists in the nvgpu_dma_alloc_map*() routines: you
+ * cannot use nvgpu_gmmu_map() on said buffer - it will overwrite the necessary
+ * information for the DMA unmap routines to actually unmap the buffer. You
+ * will either leak mappings or see GMMU faults.
+ */
+int nvgpu_dma_alloc_map(struct vm_gk20a *vm, size_t size,
+                struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_map_flags - Allocate DMA memory and map into GMMU.
+ *
+ * @vm    - VM context for GMMU mapping.
+ * @flags - Flags modifying the operation of the DMA allocation.
+ * @size  - Size of the allocation in bytes.
+ * @mem   - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA and map that memory into the GMMU.
+ * Note this is different than mapping it into the CPU. This memory can be
+ * either placed in VIDMEM or SYSMEM, which ever is more convenient for the
+ * driver.
+ *
+ * This version passes @flags on to the underlying DMA allocation. The accepted
+ * flags are:
+ *
+ *   %NVGPU_DMA_NO_KERNEL_MAPPING
+ *   %NVGPU_DMA_FORCE_CONTIGUOUS
+ *   %NVGPU_DMA_READ_ONLY
+ */
+int nvgpu_dma_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_map_sys - Allocate DMA memory and map into GMMU.
+ *
+ * @vm   - VM context for GMMU mapping.
+ * @size - Size of the allocation in bytes.
+ * @mem  - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA and map that memory into the GMMU.
+ * This memory will be placed in SYSMEM.
+ */
+int nvgpu_dma_alloc_map_sys(struct vm_gk20a *vm, size_t size,
+                struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_map_flags_sys - Allocate DMA memory and map into GMMU.
+ *
+ * @vm    - VM context for GMMU mapping.
+ * @flags - Flags modifying the operation of the DMA allocation.
+ * @size  - Size of the allocation in bytes.
+ * @mem   - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA and map that memory into the GMMU.
+ * This memory will be placed in SYSMEM.
+ *
+ * This version passes @flags on to the underlying DMA allocation. The accepted
+ * flags are:
+ *
+ *   %NVGPU_DMA_NO_KERNEL_MAPPING
+ *   %NVGPU_DMA_FORCE_CONTIGUOUS
+ *   %NVGPU_DMA_READ_ONLY
+ */
+int nvgpu_dma_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_map_vid - Allocate DMA memory and map into GMMU.
+ *
+ * @vm   - VM context for GMMU mapping.
+ * @size - Size of the allocation in bytes.
+ * @mem  - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA and map that memory into the GMMU.
+ * This memory will be placed in VIDMEM.
+ */
+int nvgpu_dma_alloc_map_vid(struct vm_gk20a *vm, size_t size,
+                struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_alloc_map_flags_vid - Allocate DMA memory and map into GMMU.
+ *
+ * @vm    - VM context for GMMU mapping.
+ * @flags - Flags modifying the operation of the DMA allocation.
+ * @size  - Size of the allocation in bytes.
+ * @mem   - Struct for storing the allocation information.
+ *
+ * Allocate memory suitable for doing DMA and map that memory into the GMMU.
+ * This memory will be placed in VIDMEM.
+ *
+ * This version passes @flags on to the underlying DMA allocation. The accepted
+ * flags are:
+ *
+ *   %NVGPU_DMA_NO_KERNEL_MAPPING
+ *   %NVGPU_DMA_FORCE_CONTIGUOUS
+ *   %NVGPU_DMA_READ_ONLY
+ */
+int nvgpu_dma_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem);
+
+/**
+ * nvgpu_dma_unmap_free - Free a DMA allocation
+ *
+ * @g   - The GPU.
+ * @mem - An allocation to free.
+ *
+ * Free memory created with any of:
+ *
+ *   nvgpu_dma_alloc_map()
+ *   nvgpu_dma_alloc_map_flags()
+ *   nvgpu_dma_alloc_map_sys()
+ *   nvgpu_dma_alloc_map_flags_sys()
+ *   nvgpu_dma_alloc_map_vid()
+ *   nvgpu_dma_alloc_map_flags_vid()
+ */
+void nvgpu_dma_unmap_free(struct vm_gk20a *vm, struct nvgpu_mem *mem);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
new file mode 100644
index 00000000..ad5b3db3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_ENABLED_H__
+#define __NVGPU_ENABLED_H__
+
+struct gk20a;
+
+#include <nvgpu/types.h>
+
+/*
+ * Available flags that describe what's enabled and what's not in the GPU. Each
+ * flag here is defined by it's offset in a bitmap.
+ */
+#define NVGPU_IS_FMODEL                         1
+#define NVGPU_DRIVER_IS_DYING                   2
+#define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3
+
+/*
+ * ECC flags
+ */
+/* SM LRF ECC is enabled */
+#define NVGPU_ECC_ENABLED_SM_LRF                8
+/* SM SHM ECC is enabled */
+#define NVGPU_ECC_ENABLED_SM_SHM                9
+/* TEX ECC is enabled */
+#define NVGPU_ECC_ENABLED_TEX                   10
+/* L2 ECC is enabled */
+#define NVGPU_ECC_ENABLED_LTC                   11
+/*
+ * MM flags.
+ */
+#define NVGPU_MM_UNIFY_ADDRESS_SPACES           16
+/* false if vidmem aperture actually points to sysmem */
+#define NVGPU_MM_HONORS_APERTURE                17
+/* unified or split memory with separate vidmem? */
+#define NVGPU_MM_UNIFIED_MEMORY                 18
+/* kernel mode ce vidmem clearing channels need to be in a tsg */
+#define NVGPU_MM_CE_TSG_REQUIRED                19
+/* User-space managed address spaces support */
+#define NVGPU_SUPPORT_USERSPACE_MANAGED_AS      20
+/* IO coherence support is available */
+#define NVGPU_SUPPORT_IO_COHERENCE              21
+/* MAP_BUFFER_EX with partial mappings */
+#define NVGPU_SUPPORT_PARTIAL_MAPPINGS          22
+/* MAP_BUFFER_EX with sparse allocations */
+#define NVGPU_SUPPORT_SPARSE_ALLOCS             23
+/* Direct PTE kind control is supported (map_buffer_ex) */
+#define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL      24
+/* Support batch mapping */
+#define NVGPU_SUPPORT_MAP_BUFFER_BATCH          25
+
+/*
+ * Host flags
+ */
+#define NVGPU_HAS_SYNCPOINTS                    30
+/* sync fence FDs are available in, e.g., submit_gpfifo */
+#define NVGPU_SUPPORT_SYNC_FENCE_FDS            31
+/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */
+#define NVGPU_SUPPORT_CYCLE_STATS               32
+/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */
+#define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT      33
+/* Both gpu driver and device support TSG */
+#define NVGPU_SUPPORT_TSG                       34
+/* Fast deterministic submits with no job tracking are supported */
+#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING 35
+/* Deterministic submits are supported even with job tracking */
+#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL 36
+/* NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is available */
+#define NVGPU_SUPPORT_RESCHEDULE_RUNLIST        37
+
+/* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */
+#define NVGPU_SUPPORT_DEVICE_EVENTS             38
+/* FECS context switch tracing is available */
+#define NVGPU_SUPPORT_FECS_CTXSW_TRACE          39
+
+/* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */
+#define NVGPU_SUPPORT_DETERMINISTIC_OPTS        40
+
+/*
+ * Security flags
+ */
+
+#define NVGPU_SEC_SECUREGPCCS                   41
+#define NVGPU_SEC_PRIVSECURITY                  42
+
+/*
+ * PMU flags.
+ */
+/* perfmon enabled or disabled for PMU */
+#define NVGPU_PMU_PERFMON                               48
+#define NVGPU_PMU_PSTATE                                49
+#define NVGPU_PMU_ZBC_SAVE                              50
+#define NVGPU_PMU_FECS_BOOTSTRAP_DONE                   51
+#define NVGPU_GPU_CAN_BLCG                              52
+#define NVGPU_GPU_CAN_SLCG                              53
+#define NVGPU_GPU_CAN_ELCG                              54
+/* Clock control support */
+#define NVGPU_SUPPORT_CLOCK_CONTROLS            55
+/* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */
+#define NVGPU_SUPPORT_GET_VOLTAGE               56
+/* NVGPU_GPU_IOCTL_GET_CURRENT is available */
+#define NVGPU_SUPPORT_GET_CURRENT               57
+/* NVGPU_GPU_IOCTL_GET_POWER is available */
+#define NVGPU_SUPPORT_GET_POWER                 58
+/* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */
+#define NVGPU_SUPPORT_GET_TEMPERATURE           59
+/* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */
+#define NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT     60
+
+/* whether to run PREOS binary on dGPUs */
+#define NVGPU_PMU_RUN_PREOS                     61
+
+/* set if ASPM is enabled; only makes sense for PCI */
+#define NVGPU_SUPPORT_ASPM                      62
+/*
+ * Must be greater than the largest bit offset in the above list.
+ */
+#define NVGPU_MAX_ENABLED_BITS                  64
+
+/**
+ * nvgpu_is_enabled - Check if the passed flag is enabled.
+ *
+ * @g     - The GPU.
+ * @flag  - Which flag to check.
+ *
+ * Returns true if the passed @flag is true; false otherwise.
+ */
+bool nvgpu_is_enabled(struct gk20a *g, int flag);
+
+/**
+ * __nvgpu_set_enabled - Set the state of a flag.
+ *
+ * @g     - The GPU.
+ * @flag  - Which flag to modify.
+ * @state - The state to set the flag to.
+ *
+ * Set the state of the passed @flag to @state. This will return the previous
+ * state of the passed @flag.
+ */
+bool __nvgpu_set_enabled(struct gk20a *g, int flag, bool state);
+
+int nvgpu_init_enabled_flags(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/errno.h b/drivers/gpu/nvgpu/include/nvgpu/errno.h
new file mode 100644
index 00000000..12ba118e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/errno.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_ERRNO_H__
+#define __NVGPU_ERRNO_H__
+
+/*
+ * Explicit include to get all the -E* error messages. Useful for header files
+ * with static inlines that return error messages. In actual C code normally
+ * enough Linux/QNX headers bleed in to get the error messages but header files
+ * with sparse includes do not have this luxury.
+ */
+
+#ifdef __KERNEL__
+#include <linux/errno.h>
+#endif
+
+/*
+ * TODO: add else path above for QNX.
+ */
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
new file mode 100644
index 00000000..4be16576
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __FALCON_H__
+#define __FALCON_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/lock.h>
+
+/*
+ * Falcon Id Defines
+ */
+#define FALCON_ID_PMU       (0)
+#define FALCON_ID_FECS      (2)
+#define FALCON_ID_GPCCS     (3)
+#define FALCON_ID_NVDEC     (4)
+#define FALCON_ID_SEC2      (7)
+
+/*
+ * Falcon Base address Defines
+ */
+#define FALCON_NVDEC_BASE  0x00084000
+#define FALCON_PWR_BASE    0x0010a000
+#define FALCON_SEC_BASE    0x00087000
+#define FALCON_FECS_BASE   0x00409000
+#define FALCON_GPCCS_BASE  0x0041a000
+
+/* Falcon Register index */
+#define FALCON_REG_R0           (0)
+#define FALCON_REG_R1           (1)
+#define FALCON_REG_R2           (2)
+#define FALCON_REG_R3           (3)
+#define FALCON_REG_R4           (4)
+#define FALCON_REG_R5           (5)
+#define FALCON_REG_R6           (6)
+#define FALCON_REG_R7           (7)
+#define FALCON_REG_R8           (8)
+#define FALCON_REG_R9           (9)
+#define FALCON_REG_R10          (10)
+#define FALCON_REG_R11          (11)
+#define FALCON_REG_R12          (12)
+#define FALCON_REG_R13          (13)
+#define FALCON_REG_R14          (14)
+#define FALCON_REG_R15          (15)
+#define FALCON_REG_IV0          (16)
+#define FALCON_REG_IV1          (17)
+#define FALCON_REG_UNDEFINED    (18)
+#define FALCON_REG_EV           (19)
+#define FALCON_REG_SP           (20)
+#define FALCON_REG_PC           (21)
+#define FALCON_REG_IMB          (22)
+#define FALCON_REG_DMB          (23)
+#define FALCON_REG_CSW          (24)
+#define FALCON_REG_CCR          (25)
+#define FALCON_REG_SEC          (26)
+#define FALCON_REG_CTX          (27)
+#define FALCON_REG_EXCI         (28)
+#define FALCON_REG_RSVD0        (29)
+#define FALCON_REG_RSVD1        (30)
+#define FALCON_REG_RSVD2        (31)
+#define FALCON_REG_SIZE         (32)
+
+#define FALCON_MAILBOX_COUNT 0x02
+#define FALCON_BLOCK_SIZE 0x100
+
+#define GET_IMEM_TAG(IMEM_ADDR) (IMEM_ADDR >> 8)
+
+#define GET_NEXT_BLOCK(ADDR) \
+        ((((ADDR + (FALCON_BLOCK_SIZE - 1)) & ~(FALCON_BLOCK_SIZE-1)) \
+                / FALCON_BLOCK_SIZE) << 8)
+
+/*
+ * Falcon HWCFG request read types defines
+ */
+enum flcn_hwcfg_read {
+        FALCON_IMEM_SIZE = 0,
+        FALCON_DMEM_SIZE,
+        FALCON_CORE_REV,
+        FALCON_SECURITY_MODEL,
+        FLACON_MAILBOX_COUNT
+};
+
+/*
+ * Falcon HWCFG request write types defines
+ */
+enum flcn_hwcfg_write {
+        FALCON_STARTCPU = 0,
+        FALCON_STARTCPU_SECURE,
+        FALCON_BOOTVEC,
+        FALCON_ITF_EN
+};
+
+#define FALCON_MEM_SCRUBBING_TIMEOUT_MAX 1000
+#define FALCON_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
+
+enum flcn_dma_dir {
+        DMA_TO_FB = 0,
+        DMA_FROM_FB
+};
+
+enum flcn_mem_type {
+        MEM_DMEM = 0,
+        MEM_IMEM
+};
+
+/* Falcon ucode header format
+ * OS Code Offset
+ * OS Code Size
+ * OS Data Offset
+ * OS Data Size
+ * NumApps (N)
+ * App   0 Code Offset
+ * App   0 Code Size
+ * .  .  .  .
+ * App   N - 1 Code Offset
+ * App   N - 1 Code Size
+ * App   0 Data Offset
+ * App   0 Data Size
+ * .  .  .  .
+ * App   N - 1 Data Offset
+ * App   N - 1 Data Size
+ * OS Ovl Offset
+ * OS Ovl Size
+*/
+#define OS_CODE_OFFSET 0x0
+#define OS_CODE_SIZE   0x1
+#define OS_DATA_OFFSET 0x2
+#define OS_DATA_SIZE   0x3
+#define NUM_APPS       0x4
+#define APP_0_CODE_OFFSET 0x5
+#define APP_0_CODE_SIZE   0x6
+
+struct nvgpu_falcon_dma_info {
+        u32 fb_base;
+        u32 fb_off;
+        u32 flcn_mem_off;
+        u32 size_in_bytes;
+        enum flcn_dma_dir dir;
+        u32 ctx_dma;
+        enum flcn_mem_type flcn_mem;
+        u32 is_wait_complete;
+};
+
+struct gk20a;
+struct nvgpu_falcon;
+
+struct nvgpu_falcon_version_ops {
+        void (*start_cpu_secure)(struct nvgpu_falcon *flcn);
+        void (*write_dmatrfbase)(struct nvgpu_falcon *flcn, u32 addr);
+};
+
+/* ops which are falcon engine specific */
+struct nvgpu_falcon_engine_dependency_ops {
+        int (*reset_eng)(struct gk20a *g);
+};
+
+struct nvgpu_falcon_ops {
+        int (*reset)(struct nvgpu_falcon *flcn);
+        void (*set_irq)(struct nvgpu_falcon *flcn, bool enable);
+        bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn);
+        bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn);
+        bool (*is_falcon_idle)(struct nvgpu_falcon *flcn);
+        bool (*is_falcon_scrubbing_done)(struct nvgpu_falcon *flcn);
+        int (*copy_from_dmem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
+                u32 size, u8 port);
+        int (*copy_to_dmem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
+                u32 size, u8 port);
+        int (*copy_from_imem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
+                u32 size, u8 port);
+        int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
+                u32 size, u8 port, bool sec, u32 tag);
+        int (*dma_copy)(struct nvgpu_falcon *flcn,
+                        struct nvgpu_falcon_dma_info *dma_info);
+        u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index);
+        void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index,
+                u32 data);
+        int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector);
+        void (*dump_falcon_stats)(struct nvgpu_falcon *flcn);
+};
+
+struct nvgpu_falcon {
+        struct gk20a *g;
+        u32 flcn_id;
+        u32 flcn_base;
+        u32 flcn_core_rev;
+        bool is_falcon_supported;
+        bool is_interrupt_enabled;
+        u32 intr_mask;
+        u32 intr_dest;
+        bool isr_enabled;
+        struct nvgpu_mutex isr_mutex;
+        struct nvgpu_mutex copy_lock;
+        struct nvgpu_falcon_ops flcn_ops;
+        struct nvgpu_falcon_version_ops flcn_vops;
+        struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops;
+};
+
+int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn);
+int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout);
+int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn,
+                unsigned int timeout);
+int nvgpu_flcn_reset(struct nvgpu_falcon *flcn);
+void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable,
+        u32 intr_mask, u32 intr_dest);
+bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn);
+bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn);
+bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn);
+int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn,
+        u32 src, u8 *dst, u32 size, u8 port);
+int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn,
+        u32 dst, u8 *src, u32 size, u8 port);
+int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn,
+        u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag);
+int nvgpu_flcn_copy_from_imem(struct nvgpu_falcon *flcn,
+        u32 src, u8 *dst, u32 size, u8 port);
+int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn,
+        struct nvgpu_falcon_dma_info *dma_info);
+u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index);
+void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index,
+        u32 data);
+int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
+void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size);
+void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size);
+void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn);
+
+void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id);
+
+
+#endif /* __FALCON_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/firmware.h b/drivers/gpu/nvgpu/include/nvgpu/firmware.h
new file mode 100644
index 00000000..b541947a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/firmware.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NVGPU_FIRMWARE_H_
+#define _NVGPU_FIRMWARE_H_
+
+struct gk20a;
+
+#define NVGPU_REQUEST_FIRMWARE_NO_WARN          (1UL << 0)
+#define NVGPU_REQUEST_FIRMWARE_NO_SOC           (1UL << 1)
+
+struct nvgpu_firmware {
+        u8 *data;
+        size_t size;
+};
+
+/**
+ * nvgpu_request_firmware - load a firmware blob from filesystem.
+ *
+ * @g           The GPU driver struct for device to load firmware for
+ * @fw_name     The base name of the firmware file.
+ * @flags       Flags for loading;
+ *
+ *              NVGPU_REQUEST_FIRMWARE_NO_WARN: Do not display warning on
+ *              failed load.
+ *
+ *              NVGPU_REQUEST_FIRMWARE_NO_SOC: Do not attempt loading from
+ *              path <SOC_NAME>.
+ *
+ * nvgpu_request_firmware() will load firmware from:
+ *
+ * <system firmware load path>/<GPU name>/<fw_name>
+ *
+ * If that fails and NO_SOC is not enabled, it'll try next from:
+ *
+ * <system firmware load path>/<SOC name>/<fw_name>
+ *
+ * It'll allocate a nvgpu_firmware structure and initializes it and returns
+ * it to caller.
+ */
+struct nvgpu_firmware *nvgpu_request_firmware(struct gk20a *g,
+                                              const char *fw_name,
+                                              int flags);
+
+/**
+ * nvgpu_release_firmware - free firmware and associated nvgpu_firmware blob
+ *
+ * @g           The GPU driver struct for device to free firmware for
+ * @fw          The firmware to free. fw blob will also be freed.
+ */
+void nvgpu_release_firmware(struct gk20a *g, struct nvgpu_firmware *fw);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
new file mode 100644
index 00000000..1622849a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __FLCNIFCMN_H__
+#define __FLCNIFCMN_H__
+
+#define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0
+
+struct falc_u64 {
+        u32 lo;
+        u32 hi;
+};
+
+struct falc_dma_addr {
+        u32 dma_base;
+        /*
+         * dma_base1 is 9-bit MSB for FB Base
+         * address for the transfer in FB after
+         * address using 49b FB address
+         */
+        u16 dma_base1;
+        u8 dma_offset;
+};
+
+struct pmu_mem_v0 {
+        u32 dma_base;
+        u8  dma_offset;
+        u8  dma_idx;
+};
+
+struct pmu_mem_v1 {
+        u32 dma_base;
+        u8  dma_offset;
+        u8  dma_idx;
+        u16 fb_size;
+};
+
+struct pmu_mem_v2 {
+        struct falc_dma_addr dma_addr;
+        u8  dma_idx;
+        u16 fb_size;
+};
+
+struct pmu_mem_desc_v0 {
+        struct falc_u64 dma_addr;
+        u16       dma_sizemax;
+        u8        dma_idx;
+};
+
+struct pmu_dmem {
+        u16 size;
+        u32 offset;
+};
+
+struct flcn_mem_desc_v0 {
+        struct falc_u64 address;
+        u32 params;
+};
+
+#define nv_flcn_mem_desc flcn_mem_desc_v0
+
+struct pmu_allocation_v0 {
+        u8 pad[3];
+        u8 fb_mem_use;
+        struct {
+                struct pmu_dmem dmem;
+                struct pmu_mem_v0 fb;
+        } alloc;
+};
+
+struct pmu_allocation_v1 {
+        struct {
+                struct pmu_dmem dmem;
+                struct pmu_mem_v1 fb;
+        } alloc;
+};
+
+struct pmu_allocation_v2 {
+        struct {
+                struct pmu_dmem dmem;
+                struct pmu_mem_desc_v0 fb;
+        } alloc;
+};
+
+struct pmu_allocation_v3 {
+        struct {
+                struct pmu_dmem dmem;
+                struct flcn_mem_desc_v0 fb;
+        } alloc;
+};
+
+#define nv_pmu_allocation pmu_allocation_v3
+
+struct pmu_hdr {
+        u8 unit_id;
+        u8 size;
+        u8 ctrl_flags;
+        u8 seq_id;
+};
+
+#define PMU_MSG_HDR_SIZE        sizeof(struct pmu_hdr)
+#define PMU_CMD_HDR_SIZE        sizeof(struct pmu_hdr)
+
+#define nv_pmu_hdr pmu_hdr
+typedef u8 flcn_status;
+
+#define PMU_DMEM_ALLOC_ALIGNMENT        (4)
+#define PMU_DMEM_ALIGNMENT              (4)
+
+#define PMU_CMD_FLAGS_PMU_MASK          (0xF0)
+
+#define PMU_CMD_FLAGS_STATUS            BIT(0)
+#define PMU_CMD_FLAGS_INTR              BIT(1)
+#define PMU_CMD_FLAGS_EVENT             BIT(2)
+#define PMU_CMD_FLAGS_WATERMARK         BIT(3)
+
+#define ALIGN_UP(v, gran)       (((v) + ((gran) - 1)) & ~((gran)-1))
+
+#define NV_UNSIGNED_ROUNDED_DIV(a, b)    (((a) + ((b) / 2)) / (b))
+
+#endif /* _FLCNIFCMN_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
new file mode 100644
index 00000000..15a656e4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_FUSE_H__
+#define __NVGPU_FUSE_H__
+
+struct gk20a;
+
+int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g);
+
+void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val);
+void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val);
+void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val);
+void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val);
+int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
+int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
new file mode 100644
index 00000000..ca07e359
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_GMMU_H__
+#define __NVGPU_GMMU_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/list.h>
+#include <nvgpu/rbtree.h>
+#include <nvgpu/lock.h>
+
+#ifdef CONFIG_TEGRA_19x_GPU
+#include <nvgpu/gmmu_t19x.h>
+#endif
+
+/*
+ * This is the GMMU API visible to blocks outside of the GMMU. Basically this
+ * API supports all the different types of mappings that might be done in the
+ * GMMU.
+ */
+
+struct vm_gk20a;
+struct nvgpu_mem;
+
+enum gmmu_pgsz_gk20a {
+        gmmu_page_size_small  = 0,
+        gmmu_page_size_big    = 1,
+        gmmu_page_size_kernel = 2,
+        gmmu_nr_page_sizes    = 3,
+};
+
+enum gk20a_mem_rw_flag {
+        gk20a_mem_flag_none = 0,        /* RW */
+        gk20a_mem_flag_read_only = 1,   /* RO */
+        gk20a_mem_flag_write_only = 2,  /* WO */
+};
+
+/*
+ * Minimum size of a cache. The number of different caches in the nvgpu_pd_cache
+ * structure is of course depending on this. The MIN_SHIFT define is the right
+ * number of bits to shift to determine which list to use in the array of lists.
+ */
+#define NVGPU_PD_CACHE_MIN              256
+#define NVGPU_PD_CACHE_MIN_SHIFT        9
+#define NVGPU_PD_CACHE_COUNT            4
+
+struct nvgpu_pd_mem_entry {
+        struct nvgpu_mem                mem;
+
+        /*
+         * Size of the page directories (not the mem). bmap is a bitmap showing
+         * which PDs have been allocated. The size of mem will always be one
+         * page. pd_size will always be a power of 2.
+         */
+        u32                             pd_size;
+        unsigned long                   alloc_map;
+
+        struct nvgpu_list_node          list_entry;
+        struct nvgpu_rbtree_node        tree_entry;
+};
+
+static inline struct nvgpu_pd_mem_entry *
+nvgpu_pd_mem_entry_from_list_entry(struct nvgpu_list_node *node)
+{
+        return (struct nvgpu_pd_mem_entry *)
+                ((uintptr_t)node -
+                 offsetof(struct nvgpu_pd_mem_entry, list_entry));
+};
+
+static inline struct nvgpu_pd_mem_entry *
+nvgpu_pd_mem_entry_from_tree_entry(struct nvgpu_rbtree_node *node)
+{
+        return (struct nvgpu_pd_mem_entry *)
+                ((uintptr_t)node -
+                 offsetof(struct nvgpu_pd_mem_entry, tree_entry));
+};
+
+/*
+ * A cache for allocating PD memory from. This enables smaller PDs to be packed
+ * into single pages.
+ *
+ * This is fairly complex so see the documentation in pd_cache.c for a full
+ * description of how this is organized.
+ */
+struct nvgpu_pd_cache {
+        /*
+         * Array of lists of full nvgpu_pd_mem_entries and partially full (or
+         * empty) nvgpu_pd_mem_entries.
+         */
+        struct nvgpu_list_node           full[NVGPU_PD_CACHE_COUNT];
+        struct nvgpu_list_node           partial[NVGPU_PD_CACHE_COUNT];
+
+        /*
+         * Tree of all allocated struct nvgpu_mem's for fast look up.
+         */
+        struct nvgpu_rbtree_node        *mem_tree;
+
+        /*
+         * All access to the cache much be locked. This protects the lists and
+         * the rb tree.
+         */
+        struct nvgpu_mutex               lock;
+};
+
+/*
+ * GMMU page directory. This is the kernel's tracking of a list of PDEs or PTEs
+ * in the GMMU.
+ */
+struct nvgpu_gmmu_pd {
+        /*
+         * DMA memory describing the PTEs or PDEs. @mem_offs describes the
+         * offset of the PDE table in @mem. @cached specifies if this PD is
+         * using pd_cache memory.
+         */
+        struct nvgpu_mem        *mem;
+        u32                      mem_offs;
+        bool                     cached;
+
+        /*
+         * List of pointers to the next level of page tables. Does not
+         * need to be populated when this PD is pointing to PTEs.
+         */
+        struct nvgpu_gmmu_pd    *entries;
+        int                      num_entries;
+};
+
+/*
+ * Reduce the number of arguments getting passed through the various levels of
+ * GMMU mapping functions.
+ *
+ * The following fields are set statically and do not change throughout the
+ * mapping call:
+ *
+ *   pgsz:        Index into the page size table.
+ *   kind_v:      Kind attributes for mapping.
+ *   cacheable:   Cacheability of the mapping.
+ *   rw_flag:     Flag from enum gk20a_mem_rw_flag
+ *   sparse:      Set if the mapping should be sparse.
+ *   priv:        Privilidged mapping.
+ *   coherent:    Set if the mapping should be IO coherent.
+ *   valid:       Set if the PTE should be marked valid.
+ *   aperture:    VIDMEM or SYSMEM.
+ *   debug:       When set print debugging info.
+ *
+ * These fields are dynamically updated as necessary during the map:
+ *
+ *   ctag:        Comptag line in the comptag cache;
+ *                updated every time we write a PTE.
+ */
+struct nvgpu_gmmu_attrs {
+        u32                      pgsz;
+        u32                      kind_v;
+        u64                      ctag;
+        bool                     cacheable;
+        int                      rw_flag;
+        bool                     sparse;
+        bool                     priv;
+        bool                     coherent;
+        bool                     valid;
+        enum nvgpu_aperture      aperture;
+        bool                     debug;
+
+#ifdef CONFIG_TEGRA_19x_GPU
+        struct nvgpu_gmmu_attrs_t19x t19x_attrs;
+#endif
+};
+
+struct gk20a_mmu_level {
+        int hi_bit[2];
+        int lo_bit[2];
+
+        /*
+         * Build map from virt_addr -> phys_addr.
+         */
+        void (*update_entry)(struct vm_gk20a *vm,
+                             const struct gk20a_mmu_level *l,
+                             struct nvgpu_gmmu_pd *pd,
+                             u32 pd_idx,
+                             u64 phys_addr,
+                             u64 virt_addr,
+                             struct nvgpu_gmmu_attrs *attrs);
+        u32 entry_size;
+        /*
+         * Get pde page size
+         */
+        enum gmmu_pgsz_gk20a (*get_pgsz)(struct gk20a *g,
+                                         struct nvgpu_gmmu_pd *pd, u32 pd_idx);
+};
+
+static inline const char *nvgpu_gmmu_perm_str(enum gk20a_mem_rw_flag p)
+{
+        switch (p) {
+        case gk20a_mem_flag_none:
+                return "RW";
+        case gk20a_mem_flag_write_only:
+                return "WO";
+        case gk20a_mem_flag_read_only:
+                return "RO";
+        default:
+                return "??";
+        }
+}
+
+int nvgpu_gmmu_init_page_table(struct vm_gk20a *vm);
+
+/**
+ * nvgpu_gmmu_map - Map memory into the GMMU.
+ *
+ * Kernel space.
+ */
+u64 nvgpu_gmmu_map(struct vm_gk20a *vm,
+                   struct nvgpu_mem *mem,
+                   u64 size,
+                   u32 flags,
+                   int rw_flag,
+                   bool priv,
+                   enum nvgpu_aperture aperture);
+
+/**
+ * nvgpu_gmmu_map_fixed - Map memory into the GMMU.
+ *
+ * Kernel space.
+ */
+u64 nvgpu_gmmu_map_fixed(struct vm_gk20a *vm,
+                         struct nvgpu_mem *mem,
+                         u64 addr,
+                         u64 size,
+                         u32 flags,
+                         int rw_flag,
+                         bool priv,
+                         enum nvgpu_aperture aperture);
+
+/**
+ * nvgpu_gmmu_unmap - Unmap a buffer.
+ *
+ * Kernel space.
+ */
+void nvgpu_gmmu_unmap(struct vm_gk20a *vm,
+                      struct nvgpu_mem *mem,
+                      u64 gpu_va);
+
+int __nvgpu_pd_alloc(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pd, u32 bytes);
+void __nvgpu_pd_free(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pd);
+int __nvgpu_pd_cache_alloc_direct(struct gk20a *g,
+                                  struct nvgpu_gmmu_pd *pd, u32 bytes);
+void __nvgpu_pd_cache_free_direct(struct gk20a *g, struct nvgpu_gmmu_pd *pd);
+int nvgpu_pd_cache_init(struct gk20a *g);
+void nvgpu_pd_cache_fini(struct gk20a *g);
+
+/*
+ * Some useful routines that are shared across chips.
+ */
+static inline u32 pd_offset_from_index(const struct gk20a_mmu_level *l,
+                                       u32 pd_idx)
+{
+        return (pd_idx * l->entry_size) / sizeof(u32);
+}
+
+static inline void pd_write(struct gk20a *g, struct nvgpu_gmmu_pd *pd,
+                            size_t w, size_t data)
+{
+        nvgpu_mem_wr32(g, pd->mem, (pd->mem_offs / sizeof(u32)) + w, data);
+}
+
+/**
+ * __nvgpu_pte_words - Compute number of words in a PTE.
+ *
+ * @g  - The GPU.
+ *
+ * This computes and returns the size of a PTE for the passed chip.
+ */
+u32 __nvgpu_pte_words(struct gk20a *g);
+
+/**
+ * __nvgpu_get_pte - Get the contents of a PTE by virtual address
+ *
+ * @g     - The GPU.
+ * @vm    - VM to look in.
+ * @vaddr - GPU virtual address.
+ * @pte   - [out] Set to the contents of the PTE.
+ *
+ * Find a PTE in the passed VM based on the passed GPU virtual address. This
+ * will @pte with a copy of the contents of the PTE. @pte must be an array of
+ * u32s large enough to contain the PTE. This can be computed using
+ * __nvgpu_pte_words().
+ *
+ * If you wish to write to this PTE then you may modify @pte and then use the
+ * __nvgpu_set_pte().
+ *
+ * This function returns 0 if the PTE is found and -EINVAL otherwise.
+ */
+int __nvgpu_get_pte(struct gk20a *g, struct vm_gk20a *vm, u64 vaddr, u32 *pte);
+
+/**
+ * __nvgpu_set_pte - Set a PTE based on virtual address
+ *
+ * @g     - The GPU.
+ * @vm    - VM to look in.
+ * @vaddr - GPU virtual address.
+ * @pte   - The contents of the PTE to write.
+ *
+ * Find a PTE and overwrite the contents of that PTE with the passed in data
+ * located in @pte. If the PTE does not exist then no writing will happen. That
+ * is this function will not fill out the page tables for you. The expectation
+ * is that the passed @vaddr has already been mapped and this is just modifying
+ * the mapping (for instance changing invalid to valid).
+ *
+ * @pte must contain at least the required words for the PTE. See
+ * __nvgpu_pte_words().
+ *
+ * This function returns 0 on success and -EINVAL otherwise.
+ */
+int __nvgpu_set_pte(struct gk20a *g, struct vm_gk20a *vm, u64 vaddr, u32 *pte);
+
+
+/*
+ * Internal debugging routines. Probably not something you want to use.
+ */
+#define pte_dbg(g, attrs, fmt, args...)                                 \
+        do {                                                            \
+                if (attrs && attrs->debug)                              \
+                        nvgpu_info(g, fmt, ##args);                     \
+                else                                                    \
+                        nvgpu_log(g, gpu_dbg_pte, fmt, ##args);         \
+        } while (0)
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hashtable.h b/drivers/gpu/nvgpu/include/nvgpu/hashtable.h
new file mode 100644
index 00000000..5ce56f05
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hashtable.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_SORT_H__
+#define __NVGPU_SORT_H__
+
+#ifdef __KERNEL__
+#include <linux/hashtable.h>
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h
new file mode 100644
index 00000000..d3bb9e98
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_bus_gk20a_h_
+#define _hw_bus_gk20a_h_
+
+static inline u32 bus_bar0_window_r(void)
+{
+        return 0x00001700U;
+}
+static inline u32 bus_bar0_window_base_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 bus_bar0_window_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 bus_bar1_block_r(void)
+{
+        return 0x00001704U;
+}
+static inline u32 bus_bar1_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar1_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar1_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar2_block_r(void)
+{
+        return 0x00001714U;
+}
+static inline u32 bus_bar2_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar2_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar2_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar1_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bar2_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_intr_0_r(void)
+{
+        return 0x00001100U;
+}
+static inline u32 bus_intr_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 bus_intr_en_0_r(void)
+{
+        return 0x00001140U;
+}
+static inline u32 bus_intr_en_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_en_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_en_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h
new file mode 100644
index 00000000..95151f62
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ccsr_gk20a_h_
+#define _hw_ccsr_gk20a_h_
+
+static inline u32 ccsr_channel_inst_r(u32 i)
+{
+        return 0x00800000U + i*8U;
+}
+static inline u32 ccsr_channel_inst__size_1_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ccsr_channel_inst_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 ccsr_channel_inst_bind_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_bind_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 ccsr_channel_r(u32 i)
+{
+        return 0x00800004U + i*8U;
+}
+static inline u32 ccsr_channel__size_1_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ccsr_channel_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ccsr_channel_enable_set_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 ccsr_channel_enable_set_true_f(void)
+{
+        return 0x400U;
+}
+static inline u32 ccsr_channel_enable_clr_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ccsr_channel_runlist_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 ccsr_channel_status_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h
new file mode 100644
index 00000000..87481cd4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce2_gk20a_h_
+#define _hw_ce2_gk20a_h_
+
+static inline u32 ce2_intr_status_r(void)
+{
+        return 0x00106908U;
+}
+static inline u32 ce2_intr_status_blockpipe_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce2_intr_status_blockpipe_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce2_intr_status_launcherr_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ce2_intr_status_launcherr_reset_f(void)
+{
+        return 0x4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h
new file mode 100644
index 00000000..131fd12e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ctxsw_prog_gk20a_h_
+#define _hw_ctxsw_prog_gk20a_h_
+
+static inline u32 ctxsw_prog_fecs_header_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_main_image_patch_count_o(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ctxsw_prog_main_image_context_id_o(void)
+{
+        return 0x000000f0U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
+{
+        return 0x00000014U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
+{
+        return 0x00000018U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_o(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_main_image_pm_o(void)
+{
+        return 0x00000028U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
+{
+        return 0x7U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
+{
+        return 0x0000002cU;
+}
+static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
+{
+        return 0x600dc0deU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_local_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
+{
+        return 0xad0becabU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+        return 2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
+{
+        return 0x000000acU;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
+{
+        return 0x000000b0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
+{
+        return 0x000000b4U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
+{
+        return 0x600dbeefU;
+}
+static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void)
+{
+        return 0x00000014U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
+{
+        return 0x00000018U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
+{
+        return 0xffU << 24U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
+{
+        return (r >> 24U) & 0xffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
+{
+        return 0xa000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
+{
+        return 0xb000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
+{
+        return 0xc000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
+{
+        return 0xd000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
+{
+        return 0x5000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
+{
+        return 0xff000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h
new file mode 100644
index 00000000..27fb5884
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_falcon_gk20a_h_
+#define _hw_falcon_gk20a_h_
+
+static inline u32 falcon_falcon_irqsset_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqsclr_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 falcon_falcon_irqstat_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 falcon_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqmode_r(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 falcon_falcon_irqmset_r(void)
+{
+        return 0x00000010U;
+}
+static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_r(void)
+{
+        return 0x00000014U;
+}
+static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqmask_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 falcon_falcon_irqdest_r(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 falcon_falcon_curctx_r(void)
+{
+        return 0x00000050U;
+}
+static inline u32 falcon_falcon_nxtctx_r(void)
+{
+        return 0x00000054U;
+}
+static inline u32 falcon_falcon_mailbox0_r(void)
+{
+        return 0x00000040U;
+}
+static inline u32 falcon_falcon_mailbox1_r(void)
+{
+        return 0x00000044U;
+}
+static inline u32 falcon_falcon_itfen_r(void)
+{
+        return 0x00000048U;
+}
+static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_r(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 falcon_falcon_os_r(void)
+{
+        return 0x00000080U;
+}
+static inline u32 falcon_falcon_engctl_r(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 falcon_falcon_cpuctl_r(void)
+{
+        return 0x00000100U;
+}
+static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_stopped_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 falcon_falcon_imemc_r(u32 i)
+{
+        return 0x00000180U + i*16U;
+}
+static inline u32 falcon_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_imemd_r(u32 i)
+{
+        return 0x00000184U + i*16U;
+}
+static inline u32 falcon_falcon_imemt_r(u32 i)
+{
+        return 0x00000188U + i*16U;
+}
+static inline u32 falcon_falcon_bootvec_r(void)
+{
+        return 0x00000104U;
+}
+static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 falcon_falcon_dmactl_r(void)
+{
+        return 0x0000010cU;
+}
+static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_hwcfg_r(void)
+{
+        return 0x00000108U;
+}
+static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_dmatrfbase_r(void)
+{
+        return 0x00000110U;
+}
+static inline u32 falcon_falcon_dmatrfmoffs_r(void)
+{
+        return 0x00000114U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_r(void)
+{
+        return 0x00000118U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 falcon_falcon_dmatrffboffs_r(void)
+{
+        return 0x0000011cU;
+}
+static inline u32 falcon_falcon_imstat_r(void)
+{
+        return 0x00000144U;
+}
+static inline u32 falcon_falcon_traceidx_r(void)
+{
+        return 0x00000148U;
+}
+static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 falcon_falcon_traceidx_idx_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 falcon_falcon_tracepc_r(void)
+{
+        return 0x0000014cU;
+}
+static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 falcon_falcon_exterraddr_r(void)
+{
+        return 0x00000168U;
+}
+static inline u32 falcon_falcon_exterrstat_r(void)
+{
+        return 0x0000016cU;
+}
+static inline u32 falcon_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 falcon_falcon_icd_cmd_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 falcon_falcon_icd_rdata_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 falcon_falcon_dmemc_r(u32 i)
+{
+        return 0x000001c0U + i*8U;
+}
+static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 falcon_falcon_dmemd_r(u32 i)
+{
+        return 0x000001c4U + i*8U;
+}
+static inline u32 falcon_falcon_debug1_r(void)
+{
+        return 0x00000090U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
+{
+        return 1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 falcon_falcon_debuginfo_r(void)
+{
+        return 0x00000094U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h
new file mode 100644
index 00000000..42df4f5e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fb_gk20a_h_
+#define _hw_fb_gk20a_h_
+
+static inline u32 fb_mmu_ctrl_r(void)
+{
+        return 0x00100c80U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_mmu_invalidate_pdb_r(void)
+{
+        return 0x00100cb8U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_invalidate_r(void)
+{
+        return 0x00100cbcU;
+}
+static inline u32 fb_mmu_invalidate_all_va_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_trigger_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_debug_wr_r(void)
+{
+        return 0x00100cc8U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_s(void)
+{
+        return 2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_rd_r(void)
+{
+        return 0x00100cccU;
+}
+static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_rd_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_ctrl_r(void)
+{
+        return 0x00100cc4U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_vpr_info_r(void)
+{
+        return 0x00100cd0U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+        return 0x00100c10U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h
new file mode 100644
index 00000000..e61e386d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h
@@ -0,0 +1,619 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fifo_gk20a_h_
+#define _hw_fifo_gk20a_h_
+
+static inline u32 fifo_bar1_base_r(void)
+{
+        return 0x00002254U;
+}
+static inline u32 fifo_bar1_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_bar1_base_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_bar1_base_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_runlist_base_r(void)
+{
+        return 0x00002270U;
+}
+static inline u32 fifo_runlist_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_runlist_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 fifo_runlist_r(void)
+{
+        return 0x00002274U;
+}
+static inline u32 fifo_runlist_engine_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 fifo_eng_runlist_base_r(u32 i)
+{
+        return 0x00002280U + i*8U;
+}
+static inline u32 fifo_eng_runlist_base__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_eng_runlist_r(u32 i)
+{
+        return 0x00002284U + i*8U;
+}
+static inline u32 fifo_eng_runlist__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_eng_runlist_length_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 fifo_eng_runlist_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_runlist_timeslice_r(u32 i)
+{
+        return 0x00002310U + i*4U;
+}
+static inline u32 fifo_runlist_timeslice_timeout_128_f(void)
+{
+        return 0x80U;
+}
+static inline u32 fifo_runlist_timeslice_timescale_3_f(void)
+{
+        return 0x3000U;
+}
+static inline u32 fifo_runlist_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_eng_timeout_r(void)
+{
+        return 0x00002a0cU;
+}
+static inline u32 fifo_eng_timeout_period_max_f(void)
+{
+        return 0x7fffffffU;
+}
+static inline u32 fifo_eng_timeout_detection_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fifo_eng_timeout_detection_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_pb_timeslice_r(u32 i)
+{
+        return 0x00002350U + i*4U;
+}
+static inline u32 fifo_pb_timeslice_timeout_16_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fifo_pb_timeslice_timescale_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_pb_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_pbdma_map_r(u32 i)
+{
+        return 0x00002390U + i*4U;
+}
+static inline u32 fifo_intr_0_r(void)
+{
+        return 0x00002100U;
+}
+static inline u32 fifo_intr_0_bind_error_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_bind_error_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_pio_error_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fifo_intr_0_pio_error_reset_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fifo_intr_0_sched_error_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_sched_error_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_chsw_error_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_chsw_error_reset_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_lb_error_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_lb_error_reset_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_intr_0_runlist_event_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fifo_intr_0_channel_intr_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fifo_intr_en_0_r(void)
+{
+        return 0x00002140U;
+}
+static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 fifo_intr_en_1_r(void)
+{
+        return 0x00002528U;
+}
+static inline u32 fifo_intr_bind_error_r(void)
+{
+        return 0x0000252cU;
+}
+static inline u32 fifo_intr_sched_error_r(void)
+{
+        return 0x0000254cU;
+}
+static inline u32 fifo_intr_sched_error_code_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 fifo_intr_chsw_error_r(void)
+{
+        return 0x0000256cU;
+}
+static inline u32 fifo_intr_mmu_fault_id_r(void)
+{
+        return 0x0000259cU;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
+{
+        return 0x00002800U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
+{
+        return 0x00002804U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
+{
+        return 0x00002808U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
+{
+        return 0x0000280cU + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
+{
+        return (r >> 8U) & 0x1fU;
+}
+static inline u32 fifo_intr_pbdma_id_r(void)
+{
+        return 0x000025a0U;
+}
+static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_intr_runlist_r(void)
+{
+        return 0x00002a00U;
+}
+static inline u32 fifo_fb_timeout_r(void)
+{
+        return 0x00002a04U;
+}
+static inline u32 fifo_fb_timeout_period_m(void)
+{
+        return 0x3fffffffU << 0U;
+}
+static inline u32 fifo_fb_timeout_period_max_f(void)
+{
+        return 0x3fffffffU;
+}
+static inline u32 fifo_pb_timeout_r(void)
+{
+        return 0x00002a08U;
+}
+static inline u32 fifo_pb_timeout_detection_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fifo_error_sched_disable_r(void)
+{
+        return 0x0000262cU;
+}
+static inline u32 fifo_sched_disable_r(void)
+{
+        return 0x00002630U;
+}
+static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_runlist_m(u32 i)
+{
+        return 0x1U << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_preempt_r(void)
+{
+        return 0x00002634U;
+}
+static inline u32 fifo_preempt_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_preempt_type_channel_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_preempt_type_tsg_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_preempt_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_preempt_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_trigger_mmu_fault_r(u32 i)
+{
+        return 0x00002a30U + i*4U;
+}
+static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_engine_status_r(u32 i)
+{
+        return 0x00002640U + i*8U;
+}
+static inline u32 fifo_engine_status__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fifo_engine_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_engine_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_ctx_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_engine_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_engine_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_faulted_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fifo_engine_status_faulted_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_engine_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fifo_engine_status_engine_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_engine_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 fifo_pbdma_status_r(u32 i)
+{
+        return 0x00003080U + i*4U;
+}
+static inline u32 fifo_pbdma_status__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_pbdma_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_chsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h
new file mode 100644
index 00000000..d270b5f3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_flush_gk20a_h_
+#define _hw_flush_gk20a_h_
+
+static inline u32 flush_l2_system_invalidate_r(void)
+{
+        return 0x00070004U;
+}
+static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_r(void)
+{
+        return 0x00070010U;
+}
+static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_r(void)
+{
+        return 0x0007000cU;
+}
+static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_r(void)
+{
+        return 0x00070000U;
+}
+static inline u32 flush_fb_flush_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_fb_flush_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h
new file mode 100644
index 00000000..94330a6c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h
@@ -0,0 +1,1199 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gmmu_gk20a_h_
+#define _hw_gmmu_gk20a_h_
+
+static inline u32 gmmu_pde_aperture_big_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pde_aperture_big_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_aperture_big_video_memory_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gmmu_pde_size_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pde_size_full_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_address_big_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_pde_address_big_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pde_aperture_small_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pde_aperture_small_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_aperture_small_video_memory_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gmmu_pde_vol_small_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pde_vol_small_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_pde_vol_small_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_vol_big_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pde_vol_big_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_pde_vol_big_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_address_small_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_pde_address_small_sys_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pde_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pde__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_pte__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_pte_valid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_valid_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_pte_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pte_privilege_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_privilege_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_pte_privilege_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pte_address_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_pte_address_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_address_vid_f(u32 v)
+{
+        return (v & 0x1ffffffU) << 4U;
+}
+static inline u32 gmmu_pte_address_vid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_vol_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_vol_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_pte_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pte_aperture_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_aperture_video_memory_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_pte_read_only_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_read_only_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_pte_write_disable_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_write_disable_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gmmu_pte_read_disable_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_read_disable_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gmmu_pte_comptagline_s(void)
+{
+        return 17U;
+}
+static inline u32 gmmu_pte_comptagline_f(u32 v)
+{
+        return (v & 0x1ffffU) << 12U;
+}
+static inline u32 gmmu_pte_comptagline_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_f(u32 v)
+{
+        return (v & 0xffU) << 4U;
+}
+static inline u32 gmmu_pte_kind_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_kind_invalid_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 gmmu_pte_kind_pitch_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gmmu_pte_kind_z16_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gmmu_pte_kind_z16_2c_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 gmmu_pte_kind_z16_2z_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 gmmu_pte_kind_z16_4cz_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gmmu_pte_kind_s8z24_v(void)
+{
+        return 0x00000011U;
+}
+static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
+{
+        return 0x00000012U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
+{
+        return 0x00000013U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
+{
+        return 0x00000014U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
+{
+        return 0x00000017U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
+{
+        return 0x00000019U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
+{
+        return 0x0000001aU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
+{
+        return 0x0000001bU;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
+{
+        return 0x0000001dU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
+{
+        return 0x0000001eU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
+{
+        return 0x0000001fU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
+{
+        return 0x00000021U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
+{
+        return 0x00000022U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
+{
+        return 0x00000023U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
+{
+        return 0x00000024U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
+{
+        return 0x00000026U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
+{
+        return 0x00000027U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
+{
+        return 0x00000029U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
+{
+        return 0x0000002eU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
+{
+        return 0x0000002fU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
+{
+        return 0x00000033U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
+{
+        return 0x00000034U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
+{
+        return 0x00000035U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
+{
+        return 0x0000003aU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
+{
+        return 0x0000003bU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
+{
+        return 0x0000003dU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
+{
+        return 0x0000003eU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
+{
+        return 0x0000003fU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
+{
+        return 0x00000041U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000042U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000043U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000044U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
+{
+        return 0x00000045U;
+}
+static inline u32 gmmu_pte_kind_z24s8_v(void)
+{
+        return 0x00000046U;
+}
+static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
+{
+        return 0x00000047U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
+{
+        return 0x00000048U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
+{
+        return 0x00000049U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
+{
+        return 0x0000004aU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
+{
+        return 0x0000004bU;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
+{
+        return 0x0000004dU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
+{
+        return 0x0000004eU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
+{
+        return 0x0000004fU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
+{
+        return 0x00000050U;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
+{
+        return 0x00000051U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
+{
+        return 0x00000052U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
+{
+        return 0x00000053U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
+{
+        return 0x00000054U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
+{
+        return 0x00000055U;
+}
+static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
+{
+        return 0x00000056U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
+{
+        return 0x00000057U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
+{
+        return 0x00000058U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
+{
+        return 0x00000059U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
+{
+        return 0x0000005aU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
+{
+        return 0x0000005bU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
+{
+        return 0x0000005cU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
+{
+        return 0x0000005dU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
+{
+        return 0x0000005eU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000063U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000064U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000065U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
+{
+        return 0x00000066U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
+{
+        return 0x00000067U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
+{
+        return 0x00000068U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
+{
+        return 0x00000069U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
+{
+        return 0x0000006aU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
+{
+        return 0x0000006fU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
+{
+        return 0x00000070U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
+{
+        return 0x00000071U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
+{
+        return 0x00000072U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
+{
+        return 0x00000073U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
+{
+        return 0x00000074U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
+{
+        return 0x00000075U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
+{
+        return 0x00000076U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000077U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000078U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000079U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
+{
+        return 0x0000007aU;
+}
+static inline u32 gmmu_pte_kind_zf32_v(void)
+{
+        return 0x0000007bU;
+}
+static inline u32 gmmu_pte_kind_zf32_1z_v(void)
+{
+        return 0x0000007cU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
+{
+        return 0x0000007dU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
+{
+        return 0x0000007eU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
+{
+        return 0x0000007fU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
+{
+        return 0x00000081U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
+{
+        return 0x00000082U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
+{
+        return 0x00000083U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
+{
+        return 0x00000084U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
+{
+        return 0x00000085U;
+}
+static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
+{
+        return 0x00000086U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
+{
+        return 0x00000087U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
+{
+        return 0x00000088U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
+{
+        return 0x00000089U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
+{
+        return 0x0000008aU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x0000008bU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x0000008cU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x0000008dU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x0000008eU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x0000008fU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x00000090U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x00000091U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x00000092U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000097U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000098U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000099U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x0000009aU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x0000009bU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x0000009cU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x0000009dU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x0000009eU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x0000009fU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000a1U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000a2U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000a3U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000a5U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000a6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x000000a7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x000000a9U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x000000aaU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x000000abU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x000000acU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x000000adU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x000000aeU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x000000b3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x000000b4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x000000b5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x000000b6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x000000b7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x000000b8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x000000b9U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x000000baU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x000000bbU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000bcU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000bdU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000beU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000bfU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000c1U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000c2U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
+{
+        return 0x000000c3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
+{
+        return 0x000000c4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
+{
+        return 0x000000c5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
+{
+        return 0x000000c6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
+{
+        return 0x000000c7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
+{
+        return 0x000000c8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
+{
+        return 0x000000ceU;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
+{
+        return 0x000000cfU;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
+{
+        return 0x000000d0U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
+{
+        return 0x000000d1U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
+{
+        return 0x000000d2U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
+{
+        return 0x000000d3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
+{
+        return 0x000000d4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
+{
+        return 0x000000d5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
+{
+        return 0x000000d6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
+{
+        return 0x000000d7U;
+}
+static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
+{
+        return 0x000000feU;
+}
+static inline u32 gmmu_pte_kind_c32_2c_v(void)
+{
+        return 0x000000d8U;
+}
+static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
+{
+        return 0x000000d9U;
+}
+static inline u32 gmmu_pte_kind_c32_2cba_v(void)
+{
+        return 0x000000daU;
+}
+static inline u32 gmmu_pte_kind_c32_2cra_v(void)
+{
+        return 0x000000dbU;
+}
+static inline u32 gmmu_pte_kind_c32_2bra_v(void)
+{
+        return 0x000000dcU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
+{
+        return 0x000000ddU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
+{
+        return 0x000000deU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
+{
+        return 0x000000ccU;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
+{
+        return 0x000000dfU;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
+{
+        return 0x000000e0U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
+{
+        return 0x000000e1U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
+{
+        return 0x000000e2U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
+{
+        return 0x000000e3U;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
+{
+        return 0x000000e4U;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
+{
+        return 0x000000e5U;
+}
+static inline u32 gmmu_pte_kind_c64_2c_v(void)
+{
+        return 0x000000e6U;
+}
+static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
+{
+        return 0x000000e7U;
+}
+static inline u32 gmmu_pte_kind_c64_2cba_v(void)
+{
+        return 0x000000e8U;
+}
+static inline u32 gmmu_pte_kind_c64_2cra_v(void)
+{
+        return 0x000000e9U;
+}
+static inline u32 gmmu_pte_kind_c64_2bra_v(void)
+{
+        return 0x000000eaU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
+{
+        return 0x000000ebU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
+{
+        return 0x000000cdU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
+{
+        return 0x000000edU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
+{
+        return 0x000000eeU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
+{
+        return 0x000000efU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
+{
+        return 0x000000f0U;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
+{
+        return 0x000000f1U;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
+{
+        return 0x000000f2U;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
+{
+        return 0x000000f3U;
+}
+static inline u32 gmmu_pte_kind_c128_2c_v(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 gmmu_pte_kind_c128_2cr_v(void)
+{
+        return 0x000000f5U;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
+{
+        return 0x000000f6U;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
+{
+        return 0x000000f7U;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
+{
+        return 0x000000f9U;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
+{
+        return 0x000000faU;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
+{
+        return 0x000000fbU;
+}
+static inline u32 gmmu_pte_kind_x8c24_v(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
+{
+        return 0x000000fdU;
+}
+static inline u32 gmmu_pte_kind_smsked_message_v(void)
+{
+        return 0x000000caU;
+}
+static inline u32 gmmu_pte_kind_smhost_message_v(void)
+{
+        return 0x000000cbU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
new file mode 100644
index 00000000..ef259bcf
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
@@ -0,0 +1,3771 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gr_gk20a_h_
+#define _hw_gr_gk20a_h_
+
+static inline u32 gr_intr_r(void)
+{
+        return 0x00400100U;
+}
+static inline u32 gr_intr_notify_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_notify_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_semaphore_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_semaphore_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_semaphore_timeout_not_pending_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_intr_semaphore_timeout_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_intr_semaphore_timeout_reset_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_intr_illegal_method_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_method_reset_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_notify_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_illegal_notify_reset_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 gr_intr_firmware_method_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_firmware_method_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_illegal_class_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_illegal_class_reset_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_fecs_error_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_fecs_error_reset_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_class_error_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_class_error_reset_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_exception_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_intr_exception_reset_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_fecs_intr_r(void)
+{
+        return 0x00400144U;
+}
+static inline u32 gr_class_error_r(void)
+{
+        return 0x00400110U;
+}
+static inline u32 gr_class_error_code_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_intr_nonstall_r(void)
+{
+        return 0x00400120U;
+}
+static inline u32 gr_intr_nonstall_trap_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_en_r(void)
+{
+        return 0x0040013cU;
+}
+static inline u32 gr_exception_r(void)
+{
+        return 0x00400108U;
+}
+static inline u32 gr_exception_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception_gpc_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 gr_exception_memfmt_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_exception_ds_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_exception_sked_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 gr_exception1_r(void)
+{
+        return 0x00400118U;
+}
+static inline u32 gr_exception1_gpc_0_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_exception2_r(void)
+{
+        return 0x0040011cU;
+}
+static inline u32 gr_exception_en_r(void)
+{
+        return 0x00400138U;
+}
+static inline u32 gr_exception_en_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception1_en_r(void)
+{
+        return 0x00400130U;
+}
+static inline u32 gr_exception2_en_r(void)
+{
+        return 0x00400134U;
+}
+static inline u32 gr_gpfifo_ctl_r(void)
+{
+        return 0x00400500U;
+}
+static inline u32 gr_gpfifo_ctl_access_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpfifo_status_r(void)
+{
+        return 0x00400504U;
+}
+static inline u32 gr_trapped_addr_r(void)
+{
+        return 0x00400704U;
+}
+static inline u32 gr_trapped_addr_mthd_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 gr_trapped_addr_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_datahigh_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_priv_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_status_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_trapped_data_lo_r(void)
+{
+        return 0x00400708U;
+}
+static inline u32 gr_trapped_data_hi_r(void)
+{
+        return 0x0040070cU;
+}
+static inline u32 gr_trapped_data_mme_r(void)
+{
+        return 0x00400710U;
+}
+static inline u32 gr_trapped_data_mme_pc_v(u32 r)
+{
+        return (r >> 0U) & 0x7ffU;
+}
+static inline u32 gr_status_r(void)
+{
+        return 0x00400700U;
+}
+static inline u32 gr_status_fe_method_upper_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_status_fe_gi_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 gr_status_mask_r(void)
+{
+        return 0x00400610U;
+}
+static inline u32 gr_status_1_r(void)
+{
+        return 0x00400604U;
+}
+static inline u32 gr_status_2_r(void)
+{
+        return 0x00400608U;
+}
+static inline u32 gr_engine_status_r(void)
+{
+        return 0x0040060cU;
+}
+static inline u32 gr_engine_status_value_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+        return 0x00410204U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+        return 0x00410208U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+        return 0x00502c94U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_activity_0_r(void)
+{
+        return 0x00400380U;
+}
+static inline u32 gr_activity_1_r(void)
+{
+        return 0x00400384U;
+}
+static inline u32 gr_activity_2_r(void)
+{
+        return 0x00400388U;
+}
+static inline u32 gr_activity_4_r(void)
+{
+        return 0x00400390U;
+}
+static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
+{
+        return 0x00501000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
+{
+        return 0x00419000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
+{
+        return 0x005046a4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
+{
+        return 0x00419ea4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_pri_sked_activity_r(void)
+{
+        return 0x00407054U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
+{
+        return 0x00502c80U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
+{
+        return 0x00502c84U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
+{
+        return 0x00502c88U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
+{
+        return 0x00502c8cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504500U;
+}
+static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00501d00U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
+{
+        return 0x0041ac80U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
+{
+        return 0x0041ac84U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
+{
+        return 0x0041ac88U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
+{
+        return 0x0041ac8cU;
+}
+static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041c500U;
+}
+static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00419d00U;
+}
+static inline u32 gr_pri_be0_becs_be_activity0_r(void)
+{
+        return 0x00410200U;
+}
+static inline u32 gr_pri_bes_becs_be_activity0_r(void)
+{
+        return 0x00408a00U;
+}
+static inline u32 gr_pri_ds_mpipe_status_r(void)
+{
+        return 0x00405858U;
+}
+static inline u32 gr_pri_fe_go_idle_on_status_r(void)
+{
+        return 0x00404150U;
+}
+static inline u32 gr_pri_fe_go_idle_check_r(void)
+{
+        return 0x00404158U;
+}
+static inline u32 gr_pri_fe_go_idle_info_r(void)
+{
+        return 0x00404194U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
+{
+        return 0x00504238U;
+}
+static inline u32 gr_pri_be0_crop_status1_r(void)
+{
+        return 0x00410134U;
+}
+static inline u32 gr_pri_bes_crop_status1_r(void)
+{
+        return 0x00408934U;
+}
+static inline u32 gr_pri_be0_zrop_status_r(void)
+{
+        return 0x00410048U;
+}
+static inline u32 gr_pri_be0_zrop_status2_r(void)
+{
+        return 0x0041004cU;
+}
+static inline u32 gr_pri_bes_zrop_status_r(void)
+{
+        return 0x00408848U;
+}
+static inline u32 gr_pri_bes_zrop_status2_r(void)
+{
+        return 0x0040884cU;
+}
+static inline u32 gr_pipe_bundle_address_r(void)
+{
+        return 0x00400200U;
+}
+static inline u32 gr_pipe_bundle_address_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pipe_bundle_data_r(void)
+{
+        return 0x00400204U;
+}
+static inline u32 gr_pipe_bundle_config_r(void)
+{
+        return 0x00400208U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_hww_esr_r(void)
+{
+        return 0x00404000U;
+}
+static inline u32 gr_fe_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_fe_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_go_idle_timeout_r(void)
+{
+        return 0x00404154U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_fe_object_table_r(u32 i)
+{
+        return 0x00404200U + i*4U;
+}
+static inline u32 gr_fe_object_table_nvclass_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_r(void)
+{
+        return 0x00404488U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pri_mme_shadow_raw_data_r(void)
+{
+        return 0x0040448cU;
+}
+static inline u32 gr_mme_hww_esr_r(void)
+{
+        return 0x00404490U;
+}
+static inline u32 gr_mme_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_mme_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_memfmt_hww_esr_r(void)
+{
+        return 0x00404600U;
+}
+static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fecs_cpuctl_r(void)
+{
+        return 0x00409100U;
+}
+static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_dmactl_r(void)
+{
+        return 0x0040910cU;
+}
+static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_fecs_os_r(void)
+{
+        return 0x00409080U;
+}
+static inline u32 gr_fecs_idlestate_r(void)
+{
+        return 0x0040904cU;
+}
+static inline u32 gr_fecs_mailbox0_r(void)
+{
+        return 0x00409040U;
+}
+static inline u32 gr_fecs_mailbox1_r(void)
+{
+        return 0x00409044U;
+}
+static inline u32 gr_fecs_irqstat_r(void)
+{
+        return 0x00409008U;
+}
+static inline u32 gr_fecs_irqmode_r(void)
+{
+        return 0x0040900cU;
+}
+static inline u32 gr_fecs_irqmask_r(void)
+{
+        return 0x00409018U;
+}
+static inline u32 gr_fecs_irqdest_r(void)
+{
+        return 0x0040901cU;
+}
+static inline u32 gr_fecs_curctx_r(void)
+{
+        return 0x00409050U;
+}
+static inline u32 gr_fecs_nxtctx_r(void)
+{
+        return 0x00409054U;
+}
+static inline u32 gr_fecs_engctl_r(void)
+{
+        return 0x004090a4U;
+}
+static inline u32 gr_fecs_debug1_r(void)
+{
+        return 0x00409090U;
+}
+static inline u32 gr_fecs_debuginfo_r(void)
+{
+        return 0x00409094U;
+}
+static inline u32 gr_fecs_icd_cmd_r(void)
+{
+        return 0x00409200U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 gr_fecs_icd_rdata_r(void)
+{
+        return 0x0040920cU;
+}
+static inline u32 gr_fecs_imemc_r(u32 i)
+{
+        return 0x00409180U + i*16U;
+}
+static inline u32 gr_fecs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_imemd_r(u32 i)
+{
+        return 0x00409184U + i*16U;
+}
+static inline u32 gr_fecs_imemt_r(u32 i)
+{
+        return 0x00409188U + i*16U;
+}
+static inline u32 gr_fecs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_dmemc_r(u32 i)
+{
+        return 0x004091c0U + i*8U;
+}
+static inline u32 gr_fecs_dmemc_offs_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_v(u32 r)
+{
+        return (r >> 2U) & 0x3fU;
+}
+static inline u32 gr_fecs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_dmemd_r(u32 i)
+{
+        return 0x004091c4U + i*8U;
+}
+static inline u32 gr_fecs_dmatrfbase_r(void)
+{
+        return 0x00409110U;
+}
+static inline u32 gr_fecs_dmatrfmoffs_r(void)
+{
+        return 0x00409114U;
+}
+static inline u32 gr_fecs_dmatrffboffs_r(void)
+{
+        return 0x0040911cU;
+}
+static inline u32 gr_fecs_dmatrfcmd_r(void)
+{
+        return 0x00409118U;
+}
+static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_fecs_bootvec_r(void)
+{
+        return 0x00409104U;
+}
+static inline u32 gr_fecs_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_falcon_hwcfg_r(void)
+{
+        return 0x00409108U;
+}
+static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
+{
+        return 0x0041a108U;
+}
+static inline u32 gr_fecs_falcon_rm_r(void)
+{
+        return 0x00409084U;
+}
+static inline u32 gr_fecs_current_ctx_r(void)
+{
+        return 0x00409b00U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_current_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_current_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_current_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_method_data_r(void)
+{
+        return 0x00409500U;
+}
+static inline u32 gr_fecs_method_push_r(void)
+{
+        return 0x00409504U;
+}
+static inline u32 gr_fecs_method_push_adr_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
+{
+        return 0x00000038U;
+}
+static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
+{
+        return 0x00000039U;
+}
+static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
+{
+        return 0x21U;
+}
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_fecs_host_int_status_r(void)
+{
+        return 0x00409c18U;
+}
+static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_host_int_clear_r(void)
+{
+        return 0x00409c20U;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fecs_host_int_enable_r(void)
+{
+        return 0x00409c24U;
+}
+static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
+{
+        return 0x00409614U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
+{
+        return (r >> 10U) & 0x1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
+{
+        return 0x0040960cU;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x00409800U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
+{
+        return 0x00409820U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
+{
+        return 0x00409840U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_fs_r(void)
+{
+        return 0x00409604U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_m(void)
+{
+        return 0x1fU << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_fecs_cfg_r(void)
+{
+        return 0x00409620U;
+}
+static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_fecs_rc_lanes_r(void)
+{
+        return 0x00409880U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_fecs_ctxsw_status_1_r(void)
+{
+        return 0x00409400U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_adr_r(void)
+{
+        return 0x00409a24U;
+}
+static inline u32 gr_fecs_new_ctx_r(void)
+{
+        return 0x00409b04U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_new_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_new_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_new_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_r(void)
+{
+        return 0x00409a0cU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_r(void)
+{
+        return 0x00409a10U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
+{
+        return 0x00409c00U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
+{
+        return 0x00502c04U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
+{
+        return 0x00502400U;
+}
+static inline u32 gr_fecs_ctxsw_idlestate_r(void)
+{
+        return 0x00409420U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
+{
+        return 0x00502420U;
+}
+static inline u32 gr_rstr2d_gpc_map0_r(void)
+{
+        return 0x0040780cU;
+}
+static inline u32 gr_rstr2d_gpc_map1_r(void)
+{
+        return 0x00407810U;
+}
+static inline u32 gr_rstr2d_gpc_map2_r(void)
+{
+        return 0x00407814U;
+}
+static inline u32 gr_rstr2d_gpc_map3_r(void)
+{
+        return 0x00407818U;
+}
+static inline u32 gr_rstr2d_gpc_map4_r(void)
+{
+        return 0x0040781cU;
+}
+static inline u32 gr_rstr2d_gpc_map5_r(void)
+{
+        return 0x00407820U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_r(void)
+{
+        return 0x004078bcU;
+}
+static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_hww_esr_r(void)
+{
+        return 0x00406018U;
+}
+static inline u32 gr_pd_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_pd_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00406028U + i*4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
+{
+        return (v & 0xfU) << 12U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
+{
+        return (v & 0xfU) << 24U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
+{
+        return (v & 0xfU) << 28U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_r(void)
+{
+        return 0x004064c0U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_r(void)
+{
+        return 0x004064c4U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
+{
+        return 0xffffU;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
+{
+        return (v & 0x7ffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_r(void)
+{
+        return 0x004064c8U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
+{
+        return (v & 0xfffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
+{
+        return 0x00000062U;
+}
+static inline u32 gr_pd_pagepool_r(void)
+{
+        return 0x004064ccU;
+}
+static inline u32 gr_pd_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_pagepool_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_dist_skip_table_r(u32 i)
+{
+        return 0x004064d0U + i*4U;
+}
+static inline u32 gr_pd_dist_skip_table__size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gr_pd_alpha_ratio_table_r(u32 i)
+{
+        return 0x00406800U + i*4U;
+}
+static inline u32 gr_pd_alpha_ratio_table__size_1_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_pd_alpha_ratio_table_gpc_4n0_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_alpha_ratio_table_gpc_4n1_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_alpha_ratio_table_gpc_4n2_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_pd_alpha_ratio_table_gpc_4n3_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gr_pd_beta_ratio_table_r(u32 i)
+{
+        return 0x00406c00U + i*4U;
+}
+static inline u32 gr_pd_beta_ratio_table__size_1_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_pd_beta_ratio_table_gpc_4n0_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_beta_ratio_table_gpc_4n1_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_beta_ratio_table_gpc_4n2_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_pd_beta_ratio_table_gpc_4n3_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gr_ds_debug_r(void)
+{
+        return 0x00405800U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 gr_ds_zbc_color_r_r(void)
+{
+        return 0x00405804U;
+}
+static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_g_r(void)
+{
+        return 0x00405808U;
+}
+static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_b_r(void)
+{
+        return 0x0040580cU;
+}
+static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_a_r(void)
+{
+        return 0x00405810U;
+}
+static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_r(void)
+{
+        return 0x00405814U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
+{
+        return (v & 0x7fU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gr_ds_zbc_z_r(void)
+{
+        return 0x00405818U;
+}
+static inline u32 gr_ds_zbc_z_val_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_ds_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_ds_zbc_z_val__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_ds_zbc_z_val__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_r(void)
+{
+        return 0x0040581cU;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_tbl_index_r(void)
+{
+        return 0x00405820U;
+}
+static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_r(void)
+{
+        return 0x00405824U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_tga_constraintlogic_r(void)
+{
+        return 0x00405830U;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
+{
+        return (v & 0xfffU) << 16U;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_ds_hww_esr_r(void)
+{
+        return 0x00405840U;
+}
+static inline u32 gr_ds_hww_esr_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_report_mask_r(void)
+{
+        return 0x00405844U;
+}
+static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00405870U + i*4U;
+}
+static inline u32 gr_scc_bundle_cb_base_r(void)
+{
+        return 0x00408004U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_bundle_cb_size_r(void)
+{
+        return 0x00408008U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_pagepool_base_r(void)
+{
+        return 0x0040800cU;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_pagepool_r(void)
+{
+        return 0x00408010U;
+}
+static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
+{
+        return 8U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 gr_scc_pagepool_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_init_r(void)
+{
+        return 0x0040802cU;
+}
+static inline u32 gr_scc_init_ram_trigger_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_scc_hww_esr_r(void)
+{
+        return 0x00408030U;
+}
+static inline u32 gr_scc_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_scc_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_sked_hww_esr_r(void)
+{
+        return 0x00407020U;
+}
+static inline u32 gr_sked_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_cwd_fs_r(void)
+{
+        return 0x00405b00U;
+}
+static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpc0_fs_gpc_r(void)
+{
+        return 0x00502608U;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_gpc0_cfg_r(void)
+{
+        return 0x00502620U;
+}
+static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpccs_rc_lanes_r(void)
+{
+        return 0x00502880U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_rc_lane_size_r(u32 i)
+{
+        return 0x00502910U + i*0U;
+}
+static inline u32 gr_gpccs_rc_lane_size__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_s(void)
+{
+        return 24U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_zcull_fs_r(void)
+{
+        return 0x00500910U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_r(void)
+{
+        return 0x00500914U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
+{
+        return 0x00500918U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
+{
+        return 0x00800000U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
+{
+        return 0x00500920U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
+{
+        return 0x00500a04U + i*32U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_gpc0_gpm_pd_active_tpcs_r(void)
+{
+        return 0x00500c08U;
+}
+static inline u32 gr_gpc0_gpm_pd_active_tpcs_num_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
+{
+        return 0x00500c10U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
+{
+        return 0x00500c30U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_gpm_sd_active_tpcs_r(void)
+{
+        return 0x00500c8cU;
+}
+static inline u32 gr_gpc0_gpm_sd_active_tpcs_num_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
+{
+        return 0x00504088U;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_r(void)
+{
+        return 0x005044e8U;
+}
+static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_value_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
+{
+        return 0x00504698U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
+{
+        return 0x0050469cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
+{
+        return 0x00503018U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_r(void)
+{
+        return 0x005030c0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_size_f(u32 v)
+{
+        return (v & 0xfffU) << 16U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_size_m(void)
+{
+        return 0xfffU << 16U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_size_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_size_default_v(void)
+{
+        return 0x00000240U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_size_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg_timeslice_mode_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg2_r(void)
+{
+        return 0x005030e4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg2_start_offset_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_f(u32 v)
+{
+        return (v & 0xfffU) << 16U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_m(void)
+{
+        return 0xfffU << 16U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_default_v(void)
+{
+        return 0x00000648U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpccs_falcon_addr_r(void)
+{
+        return 0x0041a0acU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
+{
+        return (r >> 6U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_s(void)
+{
+        return 12U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_m(void)
+{
+        return 0xfffU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_gpccs_cpuctl_r(void)
+{
+        return 0x0041a100U;
+}
+static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_gpccs_dmactl_r(void)
+{
+        return 0x0041a10cU;
+}
+static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpccs_imemc_r(u32 i)
+{
+        return 0x0041a180U + i*16U;
+}
+static inline u32 gr_gpccs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_imemd_r(u32 i)
+{
+        return 0x0041a184U + i*16U;
+}
+static inline u32 gr_gpccs_imemt_r(u32 i)
+{
+        return 0x0041a188U + i*16U;
+}
+static inline u32 gr_gpccs_imemt__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_gpccs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpccs_dmemc_r(u32 i)
+{
+        return 0x0041a1c0U + i*8U;
+}
+static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_dmemd_r(u32 i)
+{
+        return 0x0041a1c4U + i*8U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x0041a800U + i*4U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_base_r(void)
+{
+        return 0x00418808U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_r(void)
+{
+        return 0x0041880cU;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_s(void)
+{
+        return 11U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_m(void)
+{
+        return 0x7ffU << 0U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_v(u32 r)
+{
+        return (r >> 0U) & 0x7ffU;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_f(void)
+{
+        return 0x18U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
+{
+        return 0x00418810U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_crstr_gpc_map0_r(void)
+{
+        return 0x00418b08U;
+}
+static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map1_r(void)
+{
+        return 0x00418b0cU;
+}
+static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map2_r(void)
+{
+        return 0x00418b10U;
+}
+static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map3_r(void)
+{
+        return 0x00418b14U;
+}
+static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map4_r(void)
+{
+        return 0x00418b18U;
+}
+static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map5_r(void)
+{
+        return 0x00418b1cU;
+}
+static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_map_table_cfg_r(void)
+{
+        return 0x00418bb8U;
+}
+static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
+{
+        return 0x00418980U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
+{
+        return 0x00418984U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
+{
+        return 0x00418988U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
+{
+        return 3U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
+{
+        return 0x7U << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
+{
+        return (r >> 28U) & 0x7U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
+{
+        return 0x0041898cU;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
+{
+        return 0x00418c6cU;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
+{
+        return 0x00419004U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_r(void)
+{
+        return 0x00419008U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
+{
+        return 0x0041980cU;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
+{
+        return 0x00419848U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
+{
+        return 0x00419c00U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00419e44U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x00419e4cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
+{
+        return 0x00419d0cU;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
+{
+        return 0x0041ac94U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
+{
+        return 0x00504610U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
+{
+        return 0x00504614U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
+{
+        return 0x00504618U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00504624U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
+{
+        return 0x00504628U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
+{
+        return 0x00504634U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
+{
+        return 0x00504638U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00419e24U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
+{
+        return 0x0050460cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
+{
+        return 0x00419e50U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
+{
+        return 0x00504650U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
+{
+        return 0x00504224U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
+{
+        return 0x00504648U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
+{
+        return 0x00504770U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
+{
+        return 0x00419f70U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
+{
+        return 0x0050477cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
+{
+        return 0x00419f7cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
+{
+        return 0x0041be08U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
+{
+        return 0x0041bf00U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
+{
+        return 0x0041bf04U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
+{
+        return 0x0041bf08U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
+{
+        return 0x0041bf0cU;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
+{
+        return 0x0041bf10U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
+{
+        return 0x0041bf14U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
+{
+        return 0x0041bfd0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
+{
+        return (v & 0x7U) << 21U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 24U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
+{
+        return 0x0041bfd4U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
+{
+        return 0x0041bfe4U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 5U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 10U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 15U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 20U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 25U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_cfg_r(void)
+{
+        return 0x0041bec0U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_bes_zrop_settings_r(void)
+{
+        return 0x00408850U;
+}
+static inline u32 gr_bes_zrop_settings_num_active_fbps_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_bes_crop_settings_r(void)
+{
+        return 0x00408958U;
+}
+static inline u32 gr_bes_crop_settings_num_active_fbps_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gr_zcull_subregion_qty_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
+{
+        return 0x00504604U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
+{
+        return 0x00504608U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
+{
+        return 0x0050465cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
+{
+        return 0x00504660U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
+{
+        return 0x00504664U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
+{
+        return 0x00504668U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
+{
+        return 0x0050466cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
+{
+        return 0x00504658U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_r(void)
+{
+        return 0x00504670U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
+{
+        return 0x00504694U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
+{
+        return 0x00504730U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
+{
+        return 0x00504734U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
+{
+        return 0x00504738U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
+{
+        return 0x0050473cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
+{
+        return 0x00504740U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
+{
+        return 0x00504744U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
+{
+        return 0x00504748U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
+{
+        return 0x0050474cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_r(void)
+{
+        return 0x00504674U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_r(void)
+{
+        return 0x00504678U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_r(void)
+{
+        return 0x0050467cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_r(void)
+{
+        return 0x00504680U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_r(void)
+{
+        return 0x00504684U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_r(void)
+{
+        return 0x00504688U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_r(void)
+{
+        return 0x0050468cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_r(void)
+{
+        return 0x00504690U;
+}
+static inline u32 gr_fe_pwr_mode_r(void)
+{
+        return 0x00404170U;
+}
+static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fe_pwr_mode_req_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_fe_pwr_mode_req_send_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fe_pwr_mode_req_done_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_l1c_dbg_r(void)
+{
+        return 0x005044b0U;
+}
+static inline u32 gr_gpc0_tpc0_l1c_dbg_cya15_en_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_r(void)
+{
+        return 0x00419ec8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m(void)
+{
+        return 0xffU << 4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_r(void)
+{
+        return 0x00419eacU;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
+{
+        return 0x00419e10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h
new file mode 100644
index 00000000..efe7f98d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ltc_gk20a_h_
+#define _hw_ltc_gk20a_h_
+
+static inline u32 ltc_pltcg_base_v(void)
+{
+        return 0x00140000U;
+}
+static inline u32 ltc_pltcg_extent_v(void)
+{
+        return 0x0017ffffU;
+}
+static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
+{
+        return 0x001410c8U;
+}
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+        return 0x00141200U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+        return 0x0017ea00U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
+{
+        return 0x00141104U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
+{
+        return (r >> 16U) & 0x3U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
+{
+        return 0x0017e8c8U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
+{
+        return 0x001410c8U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
+{
+        return 0x0017e8ccU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
+{
+        return 0x0017e8d0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
+{
+        return 0x0001ffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
+{
+        return 0x0017e8d4U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
+{
+        return (r >> 0U) & 0x3ffffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
+{
+        return 0x0017e8dcU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(u32 r)
+{
+        return (r >> 28U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
+{
+        return 0x0017e91cU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
+{
+        return 0x0017ea44U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
+{
+        return 0x0017ea48U + i*4U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
+{
+        return 0x0017ea58U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
+{
+        return 32U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
+{
+        return 0x0017e924U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
+{
+        return 0x0017e828U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
+{
+        return 0x00140828U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_intr_r(void)
+{
+        return 0x00140820U;
+}
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+        return 0x0017e820U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+        return 0x00141020U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x0017e910U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x0017e914U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x00140910U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x00140914U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h
new file mode 100644
index 00000000..3ca2a290
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_mc_gk20a_h_
+#define _hw_mc_gk20a_h_
+
+static inline u32 mc_boot_0_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_boot_0_architecture_v(u32 r)
+{
+        return (r >> 24U) & 0x1fU;
+}
+static inline u32 mc_boot_0_implementation_v(u32 r)
+{
+        return (r >> 20U) & 0xfU;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 mc_intr_0_r(void)
+{
+        return 0x00000100U;
+}
+static inline u32 mc_intr_0_pfifo_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_intr_0_pgraph_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_intr_0_pmu_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_0_ltc_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 mc_intr_0_priv_ring_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 mc_intr_0_pbus_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_intr_1_r(void)
+{
+        return 0x00000104U;
+}
+static inline u32 mc_intr_mask_0_r(void)
+{
+        return 0x00000640U;
+}
+static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_en_0_r(void)
+{
+        return 0x00000140U;
+}
+static inline u32 mc_intr_en_0_inta_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 mc_intr_en_0_inta_hardware_f(void)
+{
+        return 0x1U;
+}
+static inline u32 mc_intr_mask_1_r(void)
+{
+        return 0x00000644U;
+}
+static inline u32 mc_intr_mask_1_pmu_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_intr_mask_1_pmu_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 mc_intr_mask_1_pmu_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 mc_intr_mask_1_pmu_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_en_1_r(void)
+{
+        return 0x00000144U;
+}
+static inline u32 mc_intr_en_1_inta_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 mc_intr_en_1_inta_hardware_f(void)
+{
+        return 0x1U;
+}
+static inline u32 mc_enable_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 mc_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_enable_l2_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 mc_enable_pmedia_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pmedia_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 mc_enable_pmedia_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 mc_enable_pmedia_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 mc_enable_priv_ring_enabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 mc_enable_ce0_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 mc_enable_pfifo_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_enable_pgraph_enabled_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_enable_pwr_v(u32 r)
+{
+        return (r >> 13U) & 0x1U;
+}
+static inline u32 mc_enable_pwr_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_enable_pwr_enabled_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 mc_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_enable_ce2_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 mc_enable_ce2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 mc_enable_blg_enabled_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 mc_enable_perfmon_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 mc_enable_pb_r(void)
+{
+        return 0x00000204U;
+}
+static inline u32 mc_enable_pb_0_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pb_0_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 mc_enable_pb_0_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 mc_enable_pb_0_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 mc_enable_pb_0_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 mc_elpg_enable_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 mc_elpg_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_elpg_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_elpg_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h
new file mode 100644
index 00000000..338edef2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h
@@ -0,0 +1,567 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pbdma_gk20a_h_
+#define _hw_pbdma_gk20a_h_
+
+static inline u32 pbdma_gp_entry1_r(void)
+{
+        return 0x10000004U;
+}
+static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pbdma_gp_entry1_length_f(u32 v)
+{
+        return (v & 0x1fffffU) << 10U;
+}
+static inline u32 pbdma_gp_entry1_length_v(u32 r)
+{
+        return (r >> 10U) & 0x1fffffU;
+}
+static inline u32 pbdma_gp_base_r(u32 i)
+{
+        return 0x00040048U + i*8192U;
+}
+static inline u32 pbdma_gp_base__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pbdma_gp_base_offset_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 3U;
+}
+static inline u32 pbdma_gp_base_rsvd_s(void)
+{
+        return 3U;
+}
+static inline u32 pbdma_gp_base_hi_r(u32 i)
+{
+        return 0x0004004cU + i*8192U;
+}
+static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 pbdma_gp_fetch_r(u32 i)
+{
+        return 0x00040050U + i*8192U;
+}
+static inline u32 pbdma_gp_get_r(u32 i)
+{
+        return 0x00040014U + i*8192U;
+}
+static inline u32 pbdma_gp_put_r(u32 i)
+{
+        return 0x00040000U + i*8192U;
+}
+static inline u32 pbdma_timeout_r(u32 i)
+{
+        return 0x0004012cU + i*8192U;
+}
+static inline u32 pbdma_timeout__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pbdma_timeout_period_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 pbdma_timeout_period_max_f(void)
+{
+        return 0xffffffffU;
+}
+static inline u32 pbdma_pb_fetch_r(u32 i)
+{
+        return 0x00040054U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_hi_r(u32 i)
+{
+        return 0x00040058U + i*8192U;
+}
+static inline u32 pbdma_get_r(u32 i)
+{
+        return 0x00040018U + i*8192U;
+}
+static inline u32 pbdma_get_hi_r(u32 i)
+{
+        return 0x0004001cU + i*8192U;
+}
+static inline u32 pbdma_put_r(u32 i)
+{
+        return 0x0004005cU + i*8192U;
+}
+static inline u32 pbdma_put_hi_r(u32 i)
+{
+        return 0x00040060U + i*8192U;
+}
+static inline u32 pbdma_formats_r(u32 i)
+{
+        return 0x0004009cU + i*8192U;
+}
+static inline u32 pbdma_formats_gp_fermi0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_formats_pb_fermi1_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_formats_mp_fermi0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_r(u32 i)
+{
+        return 0x00040084U + i*8192U;
+}
+static inline u32 pbdma_pb_header_priv_user_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_method_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_subchannel_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_level_main_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_pb_header_type_inc_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_pb_header_type_non_inc_f(void)
+{
+        return 0x60000000U;
+}
+static inline u32 pbdma_hdr_shadow_r(u32 i)
+{
+        return 0x00040118U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_0_r(u32 i)
+{
+        return 0x00040110U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_1_r(u32 i)
+{
+        return 0x00040114U + i*8192U;
+}
+static inline u32 pbdma_subdevice_r(u32 i)
+{
+        return 0x00040094U + i*8192U;
+}
+static inline u32 pbdma_subdevice_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 pbdma_subdevice_status_active_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_method0_r(u32 i)
+{
+        return 0x000400c0U + i*8192U;
+}
+static inline u32 pbdma_method0_addr_f(u32 v)
+{
+        return (v & 0xfffU) << 2U;
+}
+static inline u32 pbdma_method0_addr_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 pbdma_method0_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 pbdma_method0_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_method0_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_method1_r(u32 i)
+{
+        return 0x000400c8U + i*8192U;
+}
+static inline u32 pbdma_method2_r(u32 i)
+{
+        return 0x000400d0U + i*8192U;
+}
+static inline u32 pbdma_method3_r(u32 i)
+{
+        return 0x000400d8U + i*8192U;
+}
+static inline u32 pbdma_data0_r(u32 i)
+{
+        return 0x000400c4U + i*8192U;
+}
+static inline u32 pbdma_target_r(u32 i)
+{
+        return 0x000400acU + i*8192U;
+}
+static inline u32 pbdma_target_engine_sw_f(void)
+{
+        return 0x1fU;
+}
+static inline u32 pbdma_acquire_r(u32 i)
+{
+        return 0x00040030U + i*8192U;
+}
+static inline u32 pbdma_acquire_retry_man_2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_acquire_retry_exp_2_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
+{
+        return (v & 0xfU) << 11U;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_f(void)
+{
+        return 0x7800U;
+}
+static inline u32 pbdma_acquire_timeout_man_f(u32 v)
+{
+        return (v & 0xffffU) << 15U;
+}
+static inline u32 pbdma_acquire_timeout_man_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 pbdma_acquire_timeout_man_max_f(void)
+{
+        return 0x7fff8000U;
+}
+static inline u32 pbdma_acquire_timeout_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_acquire_timeout_en_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_status_r(u32 i)
+{
+        return 0x00040100U + i*8192U;
+}
+static inline u32 pbdma_channel_r(u32 i)
+{
+        return 0x00040120U + i*8192U;
+}
+static inline u32 pbdma_signature_r(u32 i)
+{
+        return 0x00040010U + i*8192U;
+}
+static inline u32 pbdma_signature_hw_valid_f(void)
+{
+        return 0xfaceU;
+}
+static inline u32 pbdma_signature_sw_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_r(u32 i)
+{
+        return 0x00040008U + i*8192U;
+}
+static inline u32 pbdma_userd_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pbdma_userd_addr_f(u32 v)
+{
+        return (v & 0x7fffffU) << 9U;
+}
+static inline u32 pbdma_userd_hi_r(u32 i)
+{
+        return 0x0004000cU + i*8192U;
+}
+static inline u32 pbdma_userd_hi_addr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_hce_ctrl_r(u32 i)
+{
+        return 0x000400e4U + i*8192U;
+}
+static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_r(u32 i)
+{
+        return 0x00040108U + i*8192U;
+}
+static inline u32 pbdma_intr_0_memreq_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pbdma_intr_0_memreq_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pbdma_intr_0_memflush_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_memop_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_intr_0_lbreq_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
+{
+        return 0x400U;
+}
+static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
+{
+        return 0x800U;
+}
+static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 pbdma_intr_0_gpptr_pending_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 pbdma_intr_0_gpentry_pending_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 pbdma_intr_0_pbptr_pending_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 pbdma_intr_0_pbentry_pending_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 pbdma_intr_0_method_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_intr_0_device_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 pbdma_intr_0_semaphore_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 pbdma_intr_0_acquire_pending_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 pbdma_intr_0_pri_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_intr_0_pbseg_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 pbdma_intr_0_signature_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+        return 0x00040148U + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_r(u32 i)
+{
+        return 0x0004010cU + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_en_1_r(u32 i)
+{
+        return 0x0004014cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_r(u32 i)
+{
+        return 0x0004013cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_udma_nop_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 pbdma_syncpointa_r(u32 i)
+{
+        return 0x000400a4U + i*8192U;
+}
+static inline u32 pbdma_syncpointa_payload_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pbdma_syncpointb_r(u32 i)
+{
+        return 0x000400a8U + i*8192U;
+}
+static inline u32 pbdma_syncpointb_op_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 pbdma_syncpointb_op_wait_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h
new file mode 100644
index 00000000..a93560fb
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_perf_gk20a_h_
+#define _hw_perf_gk20a_h_
+
+static inline u32 perf_pmasys_control_r(void)
+{
+        return 0x001b4000U;
+}
+static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
+{
+        return 0x10U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
+{
+        return 0x20U;
+}
+static inline u32 perf_pmasys_mem_block_r(void)
+{
+        return 0x001b4070U;
+}
+static inline u32 perf_pmasys_mem_block_base_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 perf_pmasys_mem_block_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 perf_pmasys_mem_block_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_outbase_r(void)
+{
+        return 0x001b4074U;
+}
+static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_outbaseupper_r(void)
+{
+        return 0x001b4078U;
+}
+static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 perf_pmasys_outsize_r(void)
+{
+        return 0x001b407cU;
+}
+static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_mem_bytes_r(void)
+{
+        return 0x001b4084U;
+}
+static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_mem_bump_r(void)
+{
+        return 0x001b4088U;
+}
+static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_r(void)
+{
+        return 0x001b40a4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
+{
+        return 0x10U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h
new file mode 100644
index 00000000..10923e2b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pram_gk20a_h_
+#define _hw_pram_gk20a_h_
+
+static inline u32 pram_data032_r(u32 i)
+{
+        return 0x00700000U + i*4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
new file mode 100644
index 00000000..ca2775eb
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringmaster_gk20a_h_
+#define _hw_pri_ringmaster_gk20a_h_
+
+static inline u32 pri_ringmaster_command_r(void)
+{
+        return 0x0012004cU;
+}
+static inline u32 pri_ringmaster_command_cmd_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 pri_ringmaster_command_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_command_data_r(void)
+{
+        return 0x00120048U;
+}
+static inline u32 pri_ringmaster_start_results_r(void)
+{
+        return 0x00120050U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pri_ringmaster_intr_status0_r(void)
+{
+        return 0x00120058U;
+}
+static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status1_r(void)
+{
+        return 0x0012005cU;
+}
+static inline u32 pri_ringmaster_global_ctl_r(void)
+{
+        return 0x00120060U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_enum_fbp_r(void)
+{
+        return 0x00120074U;
+}
+static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_gpc_r(void)
+{
+        return 0x00120078U;
+}
+static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h
new file mode 100644
index 00000000..06e08bd5
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h
@@ -0,0 +1,231 @@
+/*
+ * drivers/video/tegra/host/gk20a/hw_pri_ringstation_fbp_gk20a.h
+ *
+ * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+ /*
+  * Function naming determines intended use:
+  *
+  *     <x>_r(void) : Returns the offset for register <x>.
+  *
+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+  *
+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+  *
+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+  *         and masked to place it at field <y> of register <x>.  This value
+  *         can be |'d with others to produce a full register value for
+  *         register <x>.
+  *
+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+  *         value can be ~'d and then &'d to clear the value of field <y> for
+  *         register <x>.
+  *
+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+  *         to place it at field <y> of register <x>.  This value can be |'d
+  *         with others to produce a full register value for <x>.
+  *
+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+  *         <x> value 'r' after being shifted to place its LSB at bit 0.
+  *         This value is suitable for direct comparison with other unshifted
+  *         values appropriate for use in field <y> of register <x>.
+  *
+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+  *         field <y> of register <x>.  This value is suitable for direct
+  *         comparison with unshifted values appropriate for use in field <y>
+  *         of register <x>.
+  */
+
+#ifndef __hw_pri_ringstation_fbp_gk20a_h__
+#define __hw_pri_ringstation_fbp_gk20a_h__
+/*This file is autogenerated.  Do not edit. */
+
+static inline u32 pri_ringstation_fbp_master_config_r(u32 i)
+{
+        return 0x00124300+((i)*4);
+}
+static inline u32 pri_ringstation_fbp_master_config__size_1_v(void)
+{
+        return 64;
+}
+static inline u32 pri_ringstation_fbp_master_config_timeout_s(void)
+{
+        return 18;
+}
+static inline u32 pri_ringstation_fbp_master_config_timeout_f(u32 v)
+{
+        return (v & 0x3ffff) << 0;
+}
+static inline u32 pri_ringstation_fbp_master_config_timeout_m(void)
+{
+        return 0x3ffff << 0;
+}
+static inline u32 pri_ringstation_fbp_master_config_timeout_v(u32 r)
+{
+        return (r >> 0) & 0x3ffff;
+}
+static inline u32 pri_ringstation_fbp_master_config_timeout_i_v(void)
+{
+        return 0x00000064;
+}
+static inline u32 pri_ringstation_fbp_master_config_timeout_i_f(void)
+{
+        return 0x64;
+}
+static inline u32 pri_ringstation_fbp_master_config_fs_action_s(void)
+{
+        return 1;
+}
+static inline u32 pri_ringstation_fbp_master_config_fs_action_f(u32 v)
+{
+        return (v & 0x1) << 30;
+}
+static inline u32 pri_ringstation_fbp_master_config_fs_action_m(void)
+{
+        return 0x1 << 30;
+}
+static inline u32 pri_ringstation_fbp_master_config_fs_action_v(u32 r)
+{
+        return (r >> 30) & 0x1;
+}
+static inline u32 pri_ringstation_fbp_master_config_fs_action_error_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pri_ringstation_fbp_master_config_fs_action_error_f(void)
+{
+        return 0x0;
+}
+static inline u32 pri_ringstation_fbp_master_config_fs_action_soldier_on_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 pri_ringstation_fbp_master_config_fs_action_soldier_on_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 pri_ringstation_fbp_master_config_reset_action_s(void)
+{
+        return 1;
+}
+static inline u32 pri_ringstation_fbp_master_config_reset_action_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 pri_ringstation_fbp_master_config_reset_action_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 pri_ringstation_fbp_master_config_reset_action_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 pri_ringstation_fbp_master_config_reset_action_error_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pri_ringstation_fbp_master_config_reset_action_error_f(void)
+{
+        return 0x0;
+}
+static inline u32 pri_ringstation_fbp_master_config_reset_action_soldier_on_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 pri_ringstation_fbp_master_config_reset_action_soldier_on_f(void)
+{
+        return 0x80000000;
+}
+static inline u32 pri_ringstation_fbp_master_config_setup_clocks_s(void)
+{
+        return 3;
+}
+static inline u32 pri_ringstation_fbp_master_config_setup_clocks_f(u32 v)
+{
+        return (v & 0x7) << 20;
+}
+static inline u32 pri_ringstation_fbp_master_config_setup_clocks_m(void)
+{
+        return 0x7 << 20;
+}
+static inline u32 pri_ringstation_fbp_master_config_setup_clocks_v(u32 r)
+{
+        return (r >> 20) & 0x7;
+}
+static inline u32 pri_ringstation_fbp_master_config_setup_clocks_i_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pri_ringstation_fbp_master_config_setup_clocks_i_f(void)
+{
+        return 0x0;
+}
+static inline u32 pri_ringstation_fbp_master_config_wait_clocks_s(void)
+{
+        return 3;
+}
+static inline u32 pri_ringstation_fbp_master_config_wait_clocks_f(u32 v)
+{
+        return (v & 0x7) << 24;
+}
+static inline u32 pri_ringstation_fbp_master_config_wait_clocks_m(void)
+{
+        return 0x7 << 24;
+}
+static inline u32 pri_ringstation_fbp_master_config_wait_clocks_v(u32 r)
+{
+        return (r >> 24) & 0x7;
+}
+static inline u32 pri_ringstation_fbp_master_config_wait_clocks_i_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pri_ringstation_fbp_master_config_wait_clocks_i_f(void)
+{
+        return 0x0;
+}
+static inline u32 pri_ringstation_fbp_master_config_hold_clocks_s(void)
+{
+        return 3;
+}
+static inline u32 pri_ringstation_fbp_master_config_hold_clocks_f(u32 v)
+{
+        return (v & 0x7) << 27;
+}
+static inline u32 pri_ringstation_fbp_master_config_hold_clocks_m(void)
+{
+        return 0x7 << 27;
+}
+static inline u32 pri_ringstation_fbp_master_config_hold_clocks_v(u32 r)
+{
+        return (r >> 27) & 0x7;
+}
+static inline u32 pri_ringstation_fbp_master_config_hold_clocks_i_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 pri_ringstation_fbp_master_config_hold_clocks_i_f(void)
+{
+        return 0x0;
+}
+
+#endif /* __hw_pri_ringstation_fbp_gk20a_h__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
new file mode 100644
index 00000000..6b57429e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gk20a_h_
+#define _hw_pri_ringstation_gpc_gk20a_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300U + i*4U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
new file mode 100644
index 00000000..e4d5c3ba
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_sys_gk20a_h_
+#define _hw_pri_ringstation_sys_gk20a_h_
+
+static inline u32 pri_ringstation_sys_master_config_r(u32 i)
+{
+        return 0x00122300U + i*4U;
+}
+static inline u32 pri_ringstation_sys_decode_config_r(void)
+{
+        return 0x00122204U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120U;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124U;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128U;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h
new file mode 100644
index 00000000..5ef03f5a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_proj_gk20a_h_
+#define _hw_proj_gk20a_h_
+
+static inline u32 proj_gpc_base_v(void)
+{
+        return 0x00500000U;
+}
+static inline u32 proj_gpc_shared_base_v(void)
+{
+        return 0x00418000U;
+}
+static inline u32 proj_gpc_stride_v(void)
+{
+        return 0x00008000U;
+}
+static inline u32 proj_ltc_stride_v(void)
+{
+        return 0x00002000U;
+}
+static inline u32 proj_lts_stride_v(void)
+{
+        return 0x00000400U;
+}
+static inline u32 proj_fbpa_stride_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 proj_ppc_in_gpc_base_v(void)
+{
+        return 0x00003000U;
+}
+static inline u32 proj_ppc_in_gpc_shared_base_v(void)
+{
+        return 0x00003e00U;
+}
+static inline u32 proj_ppc_in_gpc_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_rop_base_v(void)
+{
+        return 0x00410000U;
+}
+static inline u32 proj_rop_shared_base_v(void)
+{
+        return 0x00408800U;
+}
+static inline u32 proj_rop_stride_v(void)
+{
+        return 0x00000400U;
+}
+static inline u32 proj_tpc_in_gpc_base_v(void)
+{
+        return 0x00004000U;
+}
+static inline u32 proj_tpc_in_gpc_stride_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 proj_tpc_in_gpc_shared_base_v(void)
+{
+        return 0x00001800U;
+}
+static inline u32 proj_host_num_engines_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_host_num_pbdma_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_fbps_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_gpcs_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_zcull_banks_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 proj_scal_max_gpcs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 proj_scal_max_tpc_per_gpc_v(void)
+{
+        return 0x00000008U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
new file mode 100644
index 00000000..71b73d2a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
@@ -0,0 +1,783 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pwr_gk20a_h_
+#define _hw_pwr_gk20a_h_
+
+static inline u32 pwr_falcon_irqsset_r(void)
+{
+        return 0x0010a000U;
+}
+static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqsclr_r(void)
+{
+        return 0x0010a004U;
+}
+static inline u32 pwr_falcon_irqstat_r(void)
+{
+        return 0x0010a008U;
+}
+static inline u32 pwr_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqmode_r(void)
+{
+        return 0x0010a00cU;
+}
+static inline u32 pwr_falcon_irqmset_r(void)
+{
+        return 0x0010a010U;
+}
+static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_r(void)
+{
+        return 0x0010a014U;
+}
+static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqmask_r(void)
+{
+        return 0x0010a018U;
+}
+static inline u32 pwr_falcon_irqdest_r(void)
+{
+        return 0x0010a01cU;
+}
+static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 pwr_falcon_curctx_r(void)
+{
+        return 0x0010a050U;
+}
+static inline u32 pwr_falcon_nxtctx_r(void)
+{
+        return 0x0010a054U;
+}
+static inline u32 pwr_falcon_mailbox0_r(void)
+{
+        return 0x0010a040U;
+}
+static inline u32 pwr_falcon_mailbox1_r(void)
+{
+        return 0x0010a044U;
+}
+static inline u32 pwr_falcon_itfen_r(void)
+{
+        return 0x0010a048U;
+}
+static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_r(void)
+{
+        return 0x0010a04cU;
+}
+static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 pwr_falcon_os_r(void)
+{
+        return 0x0010a080U;
+}
+static inline u32 pwr_falcon_engctl_r(void)
+{
+        return 0x0010a0a4U;
+}
+static inline u32 pwr_falcon_cpuctl_r(void)
+{
+        return 0x0010a100U;
+}
+static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+        return 0x0010a180U + i*16U;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+        return 0x0010a184U + i*16U;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+        return 0x0010a188U + i*16U;
+}
+static inline u32 pwr_falcon_bootvec_r(void)
+{
+        return 0x0010a104U;
+}
+static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_falcon_dmactl_r(void)
+{
+        return 0x0010a10cU;
+}
+static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_falcon_hwcfg_r(void)
+{
+        return 0x0010a108U;
+}
+static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_dmatrfbase_r(void)
+{
+        return 0x0010a110U;
+}
+static inline u32 pwr_falcon_dmatrfmoffs_r(void)
+{
+        return 0x0010a114U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_r(void)
+{
+        return 0x0010a118U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 pwr_falcon_dmatrffboffs_r(void)
+{
+        return 0x0010a11cU;
+}
+static inline u32 pwr_falcon_exterraddr_r(void)
+{
+        return 0x0010a168U;
+}
+static inline u32 pwr_falcon_exterrstat_r(void)
+{
+        return 0x0010a16cU;
+}
+static inline u32 pwr_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
+{
+        return 0x0010a200U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
+{
+        return 0x0010a20cU;
+}
+static inline u32 pwr_falcon_dmemc_r(u32 i)
+{
+        return 0x0010a1c0U + i*8U;
+}
+static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 pwr_falcon_dmemd_r(u32 i)
+{
+        return 0x0010a1c4U + i*8U;
+}
+static inline u32 pwr_pmu_new_instblk_r(void)
+{
+        return 0x0010a480U;
+}
+static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 pwr_pmu_mutex_id_r(void)
+{
+        return 0x0010a488U;
+}
+static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_id_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 pwr_pmu_mutex_id_release_r(void)
+{
+        return 0x0010a48cU;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_mutex_r(u32 i)
+{
+        return 0x0010a580U + i*4U;
+}
+static inline u32 pwr_pmu_mutex__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 pwr_pmu_mutex_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_queue_head_r(u32 i)
+{
+        return 0x0010a4a0U + i*4U;
+}
+static inline u32 pwr_pmu_queue_head__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_queue_head_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_head_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_queue_tail_r(u32 i)
+{
+        return 0x0010a4b0U + i*4U;
+}
+static inline u32 pwr_pmu_queue_tail__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_head_r(void)
+{
+        return 0x0010a4c8U;
+}
+static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_tail_r(void)
+{
+        return 0x0010a4ccU;
+}
+static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_idle_mask_r(u32 i)
+{
+        return 0x0010a504U + i*16U;
+}
+static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pwr_pmu_idle_count_r(u32 i)
+{
+        return 0x0010a508U + i*16U;
+}
+static inline u32 pwr_pmu_idle_count_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_count_value_v(u32 r)
+{
+        return (r >> 0U) & 0x7fffffffU;
+}
+static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
+{
+        return 0x0010a50cU + i*16U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
+{
+        return 0x0010a9f0U + i*8U;
+}
+static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
+{
+        return 0x0010a9f4U + i*8U;
+}
+static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
+{
+        return 0x0010aa30U + i*8U;
+}
+static inline u32 pwr_pmu_debug_r(u32 i)
+{
+        return 0x0010a5c0U + i*4U;
+}
+static inline u32 pwr_pmu_debug__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_mailbox_r(u32 i)
+{
+        return 0x0010a450U + i*4U;
+}
+static inline u32 pwr_pmu_mailbox__size_1_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 pwr_pmu_bar0_addr_r(void)
+{
+        return 0x0010a7a0U;
+}
+static inline u32 pwr_pmu_bar0_data_r(void)
+{
+        return 0x0010a7a4U;
+}
+static inline u32 pwr_pmu_bar0_ctl_r(void)
+{
+        return 0x0010a7acU;
+}
+static inline u32 pwr_pmu_bar0_timeout_r(void)
+{
+        return 0x0010a7a8U;
+}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+        return 0x0010a988U;
+}
+static inline u32 pwr_pmu_bar0_error_status_r(void)
+{
+        return 0x0010a7b0U;
+}
+static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
+{
+        return 0x0010a6c0U + i*4U;
+}
+static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
+{
+        return 0x0010a6e8U + i*4U;
+}
+static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
+{
+        return 0x0010a710U + i*4U;
+}
+static inline u32 pwr_pmu_pg_intren_r(u32 i)
+{
+        return 0x0010a760U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_r(u32 i)
+{
+        return 0x0010a600U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_s(void)
+{
+        return 1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h
new file mode 100644
index 00000000..ed385d9e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h
@@ -0,0 +1,443 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ram_gk20a_h_
+#define _hw_ram_gk20a_h_
+
+static inline u32 ram_in_ramfc_s(void)
+{
+        return 4096U;
+}
+static inline u32 ram_in_ramfc_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_in_page_dir_base_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ram_in_page_dir_base_target_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 ram_in_page_dir_base_vol_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_page_dir_base_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_page_dir_base_lo_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_page_dir_base_hi_w(void)
+{
+        return 129U;
+}
+static inline u32 ram_in_adr_limit_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_adr_limit_lo_w(void)
+{
+        return 130U;
+}
+static inline u32 ram_in_adr_limit_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_adr_limit_hi_w(void)
+{
+        return 131U;
+}
+static inline u32 ram_in_engine_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_engine_cs_wfi_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_engine_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_engine_cs_fg_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_engine_cs_fg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ram_in_gr_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_gr_wfi_target_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_mode_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
+{
+        return 133U;
+}
+static inline u32 ram_in_base_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ram_in_alloc_size_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ram_fc_size_val_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_fc_gp_put_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_userd_w(void)
+{
+        return 2U;
+}
+static inline u32 ram_fc_userd_hi_w(void)
+{
+        return 3U;
+}
+static inline u32 ram_fc_signature_w(void)
+{
+        return 4U;
+}
+static inline u32 ram_fc_gp_get_w(void)
+{
+        return 5U;
+}
+static inline u32 ram_fc_pb_get_w(void)
+{
+        return 6U;
+}
+static inline u32 ram_fc_pb_get_hi_w(void)
+{
+        return 7U;
+}
+static inline u32 ram_fc_pb_top_level_get_w(void)
+{
+        return 8U;
+}
+static inline u32 ram_fc_pb_top_level_get_hi_w(void)
+{
+        return 9U;
+}
+static inline u32 ram_fc_acquire_w(void)
+{
+        return 12U;
+}
+static inline u32 ram_fc_semaphorea_w(void)
+{
+        return 14U;
+}
+static inline u32 ram_fc_semaphoreb_w(void)
+{
+        return 15U;
+}
+static inline u32 ram_fc_semaphorec_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_fc_semaphored_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_fc_gp_base_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_fc_gp_base_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_fc_gp_fetch_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_fc_pb_fetch_w(void)
+{
+        return 21U;
+}
+static inline u32 ram_fc_pb_fetch_hi_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_fc_pb_put_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_fc_pb_put_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_fc_pb_header_w(void)
+{
+        return 33U;
+}
+static inline u32 ram_fc_pb_count_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_fc_subdevice_w(void)
+{
+        return 37U;
+}
+static inline u32 ram_fc_formats_w(void)
+{
+        return 39U;
+}
+static inline u32 ram_fc_syncpointa_w(void)
+{
+        return 41U;
+}
+static inline u32 ram_fc_syncpointb_w(void)
+{
+        return 42U;
+}
+static inline u32 ram_fc_target_w(void)
+{
+        return 43U;
+}
+static inline u32 ram_fc_hce_ctrl_w(void)
+{
+        return 57U;
+}
+static inline u32 ram_fc_chid_w(void)
+{
+        return 58U;
+}
+static inline u32 ram_fc_chid_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_fc_chid_id_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_runlist_timeslice_w(void)
+{
+        return 62U;
+}
+static inline u32 ram_fc_pb_timeslice_w(void)
+{
+        return 63U;
+}
+static inline u32 ram_userd_base_shift_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 ram_userd_chan_size_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_userd_put_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_userd_get_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_userd_ref_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_userd_put_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_userd_ref_threshold_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_userd_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_userd_get_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_userd_gp_get_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_userd_gp_put_w(void)
+{
+        return 35U;
+}
+static inline u32 ram_userd_gp_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_gp_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_rl_entry_size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+        return (v & 0xfU) << 14U;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+        return 0xc000U;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+        return (v & 0xffU) << 18U;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+        return (v & 0x3fU) << 26U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_sim_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_sim_gk20a.h
new file mode 100644
index 00000000..9d68b35b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_sim_gk20a.h
@@ -0,0 +1,2153 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+ /*
+  * Function naming determines intended use:
+  *
+  *     <x>_r(void) : Returns the offset for register <x>.
+  *
+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+  *
+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+  *
+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+  *         and masked to place it at field <y> of register <x>.  This value
+  *         can be |'d with others to produce a full register value for
+  *         register <x>.
+  *
+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+  *         value can be ~'d and then &'d to clear the value of field <y> for
+  *         register <x>.
+  *
+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+  *         to place it at field <y> of register <x>.  This value can be |'d
+  *         with others to produce a full register value for <x>.
+  *
+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+  *         <x> value 'r' after being shifted to place its LSB at bit 0.
+  *         This value is suitable for direct comparison with other unshifted
+  *         values appropriate for use in field <y> of register <x>.
+  *
+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+  *         field <y> of register <x>.  This value is suitable for direct
+  *         comparison with unshifted values appropriate for use in field <y>
+  *         of register <x>.
+  */
+
+#ifndef __hw_sim_gk20a_h__
+#define __hw_sim_gk20a_h__
+/*This file is autogenerated.  Do not edit. */
+
+static inline u32 sim_send_ring_r(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_target_s(void)
+{
+        return 2;
+}
+static inline u32 sim_send_ring_target_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 sim_send_ring_target_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 sim_send_ring_target_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 sim_send_ring_target_phys_init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_send_ring_target_phys_init_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_send_ring_target_phys__init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_send_ring_target_phys__init_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_send_ring_target_phys__prod_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_send_ring_target_phys__prod_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_send_ring_target_phys_nvm_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_send_ring_target_phys_nvm_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_send_ring_target_phys_pci_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_send_ring_target_phys_pci_f(void)
+{
+        return 0x2;
+}
+static inline u32 sim_send_ring_target_phys_pci_coherent_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 sim_send_ring_target_phys_pci_coherent_f(void)
+{
+        return 0x3;
+}
+static inline u32 sim_send_ring_status_s(void)
+{
+        return 1;
+}
+static inline u32 sim_send_ring_status_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 sim_send_ring_status_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 sim_send_ring_status_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 sim_send_ring_status_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_status_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_status__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_status__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_status__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_status__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_status_invalid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_status_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_status_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_send_ring_status_valid_f(void)
+{
+        return 0x8;
+}
+static inline u32 sim_send_ring_size_s(void)
+{
+        return 2;
+}
+static inline u32 sim_send_ring_size_f(u32 v)
+{
+        return (v & 0x3) << 4;
+}
+static inline u32 sim_send_ring_size_m(void)
+{
+        return 0x3 << 4;
+}
+static inline u32 sim_send_ring_size_v(u32 r)
+{
+        return (r >> 4) & 0x3;
+}
+static inline u32 sim_send_ring_size_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_size_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_size__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_size__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_size__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_size__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_size_4kb_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_size_4kb_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_size_8kb_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_send_ring_size_8kb_f(void)
+{
+        return 0x10;
+}
+static inline u32 sim_send_ring_size_12kb_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_send_ring_size_12kb_f(void)
+{
+        return 0x20;
+}
+static inline u32 sim_send_ring_size_16kb_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 sim_send_ring_size_16kb_f(void)
+{
+        return 0x30;
+}
+static inline u32 sim_send_ring_gp_in_ring_s(void)
+{
+        return 1;
+}
+static inline u32 sim_send_ring_gp_in_ring_f(u32 v)
+{
+        return (v & 0x1) << 11;
+}
+static inline u32 sim_send_ring_gp_in_ring_m(void)
+{
+        return 0x1 << 11;
+}
+static inline u32 sim_send_ring_gp_in_ring_v(u32 r)
+{
+        return (r >> 11) & 0x1;
+}
+static inline u32 sim_send_ring_gp_in_ring__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_gp_in_ring__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_gp_in_ring__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_gp_in_ring__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_gp_in_ring_no_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_gp_in_ring_no_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_gp_in_ring_yes_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_send_ring_gp_in_ring_yes_f(void)
+{
+        return 0x800;
+}
+static inline u32 sim_send_ring_addr_lo_s(void)
+{
+        return 20;
+}
+static inline u32 sim_send_ring_addr_lo_f(u32 v)
+{
+        return (v & 0xfffff) << 12;
+}
+static inline u32 sim_send_ring_addr_lo_m(void)
+{
+        return 0xfffff << 12;
+}
+static inline u32 sim_send_ring_addr_lo_v(u32 r)
+{
+        return (r >> 12) & 0xfffff;
+}
+static inline u32 sim_send_ring_addr_lo__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_addr_lo__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_addr_lo__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_addr_lo__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_hi_r(void)
+{
+        return 0x00000004;
+}
+static inline u32 sim_send_ring_hi_addr_s(void)
+{
+        return 20;
+}
+static inline u32 sim_send_ring_hi_addr_f(u32 v)
+{
+        return (v & 0xfffff) << 0;
+}
+static inline u32 sim_send_ring_hi_addr_m(void)
+{
+        return 0xfffff << 0;
+}
+static inline u32 sim_send_ring_hi_addr_v(u32 r)
+{
+        return (r >> 0) & 0xfffff;
+}
+static inline u32 sim_send_ring_hi_addr__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_hi_addr__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_ring_hi_addr__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_send_ring_hi_addr__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_send_put_r(void)
+{
+        return 0x00000008;
+}
+static inline u32 sim_send_put_pointer_s(void)
+{
+        return 29;
+}
+static inline u32 sim_send_put_pointer_f(u32 v)
+{
+        return (v & 0x1fffffff) << 3;
+}
+static inline u32 sim_send_put_pointer_m(void)
+{
+        return 0x1fffffff << 3;
+}
+static inline u32 sim_send_put_pointer_v(u32 r)
+{
+        return (r >> 3) & 0x1fffffff;
+}
+static inline u32 sim_send_get_r(void)
+{
+        return 0x0000000c;
+}
+static inline u32 sim_send_get_pointer_s(void)
+{
+        return 29;
+}
+static inline u32 sim_send_get_pointer_f(u32 v)
+{
+        return (v & 0x1fffffff) << 3;
+}
+static inline u32 sim_send_get_pointer_m(void)
+{
+        return 0x1fffffff << 3;
+}
+static inline u32 sim_send_get_pointer_v(u32 r)
+{
+        return (r >> 3) & 0x1fffffff;
+}
+static inline u32 sim_recv_ring_r(void)
+{
+        return 0x00000010;
+}
+static inline u32 sim_recv_ring_target_s(void)
+{
+        return 2;
+}
+static inline u32 sim_recv_ring_target_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 sim_recv_ring_target_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 sim_recv_ring_target_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 sim_recv_ring_target_phys_init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_recv_ring_target_phys_init_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_recv_ring_target_phys__init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_recv_ring_target_phys__init_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_recv_ring_target_phys__prod_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_recv_ring_target_phys__prod_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_recv_ring_target_phys_nvm_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_recv_ring_target_phys_nvm_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_recv_ring_target_phys_pci_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_recv_ring_target_phys_pci_f(void)
+{
+        return 0x2;
+}
+static inline u32 sim_recv_ring_target_phys_pci_coherent_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 sim_recv_ring_target_phys_pci_coherent_f(void)
+{
+        return 0x3;
+}
+static inline u32 sim_recv_ring_status_s(void)
+{
+        return 1;
+}
+static inline u32 sim_recv_ring_status_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 sim_recv_ring_status_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 sim_recv_ring_status_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 sim_recv_ring_status_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_status_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_status__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_status__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_status__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_status__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_status_invalid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_status_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_status_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_recv_ring_status_valid_f(void)
+{
+        return 0x8;
+}
+static inline u32 sim_recv_ring_size_s(void)
+{
+        return 2;
+}
+static inline u32 sim_recv_ring_size_f(u32 v)
+{
+        return (v & 0x3) << 4;
+}
+static inline u32 sim_recv_ring_size_m(void)
+{
+        return 0x3 << 4;
+}
+static inline u32 sim_recv_ring_size_v(u32 r)
+{
+        return (r >> 4) & 0x3;
+}
+static inline u32 sim_recv_ring_size_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_size_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_size__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_size__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_size__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_size__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_size_4kb_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_size_4kb_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_size_8kb_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_recv_ring_size_8kb_f(void)
+{
+        return 0x10;
+}
+static inline u32 sim_recv_ring_size_12kb_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_recv_ring_size_12kb_f(void)
+{
+        return 0x20;
+}
+static inline u32 sim_recv_ring_size_16kb_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 sim_recv_ring_size_16kb_f(void)
+{
+        return 0x30;
+}
+static inline u32 sim_recv_ring_gp_in_ring_s(void)
+{
+        return 1;
+}
+static inline u32 sim_recv_ring_gp_in_ring_f(u32 v)
+{
+        return (v & 0x1) << 11;
+}
+static inline u32 sim_recv_ring_gp_in_ring_m(void)
+{
+        return 0x1 << 11;
+}
+static inline u32 sim_recv_ring_gp_in_ring_v(u32 r)
+{
+        return (r >> 11) & 0x1;
+}
+static inline u32 sim_recv_ring_gp_in_ring__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_gp_in_ring__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_gp_in_ring__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_gp_in_ring__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_gp_in_ring_no_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_gp_in_ring_no_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_gp_in_ring_yes_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_recv_ring_gp_in_ring_yes_f(void)
+{
+        return 0x800;
+}
+static inline u32 sim_recv_ring_addr_lo_s(void)
+{
+        return 20;
+}
+static inline u32 sim_recv_ring_addr_lo_f(u32 v)
+{
+        return (v & 0xfffff) << 12;
+}
+static inline u32 sim_recv_ring_addr_lo_m(void)
+{
+        return 0xfffff << 12;
+}
+static inline u32 sim_recv_ring_addr_lo_v(u32 r)
+{
+        return (r >> 12) & 0xfffff;
+}
+static inline u32 sim_recv_ring_addr_lo__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_addr_lo__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_addr_lo__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_addr_lo__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_hi_r(void)
+{
+        return 0x00000014;
+}
+static inline u32 sim_recv_ring_hi_addr_s(void)
+{
+        return 20;
+}
+static inline u32 sim_recv_ring_hi_addr_f(u32 v)
+{
+        return (v & 0xfffff) << 0;
+}
+static inline u32 sim_recv_ring_hi_addr_m(void)
+{
+        return 0xfffff << 0;
+}
+static inline u32 sim_recv_ring_hi_addr_v(u32 r)
+{
+        return (r >> 0) & 0xfffff;
+}
+static inline u32 sim_recv_ring_hi_addr__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_hi_addr__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_ring_hi_addr__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_recv_ring_hi_addr__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_recv_put_r(void)
+{
+        return 0x00000018;
+}
+static inline u32 sim_recv_put_pointer_s(void)
+{
+        return 11;
+}
+static inline u32 sim_recv_put_pointer_f(u32 v)
+{
+        return (v & 0x7ff) << 3;
+}
+static inline u32 sim_recv_put_pointer_m(void)
+{
+        return 0x7ff << 3;
+}
+static inline u32 sim_recv_put_pointer_v(u32 r)
+{
+        return (r >> 3) & 0x7ff;
+}
+static inline u32 sim_recv_get_r(void)
+{
+        return 0x0000001c;
+}
+static inline u32 sim_recv_get_pointer_s(void)
+{
+        return 11;
+}
+static inline u32 sim_recv_get_pointer_f(u32 v)
+{
+        return (v & 0x7ff) << 3;
+}
+static inline u32 sim_recv_get_pointer_m(void)
+{
+        return 0x7ff << 3;
+}
+static inline u32 sim_recv_get_pointer_v(u32 r)
+{
+        return (r >> 3) & 0x7ff;
+}
+static inline u32 sim_config_r(void)
+{
+        return 0x00000020;
+}
+static inline u32 sim_config_mode_s(void)
+{
+        return 1;
+}
+static inline u32 sim_config_mode_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 sim_config_mode_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 sim_config_mode_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 sim_config_mode_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_config_mode_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_config_mode_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_config_mode_enabled_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_config_channels_s(void)
+{
+        return 7;
+}
+static inline u32 sim_config_channels_f(u32 v)
+{
+        return (v & 0x7f) << 1;
+}
+static inline u32 sim_config_channels_m(void)
+{
+        return 0x7f << 1;
+}
+static inline u32 sim_config_channels_v(u32 r)
+{
+        return (r >> 1) & 0x7f;
+}
+static inline u32 sim_config_channels_none_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_config_channels_none_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_config_cached_only_s(void)
+{
+        return 1;
+}
+static inline u32 sim_config_cached_only_f(u32 v)
+{
+        return (v & 0x1) << 8;
+}
+static inline u32 sim_config_cached_only_m(void)
+{
+        return 0x1 << 8;
+}
+static inline u32 sim_config_cached_only_v(u32 r)
+{
+        return (r >> 8) & 0x1;
+}
+static inline u32 sim_config_cached_only_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_config_cached_only_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_config_cached_only_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_config_cached_only_enabled_f(void)
+{
+        return 0x100;
+}
+static inline u32 sim_config_validity_s(void)
+{
+        return 2;
+}
+static inline u32 sim_config_validity_f(u32 v)
+{
+        return (v & 0x3) << 9;
+}
+static inline u32 sim_config_validity_m(void)
+{
+        return 0x3 << 9;
+}
+static inline u32 sim_config_validity_v(u32 r)
+{
+        return (r >> 9) & 0x3;
+}
+static inline u32 sim_config_validity__init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_config_validity__init_f(void)
+{
+        return 0x200;
+}
+static inline u32 sim_config_validity_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_config_validity_valid_f(void)
+{
+        return 0x200;
+}
+static inline u32 sim_config_simulation_s(void)
+{
+        return 2;
+}
+static inline u32 sim_config_simulation_f(u32 v)
+{
+        return (v & 0x3) << 12;
+}
+static inline u32 sim_config_simulation_m(void)
+{
+        return 0x3 << 12;
+}
+static inline u32 sim_config_simulation_v(u32 r)
+{
+        return (r >> 12) & 0x3;
+}
+static inline u32 sim_config_simulation_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_config_simulation_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_config_simulation_fmodel_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_config_simulation_fmodel_f(void)
+{
+        return 0x1000;
+}
+static inline u32 sim_config_simulation_rtlsim_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_config_simulation_rtlsim_f(void)
+{
+        return 0x2000;
+}
+static inline u32 sim_config_secondary_display_s(void)
+{
+        return 1;
+}
+static inline u32 sim_config_secondary_display_f(u32 v)
+{
+        return (v & 0x1) << 14;
+}
+static inline u32 sim_config_secondary_display_m(void)
+{
+        return 0x1 << 14;
+}
+static inline u32 sim_config_secondary_display_v(u32 r)
+{
+        return (r >> 14) & 0x1;
+}
+static inline u32 sim_config_secondary_display_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_config_secondary_display_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_config_secondary_display_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_config_secondary_display_enabled_f(void)
+{
+        return 0x4000;
+}
+static inline u32 sim_config_num_heads_s(void)
+{
+        return 8;
+}
+static inline u32 sim_config_num_heads_f(u32 v)
+{
+        return (v & 0xff) << 17;
+}
+static inline u32 sim_config_num_heads_m(void)
+{
+        return 0xff << 17;
+}
+static inline u32 sim_config_num_heads_v(u32 r)
+{
+        return (r >> 17) & 0xff;
+}
+static inline u32 sim_event_ring_r(void)
+{
+        return 0x00000030;
+}
+static inline u32 sim_event_ring_target_s(void)
+{
+        return 2;
+}
+static inline u32 sim_event_ring_target_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 sim_event_ring_target_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 sim_event_ring_target_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 sim_event_ring_target_phys_init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_event_ring_target_phys_init_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_event_ring_target_phys__init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_event_ring_target_phys__init_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_event_ring_target_phys__prod_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_event_ring_target_phys__prod_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_event_ring_target_phys_nvm_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_event_ring_target_phys_nvm_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_event_ring_target_phys_pci_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_event_ring_target_phys_pci_f(void)
+{
+        return 0x2;
+}
+static inline u32 sim_event_ring_target_phys_pci_coherent_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 sim_event_ring_target_phys_pci_coherent_f(void)
+{
+        return 0x3;
+}
+static inline u32 sim_event_ring_status_s(void)
+{
+        return 1;
+}
+static inline u32 sim_event_ring_status_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 sim_event_ring_status_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 sim_event_ring_status_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 sim_event_ring_status_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_status_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_status__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_status__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_status__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_status__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_status_invalid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_status_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_status_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_event_ring_status_valid_f(void)
+{
+        return 0x8;
+}
+static inline u32 sim_event_ring_size_s(void)
+{
+        return 2;
+}
+static inline u32 sim_event_ring_size_f(u32 v)
+{
+        return (v & 0x3) << 4;
+}
+static inline u32 sim_event_ring_size_m(void)
+{
+        return 0x3 << 4;
+}
+static inline u32 sim_event_ring_size_v(u32 r)
+{
+        return (r >> 4) & 0x3;
+}
+static inline u32 sim_event_ring_size_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_size_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_size__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_size__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_size__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_size__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_size_4kb_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_size_4kb_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_size_8kb_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_event_ring_size_8kb_f(void)
+{
+        return 0x10;
+}
+static inline u32 sim_event_ring_size_12kb_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_event_ring_size_12kb_f(void)
+{
+        return 0x20;
+}
+static inline u32 sim_event_ring_size_16kb_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 sim_event_ring_size_16kb_f(void)
+{
+        return 0x30;
+}
+static inline u32 sim_event_ring_gp_in_ring_s(void)
+{
+        return 1;
+}
+static inline u32 sim_event_ring_gp_in_ring_f(u32 v)
+{
+        return (v & 0x1) << 11;
+}
+static inline u32 sim_event_ring_gp_in_ring_m(void)
+{
+        return 0x1 << 11;
+}
+static inline u32 sim_event_ring_gp_in_ring_v(u32 r)
+{
+        return (r >> 11) & 0x1;
+}
+static inline u32 sim_event_ring_gp_in_ring__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_gp_in_ring__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_gp_in_ring__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_gp_in_ring__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_gp_in_ring_no_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_gp_in_ring_no_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_gp_in_ring_yes_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_event_ring_gp_in_ring_yes_f(void)
+{
+        return 0x800;
+}
+static inline u32 sim_event_ring_addr_lo_s(void)
+{
+        return 20;
+}
+static inline u32 sim_event_ring_addr_lo_f(u32 v)
+{
+        return (v & 0xfffff) << 12;
+}
+static inline u32 sim_event_ring_addr_lo_m(void)
+{
+        return 0xfffff << 12;
+}
+static inline u32 sim_event_ring_addr_lo_v(u32 r)
+{
+        return (r >> 12) & 0xfffff;
+}
+static inline u32 sim_event_ring_addr_lo__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_addr_lo__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_addr_lo__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_addr_lo__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_hi_v(void)
+{
+        return 0x00000034;
+}
+static inline u32 sim_event_ring_hi_addr_s(void)
+{
+        return 20;
+}
+static inline u32 sim_event_ring_hi_addr_f(u32 v)
+{
+        return (v & 0xfffff) << 0;
+}
+static inline u32 sim_event_ring_hi_addr_m(void)
+{
+        return 0xfffff << 0;
+}
+static inline u32 sim_event_ring_hi_addr_v(u32 r)
+{
+        return (r >> 0) & 0xfffff;
+}
+static inline u32 sim_event_ring_hi_addr__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_hi_addr__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_ring_hi_addr__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_event_ring_hi_addr__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_event_put_r(void)
+{
+        return 0x00000038;
+}
+static inline u32 sim_event_put_pointer_s(void)
+{
+        return 30;
+}
+static inline u32 sim_event_put_pointer_f(u32 v)
+{
+        return (v & 0x3fffffff) << 2;
+}
+static inline u32 sim_event_put_pointer_m(void)
+{
+        return 0x3fffffff << 2;
+}
+static inline u32 sim_event_put_pointer_v(u32 r)
+{
+        return (r >> 2) & 0x3fffffff;
+}
+static inline u32 sim_event_get_r(void)
+{
+        return 0x0000003c;
+}
+static inline u32 sim_event_get_pointer_s(void)
+{
+        return 30;
+}
+static inline u32 sim_event_get_pointer_f(u32 v)
+{
+        return (v & 0x3fffffff) << 2;
+}
+static inline u32 sim_event_get_pointer_m(void)
+{
+        return 0x3fffffff << 2;
+}
+static inline u32 sim_event_get_pointer_v(u32 r)
+{
+        return (r >> 2) & 0x3fffffff;
+}
+static inline u32 sim_status_r(void)
+{
+        return 0x00000028;
+}
+static inline u32 sim_status_send_put_s(void)
+{
+        return 1;
+}
+static inline u32 sim_status_send_put_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 sim_status_send_put_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 sim_status_send_put_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 sim_status_send_put__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_send_put__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_send_put_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_send_put_idle_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_send_put_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_send_put_pending_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_status_send_get_s(void)
+{
+        return 1;
+}
+static inline u32 sim_status_send_get_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 sim_status_send_get_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 sim_status_send_get_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 sim_status_send_get__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_send_get__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_send_get_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_send_get_idle_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_send_get_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_send_get_pending_f(void)
+{
+        return 0x2;
+}
+static inline u32 sim_status_send_get_clear_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_send_get_clear_f(void)
+{
+        return 0x2;
+}
+static inline u32 sim_status_recv_put_s(void)
+{
+        return 1;
+}
+static inline u32 sim_status_recv_put_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 sim_status_recv_put_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 sim_status_recv_put_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 sim_status_recv_put__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_recv_put__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_recv_put_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_recv_put_idle_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_recv_put_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_recv_put_pending_f(void)
+{
+        return 0x4;
+}
+static inline u32 sim_status_recv_put_clear_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_recv_put_clear_f(void)
+{
+        return 0x4;
+}
+static inline u32 sim_status_recv_get_s(void)
+{
+        return 1;
+}
+static inline u32 sim_status_recv_get_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 sim_status_recv_get_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 sim_status_recv_get_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 sim_status_recv_get__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_recv_get__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_recv_get_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_recv_get_idle_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_recv_get_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_recv_get_pending_f(void)
+{
+        return 0x8;
+}
+static inline u32 sim_status_event_put_s(void)
+{
+        return 1;
+}
+static inline u32 sim_status_event_put_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 sim_status_event_put_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 sim_status_event_put_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 sim_status_event_put__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_event_put__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_event_put_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_event_put_idle_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_event_put_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_event_put_pending_f(void)
+{
+        return 0x10;
+}
+static inline u32 sim_status_event_put_clear_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_event_put_clear_f(void)
+{
+        return 0x10;
+}
+static inline u32 sim_status_event_get_s(void)
+{
+        return 1;
+}
+static inline u32 sim_status_event_get_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 sim_status_event_get_m(void)
+{
+        return 0x1 << 5;
+}
+static inline u32 sim_status_event_get_v(u32 r)
+{
+        return (r >> 5) & 0x1;
+}
+static inline u32 sim_status_event_get__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_event_get__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_event_get_idle_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_status_event_get_idle_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_status_event_get_pending_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_status_event_get_pending_f(void)
+{
+        return 0x20;
+}
+static inline u32 sim_control_r(void)
+{
+        return 0x0000002c;
+}
+static inline u32 sim_control_send_put_s(void)
+{
+        return 1;
+}
+static inline u32 sim_control_send_put_f(u32 v)
+{
+        return (v & 0x1) << 0;
+}
+static inline u32 sim_control_send_put_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 sim_control_send_put_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 sim_control_send_put__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_send_put__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_send_put_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_send_put_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_send_put_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_control_send_put_enabled_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_control_send_get_s(void)
+{
+        return 1;
+}
+static inline u32 sim_control_send_get_f(u32 v)
+{
+        return (v & 0x1) << 1;
+}
+static inline u32 sim_control_send_get_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 sim_control_send_get_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 sim_control_send_get__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_send_get__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_send_get_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_send_get_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_send_get_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_control_send_get_enabled_f(void)
+{
+        return 0x2;
+}
+static inline u32 sim_control_recv_put_s(void)
+{
+        return 1;
+}
+static inline u32 sim_control_recv_put_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 sim_control_recv_put_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 sim_control_recv_put_v(u32 r)
+{
+        return (r >> 2) & 0x1;
+}
+static inline u32 sim_control_recv_put__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_recv_put__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_recv_put_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_recv_put_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_recv_put_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_control_recv_put_enabled_f(void)
+{
+        return 0x4;
+}
+static inline u32 sim_control_recv_get_s(void)
+{
+        return 1;
+}
+static inline u32 sim_control_recv_get_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 sim_control_recv_get_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 sim_control_recv_get_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 sim_control_recv_get__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_recv_get__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_recv_get_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_recv_get_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_recv_get_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_control_recv_get_enabled_f(void)
+{
+        return 0x8;
+}
+static inline u32 sim_control_event_put_s(void)
+{
+        return 1;
+}
+static inline u32 sim_control_event_put_f(u32 v)
+{
+        return (v & 0x1) << 4;
+}
+static inline u32 sim_control_event_put_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 sim_control_event_put_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 sim_control_event_put__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_event_put__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_event_put_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_event_put_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_event_put_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_control_event_put_enabled_f(void)
+{
+        return 0x10;
+}
+static inline u32 sim_control_event_get_s(void)
+{
+        return 1;
+}
+static inline u32 sim_control_event_get_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 sim_control_event_get_m(void)
+{
+        return 0x1 << 5;
+}
+static inline u32 sim_control_event_get_v(u32 r)
+{
+        return (r >> 5) & 0x1;
+}
+static inline u32 sim_control_event_get__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_event_get__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_event_get_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_control_event_get_disabled_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_control_event_get_enabled_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_control_event_get_enabled_f(void)
+{
+        return 0x20;
+}
+static inline u32 sim_dma_r(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_target_s(void)
+{
+        return 2;
+}
+static inline u32 sim_dma_target_f(u32 v)
+{
+        return (v & 0x3) << 0;
+}
+static inline u32 sim_dma_target_m(void)
+{
+        return 0x3 << 0;
+}
+static inline u32 sim_dma_target_v(u32 r)
+{
+        return (r >> 0) & 0x3;
+}
+static inline u32 sim_dma_target_phys_init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_dma_target_phys_init_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_dma_target_phys__init_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_dma_target_phys__init_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_dma_target_phys__prod_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_dma_target_phys__prod_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_dma_target_phys_nvm_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_dma_target_phys_nvm_f(void)
+{
+        return 0x1;
+}
+static inline u32 sim_dma_target_phys_pci_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_dma_target_phys_pci_f(void)
+{
+        return 0x2;
+}
+static inline u32 sim_dma_target_phys_pci_coherent_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 sim_dma_target_phys_pci_coherent_f(void)
+{
+        return 0x3;
+}
+static inline u32 sim_dma_status_s(void)
+{
+        return 1;
+}
+static inline u32 sim_dma_status_f(u32 v)
+{
+        return (v & 0x1) << 3;
+}
+static inline u32 sim_dma_status_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 sim_dma_status_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 sim_dma_status_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_status_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_status__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_status__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_status__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_status__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_status_invalid_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_status_invalid_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_status_valid_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_dma_status_valid_f(void)
+{
+        return 0x8;
+}
+static inline u32 sim_dma_size_s(void)
+{
+        return 2;
+}
+static inline u32 sim_dma_size_f(u32 v)
+{
+        return (v & 0x3) << 4;
+}
+static inline u32 sim_dma_size_m(void)
+{
+        return 0x3 << 4;
+}
+static inline u32 sim_dma_size_v(u32 r)
+{
+        return (r >> 4) & 0x3;
+}
+static inline u32 sim_dma_size_init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_size_init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_size__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_size__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_size__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_size__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_size_4kb_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_size_4kb_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_size_8kb_v(void)
+{
+        return 0x00000001;
+}
+static inline u32 sim_dma_size_8kb_f(void)
+{
+        return 0x10;
+}
+static inline u32 sim_dma_size_12kb_v(void)
+{
+        return 0x00000002;
+}
+static inline u32 sim_dma_size_12kb_f(void)
+{
+        return 0x20;
+}
+static inline u32 sim_dma_size_16kb_v(void)
+{
+        return 0x00000003;
+}
+static inline u32 sim_dma_size_16kb_f(void)
+{
+        return 0x30;
+}
+static inline u32 sim_dma_addr_lo_s(void)
+{
+        return 20;
+}
+static inline u32 sim_dma_addr_lo_f(u32 v)
+{
+        return (v & 0xfffff) << 12;
+}
+static inline u32 sim_dma_addr_lo_m(void)
+{
+        return 0xfffff << 12;
+}
+static inline u32 sim_dma_addr_lo_v(u32 r)
+{
+        return (r >> 12) & 0xfffff;
+}
+static inline u32 sim_dma_addr_lo__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_addr_lo__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_addr_lo__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_addr_lo__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_hi_r(void)
+{
+        return 0x00000004;
+}
+static inline u32 sim_dma_hi_addr_s(void)
+{
+        return 20;
+}
+static inline u32 sim_dma_hi_addr_f(u32 v)
+{
+        return (v & 0xfffff) << 0;
+}
+static inline u32 sim_dma_hi_addr_m(void)
+{
+        return 0xfffff << 0;
+}
+static inline u32 sim_dma_hi_addr_v(u32 r)
+{
+        return (r >> 0) & 0xfffff;
+}
+static inline u32 sim_dma_hi_addr__init_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_hi_addr__init_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_dma_hi_addr__prod_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_dma_hi_addr__prod_f(void)
+{
+        return 0x0;
+}
+static inline u32 sim_msg_signature_r(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_msg_signature_valid_v(void)
+{
+        return 0x43505256;
+}
+static inline u32 sim_msg_length_r(void)
+{
+        return 0x00000004;
+}
+static inline u32 sim_msg_function_r(void)
+{
+        return 0x00000008;
+}
+static inline u32 sim_msg_function_sim_escape_read_v(void)
+{
+        return 0x00000023;
+}
+static inline u32 sim_msg_function_sim_escape_write_v(void)
+{
+        return 0x00000024;
+}
+static inline u32 sim_msg_result_r(void)
+{
+        return 0x0000000c;
+}
+static inline u32 sim_msg_result_success_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 sim_msg_result_rpc_pending_v(void)
+{
+        return 0xFFFFFFFF;
+}
+static inline u32 sim_msg_sequence_r(void)
+{
+        return 0x00000010;
+}
+static inline u32 sim_msg_spare_r(void)
+{
+        return 0x00000014;
+}
+static inline u32 sim_msg_spare__init_v(void)
+{
+        return 0x00000000;
+}
+
+#endif /* __hw_sim_gk20a_h__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h
new file mode 100644
index 00000000..075c9bcc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h
@@ -0,0 +1,367 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_therm_gk20a_h_
+#define _hw_therm_gk20a_h_
+
+static inline u32 therm_use_a_r(void)
+{
+        return 0x00020798U;
+}
+static inline u32 therm_use_a_ext_therm_0_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_use_a_ext_therm_1_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_use_a_ext_therm_2_enable_f(void)
+{
+        return 0x4U;
+}
+static inline u32 therm_evt_ext_therm_0_r(void)
+{
+        return 0x00020700U;
+}
+static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_evt_ext_therm_0_priority_f(u32 v)
+{
+        return (v & 0x1fU) << 24U;
+}
+static inline u32 therm_evt_ext_therm_1_r(void)
+{
+        return 0x00020704U;
+}
+static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_evt_ext_therm_1_priority_f(u32 v)
+{
+        return (v & 0x1fU) << 24U;
+}
+static inline u32 therm_evt_ext_therm_2_r(void)
+{
+        return 0x00020708U;
+}
+static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_evt_ext_therm_2_priority_f(u32 v)
+{
+        return (v & 0x1fU) << 24U;
+}
+static inline u32 therm_weight_1_r(void)
+{
+        return 0x00020024U;
+}
+static inline u32 therm_config1_r(void)
+{
+        return 0x00020050U;
+}
+static inline u32 therm_config2_r(void)
+{
+        return 0x00020130U;
+}
+static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 therm_config2_grad_enable_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 therm_gate_ctrl_r(u32 i)
+{
+        return 0x00020200U + i*4U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_m(void)
+{
+        return 0x3U << 2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
+{
+        return 0x4U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_m(void)
+{
+        return 0x3U << 4U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
+{
+        return 0x10U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
+{
+        return 0x20U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
+{
+        return 0x1fU << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
+{
+        return (v & 0x7U) << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
+{
+        return 0x7U << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
+{
+        return 0xfU << 20U;
+}
+static inline u32 therm_fecs_idle_filter_r(void)
+{
+        return 0x00020288U;
+}
+static inline u32 therm_fecs_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_hubmmu_idle_filter_r(void)
+{
+        return 0x0002028cU;
+}
+static inline u32 therm_hubmmu_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_clk_slowdown_r(u32 i)
+{
+        return 0x00020160U + i*4U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 16U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_m(void)
+{
+        return 0x3fU << 16U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
+{
+        return (r >> 16U) & 0x3fU;
+}
+static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_grad_stepping_table_r(u32 i)
+{
+        return 0x000202c8U + i*4U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
+{
+        return 0x6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
+{
+        return 0xeU;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
+{
+        return (v & 0x3fU) << 12U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
+{
+        return 0x3fU << 12U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
+{
+        return (v & 0x3fU) << 18U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
+{
+        return 0x3fU << 18U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
+{
+        return (v & 0x3fU) << 24U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
+{
+        return 0x3fU << 24U;
+}
+static inline u32 therm_grad_stepping0_r(void)
+{
+        return 0x000202c0U;
+}
+static inline u32 therm_grad_stepping0_feature_s(void)
+{
+        return 1U;
+}
+static inline u32 therm_grad_stepping0_feature_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 therm_grad_stepping0_feature_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 therm_grad_stepping0_feature_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 therm_grad_stepping0_feature_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_grad_stepping1_r(void)
+{
+        return 0x000202c4U;
+}
+static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 therm_clk_timing_r(u32 i)
+{
+        return 0x000203c0U + i*4U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
+{
+        return 0x10000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
new file mode 100644
index 00000000..f0dbfc30
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2013-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_timer_gk20a_h_
+#define _hw_timer_gk20a_h_
+
+static inline u32 timer_pri_timeout_r(void)
+{
+        return 0x00009080U;
+}
+static inline u32 timer_pri_timeout_period_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 timer_pri_timeout_period_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 timer_pri_timeout_period_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 timer_pri_timeout_en_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 timer_pri_timeout_en_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 timer_pri_timeout_en_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 timer_pri_timeout_en_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 timer_pri_timeout_en_en_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 timer_pri_timeout_save_0_r(void)
+{
+        return 0x00009084U;
+}
+static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
+{
+        return (r >> 2) & 0x3fffff;
+}
+static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
+static inline u32 timer_pri_timeout_save_1_r(void)
+{
+        return 0x00009088U;
+}
+static inline u32 timer_pri_timeout_fecs_errcode_r(void)
+{
+        return 0x0000908cU;
+}
+static inline u32 timer_time_0_r(void)
+{
+        return 0x00009400U;
+}
+static inline u32 timer_time_1_r(void)
+{
+        return 0x00009410U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h
new file mode 100644
index 00000000..be7fa4a6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_top_gk20a_h_
+#define _hw_top_gk20a_h_
+
+static inline u32 top_num_gpcs_r(void)
+{
+        return 0x00022430U;
+}
+static inline u32 top_num_gpcs_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_tpc_per_gpc_r(void)
+{
+        return 0x00022434U;
+}
+static inline u32 top_tpc_per_gpc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_fbps_r(void)
+{
+        return 0x00022438U;
+}
+static inline u32 top_num_fbps_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_device_info_r(u32 i)
+{
+        return 0x00022700U + i*4U;
+}
+static inline u32 top_device_info__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 top_device_info_chain_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 top_device_info_chain_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_engine_enum_v(u32 r)
+{
+        return (r >> 26U) & 0xfU;
+}
+static inline u32 top_device_info_runlist_enum_v(u32 r)
+{
+        return (r >> 21U) & 0xfU;
+}
+static inline u32 top_device_info_intr_enum_v(u32 r)
+{
+        return (r >> 15U) & 0x1fU;
+}
+static inline u32 top_device_info_reset_enum_v(u32 r)
+{
+        return (r >> 9U) & 0x1fU;
+}
+static inline u32 top_device_info_type_enum_v(u32 r)
+{
+        return (r >> 2U) & 0x1fffffffU;
+}
+static inline u32 top_device_info_type_enum_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_type_enum_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 top_device_info_type_enum_copy0_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_type_enum_copy0_f(void)
+{
+        return 0x4U;
+}
+static inline u32 top_device_info_type_enum_copy1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 top_device_info_type_enum_copy1_f(void)
+{
+        return 0x8U;
+}
+static inline u32 top_device_info_type_enum_copy2_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_type_enum_copy2_f(void)
+{
+        return 0xcU;
+}
+static inline u32 top_device_info_engine_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 top_device_info_runlist_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 top_device_info_intr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 top_device_info_reset_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_entry_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 top_device_info_entry_not_valid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_entry_enum_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 top_device_info_entry_engine_type_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_entry_data_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_fs_status_fbp_r(void)
+{
+        return 0x00022548U;
+}
+static inline u32 top_fs_status_fbp_cluster_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 top_fs_status_fbp_cluster_enable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_fs_status_fbp_cluster_enable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 top_fs_status_fbp_cluster_disable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_fs_status_fbp_cluster_disable_f(void)
+{
+        return 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h
new file mode 100644
index 00000000..f28c21f1
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_trim_gk20a_h_
+#define _hw_trim_gk20a_h_
+
+static inline u32 trim_sys_gpcpll_cfg_r(void)
+{
+        return 0x00137000U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
+{
+        return 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
+{
+        return 0x10U;
+}
+static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
+{
+        return (r >> 17U) & 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 trim_sys_gpcpll_coeff_r(void)
+{
+        return 0x00137004U;
+}
+static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
+{
+        return (v & 0x3fU) << 16U;
+}
+static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
+{
+        return 0x3fU << 16U;
+}
+static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
+{
+        return (r >> 16U) & 0x3fU;
+}
+static inline u32 trim_sys_sel_vco_r(void)
+{
+        return 0x00137100U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
+{
+        return 0x1U;
+}
+static inline u32 trim_sys_gpc2clk_out_r(void)
+{
+        return 0x00137250U;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
+{
+        return 6U;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
+{
+        return 0x3cU;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
+{
+        return 6U;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
+{
+        return 0x3fU << 8U;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
+{
+        return (r >> 8U) & 0x3fU;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
+{
+        return 0x00134124U + i*512U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
+{
+        return (v & 0x3fffU) << 0U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
+{
+        return 0x00134128U + i*512U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 trim_sys_gpcpll_cfg2_r(void)
+{
+        return 0x0013700cU;
+}
+static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
+{
+        return 0xffU << 24U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_r(void)
+{
+        return 0x00137018U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
+{
+        return 0x0013701cU;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
+{
+        return 0x1U << 22U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
+{
+        return 0x001328a0U;
+}
+static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
new file mode 100644
index 00000000..15cddae2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_bus_gm20b_h_
+#define _hw_bus_gm20b_h_
+
+static inline u32 bus_bar0_window_r(void)
+{
+        return 0x00001700U;
+}
+static inline u32 bus_bar0_window_base_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 bus_bar0_window_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 bus_bar1_block_r(void)
+{
+        return 0x00001704U;
+}
+static inline u32 bus_bar1_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar1_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar1_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar2_block_r(void)
+{
+        return 0x00001714U;
+}
+static inline u32 bus_bar2_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar2_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar2_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar1_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bar2_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bind_status_r(void)
+{
+        return 0x00001710U;
+}
+static inline u32 bus_bind_status_bar1_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar1_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar1_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 bus_bind_status_bar2_pending_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar2_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar2_pending_busy_f(void)
+{
+        return 0x4U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 bus_intr_0_r(void)
+{
+        return 0x00001100U;
+}
+static inline u32 bus_intr_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 bus_intr_en_0_r(void)
+{
+        return 0x00001140U;
+}
+static inline u32 bus_intr_en_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_en_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_en_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
new file mode 100644
index 00000000..adfce723
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ccsr_gm20b_h_
+#define _hw_ccsr_gm20b_h_
+
+static inline u32 ccsr_channel_inst_r(u32 i)
+{
+        return 0x00800000U + i*8U;
+}
+static inline u32 ccsr_channel_inst__size_1_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ccsr_channel_inst_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 ccsr_channel_inst_bind_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_bind_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 ccsr_channel_r(u32 i)
+{
+        return 0x00800004U + i*8U;
+}
+static inline u32 ccsr_channel__size_1_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ccsr_channel_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ccsr_channel_enable_set_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 ccsr_channel_enable_set_true_f(void)
+{
+        return 0x400U;
+}
+static inline u32 ccsr_channel_enable_clr_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ccsr_channel_status_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
+{
+        return 0x100U;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h
new file mode 100644
index 00000000..fb741a77
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce2_gm20b_h_
+#define _hw_ce2_gm20b_h_
+
+static inline u32 ce2_intr_status_r(void)
+{
+        return 0x00106908U;
+}
+static inline u32 ce2_intr_status_blockpipe_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce2_intr_status_blockpipe_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce2_intr_status_launcherr_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ce2_intr_status_launcherr_reset_f(void)
+{
+        return 0x4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
new file mode 100644
index 00000000..b60dfc36
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ctxsw_prog_gm20b_h_
+#define _hw_ctxsw_prog_gm20b_h_
+
+static inline u32 ctxsw_prog_fecs_header_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void)
+{
+        return 0x400U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_patch_count_o(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ctxsw_prog_main_image_context_id_o(void)
+{
+        return 0x000000f0U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
+{
+        return 0x00000014U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
+{
+        return 0x00000018U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_o(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_main_image_pm_o(void)
+{
+        return 0x00000028U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
+{
+        return 0x7U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_pc_sampling_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 ctxsw_prog_main_image_pm_pc_sampling_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
+{
+        return 0x0000002cU;
+}
+static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
+{
+        return 0x600dc0deU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_local_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
+{
+        return 0xad0becabU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+        return 2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
+{
+        return 0x000000acU;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
+{
+        return 0x000000b0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
+{
+        return 0x000000b4U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
+{
+        return 0x600dbeefU;
+}
+static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void)
+{
+        return 0x00000014U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
+{
+        return 0x00000018U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
+{
+        return 0xffU << 24U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
+{
+        return (r >> 24U) & 0xffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
+{
+        return 0xa000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
+{
+        return 0xb000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
+{
+        return 0xc000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
+{
+        return 0xd000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
+{
+        return 0x5000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
+{
+        return 0xff000000U;
+}
+static inline u32 ctxsw_prog_main_image_preemption_options_o(void)
+{
+        return 0x00000060U;
+}
+static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void)
+{
+        return 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h
new file mode 100644
index 00000000..a17c9a9a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h
@@ -0,0 +1,595 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_falcon_gm20b_h_
+#define _hw_falcon_gm20b_h_
+
+static inline u32 falcon_falcon_irqsset_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqsclr_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 falcon_falcon_irqstat_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 falcon_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqmode_r(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 falcon_falcon_irqmset_r(void)
+{
+        return 0x00000010U;
+}
+static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_r(void)
+{
+        return 0x00000014U;
+}
+static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqmask_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 falcon_falcon_irqdest_r(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 falcon_falcon_curctx_r(void)
+{
+        return 0x00000050U;
+}
+static inline u32 falcon_falcon_nxtctx_r(void)
+{
+        return 0x00000054U;
+}
+static inline u32 falcon_falcon_mailbox0_r(void)
+{
+        return 0x00000040U;
+}
+static inline u32 falcon_falcon_mailbox1_r(void)
+{
+        return 0x00000044U;
+}
+static inline u32 falcon_falcon_itfen_r(void)
+{
+        return 0x00000048U;
+}
+static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_r(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 falcon_falcon_os_r(void)
+{
+        return 0x00000080U;
+}
+static inline u32 falcon_falcon_engctl_r(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 falcon_falcon_cpuctl_r(void)
+{
+        return 0x00000100U;
+}
+static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_stopped_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_alias_r(void)
+{
+        return 0x00000130U;
+}
+static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_imemc_r(u32 i)
+{
+        return 0x00000180U + i*16U;
+}
+static inline u32 falcon_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_imemd_r(u32 i)
+{
+        return 0x00000184U + i*16U;
+}
+static inline u32 falcon_falcon_imemt_r(u32 i)
+{
+        return 0x00000188U + i*16U;
+}
+static inline u32 falcon_falcon_sctl_r(void)
+{
+        return 0x00000240U;
+}
+static inline u32 falcon_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 falcon_falcon_bootvec_r(void)
+{
+        return 0x00000104U;
+}
+static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 falcon_falcon_dmactl_r(void)
+{
+        return 0x0000010cU;
+}
+static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_hwcfg_r(void)
+{
+        return 0x00000108U;
+}
+static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_dmatrfbase_r(void)
+{
+        return 0x00000110U;
+}
+static inline u32 falcon_falcon_dmatrfmoffs_r(void)
+{
+        return 0x00000114U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_r(void)
+{
+        return 0x00000118U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 falcon_falcon_dmatrffboffs_r(void)
+{
+        return 0x0000011cU;
+}
+static inline u32 falcon_falcon_imctl_debug_r(void)
+{
+        return 0x0000015cU;
+}
+static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 falcon_falcon_imstat_r(void)
+{
+        return 0x00000144U;
+}
+static inline u32 falcon_falcon_traceidx_r(void)
+{
+        return 0x00000148U;
+}
+static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 falcon_falcon_traceidx_idx_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 falcon_falcon_tracepc_r(void)
+{
+        return 0x0000014cU;
+}
+static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 falcon_falcon_exterraddr_r(void)
+{
+        return 0x00000168U;
+}
+static inline u32 falcon_falcon_exterrstat_r(void)
+{
+        return 0x0000016cU;
+}
+static inline u32 falcon_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 falcon_falcon_icd_cmd_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 falcon_falcon_icd_rdata_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 falcon_falcon_dmemc_r(u32 i)
+{
+        return 0x000001c0U + i*8U;
+}
+static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 falcon_falcon_dmemd_r(u32 i)
+{
+        return 0x000001c4U + i*8U;
+}
+static inline u32 falcon_falcon_debug1_r(void)
+{
+        return 0x00000090U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
+{
+        return 1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 falcon_falcon_debuginfo_r(void)
+{
+        return 0x00000094U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
new file mode 100644
index 00000000..531d0400
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fb_gm20b_h_
+#define _hw_fb_gm20b_h_
+
+static inline u32 fb_fbhub_num_active_ltcs_r(void)
+{
+        return 0x00100800U;
+}
+static inline u32 fb_mmu_ctrl_r(void)
+{
+        return 0x00100c80U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
+{
+        return (r >> 11U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_true_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 fb_priv_mmu_phy_secure_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 fb_mmu_invalidate_pdb_r(void)
+{
+        return 0x00100cb8U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_invalidate_r(void)
+{
+        return 0x00100cbcU;
+}
+static inline u32 fb_mmu_invalidate_all_va_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_trigger_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_debug_wr_r(void)
+{
+        return 0x00100cc8U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_s(void)
+{
+        return 2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_rd_r(void)
+{
+        return 0x00100cccU;
+}
+static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_rd_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_ctrl_r(void)
+{
+        return 0x00100cc4U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_vpr_info_r(void)
+{
+        return 0x00100cd0U;
+}
+static inline u32 fb_mmu_vpr_info_index_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fb_mmu_vpr_info_index_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_wpr_info_r(void)
+{
+        return 0x00100cd4U;
+}
+static inline u32 fb_mmu_wpr_info_index_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 fb_mmu_wpr_info_index_allow_read_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_wpr_info_index_allow_write_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+        return 0x00100c10U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
new file mode 100644
index 00000000..d32506dd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fifo_gm20b_h_
+#define _hw_fifo_gm20b_h_
+
+static inline u32 fifo_bar1_base_r(void)
+{
+        return 0x00002254U;
+}
+static inline u32 fifo_bar1_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_bar1_base_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_bar1_base_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_runlist_base_r(void)
+{
+        return 0x00002270U;
+}
+static inline u32 fifo_runlist_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_runlist_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 fifo_runlist_r(void)
+{
+        return 0x00002274U;
+}
+static inline u32 fifo_runlist_engine_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 fifo_eng_runlist_base_r(u32 i)
+{
+        return 0x00002280U + i*8U;
+}
+static inline u32 fifo_eng_runlist_base__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_eng_runlist_r(u32 i)
+{
+        return 0x00002284U + i*8U;
+}
+static inline u32 fifo_eng_runlist__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_eng_runlist_length_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 fifo_eng_runlist_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_pb_timeslice_r(u32 i)
+{
+        return 0x00002350U + i*4U;
+}
+static inline u32 fifo_pb_timeslice_timeout_16_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fifo_pb_timeslice_timescale_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_pb_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_pbdma_map_r(u32 i)
+{
+        return 0x00002390U + i*4U;
+}
+static inline u32 fifo_intr_0_r(void)
+{
+        return 0x00002100U;
+}
+static inline u32 fifo_intr_0_bind_error_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_bind_error_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_sched_error_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_sched_error_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_chsw_error_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_chsw_error_reset_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_lb_error_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_lb_error_reset_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_intr_0_runlist_event_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fifo_intr_0_channel_intr_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fifo_intr_en_0_r(void)
+{
+        return 0x00002140U;
+}
+static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 fifo_intr_en_1_r(void)
+{
+        return 0x00002528U;
+}
+static inline u32 fifo_intr_bind_error_r(void)
+{
+        return 0x0000252cU;
+}
+static inline u32 fifo_intr_sched_error_r(void)
+{
+        return 0x0000254cU;
+}
+static inline u32 fifo_intr_sched_error_code_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 fifo_intr_chsw_error_r(void)
+{
+        return 0x0000256cU;
+}
+static inline u32 fifo_intr_mmu_fault_id_r(void)
+{
+        return 0x0000259cU;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
+{
+        return 0x00002800U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
+{
+        return 0x00002804U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
+{
+        return 0x00002808U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
+{
+        return 0x0000280cU + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
+{
+        return (r >> 8U) & 0x3fU;
+}
+static inline u32 fifo_intr_pbdma_id_r(void)
+{
+        return 0x000025a0U;
+}
+static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_intr_runlist_r(void)
+{
+        return 0x00002a00U;
+}
+static inline u32 fifo_fb_timeout_r(void)
+{
+        return 0x00002a04U;
+}
+static inline u32 fifo_fb_timeout_period_m(void)
+{
+        return 0x3fffffffU << 0U;
+}
+static inline u32 fifo_fb_timeout_period_max_f(void)
+{
+        return 0x3fffffffU;
+}
+static inline u32 fifo_error_sched_disable_r(void)
+{
+        return 0x0000262cU;
+}
+static inline u32 fifo_sched_disable_r(void)
+{
+        return 0x00002630U;
+}
+static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_runlist_m(u32 i)
+{
+        return 0x1U << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_preempt_r(void)
+{
+        return 0x00002634U;
+}
+static inline u32 fifo_preempt_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_preempt_type_channel_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_preempt_type_tsg_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_preempt_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_preempt_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_trigger_mmu_fault_r(u32 i)
+{
+        return 0x00002a30U + i*4U;
+}
+static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_engine_status_r(u32 i)
+{
+        return 0x00002640U + i*8U;
+}
+static inline u32 fifo_engine_status__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fifo_engine_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_engine_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_ctx_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_engine_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_engine_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_faulted_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fifo_engine_status_faulted_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_engine_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fifo_engine_status_engine_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_engine_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 fifo_pbdma_status_r(u32 i)
+{
+        return 0x00003080U + i*4U;
+}
+static inline u32 fifo_pbdma_status__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_pbdma_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_chsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h
new file mode 100644
index 00000000..3b5801b6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_flush_gm20b_h_
+#define _hw_flush_gm20b_h_
+
+static inline u32 flush_l2_system_invalidate_r(void)
+{
+        return 0x00070004U;
+}
+static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_r(void)
+{
+        return 0x00070010U;
+}
+static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_r(void)
+{
+        return 0x0007000cU;
+}
+static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_r(void)
+{
+        return 0x00070000U;
+}
+static inline u32 flush_fb_flush_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_fb_flush_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
new file mode 100644
index 00000000..99b4b3f3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fuse_gm20b_h_
+#define _hw_fuse_gm20b_h_
+
+static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021c38U + i*4U;
+}
+static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021838U + i*4U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
+{
+        return 0x00021944U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
+{
+        return 0x00021948U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fuse_status_opt_fbio_r(void)
+{
+        return 0x00021c14U;
+}
+static inline u32 fuse_status_opt_fbio_data_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fuse_status_opt_fbio_data_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 fuse_status_opt_fbio_data_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
+{
+        return 0x00021d70U + i*4U;
+}
+static inline u32 fuse_status_opt_fbp_r(void)
+{
+        return 0x00021d38U;
+}
+static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fuse_opt_sec_debug_en_r(void)
+{
+        return 0x00021218U;
+}
+static inline u32 fuse_opt_priv_sec_en_r(void)
+{
+        return 0x00021434U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
new file mode 100644
index 00000000..e11ac246
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
@@ -0,0 +1,1207 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gmmu_gm20b_h_
+#define _hw_gmmu_gm20b_h_
+
+static inline u32 gmmu_pde_aperture_big_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pde_aperture_big_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_aperture_big_video_memory_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gmmu_pde_size_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pde_size_full_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_address_big_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_pde_address_big_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pde_aperture_small_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pde_aperture_small_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_aperture_small_video_memory_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gmmu_pde_vol_small_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pde_vol_small_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_pde_vol_small_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_vol_big_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pde_vol_big_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_pde_vol_big_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pde_address_small_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_pde_address_small_sys_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pde_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pde__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_pte__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_pte_valid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_valid_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_pte_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pte_privilege_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_privilege_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_pte_privilege_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pte_address_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_pte_address_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_address_vid_f(u32 v)
+{
+        return (v & 0x1ffffffU) << 4U;
+}
+static inline u32 gmmu_pte_address_vid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_vol_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_vol_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_pte_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pte_aperture_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_aperture_video_memory_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_pte_read_only_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_pte_read_only_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_pte_write_disable_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_write_disable_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gmmu_pte_read_disable_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_read_disable_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gmmu_pte_comptagline_s(void)
+{
+        return 17U;
+}
+static inline u32 gmmu_pte_comptagline_f(u32 v)
+{
+        return (v & 0x1ffffU) << 12U;
+}
+static inline u32 gmmu_pte_comptagline_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_f(u32 v)
+{
+        return (v & 0xffU) << 4U;
+}
+static inline u32 gmmu_pte_kind_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_kind_invalid_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 gmmu_pte_kind_pitch_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gmmu_pte_kind_z16_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gmmu_pte_kind_z16_2c_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 gmmu_pte_kind_z16_2z_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 gmmu_pte_kind_z16_4cz_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gmmu_pte_kind_s8z24_v(void)
+{
+        return 0x00000011U;
+}
+static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
+{
+        return 0x00000012U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
+{
+        return 0x00000013U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
+{
+        return 0x00000014U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
+{
+        return 0x00000017U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
+{
+        return 0x00000019U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
+{
+        return 0x0000001aU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
+{
+        return 0x0000001bU;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
+{
+        return 0x0000001dU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
+{
+        return 0x0000001eU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
+{
+        return 0x0000001fU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
+{
+        return 0x00000021U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
+{
+        return 0x00000022U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
+{
+        return 0x00000023U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
+{
+        return 0x00000024U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
+{
+        return 0x00000026U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
+{
+        return 0x00000027U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
+{
+        return 0x00000029U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
+{
+        return 0x0000002eU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
+{
+        return 0x0000002fU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
+{
+        return 0x00000033U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
+{
+        return 0x00000034U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
+{
+        return 0x00000035U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
+{
+        return 0x0000003aU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
+{
+        return 0x0000003bU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
+{
+        return 0x0000003dU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
+{
+        return 0x0000003eU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
+{
+        return 0x0000003fU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
+{
+        return 0x00000041U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000042U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000043U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000044U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
+{
+        return 0x00000045U;
+}
+static inline u32 gmmu_pte_kind_z24s8_v(void)
+{
+        return 0x00000046U;
+}
+static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
+{
+        return 0x00000047U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
+{
+        return 0x00000048U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
+{
+        return 0x00000049U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
+{
+        return 0x0000004aU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
+{
+        return 0x0000004bU;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
+{
+        return 0x0000004dU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
+{
+        return 0x0000004eU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
+{
+        return 0x0000004fU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
+{
+        return 0x00000050U;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
+{
+        return 0x00000051U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
+{
+        return 0x00000052U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
+{
+        return 0x00000053U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
+{
+        return 0x00000054U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
+{
+        return 0x00000055U;
+}
+static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
+{
+        return 0x00000056U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
+{
+        return 0x00000057U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
+{
+        return 0x00000058U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
+{
+        return 0x00000059U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
+{
+        return 0x0000005aU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
+{
+        return 0x0000005bU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
+{
+        return 0x0000005cU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
+{
+        return 0x0000005dU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
+{
+        return 0x0000005eU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000063U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000064U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000065U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
+{
+        return 0x00000066U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
+{
+        return 0x00000067U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
+{
+        return 0x00000068U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
+{
+        return 0x00000069U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
+{
+        return 0x0000006aU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
+{
+        return 0x0000006fU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
+{
+        return 0x00000070U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
+{
+        return 0x00000071U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
+{
+        return 0x00000072U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
+{
+        return 0x00000073U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
+{
+        return 0x00000074U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
+{
+        return 0x00000075U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
+{
+        return 0x00000076U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000077U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000078U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000079U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
+{
+        return 0x0000007aU;
+}
+static inline u32 gmmu_pte_kind_zf32_v(void)
+{
+        return 0x0000007bU;
+}
+static inline u32 gmmu_pte_kind_zf32_1z_v(void)
+{
+        return 0x0000007cU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
+{
+        return 0x0000007dU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
+{
+        return 0x0000007eU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
+{
+        return 0x0000007fU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
+{
+        return 0x00000081U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
+{
+        return 0x00000082U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
+{
+        return 0x00000083U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
+{
+        return 0x00000084U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
+{
+        return 0x00000085U;
+}
+static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
+{
+        return 0x00000086U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
+{
+        return 0x00000087U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
+{
+        return 0x00000088U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
+{
+        return 0x00000089U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
+{
+        return 0x0000008aU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x0000008bU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x0000008cU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x0000008dU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x0000008eU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x0000008fU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x00000090U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x00000091U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x00000092U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000097U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000098U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000099U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x0000009aU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x0000009bU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x0000009cU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x0000009dU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x0000009eU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x0000009fU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000a1U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000a2U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000a3U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000a5U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000a6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x000000a7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x000000a9U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x000000aaU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x000000abU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x000000acU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x000000adU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x000000aeU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x000000b3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x000000b4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x000000b5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x000000b6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x000000b7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x000000b8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x000000b9U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x000000baU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x000000bbU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000bcU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000bdU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000beU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000bfU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000c1U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000c2U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
+{
+        return 0x000000c3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
+{
+        return 0x000000c4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
+{
+        return 0x000000c5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
+{
+        return 0x000000c6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
+{
+        return 0x000000c7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
+{
+        return 0x000000c8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
+{
+        return 0x000000ceU;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
+{
+        return 0x000000cfU;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
+{
+        return 0x000000d0U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
+{
+        return 0x000000d1U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
+{
+        return 0x000000d2U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
+{
+        return 0x000000d3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
+{
+        return 0x000000d4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
+{
+        return 0x000000d5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
+{
+        return 0x000000d6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
+{
+        return 0x000000d7U;
+}
+static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
+{
+        return 0x000000feU;
+}
+static inline u32 gmmu_pte_kind_c32_2c_v(void)
+{
+        return 0x000000d8U;
+}
+static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
+{
+        return 0x000000d9U;
+}
+static inline u32 gmmu_pte_kind_c32_2cba_v(void)
+{
+        return 0x000000daU;
+}
+static inline u32 gmmu_pte_kind_c32_2cra_v(void)
+{
+        return 0x000000dbU;
+}
+static inline u32 gmmu_pte_kind_c32_2bra_v(void)
+{
+        return 0x000000dcU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
+{
+        return 0x000000ddU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
+{
+        return 0x000000deU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
+{
+        return 0x000000ccU;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
+{
+        return 0x000000dfU;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
+{
+        return 0x000000e0U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
+{
+        return 0x000000e1U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
+{
+        return 0x000000e2U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
+{
+        return 0x000000e3U;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
+{
+        return 0x000000e4U;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
+{
+        return 0x000000e5U;
+}
+static inline u32 gmmu_pte_kind_c64_2c_v(void)
+{
+        return 0x000000e6U;
+}
+static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
+{
+        return 0x000000e7U;
+}
+static inline u32 gmmu_pte_kind_c64_2cba_v(void)
+{
+        return 0x000000e8U;
+}
+static inline u32 gmmu_pte_kind_c64_2cra_v(void)
+{
+        return 0x000000e9U;
+}
+static inline u32 gmmu_pte_kind_c64_2bra_v(void)
+{
+        return 0x000000eaU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
+{
+        return 0x000000ebU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
+{
+        return 0x000000cdU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
+{
+        return 0x000000edU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
+{
+        return 0x000000eeU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
+{
+        return 0x000000efU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
+{
+        return 0x000000f0U;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
+{
+        return 0x000000f1U;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
+{
+        return 0x000000f2U;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
+{
+        return 0x000000f3U;
+}
+static inline u32 gmmu_pte_kind_c128_2c_v(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 gmmu_pte_kind_c128_2cr_v(void)
+{
+        return 0x000000f5U;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
+{
+        return 0x000000f6U;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
+{
+        return 0x000000f7U;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
+{
+        return 0x000000f9U;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
+{
+        return 0x000000faU;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
+{
+        return 0x000000fbU;
+}
+static inline u32 gmmu_pte_kind_x8c24_v(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
+{
+        return 0x000000fdU;
+}
+static inline u32 gmmu_pte_kind_smsked_message_v(void)
+{
+        return 0x000000caU;
+}
+static inline u32 gmmu_pte_kind_smhost_message_v(void)
+{
+        return 0x000000cbU;
+}
+static inline u32 gmmu_pte_kind_s8_v(void)
+{
+        return 0x0000002aU;
+}
+static inline u32 gmmu_pte_kind_s8_2s_v(void)
+{
+        return 0x0000002bU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
new file mode 100644
index 00000000..d9776b7c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -0,0 +1,3891 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gr_gm20b_h_
+#define _hw_gr_gm20b_h_
+
+static inline u32 gr_intr_r(void)
+{
+        return 0x00400100U;
+}
+static inline u32 gr_intr_notify_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_notify_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_semaphore_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_semaphore_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_illegal_method_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_method_reset_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_notify_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_illegal_notify_reset_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 gr_intr_firmware_method_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_firmware_method_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_illegal_class_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_illegal_class_reset_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_fecs_error_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_fecs_error_reset_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_class_error_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_class_error_reset_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_exception_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_intr_exception_reset_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_fecs_intr_r(void)
+{
+        return 0x00400144U;
+}
+static inline u32 gr_class_error_r(void)
+{
+        return 0x00400110U;
+}
+static inline u32 gr_class_error_code_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_intr_nonstall_r(void)
+{
+        return 0x00400120U;
+}
+static inline u32 gr_intr_nonstall_trap_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_en_r(void)
+{
+        return 0x0040013cU;
+}
+static inline u32 gr_exception_r(void)
+{
+        return 0x00400108U;
+}
+static inline u32 gr_exception_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception_gpc_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 gr_exception_memfmt_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_exception_ds_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_exception_sked_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 gr_exception1_r(void)
+{
+        return 0x00400118U;
+}
+static inline u32 gr_exception1_gpc_0_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_exception2_r(void)
+{
+        return 0x0040011cU;
+}
+static inline u32 gr_exception_en_r(void)
+{
+        return 0x00400138U;
+}
+static inline u32 gr_exception_en_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception1_en_r(void)
+{
+        return 0x00400130U;
+}
+static inline u32 gr_exception2_en_r(void)
+{
+        return 0x00400134U;
+}
+static inline u32 gr_gpfifo_ctl_r(void)
+{
+        return 0x00400500U;
+}
+static inline u32 gr_gpfifo_ctl_access_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpfifo_status_r(void)
+{
+        return 0x00400504U;
+}
+static inline u32 gr_trapped_addr_r(void)
+{
+        return 0x00400704U;
+}
+static inline u32 gr_trapped_addr_mthd_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 gr_trapped_addr_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_datahigh_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_priv_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_status_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_trapped_data_lo_r(void)
+{
+        return 0x00400708U;
+}
+static inline u32 gr_trapped_data_hi_r(void)
+{
+        return 0x0040070cU;
+}
+static inline u32 gr_trapped_data_mme_r(void)
+{
+        return 0x00400710U;
+}
+static inline u32 gr_trapped_data_mme_pc_v(u32 r)
+{
+        return (r >> 0U) & 0x7ffU;
+}
+static inline u32 gr_status_r(void)
+{
+        return 0x00400700U;
+}
+static inline u32 gr_status_fe_method_upper_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_status_fe_gi_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 gr_status_mask_r(void)
+{
+        return 0x00400610U;
+}
+static inline u32 gr_status_1_r(void)
+{
+        return 0x00400604U;
+}
+static inline u32 gr_status_2_r(void)
+{
+        return 0x00400608U;
+}
+static inline u32 gr_engine_status_r(void)
+{
+        return 0x0040060cU;
+}
+static inline u32 gr_engine_status_value_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+        return 0x00410204U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+        return 0x00410208U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+        return 0x00502c94U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_activity_0_r(void)
+{
+        return 0x00400380U;
+}
+static inline u32 gr_activity_1_r(void)
+{
+        return 0x00400384U;
+}
+static inline u32 gr_activity_2_r(void)
+{
+        return 0x00400388U;
+}
+static inline u32 gr_activity_4_r(void)
+{
+        return 0x00400390U;
+}
+static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
+{
+        return 0x00501000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
+{
+        return 0x00419000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
+{
+        return 0x005046a4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
+{
+        return 0x00419ea4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_pri_sked_activity_r(void)
+{
+        return 0x00407054U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
+{
+        return 0x00502c80U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
+{
+        return 0x00502c84U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
+{
+        return 0x00502c88U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
+{
+        return 0x00502c8cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504500U;
+}
+static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504d00U;
+}
+static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00501d00U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
+{
+        return 0x0041ac80U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
+{
+        return 0x0041ac84U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
+{
+        return 0x0041ac88U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
+{
+        return 0x0041ac8cU;
+}
+static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041c500U;
+}
+static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041cd00U;
+}
+static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00419d00U;
+}
+static inline u32 gr_pri_be0_becs_be_activity0_r(void)
+{
+        return 0x00410200U;
+}
+static inline u32 gr_pri_be1_becs_be_activity0_r(void)
+{
+        return 0x00410600U;
+}
+static inline u32 gr_pri_bes_becs_be_activity0_r(void)
+{
+        return 0x00408a00U;
+}
+static inline u32 gr_pri_ds_mpipe_status_r(void)
+{
+        return 0x00405858U;
+}
+static inline u32 gr_pri_fe_go_idle_on_status_r(void)
+{
+        return 0x00404150U;
+}
+static inline u32 gr_pri_fe_go_idle_check_r(void)
+{
+        return 0x00404158U;
+}
+static inline u32 gr_pri_fe_go_idle_info_r(void)
+{
+        return 0x00404194U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
+{
+        return 0x00504238U;
+}
+static inline u32 gr_pri_be0_crop_status1_r(void)
+{
+        return 0x00410134U;
+}
+static inline u32 gr_pri_bes_crop_status1_r(void)
+{
+        return 0x00408934U;
+}
+static inline u32 gr_pri_be0_zrop_status_r(void)
+{
+        return 0x00410048U;
+}
+static inline u32 gr_pri_be0_zrop_status2_r(void)
+{
+        return 0x0041004cU;
+}
+static inline u32 gr_pri_bes_zrop_status_r(void)
+{
+        return 0x00408848U;
+}
+static inline u32 gr_pri_bes_zrop_status2_r(void)
+{
+        return 0x0040884cU;
+}
+static inline u32 gr_pipe_bundle_address_r(void)
+{
+        return 0x00400200U;
+}
+static inline u32 gr_pipe_bundle_address_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pipe_bundle_data_r(void)
+{
+        return 0x00400204U;
+}
+static inline u32 gr_pipe_bundle_config_r(void)
+{
+        return 0x00400208U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_hww_esr_r(void)
+{
+        return 0x00404000U;
+}
+static inline u32 gr_fe_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_fe_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_go_idle_timeout_r(void)
+{
+        return 0x00404154U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_fe_object_table_r(u32 i)
+{
+        return 0x00404200U + i*4U;
+}
+static inline u32 gr_fe_object_table_nvclass_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_fe_tpc_fs_r(void)
+{
+        return 0x004041c4U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_r(void)
+{
+        return 0x00404488U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pri_mme_shadow_raw_data_r(void)
+{
+        return 0x0040448cU;
+}
+static inline u32 gr_mme_hww_esr_r(void)
+{
+        return 0x00404490U;
+}
+static inline u32 gr_mme_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_mme_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_memfmt_hww_esr_r(void)
+{
+        return 0x00404600U;
+}
+static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fecs_cpuctl_r(void)
+{
+        return 0x00409100U;
+}
+static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_cpuctl_alias_r(void)
+{
+        return 0x00409130U;
+}
+static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_dmactl_r(void)
+{
+        return 0x0040910cU;
+}
+static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_fecs_os_r(void)
+{
+        return 0x00409080U;
+}
+static inline u32 gr_fecs_idlestate_r(void)
+{
+        return 0x0040904cU;
+}
+static inline u32 gr_fecs_mailbox0_r(void)
+{
+        return 0x00409040U;
+}
+static inline u32 gr_fecs_mailbox1_r(void)
+{
+        return 0x00409044U;
+}
+static inline u32 gr_fecs_irqstat_r(void)
+{
+        return 0x00409008U;
+}
+static inline u32 gr_fecs_irqmode_r(void)
+{
+        return 0x0040900cU;
+}
+static inline u32 gr_fecs_irqmask_r(void)
+{
+        return 0x00409018U;
+}
+static inline u32 gr_fecs_irqdest_r(void)
+{
+        return 0x0040901cU;
+}
+static inline u32 gr_fecs_curctx_r(void)
+{
+        return 0x00409050U;
+}
+static inline u32 gr_fecs_nxtctx_r(void)
+{
+        return 0x00409054U;
+}
+static inline u32 gr_fecs_engctl_r(void)
+{
+        return 0x004090a4U;
+}
+static inline u32 gr_fecs_debug1_r(void)
+{
+        return 0x00409090U;
+}
+static inline u32 gr_fecs_debuginfo_r(void)
+{
+        return 0x00409094U;
+}
+static inline u32 gr_fecs_icd_cmd_r(void)
+{
+        return 0x00409200U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 gr_fecs_icd_rdata_r(void)
+{
+        return 0x0040920cU;
+}
+static inline u32 gr_fecs_imemc_r(u32 i)
+{
+        return 0x00409180U + i*16U;
+}
+static inline u32 gr_fecs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_imemd_r(u32 i)
+{
+        return 0x00409184U + i*16U;
+}
+static inline u32 gr_fecs_imemt_r(u32 i)
+{
+        return 0x00409188U + i*16U;
+}
+static inline u32 gr_fecs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_dmemc_r(u32 i)
+{
+        return 0x004091c0U + i*8U;
+}
+static inline u32 gr_fecs_dmemc_offs_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_v(u32 r)
+{
+        return (r >> 2U) & 0x3fU;
+}
+static inline u32 gr_fecs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_dmemd_r(u32 i)
+{
+        return 0x004091c4U + i*8U;
+}
+static inline u32 gr_fecs_dmatrfbase_r(void)
+{
+        return 0x00409110U;
+}
+static inline u32 gr_fecs_dmatrfmoffs_r(void)
+{
+        return 0x00409114U;
+}
+static inline u32 gr_fecs_dmatrffboffs_r(void)
+{
+        return 0x0040911cU;
+}
+static inline u32 gr_fecs_dmatrfcmd_r(void)
+{
+        return 0x00409118U;
+}
+static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_fecs_bootvec_r(void)
+{
+        return 0x00409104U;
+}
+static inline u32 gr_fecs_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_falcon_hwcfg_r(void)
+{
+        return 0x00409108U;
+}
+static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
+{
+        return 0x0041a108U;
+}
+static inline u32 gr_fecs_falcon_rm_r(void)
+{
+        return 0x00409084U;
+}
+static inline u32 gr_fecs_current_ctx_r(void)
+{
+        return 0x00409b00U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_current_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_current_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_current_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_method_data_r(void)
+{
+        return 0x00409500U;
+}
+static inline u32 gr_fecs_method_push_r(void)
+{
+        return 0x00409504U;
+}
+static inline u32 gr_fecs_method_push_adr_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
+{
+        return 0x00000038U;
+}
+static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
+{
+        return 0x00000039U;
+}
+static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
+{
+        return 0x21U;
+}
+static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void)
+{
+        return 0x0000003dU;
+}
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_fecs_host_int_status_r(void)
+{
+        return 0x00409c18U;
+}
+static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_host_int_clear_r(void)
+{
+        return 0x00409c20U;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fecs_host_int_enable_r(void)
+{
+        return 0x00409c24U;
+}
+static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
+{
+        return 0x00409614U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
+{
+        return (r >> 10U) & 0x1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
+{
+        return 0x0040960cU;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x00409800U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
+{
+        return 0x004098c0U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
+{
+        return 0x00409840U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_fs_r(void)
+{
+        return 0x00409604U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_m(void)
+{
+        return 0x1fU << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_fecs_cfg_r(void)
+{
+        return 0x00409620U;
+}
+static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_fecs_rc_lanes_r(void)
+{
+        return 0x00409880U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_fecs_ctxsw_status_1_r(void)
+{
+        return 0x00409400U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_adr_r(void)
+{
+        return 0x00409a24U;
+}
+static inline u32 gr_fecs_new_ctx_r(void)
+{
+        return 0x00409b04U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_new_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_new_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_new_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_r(void)
+{
+        return 0x00409a0cU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_r(void)
+{
+        return 0x00409a10U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
+{
+        return 0x00409c00U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
+{
+        return 0x00502c04U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
+{
+        return 0x00502400U;
+}
+static inline u32 gr_fecs_ctxsw_idlestate_r(void)
+{
+        return 0x00409420U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
+{
+        return 0x00502420U;
+}
+static inline u32 gr_rstr2d_gpc_map0_r(void)
+{
+        return 0x0040780cU;
+}
+static inline u32 gr_rstr2d_gpc_map1_r(void)
+{
+        return 0x00407810U;
+}
+static inline u32 gr_rstr2d_gpc_map2_r(void)
+{
+        return 0x00407814U;
+}
+static inline u32 gr_rstr2d_gpc_map3_r(void)
+{
+        return 0x00407818U;
+}
+static inline u32 gr_rstr2d_gpc_map4_r(void)
+{
+        return 0x0040781cU;
+}
+static inline u32 gr_rstr2d_gpc_map5_r(void)
+{
+        return 0x00407820U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_r(void)
+{
+        return 0x004078bcU;
+}
+static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_hww_esr_r(void)
+{
+        return 0x00406018U;
+}
+static inline u32 gr_pd_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_pd_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00406028U + i*4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
+{
+        return (v & 0xfU) << 12U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
+{
+        return (v & 0xfU) << 24U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
+{
+        return (v & 0xfU) << 28U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_r(void)
+{
+        return 0x004064c0U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_r(void)
+{
+        return 0x004064c4U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
+{
+        return 0xffffU;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_r(void)
+{
+        return 0x004064c8U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
+{
+        return 0x000001c0U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
+{
+        return (v & 0xfffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
+{
+        return 0x00000182U;
+}
+static inline u32 gr_pd_pagepool_r(void)
+{
+        return 0x004064ccU;
+}
+static inline u32 gr_pd_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_pagepool_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_dist_skip_table_r(u32 i)
+{
+        return 0x004064d0U + i*4U;
+}
+static inline u32 gr_pd_dist_skip_table__size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gr_ds_debug_r(void)
+{
+        return 0x00405800U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 gr_ds_zbc_color_r_r(void)
+{
+        return 0x00405804U;
+}
+static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_g_r(void)
+{
+        return 0x00405808U;
+}
+static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_b_r(void)
+{
+        return 0x0040580cU;
+}
+static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_a_r(void)
+{
+        return 0x00405810U;
+}
+static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_r(void)
+{
+        return 0x00405814U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
+{
+        return (v & 0x7fU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gr_ds_zbc_z_r(void)
+{
+        return 0x00405818U;
+}
+static inline u32 gr_ds_zbc_z_val_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_ds_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_ds_zbc_z_val__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_ds_zbc_z_val__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_r(void)
+{
+        return 0x0040581cU;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_tbl_index_r(void)
+{
+        return 0x00405820U;
+}
+static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_r(void)
+{
+        return 0x00405824U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_tga_constraintlogic_r(void)
+{
+        return 0x00405830U;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_ds_hww_esr_r(void)
+{
+        return 0x00405840U;
+}
+static inline u32 gr_ds_hww_esr_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_esr_2_r(void)
+{
+        return 0x00405848U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_report_mask_r(void)
+{
+        return 0x00405844U;
+}
+static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_ds_hww_report_mask_2_r(void)
+{
+        return 0x0040584cU;
+}
+static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00405870U + i*4U;
+}
+static inline u32 gr_scc_bundle_cb_base_r(void)
+{
+        return 0x00408004U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_bundle_cb_size_r(void)
+{
+        return 0x00408008U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_pagepool_base_r(void)
+{
+        return 0x0040800cU;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_pagepool_r(void)
+{
+        return 0x00408010U;
+}
+static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
+{
+        return 8U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 gr_scc_pagepool_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_init_r(void)
+{
+        return 0x0040802cU;
+}
+static inline u32 gr_scc_init_ram_trigger_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_scc_hww_esr_r(void)
+{
+        return 0x00408030U;
+}
+static inline u32 gr_scc_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_scc_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_sked_hww_esr_r(void)
+{
+        return 0x00407020U;
+}
+static inline u32 gr_sked_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_cwd_fs_r(void)
+{
+        return 0x00405b00U;
+}
+static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
+{
+        return 0x00405b60U + i*4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_cwd_sm_id_r(u32 i)
+{
+        return 0x00405ba0U + i*4U;
+}
+static inline u32 gr_cwd_sm_id__size_1_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpc0_fs_gpc_r(void)
+{
+        return 0x00502608U;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_gpc0_cfg_r(void)
+{
+        return 0x00502620U;
+}
+static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpccs_rc_lanes_r(void)
+{
+        return 0x00502880U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_rc_lane_size_r(u32 i)
+{
+        return 0x00502910U + i*0U;
+}
+static inline u32 gr_gpccs_rc_lane_size__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_s(void)
+{
+        return 24U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_zcull_fs_r(void)
+{
+        return 0x00500910U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_r(void)
+{
+        return 0x00500914U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
+{
+        return 0x00500918U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
+{
+        return 0x00800000U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
+{
+        return 0x00500920U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
+{
+        return 0x00500a04U + i*32U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
+{
+        return 0x00500c10U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
+{
+        return 0x00500c30U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
+{
+        return 0x00504088U;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
+{
+        return 0x00504698U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
+{
+        return 0x0050469cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
+{
+        return (r >> 8U) & 0xfffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
+{
+        return (r >> 20U) & 0xfffU;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
+{
+        return 0x00503018U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
+{
+        return 0x005030c0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
+{
+        return 0x00000400U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
+{
+        return 0x005030f4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
+{
+        return 0x005030e4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
+{
+        return 0x005030f8U;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void)
+{
+        return 0x00419a3cU;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpccs_falcon_addr_r(void)
+{
+        return 0x0041a0acU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
+{
+        return (r >> 6U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_s(void)
+{
+        return 12U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_m(void)
+{
+        return 0xfffU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_gpccs_cpuctl_r(void)
+{
+        return 0x0041a100U;
+}
+static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_gpccs_dmactl_r(void)
+{
+        return 0x0041a10cU;
+}
+static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpccs_imemc_r(u32 i)
+{
+        return 0x0041a180U + i*16U;
+}
+static inline u32 gr_gpccs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_imemd_r(u32 i)
+{
+        return 0x0041a184U + i*16U;
+}
+static inline u32 gr_gpccs_imemt_r(u32 i)
+{
+        return 0x0041a188U + i*16U;
+}
+static inline u32 gr_gpccs_imemt__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_gpccs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpccs_dmemc_r(u32 i)
+{
+        return 0x0041a1c0U + i*8U;
+}
+static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_dmemd_r(u32 i)
+{
+        return 0x0041a1c4U + i*8U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x0041a800U + i*4U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
+{
+        return 0x00418e24U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
+{
+        return 0x00418e28U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
+{
+        return 11U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
+{
+        return 0x7ffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
+{
+        return (r >> 0U) & 0x7ffU;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
+{
+        return 0x18U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
+{
+        return 0x00418ea0U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void)
+{
+        return 0xffffU << 16U;
+}
+static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
+{
+        return 0x00418e30U;
+}
+static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
+{
+        return 0x00418810U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_crstr_gpc_map0_r(void)
+{
+        return 0x00418b08U;
+}
+static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map1_r(void)
+{
+        return 0x00418b0cU;
+}
+static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map2_r(void)
+{
+        return 0x00418b10U;
+}
+static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map3_r(void)
+{
+        return 0x00418b14U;
+}
+static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map4_r(void)
+{
+        return 0x00418b18U;
+}
+static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map5_r(void)
+{
+        return 0x00418b1cU;
+}
+static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_map_table_cfg_r(void)
+{
+        return 0x00418bb8U;
+}
+static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
+{
+        return 0x00418980U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
+{
+        return 0x00418984U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
+{
+        return 0x00418988U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
+{
+        return 3U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
+{
+        return 0x7U << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
+{
+        return (r >> 28U) & 0x7U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
+{
+        return 0x0041898cU;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
+{
+        return 0x00418c6cU;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
+{
+        return 0x00419004U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_r(void)
+{
+        return 0x00419008U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
+{
+        return 0x0041980cU;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
+{
+        return 0x00419848U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
+{
+        return 0x00419c00U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
+{
+        return 0x00419c2cU;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00419e44U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00504644U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x00419e4cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x0050464cU;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
+{
+        return 0x00419d0cU;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
+{
+        return 0x0041ac94U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
+{
+        return 0x00504610U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
+{
+        return 0x00504614U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
+{
+        return 0x00504618U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void)
+{
+        return 0x0050461cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00504624U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
+{
+        return 0x00504628U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void)
+{
+        return 0x00504750U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
+{
+        return 0x00504634U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
+{
+        return 0x00504638U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void)
+{
+        return 0x00504758U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00419e24U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
+{
+        return 0x0050460cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
+{
+        return 0x00419e50U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
+{
+        return 0x00504650U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
+{
+        return 0x00504224U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
+{
+        return 0x00504648U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
+{
+        return 0x00504654U;
+}
+static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
+{
+        return 0x00504770U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
+{
+        return 0x00419f70U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
+{
+        return 0x0050477cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
+{
+        return 0x00419f7cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
+{
+        return 0x0041be08U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
+{
+        return 0x0041bf00U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
+{
+        return 0x0041bf04U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
+{
+        return 0x0041bf08U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
+{
+        return 0x0041bf0cU;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
+{
+        return 0x0041bf10U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
+{
+        return 0x0041bf14U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
+{
+        return 0x0041bfd0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
+{
+        return (v & 0x7U) << 21U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 24U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
+{
+        return 0x0041bfd4U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
+{
+        return 0x0041bfe4U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 5U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 10U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 15U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 20U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 25U;
+}
+static inline u32 gr_bes_zrop_settings_r(void)
+{
+        return 0x00408850U;
+}
+static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_be0_crop_debug3_r(void)
+{
+        return 0x00410108U;
+}
+static inline u32 gr_bes_crop_debug3_r(void)
+{
+        return 0x00408908U;
+}
+static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_bes_crop_settings_r(void)
+{
+        return 0x00408958U;
+}
+static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gr_zcull_subregion_qty_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
+{
+        return 0x00504604U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
+{
+        return 0x00504608U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
+{
+        return 0x0050465cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
+{
+        return 0x00504660U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
+{
+        return 0x00504664U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
+{
+        return 0x00504668U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
+{
+        return 0x0050466cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
+{
+        return 0x00504658U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
+{
+        return 0x00504730U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
+{
+        return 0x00504734U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
+{
+        return 0x00504738U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
+{
+        return 0x0050473cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
+{
+        return 0x00504740U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
+{
+        return 0x00504744U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
+{
+        return 0x00504748U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
+{
+        return 0x0050474cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
+{
+        return 0x00504678U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
+{
+        return 0x00504694U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
+{
+        return 0x005046f0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
+{
+        return 0x00504700U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
+{
+        return 0x005046f4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
+{
+        return 0x00504704U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
+{
+        return 0x005046f8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
+{
+        return 0x00504708U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
+{
+        return 0x005046fcU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
+{
+        return 0x0050470cU;
+}
+static inline u32 gr_fe_pwr_mode_r(void)
+{
+        return 0x00404170U;
+}
+static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fe_pwr_mode_req_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_fe_pwr_mode_req_send_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fe_pwr_mode_req_done_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
+{
+        return 0x00418880U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
+{
+        return 0x3U << 3U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
+{
+        return 0x3U << 5U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
+{
+        return 0x00418890U;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
+{
+        return 0x00418894U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
+{
+        return 0x004188b0U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
+{
+        return 0x004188b4U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
+{
+        return 0x004188b8U;
+}
+static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
+{
+        return 0x004188acU;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
+{
+        return 0x00419e10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
new file mode 100644
index 00000000..2c3ebb45
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
@@ -0,0 +1,527 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ltc_gm20b_h_
+#define _hw_ltc_gm20b_h_
+
+static inline u32 ltc_pltcg_base_v(void)
+{
+        return 0x00140000U;
+}
+static inline u32 ltc_pltcg_extent_v(void)
+{
+        return 0x0017ffffU;
+}
+static inline u32 ltc_ltc0_ltss_v(void)
+{
+        return 0x00140200U;
+}
+static inline u32 ltc_ltc0_lts0_v(void)
+{
+        return 0x00140400U;
+}
+static inline u32 ltc_ltcs_ltss_v(void)
+{
+        return 0x0017e200U;
+}
+static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+        return 0x00140518U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+        return 0x0017e318U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
+{
+        return 0x00140494U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
+{
+        return (r >> 16U) & 0x3U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
+{
+        return 0x0017e26cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
+{
+        return 0x0017e270U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
+{
+        return 0x0017e274U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
+{
+        return 0x0001ffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
+{
+        return 0x0017e278U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
+{
+        return (r >> 0U) & 0x3ffffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
+{
+        return 0x0017e27cU;
+}
+static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
+{
+        return 0x0017e000U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
+{
+        return 0x0017e280U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
+{
+        return (r >> 28U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
+{
+        return 0x0017e2acU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
+{
+        return 0x0017e338U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
+{
+        return 0x0017e33cU + i*4U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
+{
+        return 0x0017e34cU;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
+{
+        return 32U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
+{
+        return 0x0017e2b0U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
+{
+        return 0x0017e214U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
+{
+        return 0x00140214U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
+{
+        return 0x00142214U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+        return 0x0017e20cU;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+        return 0x0014040cU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x0017e2a0U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x0017e2a4U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001402a0U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001402a4U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001422a0U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001422a4U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
new file mode 100644
index 00000000..0264803f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_mc_gm20b_h_
+#define _hw_mc_gm20b_h_
+
+static inline u32 mc_boot_0_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_boot_0_architecture_v(u32 r)
+{
+        return (r >> 24U) & 0x1fU;
+}
+static inline u32 mc_boot_0_implementation_v(u32 r)
+{
+        return (r >> 20U) & 0xfU;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 mc_intr_r(u32 i)
+{
+        return 0x00000100U + i*4U;
+}
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_ltc_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 mc_intr_priv_ring_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 mc_intr_pbus_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_intr_mask_0_r(void)
+{
+        return 0x00000640U;
+}
+static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_en_0_r(void)
+{
+        return 0x00000140U;
+}
+static inline u32 mc_intr_en_0_inta_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 mc_intr_en_0_inta_hardware_f(void)
+{
+        return 0x1U;
+}
+static inline u32 mc_intr_mask_1_r(void)
+{
+        return 0x00000644U;
+}
+static inline u32 mc_intr_mask_1_pmu_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_intr_mask_1_pmu_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 mc_intr_mask_1_pmu_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 mc_intr_mask_1_pmu_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_en_1_r(void)
+{
+        return 0x00000144U;
+}
+static inline u32 mc_intr_en_1_inta_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 mc_intr_en_1_inta_hardware_f(void)
+{
+        return 0x1U;
+}
+static inline u32 mc_enable_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 mc_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_enable_l2_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 mc_enable_pmedia_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pmedia_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 mc_enable_pmedia_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 mc_enable_pmedia_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 mc_enable_priv_ring_enabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 mc_enable_ce0_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 mc_enable_pfifo_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_enable_pgraph_enabled_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_enable_pwr_v(u32 r)
+{
+        return (r >> 13U) & 0x1U;
+}
+static inline u32 mc_enable_pwr_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_enable_pwr_enabled_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 mc_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_enable_ce2_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 mc_enable_ce2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 mc_enable_blg_enabled_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 mc_enable_perfmon_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 mc_intr_ltc_r(void)
+{
+        return 0x0000017cU;
+}
+static inline u32 mc_enable_pb_r(void)
+{
+        return 0x00000204U;
+}
+static inline u32 mc_enable_pb_0_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pb_0_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 mc_enable_pb_0_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 mc_enable_pb_0_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 mc_enable_pb_0_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 mc_elpg_enable_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 mc_elpg_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_elpg_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_elpg_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
new file mode 100644
index 00000000..b8d7bbe4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pbdma_gm20b_h_
+#define _hw_pbdma_gm20b_h_
+
+static inline u32 pbdma_gp_entry1_r(void)
+{
+        return 0x10000004U;
+}
+static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pbdma_gp_entry1_length_f(u32 v)
+{
+        return (v & 0x1fffffU) << 10U;
+}
+static inline u32 pbdma_gp_entry1_length_v(u32 r)
+{
+        return (r >> 10U) & 0x1fffffU;
+}
+static inline u32 pbdma_gp_base_r(u32 i)
+{
+        return 0x00040048U + i*8192U;
+}
+static inline u32 pbdma_gp_base__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pbdma_gp_base_offset_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 3U;
+}
+static inline u32 pbdma_gp_base_rsvd_s(void)
+{
+        return 3U;
+}
+static inline u32 pbdma_gp_base_hi_r(u32 i)
+{
+        return 0x0004004cU + i*8192U;
+}
+static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 pbdma_gp_fetch_r(u32 i)
+{
+        return 0x00040050U + i*8192U;
+}
+static inline u32 pbdma_gp_get_r(u32 i)
+{
+        return 0x00040014U + i*8192U;
+}
+static inline u32 pbdma_gp_put_r(u32 i)
+{
+        return 0x00040000U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_r(u32 i)
+{
+        return 0x00040054U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_hi_r(u32 i)
+{
+        return 0x00040058U + i*8192U;
+}
+static inline u32 pbdma_get_r(u32 i)
+{
+        return 0x00040018U + i*8192U;
+}
+static inline u32 pbdma_get_hi_r(u32 i)
+{
+        return 0x0004001cU + i*8192U;
+}
+static inline u32 pbdma_put_r(u32 i)
+{
+        return 0x0004005cU + i*8192U;
+}
+static inline u32 pbdma_put_hi_r(u32 i)
+{
+        return 0x00040060U + i*8192U;
+}
+static inline u32 pbdma_formats_r(u32 i)
+{
+        return 0x0004009cU + i*8192U;
+}
+static inline u32 pbdma_formats_gp_fermi0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_formats_pb_fermi1_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_formats_mp_fermi0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_r(u32 i)
+{
+        return 0x00040084U + i*8192U;
+}
+static inline u32 pbdma_pb_header_priv_user_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_method_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_subchannel_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_level_main_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_pb_header_type_inc_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_pb_header_type_non_inc_f(void)
+{
+        return 0x60000000U;
+}
+static inline u32 pbdma_hdr_shadow_r(u32 i)
+{
+        return 0x00040118U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_0_r(u32 i)
+{
+        return 0x00040110U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_1_r(u32 i)
+{
+        return 0x00040114U + i*8192U;
+}
+static inline u32 pbdma_subdevice_r(u32 i)
+{
+        return 0x00040094U + i*8192U;
+}
+static inline u32 pbdma_subdevice_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 pbdma_subdevice_status_active_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_method0_r(u32 i)
+{
+        return 0x000400c0U + i*8192U;
+}
+static inline u32 pbdma_method0_fifo_size_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pbdma_method0_addr_f(u32 v)
+{
+        return (v & 0xfffU) << 2U;
+}
+static inline u32 pbdma_method0_addr_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 pbdma_method0_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 pbdma_method0_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_method0_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_method1_r(u32 i)
+{
+        return 0x000400c8U + i*8192U;
+}
+static inline u32 pbdma_method2_r(u32 i)
+{
+        return 0x000400d0U + i*8192U;
+}
+static inline u32 pbdma_method3_r(u32 i)
+{
+        return 0x000400d8U + i*8192U;
+}
+static inline u32 pbdma_data0_r(u32 i)
+{
+        return 0x000400c4U + i*8192U;
+}
+static inline u32 pbdma_target_r(u32 i)
+{
+        return 0x000400acU + i*8192U;
+}
+static inline u32 pbdma_target_engine_sw_f(void)
+{
+        return 0x1fU;
+}
+static inline u32 pbdma_acquire_r(u32 i)
+{
+        return 0x00040030U + i*8192U;
+}
+static inline u32 pbdma_acquire_retry_man_2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_acquire_retry_exp_2_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
+{
+        return (v & 0xfU) << 11U;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_f(void)
+{
+        return 0x7800U;
+}
+static inline u32 pbdma_acquire_timeout_man_f(u32 v)
+{
+        return (v & 0xffffU) << 15U;
+}
+static inline u32 pbdma_acquire_timeout_man_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 pbdma_acquire_timeout_man_max_f(void)
+{
+        return 0x7fff8000U;
+}
+static inline u32 pbdma_acquire_timeout_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_acquire_timeout_en_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_status_r(u32 i)
+{
+        return 0x00040100U + i*8192U;
+}
+static inline u32 pbdma_channel_r(u32 i)
+{
+        return 0x00040120U + i*8192U;
+}
+static inline u32 pbdma_signature_r(u32 i)
+{
+        return 0x00040010U + i*8192U;
+}
+static inline u32 pbdma_signature_hw_valid_f(void)
+{
+        return 0xfaceU;
+}
+static inline u32 pbdma_signature_sw_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_r(u32 i)
+{
+        return 0x00040008U + i*8192U;
+}
+static inline u32 pbdma_userd_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pbdma_userd_addr_f(u32 v)
+{
+        return (v & 0x7fffffU) << 9U;
+}
+static inline u32 pbdma_userd_hi_r(u32 i)
+{
+        return 0x0004000cU + i*8192U;
+}
+static inline u32 pbdma_userd_hi_addr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_hce_ctrl_r(u32 i)
+{
+        return 0x000400e4U + i*8192U;
+}
+static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_r(u32 i)
+{
+        return 0x00040108U + i*8192U;
+}
+static inline u32 pbdma_intr_0_memreq_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pbdma_intr_0_memreq_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pbdma_intr_0_memflush_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_memop_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_intr_0_lbreq_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
+{
+        return 0x400U;
+}
+static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
+{
+        return 0x800U;
+}
+static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 pbdma_intr_0_gpptr_pending_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 pbdma_intr_0_gpentry_pending_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 pbdma_intr_0_pbptr_pending_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 pbdma_intr_0_pbentry_pending_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 pbdma_intr_0_method_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_intr_0_device_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 pbdma_intr_0_semaphore_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 pbdma_intr_0_acquire_pending_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 pbdma_intr_0_pri_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_intr_0_pbseg_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 pbdma_intr_0_signature_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+        return 0x00040148U + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_r(u32 i)
+{
+        return 0x0004010cU + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_en_1_r(u32 i)
+{
+        return 0x0004014cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_r(u32 i)
+{
+        return 0x0004013cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_udma_nop_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 pbdma_syncpointa_r(u32 i)
+{
+        return 0x000400a4U + i*8192U;
+}
+static inline u32 pbdma_syncpointa_payload_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pbdma_syncpointb_r(u32 i)
+{
+        return 0x000400a8U + i*8192U;
+}
+static inline u32 pbdma_syncpointb_op_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 pbdma_syncpointb_op_wait_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 pbdma_runlist_timeslice_r(u32 i)
+{
+        return 0x000400f8U + i*8192U;
+}
+static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
+{
+        return 0x3000U;
+}
+static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
new file mode 100644
index 00000000..ae34cabd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_perf_gm20b_h_
+#define _hw_perf_gm20b_h_
+
+static inline u32 perf_pmasys_control_r(void)
+{
+        return 0x001b4000U;
+}
+static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
+{
+        return 0x10U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
+{
+        return 0x20U;
+}
+static inline u32 perf_pmasys_mem_block_r(void)
+{
+        return 0x001b4070U;
+}
+static inline u32 perf_pmasys_mem_block_base_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 perf_pmasys_mem_block_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 perf_pmasys_mem_block_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_outbase_r(void)
+{
+        return 0x001b4074U;
+}
+static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_outbaseupper_r(void)
+{
+        return 0x001b4078U;
+}
+static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 perf_pmasys_outsize_r(void)
+{
+        return 0x001b407cU;
+}
+static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_mem_bytes_r(void)
+{
+        return 0x001b4084U;
+}
+static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_mem_bump_r(void)
+{
+        return 0x001b4088U;
+}
+static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_r(void)
+{
+        return 0x001b40a4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
+{
+        return 0x10U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h
new file mode 100644
index 00000000..47a6bfa8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pram_gm20b_h_
+#define _hw_pram_gm20b_h_
+
+static inline u32 pram_data032_r(u32 i)
+{
+        return 0x00700000U + i*4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
new file mode 100644
index 00000000..c6f08ed3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringmaster_gm20b_h_
+#define _hw_pri_ringmaster_gm20b_h_
+
+static inline u32 pri_ringmaster_command_r(void)
+{
+        return 0x0012004cU;
+}
+static inline u32 pri_ringmaster_command_cmd_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 pri_ringmaster_command_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_command_data_r(void)
+{
+        return 0x00120048U;
+}
+static inline u32 pri_ringmaster_start_results_r(void)
+{
+        return 0x00120050U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pri_ringmaster_intr_status0_r(void)
+{
+        return 0x00120058U;
+}
+static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status1_r(void)
+{
+        return 0x0012005cU;
+}
+static inline u32 pri_ringmaster_global_ctl_r(void)
+{
+        return 0x00120060U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_enum_fbp_r(void)
+{
+        return 0x00120074U;
+}
+static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_gpc_r(void)
+{
+        return 0x00120078U;
+}
+static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_ltc_r(void)
+{
+        return 0x0012006cU;
+}
+static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
new file mode 100644
index 00000000..8d1ffb2b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gm20b_h_
+#define _hw_pri_ringstation_gpc_gm20b_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300U + i*4U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
new file mode 100644
index 00000000..ac1d2456
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_sys_gm20b_h_
+#define _hw_pri_ringstation_sys_gm20b_h_
+
+static inline u32 pri_ringstation_sys_master_config_r(u32 i)
+{
+        return 0x00122300U + i*4U;
+}
+static inline u32 pri_ringstation_sys_decode_config_r(void)
+{
+        return 0x00122204U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120U;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124U;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128U;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h
new file mode 100644
index 00000000..d44cc463
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_proj_gm20b_h_
+#define _hw_proj_gm20b_h_
+
+static inline u32 proj_gpc_base_v(void)
+{
+        return 0x00500000U;
+}
+static inline u32 proj_gpc_shared_base_v(void)
+{
+        return 0x00418000U;
+}
+static inline u32 proj_gpc_stride_v(void)
+{
+        return 0x00008000U;
+}
+static inline u32 proj_ltc_stride_v(void)
+{
+        return 0x00002000U;
+}
+static inline u32 proj_lts_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_fbpa_stride_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 proj_ppc_in_gpc_base_v(void)
+{
+        return 0x00003000U;
+}
+static inline u32 proj_ppc_in_gpc_shared_base_v(void)
+{
+        return 0x00003e00U;
+}
+static inline u32 proj_ppc_in_gpc_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_rop_base_v(void)
+{
+        return 0x00410000U;
+}
+static inline u32 proj_rop_shared_base_v(void)
+{
+        return 0x00408800U;
+}
+static inline u32 proj_rop_stride_v(void)
+{
+        return 0x00000400U;
+}
+static inline u32 proj_tpc_in_gpc_base_v(void)
+{
+        return 0x00004000U;
+}
+static inline u32 proj_tpc_in_gpc_stride_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 proj_tpc_in_gpc_shared_base_v(void)
+{
+        return 0x00001800U;
+}
+static inline u32 proj_host_num_engines_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_host_num_pbdma_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_fbps_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_gpcs_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_scal_litter_num_zcull_banks_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 proj_scal_max_gpcs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 proj_scal_max_tpc_per_gpc_v(void)
+{
+        return 0x00000008U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
new file mode 100644
index 00000000..fa232644
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
@@ -0,0 +1,827 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pwr_gm20b_h_
+#define _hw_pwr_gm20b_h_
+
+static inline u32 pwr_falcon_irqsset_r(void)
+{
+        return 0x0010a000U;
+}
+static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqsclr_r(void)
+{
+        return 0x0010a004U;
+}
+static inline u32 pwr_falcon_irqstat_r(void)
+{
+        return 0x0010a008U;
+}
+static inline u32 pwr_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqmode_r(void)
+{
+        return 0x0010a00cU;
+}
+static inline u32 pwr_falcon_irqmset_r(void)
+{
+        return 0x0010a010U;
+}
+static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_r(void)
+{
+        return 0x0010a014U;
+}
+static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqmask_r(void)
+{
+        return 0x0010a018U;
+}
+static inline u32 pwr_falcon_irqdest_r(void)
+{
+        return 0x0010a01cU;
+}
+static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 pwr_falcon_curctx_r(void)
+{
+        return 0x0010a050U;
+}
+static inline u32 pwr_falcon_nxtctx_r(void)
+{
+        return 0x0010a054U;
+}
+static inline u32 pwr_falcon_mailbox0_r(void)
+{
+        return 0x0010a040U;
+}
+static inline u32 pwr_falcon_mailbox1_r(void)
+{
+        return 0x0010a044U;
+}
+static inline u32 pwr_falcon_itfen_r(void)
+{
+        return 0x0010a048U;
+}
+static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_r(void)
+{
+        return 0x0010a04cU;
+}
+static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 pwr_falcon_os_r(void)
+{
+        return 0x0010a080U;
+}
+static inline u32 pwr_falcon_engctl_r(void)
+{
+        return 0x0010a0a4U;
+}
+static inline u32 pwr_falcon_cpuctl_r(void)
+{
+        return 0x0010a100U;
+}
+static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 pwr_falcon_cpuctl_alias_r(void)
+{
+        return 0x0010a130U;
+}
+static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_pmu_scpctl_stat_r(void)
+{
+        return 0x0010ac08U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+        return 0x0010a180U + i*16U;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+        return 0x0010a184U + i*16U;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+        return 0x0010a188U + i*16U;
+}
+static inline u32 pwr_falcon_sctl_r(void)
+{
+        return 0x0010a240U;
+}
+static inline u32 pwr_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 pwr_falcon_bootvec_r(void)
+{
+        return 0x0010a104U;
+}
+static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_falcon_dmactl_r(void)
+{
+        return 0x0010a10cU;
+}
+static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_falcon_hwcfg_r(void)
+{
+        return 0x0010a108U;
+}
+static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_dmatrfbase_r(void)
+{
+        return 0x0010a110U;
+}
+static inline u32 pwr_falcon_dmatrfmoffs_r(void)
+{
+        return 0x0010a114U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_r(void)
+{
+        return 0x0010a118U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 pwr_falcon_dmatrffboffs_r(void)
+{
+        return 0x0010a11cU;
+}
+static inline u32 pwr_falcon_exterraddr_r(void)
+{
+        return 0x0010a168U;
+}
+static inline u32 pwr_falcon_exterrstat_r(void)
+{
+        return 0x0010a16cU;
+}
+static inline u32 pwr_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
+{
+        return 0x0010a200U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
+{
+        return 0x0010a20cU;
+}
+static inline u32 pwr_falcon_dmemc_r(u32 i)
+{
+        return 0x0010a1c0U + i*8U;
+}
+static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 pwr_falcon_dmemd_r(u32 i)
+{
+        return 0x0010a1c4U + i*8U;
+}
+static inline u32 pwr_pmu_new_instblk_r(void)
+{
+        return 0x0010a480U;
+}
+static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 pwr_pmu_mutex_id_r(void)
+{
+        return 0x0010a488U;
+}
+static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_id_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 pwr_pmu_mutex_id_release_r(void)
+{
+        return 0x0010a48cU;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_mutex_r(u32 i)
+{
+        return 0x0010a580U + i*4U;
+}
+static inline u32 pwr_pmu_mutex__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 pwr_pmu_mutex_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_queue_head_r(u32 i)
+{
+        return 0x0010a4a0U + i*4U;
+}
+static inline u32 pwr_pmu_queue_head__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_queue_head_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_head_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_queue_tail_r(u32 i)
+{
+        return 0x0010a4b0U + i*4U;
+}
+static inline u32 pwr_pmu_queue_tail__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_head_r(void)
+{
+        return 0x0010a4c8U;
+}
+static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_tail_r(void)
+{
+        return 0x0010a4ccU;
+}
+static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_idle_mask_r(u32 i)
+{
+        return 0x0010a504U + i*16U;
+}
+static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pwr_pmu_idle_count_r(u32 i)
+{
+        return 0x0010a508U + i*16U;
+}
+static inline u32 pwr_pmu_idle_count_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_count_value_v(u32 r)
+{
+        return (r >> 0U) & 0x7fffffffU;
+}
+static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
+{
+        return 0x0010a50cU + i*16U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
+{
+        return 0x0010a9f0U + i*8U;
+}
+static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
+{
+        return 0x0010a9f4U + i*8U;
+}
+static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
+{
+        return 0x0010aa30U + i*8U;
+}
+static inline u32 pwr_pmu_debug_r(u32 i)
+{
+        return 0x0010a5c0U + i*4U;
+}
+static inline u32 pwr_pmu_debug__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_mailbox_r(u32 i)
+{
+        return 0x0010a450U + i*4U;
+}
+static inline u32 pwr_pmu_mailbox__size_1_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 pwr_pmu_bar0_addr_r(void)
+{
+        return 0x0010a7a0U;
+}
+static inline u32 pwr_pmu_bar0_data_r(void)
+{
+        return 0x0010a7a4U;
+}
+static inline u32 pwr_pmu_bar0_ctl_r(void)
+{
+        return 0x0010a7acU;
+}
+static inline u32 pwr_pmu_bar0_timeout_r(void)
+{
+        return 0x0010a7a8U;
+}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+        return 0x0010a988U;
+}
+static inline u32 pwr_pmu_bar0_error_status_r(void)
+{
+        return 0x0010a7b0U;
+}
+static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
+{
+        return 0x0010a6c0U + i*4U;
+}
+static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
+{
+        return 0x0010a6e8U + i*4U;
+}
+static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
+{
+        return 0x0010a710U + i*4U;
+}
+static inline u32 pwr_pmu_pg_intren_r(u32 i)
+{
+        return 0x0010a760U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_r(u32 i)
+{
+        return 0x0010ae00U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_s(void)
+{
+        return 1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
new file mode 100644
index 00000000..2414abf0
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ram_gm20b_h_
+#define _hw_ram_gm20b_h_
+
+static inline u32 ram_in_ramfc_s(void)
+{
+        return 4096U;
+}
+static inline u32 ram_in_ramfc_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_in_page_dir_base_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ram_in_page_dir_base_target_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 ram_in_page_dir_base_vol_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_big_page_size_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 ram_in_big_page_size_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 ram_in_big_page_size_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_big_page_size_128kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_big_page_size_64kb_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ram_in_page_dir_base_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_page_dir_base_lo_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_page_dir_base_hi_w(void)
+{
+        return 129U;
+}
+static inline u32 ram_in_adr_limit_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_adr_limit_lo_w(void)
+{
+        return 130U;
+}
+static inline u32 ram_in_adr_limit_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_adr_limit_hi_w(void)
+{
+        return 131U;
+}
+static inline u32 ram_in_engine_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_engine_cs_wfi_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_engine_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_engine_cs_fg_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_engine_cs_fg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ram_in_gr_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_gr_wfi_target_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_mode_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
+{
+        return 133U;
+}
+static inline u32 ram_in_base_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ram_in_alloc_size_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ram_fc_size_val_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_fc_gp_put_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_userd_w(void)
+{
+        return 2U;
+}
+static inline u32 ram_fc_userd_hi_w(void)
+{
+        return 3U;
+}
+static inline u32 ram_fc_signature_w(void)
+{
+        return 4U;
+}
+static inline u32 ram_fc_gp_get_w(void)
+{
+        return 5U;
+}
+static inline u32 ram_fc_pb_get_w(void)
+{
+        return 6U;
+}
+static inline u32 ram_fc_pb_get_hi_w(void)
+{
+        return 7U;
+}
+static inline u32 ram_fc_pb_top_level_get_w(void)
+{
+        return 8U;
+}
+static inline u32 ram_fc_pb_top_level_get_hi_w(void)
+{
+        return 9U;
+}
+static inline u32 ram_fc_acquire_w(void)
+{
+        return 12U;
+}
+static inline u32 ram_fc_semaphorea_w(void)
+{
+        return 14U;
+}
+static inline u32 ram_fc_semaphoreb_w(void)
+{
+        return 15U;
+}
+static inline u32 ram_fc_semaphorec_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_fc_semaphored_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_fc_gp_base_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_fc_gp_base_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_fc_gp_fetch_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_fc_pb_fetch_w(void)
+{
+        return 21U;
+}
+static inline u32 ram_fc_pb_fetch_hi_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_fc_pb_put_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_fc_pb_put_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_fc_pb_header_w(void)
+{
+        return 33U;
+}
+static inline u32 ram_fc_pb_count_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_fc_subdevice_w(void)
+{
+        return 37U;
+}
+static inline u32 ram_fc_formats_w(void)
+{
+        return 39U;
+}
+static inline u32 ram_fc_syncpointa_w(void)
+{
+        return 41U;
+}
+static inline u32 ram_fc_syncpointb_w(void)
+{
+        return 42U;
+}
+static inline u32 ram_fc_target_w(void)
+{
+        return 43U;
+}
+static inline u32 ram_fc_hce_ctrl_w(void)
+{
+        return 57U;
+}
+static inline u32 ram_fc_chid_w(void)
+{
+        return 58U;
+}
+static inline u32 ram_fc_chid_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_fc_chid_id_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_runlist_timeslice_w(void)
+{
+        return 62U;
+}
+static inline u32 ram_userd_base_shift_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 ram_userd_chan_size_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_userd_put_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_userd_get_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_userd_ref_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_userd_put_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_userd_ref_threshold_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_userd_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_userd_get_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_userd_gp_get_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_userd_gp_put_w(void)
+{
+        return 35U;
+}
+static inline u32 ram_userd_gp_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_gp_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_rl_entry_size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+        return (v & 0xfU) << 14U;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+        return 0xc000U;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+        return (v & 0xffU) << 18U;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+        return (v & 0x3fU) << 26U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
new file mode 100644
index 00000000..fc1cd517
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_therm_gm20b_h_
+#define _hw_therm_gm20b_h_
+
+static inline u32 therm_use_a_r(void)
+{
+        return 0x00020798U;
+}
+static inline u32 therm_use_a_ext_therm_0_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_use_a_ext_therm_1_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_use_a_ext_therm_2_enable_f(void)
+{
+        return 0x4U;
+}
+static inline u32 therm_evt_ext_therm_0_r(void)
+{
+        return 0x00020700U;
+}
+static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_evt_ext_therm_1_r(void)
+{
+        return 0x00020704U;
+}
+static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_evt_ext_therm_2_r(void)
+{
+        return 0x00020708U;
+}
+static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_weight_1_r(void)
+{
+        return 0x00020024U;
+}
+static inline u32 therm_config1_r(void)
+{
+        return 0x00020050U;
+}
+static inline u32 therm_config2_r(void)
+{
+        return 0x00020130U;
+}
+static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 therm_config2_grad_enable_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 therm_gate_ctrl_r(u32 i)
+{
+        return 0x00020200U + i*4U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_m(void)
+{
+        return 0x3U << 2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
+{
+        return 0x4U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_m(void)
+{
+        return 0x3U << 4U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
+{
+        return 0x10U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
+{
+        return 0x20U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
+{
+        return 0x1fU << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
+{
+        return (v & 0x7U) << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
+{
+        return 0x7U << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
+{
+        return 0xfU << 20U;
+}
+static inline u32 therm_fecs_idle_filter_r(void)
+{
+        return 0x00020288U;
+}
+static inline u32 therm_fecs_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_hubmmu_idle_filter_r(void)
+{
+        return 0x0002028cU;
+}
+static inline u32 therm_hubmmu_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_clk_slowdown_r(u32 i)
+{
+        return 0x00020160U + i*4U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 16U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_m(void)
+{
+        return 0x3fU << 16U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
+{
+        return (r >> 16U) & 0x3fU;
+}
+static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_grad_stepping_table_r(u32 i)
+{
+        return 0x000202c8U + i*4U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
+{
+        return 0x6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
+{
+        return 0xeU;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
+{
+        return (v & 0x3fU) << 12U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
+{
+        return 0x3fU << 12U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
+{
+        return (v & 0x3fU) << 18U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
+{
+        return 0x3fU << 18U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
+{
+        return (v & 0x3fU) << 24U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
+{
+        return 0x3fU << 24U;
+}
+static inline u32 therm_grad_stepping0_r(void)
+{
+        return 0x000202c0U;
+}
+static inline u32 therm_grad_stepping0_feature_s(void)
+{
+        return 1U;
+}
+static inline u32 therm_grad_stepping0_feature_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 therm_grad_stepping0_feature_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 therm_grad_stepping0_feature_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 therm_grad_stepping0_feature_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_grad_stepping1_r(void)
+{
+        return 0x000202c4U;
+}
+static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 therm_clk_timing_r(u32 i)
+{
+        return 0x000203c0U + i*4U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
+{
+        return 0x10000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
new file mode 100644
index 00000000..38548645
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_timer_gm20b_h_
+#define _hw_timer_gm20b_h_
+
+static inline u32 timer_pri_timeout_r(void)
+{
+        return 0x00009080U;
+}
+static inline u32 timer_pri_timeout_period_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 timer_pri_timeout_period_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 timer_pri_timeout_period_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 timer_pri_timeout_en_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 timer_pri_timeout_en_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 timer_pri_timeout_en_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 timer_pri_timeout_en_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 timer_pri_timeout_en_en_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 timer_pri_timeout_save_0_r(void)
+{
+        return 0x00009084U;
+}
+static inline u32 timer_pri_timeout_save_1_r(void)
+{
+        return 0x00009088U;
+}
+static inline u32 timer_pri_timeout_fecs_errcode_r(void)
+{
+        return 0x0000908cU;
+}
+static inline u32 timer_time_0_r(void)
+{
+        return 0x00009400U;
+}
+static inline u32 timer_time_1_r(void)
+{
+        return 0x00009410U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h
new file mode 100644
index 00000000..6d48839e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_top_gm20b_h_
+#define _hw_top_gm20b_h_
+
+static inline u32 top_num_gpcs_r(void)
+{
+        return 0x00022430U;
+}
+static inline u32 top_num_gpcs_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_tpc_per_gpc_r(void)
+{
+        return 0x00022434U;
+}
+static inline u32 top_tpc_per_gpc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_fbps_r(void)
+{
+        return 0x00022438U;
+}
+static inline u32 top_num_fbps_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_ltc_per_fbp_r(void)
+{
+        return 0x00022450U;
+}
+static inline u32 top_ltc_per_fbp_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_slices_per_ltc_r(void)
+{
+        return 0x0002245cU;
+}
+static inline u32 top_slices_per_ltc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_ltcs_r(void)
+{
+        return 0x00022454U;
+}
+static inline u32 top_device_info_r(u32 i)
+{
+        return 0x00022700U + i*4U;
+}
+static inline u32 top_device_info__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 top_device_info_chain_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 top_device_info_chain_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_engine_enum_v(u32 r)
+{
+        return (r >> 26U) & 0xfU;
+}
+static inline u32 top_device_info_runlist_enum_v(u32 r)
+{
+        return (r >> 21U) & 0xfU;
+}
+static inline u32 top_device_info_intr_enum_v(u32 r)
+{
+        return (r >> 15U) & 0x1fU;
+}
+static inline u32 top_device_info_reset_enum_v(u32 r)
+{
+        return (r >> 9U) & 0x1fU;
+}
+static inline u32 top_device_info_type_enum_v(u32 r)
+{
+        return (r >> 2U) & 0x1fffffffU;
+}
+static inline u32 top_device_info_type_enum_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_type_enum_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 top_device_info_type_enum_copy0_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_type_enum_copy0_f(void)
+{
+        return 0x4U;
+}
+static inline u32 top_device_info_type_enum_copy1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 top_device_info_type_enum_copy1_f(void)
+{
+        return 0x8U;
+}
+static inline u32 top_device_info_type_enum_copy2_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_type_enum_copy2_f(void)
+{
+        return 0xcU;
+}
+static inline u32 top_device_info_engine_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 top_device_info_runlist_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 top_device_info_intr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 top_device_info_reset_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_entry_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 top_device_info_entry_not_valid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_entry_enum_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 top_device_info_entry_engine_type_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_entry_data_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_data_type_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 top_device_info_data_type_enum2_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_data_pri_base_v(u32 r)
+{
+        return (r >> 12U) & 0x7ffU;
+}
+static inline u32 top_device_info_data_pri_base_align_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
+{
+        return (r >> 3U) & 0x1fU;
+}
+static inline u32 top_device_info_data_fault_id_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_data_fault_id_valid_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
new file mode 100644
index 00000000..8f0a77a5
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
@@ -0,0 +1,503 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_trim_gm20b_h_
+#define _hw_trim_gm20b_h_
+
+static inline u32 trim_sys_gpcpll_cfg_r(void)
+{
+        return 0x00137000U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
+{
+        return 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void)
+{
+        return 0x4U;
+}
+static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
+{
+        return 0x10U;
+}
+static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
+{
+        return (r >> 17U) & 0x1U;
+}
+static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 trim_sys_gpcpll_coeff_r(void)
+{
+        return 0x00137004U;
+}
+static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
+{
+        return (v & 0x3fU) << 16U;
+}
+static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
+{
+        return 0x3fU << 16U;
+}
+static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
+{
+        return (r >> 16U) & 0x3fU;
+}
+static inline u32 trim_sys_sel_vco_r(void)
+{
+        return 0x00137100U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
+{
+        return 0x1U;
+}
+static inline u32 trim_sys_gpc2clk_out_r(void)
+{
+        return 0x00137250U;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
+{
+        return 6U;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
+{
+        return 0x3cU;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
+{
+        return 6U;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
+{
+        return 0x3fU << 8U;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
+{
+        return (r >> 8U) & 0x3fU;
+}
+static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
+{
+        return 0x00134124U + i*512U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
+{
+        return (v & 0x3fffU) << 0U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
+{
+        return 0x00134128U + i*512U;
+}
+static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 trim_sys_gpcpll_cfg2_r(void)
+{
+        return 0x0013700cU;
+}
+static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
+{
+        return 0xffU << 24U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_r(void)
+{
+        return 0x00137018U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void)
+{
+        return 0x1ffU << 0U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r)
+{
+        return (r >> 24U) & 0x7fU;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_r(void)
+{
+        return 0x00137010U;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v)
+{
+        return (v & 0x7fU) << 0U;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void)
+{
+        return 0x7fU << 0U;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r)
+{
+        return (r >> 0U) & 0x7fU;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v)
+{
+        return (v & 0x7fU) << 8U;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void)
+{
+        return 0x7fU << 8U;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r)
+{
+        return (r >> 8U) & 0x7fU;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v)
+{
+        return (v & 0x3fU) << 16U;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void)
+{
+        return 0x3fU << 16U;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r)
+{
+        return (r >> 16U) & 0x3fU;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_r(void)
+{
+        return 0x00137014U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v)
+{
+        return (v & 0x7fU) << 0U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void)
+{
+        return 0x7fU << 0U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r)
+{
+        return (r >> 0U) & 0x7fU;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v)
+{
+        return (v & 0x7fU) << 8U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void)
+{
+        return 0x7fU << 8U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r)
+{
+        return (r >> 8U) & 0x7fU;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v)
+{
+        return (v & 0xfffU) << 16U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void)
+{
+        return 0xfffU << 16U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void)
+{
+        return 0x1U << 29U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 trim_sys_gpcpll_dvfs2_r(void)
+{
+        return 0x00137020U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
+{
+        return 0x0013701cU;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
+{
+        return 0x1U << 22U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
+{
+        return 0x001328a0U;
+}
+static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void)
+{
+        return 0x00132820U;
+}
+static inline u32 trim_sys_bypassctrl_r(void)
+{
+        return 0x00137340U;
+}
+static inline u32 trim_sys_bypassctrl_gpcpll_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void)
+{
+        return 0x1U;
+}
+static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void)
+{
+        return 0x0U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h
new file mode 100644
index 00000000..ce3aafd6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_bus_gp106_h_
+#define _hw_bus_gp106_h_
+
+static inline u32 bus_bar0_window_r(void)
+{
+        return 0x00001700U;
+}
+static inline u32 bus_bar0_window_base_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 bus_bar0_window_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 bus_bar1_block_r(void)
+{
+        return 0x00001704U;
+}
+static inline u32 bus_bar1_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar1_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar1_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar2_block_r(void)
+{
+        return 0x00001714U;
+}
+static inline u32 bus_bar2_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar2_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar2_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar1_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bar2_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bind_status_r(void)
+{
+        return 0x00001710U;
+}
+static inline u32 bus_bind_status_bar1_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar1_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar1_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 bus_bind_status_bar2_pending_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar2_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar2_pending_busy_f(void)
+{
+        return 0x4U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 bus_intr_0_r(void)
+{
+        return 0x00001100U;
+}
+static inline u32 bus_intr_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 bus_intr_en_0_r(void)
+{
+        return 0x00001140U;
+}
+static inline u32 bus_intr_en_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_en_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_en_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h
new file mode 100644
index 00000000..cd637776
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ccsr_gp106_h_
+#define _hw_ccsr_gp106_h_
+
+static inline u32 ccsr_channel_inst_r(u32 i)
+{
+        return 0x00800000U + i*8U;
+}
+static inline u32 ccsr_channel_inst__size_1_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ccsr_channel_inst_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 ccsr_channel_inst_bind_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_bind_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 ccsr_channel_r(u32 i)
+{
+        return 0x00800004U + i*8U;
+}
+static inline u32 ccsr_channel__size_1_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ccsr_channel_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ccsr_channel_enable_set_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 ccsr_channel_enable_set_true_f(void)
+{
+        return 0x400U;
+}
+static inline u32 ccsr_channel_enable_clr_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ccsr_channel_status_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
+{
+        return 0x100U;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ce_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ce_gp106.h
new file mode 100644
index 00000000..8892f42f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ce_gp106.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce_gp106_h_
+#define _hw_ce_gp106_h_
+
+static inline u32 ce_intr_status_r(u32 i)
+{
+        return 0x00104410U + i*128U;
+}
+static inline u32 ce_intr_status_blockpipe_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce_intr_status_blockpipe_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce_intr_status_launcherr_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ce_intr_status_launcherr_reset_f(void)
+{
+        return 0x4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h
new file mode 100644
index 00000000..3387d236
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ctxsw_prog_gp106_h_
+#define _hw_ctxsw_prog_gp106_h_
+
+static inline u32 ctxsw_prog_fecs_header_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_main_image_patch_count_o(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
+{
+        return 0x00000014U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
+{
+        return 0x00000018U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_o(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_main_image_pm_o(void)
+{
+        return 0x00000028U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
+{
+        return 0x7U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
+{
+        return 0x0000002cU;
+}
+static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
+{
+        return 0x000000d0U;
+}
+static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
+{
+        return 0x000000d4U;
+}
+static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
+{
+        return 0x000000d8U;
+}
+static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
+{
+        return 0x000000dcU;
+}
+static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
+{
+        return 0x600dc0deU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_local_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
+{
+        return 0xad0becabU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+        return 2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
+{
+        return 0x00000068U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
+{
+        return 0x00000084U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
+{
+        return 0x2U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h
new file mode 100644
index 00000000..6740b2a6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h
@@ -0,0 +1,599 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_falcon_gp106_h_
+#define _hw_falcon_gp106_h_
+
+static inline u32 falcon_falcon_irqsset_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqsclr_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 falcon_falcon_irqstat_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 falcon_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqmode_r(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 falcon_falcon_irqmset_r(void)
+{
+        return 0x00000010U;
+}
+static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_r(void)
+{
+        return 0x00000014U;
+}
+static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqmask_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 falcon_falcon_irqdest_r(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 falcon_falcon_curctx_r(void)
+{
+        return 0x00000050U;
+}
+static inline u32 falcon_falcon_nxtctx_r(void)
+{
+        return 0x00000054U;
+}
+static inline u32 falcon_falcon_mailbox0_r(void)
+{
+        return 0x00000040U;
+}
+static inline u32 falcon_falcon_mailbox1_r(void)
+{
+        return 0x00000044U;
+}
+static inline u32 falcon_falcon_itfen_r(void)
+{
+        return 0x00000048U;
+}
+static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_r(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 falcon_falcon_os_r(void)
+{
+        return 0x00000080U;
+}
+static inline u32 falcon_falcon_engctl_r(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 falcon_falcon_cpuctl_r(void)
+{
+        return 0x00000100U;
+}
+static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_stopped_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_alias_r(void)
+{
+        return 0x00000130U;
+}
+static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_imemc_r(u32 i)
+{
+        return 0x00000180U + i*16U;
+}
+static inline u32 falcon_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_imemd_r(u32 i)
+{
+        return 0x00000184U + i*16U;
+}
+static inline u32 falcon_falcon_imemt_r(u32 i)
+{
+        return 0x00000188U + i*16U;
+}
+static inline u32 falcon_falcon_sctl_r(void)
+{
+        return 0x00000240U;
+}
+static inline u32 falcon_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 falcon_falcon_bootvec_r(void)
+{
+        return 0x00000104U;
+}
+static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 falcon_falcon_dmactl_r(void)
+{
+        return 0x0000010cU;
+}
+static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_hwcfg_r(void)
+{
+        return 0x00000108U;
+}
+static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_dmatrfbase_r(void)
+{
+        return 0x00000110U;
+}
+static inline u32 falcon_falcon_dmatrfbase1_r(void)
+{
+        return 0x00000128U;
+}
+static inline u32 falcon_falcon_dmatrfmoffs_r(void)
+{
+        return 0x00000114U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_r(void)
+{
+        return 0x00000118U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 falcon_falcon_dmatrffboffs_r(void)
+{
+        return 0x0000011cU;
+}
+static inline u32 falcon_falcon_imctl_debug_r(void)
+{
+        return 0x0000015cU;
+}
+static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 falcon_falcon_imstat_r(void)
+{
+        return 0x00000144U;
+}
+static inline u32 falcon_falcon_traceidx_r(void)
+{
+        return 0x00000148U;
+}
+static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 falcon_falcon_traceidx_idx_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 falcon_falcon_tracepc_r(void)
+{
+        return 0x0000014cU;
+}
+static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 falcon_falcon_exterraddr_r(void)
+{
+        return 0x00000168U;
+}
+static inline u32 falcon_falcon_exterrstat_r(void)
+{
+        return 0x0000016cU;
+}
+static inline u32 falcon_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 falcon_falcon_icd_cmd_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 falcon_falcon_icd_rdata_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 falcon_falcon_dmemc_r(u32 i)
+{
+        return 0x000001c0U + i*8U;
+}
+static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 falcon_falcon_dmemd_r(u32 i)
+{
+        return 0x000001c4U + i*8U;
+}
+static inline u32 falcon_falcon_debug1_r(void)
+{
+        return 0x00000090U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
+{
+        return 1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 falcon_falcon_debuginfo_r(void)
+{
+        return 0x00000094U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
new file mode 100644
index 00000000..53288555
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
@@ -0,0 +1,603 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fb_gp106_h_
+#define _hw_fb_gp106_h_
+
+static inline u32 fb_fbhub_num_active_ltcs_r(void)
+{
+        return 0x00100800U;
+}
+static inline u32 fb_mmu_ctrl_r(void)
+{
+        return 0x00100c80U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
+{
+        return (r >> 11U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_priv_mmu_phy_secure_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 fb_mmu_invalidate_pdb_r(void)
+{
+        return 0x00100cb8U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_invalidate_r(void)
+{
+        return 0x00100cbcU;
+}
+static inline u32 fb_mmu_invalidate_all_va_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_invalidate_replay_s(void)
+{
+        return 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_f(u32 v)
+{
+        return (v & 0x7U) << 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_m(void)
+{
+        return 0x7U << 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_v(u32 r)
+{
+        return (r >> 3U) & 0x7U;
+}
+static inline u32 fb_mmu_invalidate_replay_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_replay_start_f(void)
+{
+        return 0x8U;
+}
+static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
+{
+        return 0x18U;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
+{
+        return 0x20U;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
+{
+        return 0x20U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 fb_mmu_invalidate_ack_s(void)
+{
+        return 2U;
+}
+static inline u32 fb_mmu_invalidate_ack_f(u32 v)
+{
+        return (v & 0x3U) << 7U;
+}
+static inline u32 fb_mmu_invalidate_ack_m(void)
+{
+        return 0x3U << 7U;
+}
+static inline u32 fb_mmu_invalidate_ack_v(u32 r)
+{
+        return (r >> 7U) & 0x3U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
+{
+        return 0x80U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
+{
+        return 6U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
+{
+        return (v & 0x3fU) << 9U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
+{
+        return 0x3fU << 9U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
+{
+        return (r >> 9U) & 0x3fU;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
+{
+        return 5U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
+{
+        return (v & 0x1fU) << 15U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
+{
+        return 0x1fU << 15U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
+{
+        return (r >> 15U) & 0x1fU;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
+{
+        return 3U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
+{
+        return 0x7U << 24U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
+{
+        return (r >> 24U) & 0x7U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
+{
+        return 0x5000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
+{
+        return 0x6000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
+{
+        return 0x7000000U;
+}
+static inline u32 fb_mmu_invalidate_trigger_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_debug_wr_r(void)
+{
+        return 0x00100cc8U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_s(void)
+{
+        return 2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_rd_r(void)
+{
+        return 0x00100cccU;
+}
+static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_rd_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_ctrl_r(void)
+{
+        return 0x00100cc4U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_vpr_info_r(void)
+{
+        return 0x00100cd0U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_priv_level_mask_r(void)
+{
+        return 0x00100cdcU;
+}
+static inline u32 fb_mmu_priv_level_mask_write_violation_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+        return 0x00100c10U;
+}
+static inline u32 fb_mmu_local_memory_range_r(void)
+{
+        return 0x00100ce0U;
+}
+static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r)
+{
+        return (r >> 4U) & 0x3fU;
+}
+static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fb_fbpa_fbio_delay_r(void)
+{
+        return 0x009a065cU;
+}
+static inline u32 fb_fbpa_fbio_delay_src_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 fb_fbpa_fbio_delay_src_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 fb_fbpa_fbio_delay_src_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 fb_fbpa_fbio_delay_src_max_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_m(void)
+{
+        return 0xfU << 4U;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 fb_fbpa_fbio_delay_priv_max_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_r(void)
+{
+        return 0x009a08e0U;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void)
+{
+        return 0xfU << 4U;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_niso_scrub_status_r(void)
+{
+        return 0x00100b20U;
+}
+static inline u32 fb_niso_scrub_status_flag_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fb_fbpa_fbio_iref_byte_rx_ctrl_r(void)
+{
+        return 0x009a0eb0U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fbpa_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fbpa_gp106.h
new file mode 100644
index 00000000..797a40c2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fbpa_gp106.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fbpa_gp106_h_
+#define _hw_fbpa_gp106_h_
+
+static inline u32 fbpa_cstatus_r(void)
+{
+        return 0x009a020cU;
+}
+static inline u32 fbpa_cstatus_ramamount_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffffU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h
new file mode 100644
index 00000000..804e9e4d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h
@@ -0,0 +1,695 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fifo_gp106_h_
+#define _hw_fifo_gp106_h_
+
+static inline u32 fifo_bar1_base_r(void)
+{
+        return 0x00002254U;
+}
+static inline u32 fifo_bar1_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_bar1_base_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_bar1_base_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_runlist_base_r(void)
+{
+        return 0x00002270U;
+}
+static inline u32 fifo_runlist_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_runlist_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 fifo_runlist_r(void)
+{
+        return 0x00002274U;
+}
+static inline u32 fifo_runlist_engine_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 fifo_eng_runlist_base_r(u32 i)
+{
+        return 0x00002280U + i*8U;
+}
+static inline u32 fifo_eng_runlist_base__size_1_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_eng_runlist_r(u32 i)
+{
+        return 0x00002284U + i*8U;
+}
+static inline u32 fifo_eng_runlist__size_1_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_eng_runlist_length_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 fifo_eng_runlist_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_pb_timeslice_r(u32 i)
+{
+        return 0x00002350U + i*4U;
+}
+static inline u32 fifo_pb_timeslice_timeout_16_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fifo_pb_timeslice_timescale_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_pb_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_pbdma_map_r(u32 i)
+{
+        return 0x00002390U + i*4U;
+}
+static inline u32 fifo_intr_0_r(void)
+{
+        return 0x00002100U;
+}
+static inline u32 fifo_intr_0_bind_error_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_bind_error_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_sched_error_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_sched_error_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_chsw_error_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_chsw_error_reset_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_lb_error_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_lb_error_reset_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_intr_0_runlist_event_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fifo_intr_0_channel_intr_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fifo_intr_en_0_r(void)
+{
+        return 0x00002140U;
+}
+static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 fifo_intr_en_1_r(void)
+{
+        return 0x00002528U;
+}
+static inline u32 fifo_intr_bind_error_r(void)
+{
+        return 0x0000252cU;
+}
+static inline u32 fifo_intr_sched_error_r(void)
+{
+        return 0x0000254cU;
+}
+static inline u32 fifo_intr_sched_error_code_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 fifo_intr_chsw_error_r(void)
+{
+        return 0x0000256cU;
+}
+static inline u32 fifo_intr_mmu_fault_id_r(void)
+{
+        return 0x0000259cU;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
+{
+        return 0x00002800U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
+{
+        return 0x00002804U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
+{
+        return 0x00002808U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
+{
+        return 0x0000280cU + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
+{
+        return (r >> 8U) & 0x7fU;
+}
+static inline u32 fifo_intr_pbdma_id_r(void)
+{
+        return 0x000025a0U;
+}
+static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 fifo_intr_runlist_r(void)
+{
+        return 0x00002a00U;
+}
+static inline u32 fifo_fb_timeout_r(void)
+{
+        return 0x00002a04U;
+}
+static inline u32 fifo_fb_timeout_period_m(void)
+{
+        return 0x3fffffffU << 0U;
+}
+static inline u32 fifo_fb_timeout_period_max_f(void)
+{
+        return 0x3fffffffU;
+}
+static inline u32 fifo_error_sched_disable_r(void)
+{
+        return 0x0000262cU;
+}
+static inline u32 fifo_sched_disable_r(void)
+{
+        return 0x00002630U;
+}
+static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_runlist_m(u32 i)
+{
+        return 0x1U << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_preempt_r(void)
+{
+        return 0x00002634U;
+}
+static inline u32 fifo_preempt_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_preempt_type_channel_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_preempt_type_tsg_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_preempt_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_preempt_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_trigger_mmu_fault_r(u32 i)
+{
+        return 0x00002a30U + i*4U;
+}
+static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_engine_status_r(u32 i)
+{
+        return 0x00002640U + i*8U;
+}
+static inline u32 fifo_engine_status__size_1_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 fifo_engine_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_engine_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_ctx_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_engine_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_engine_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_faulted_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fifo_engine_status_faulted_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_engine_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fifo_engine_status_engine_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_engine_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 fifo_pbdma_status_r(u32 i)
+{
+        return 0x00003080U + i*4U;
+}
+static inline u32 fifo_pbdma_status__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 fifo_pbdma_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_pbdma_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_chsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_r(void)
+{
+        return 0x00002a70U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_hi_r(void)
+{
+        return 0x00002a74U;
+}
+static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_size_r(void)
+{
+        return 0x00002a78U;
+}
+static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
+{
+        return (v & 0x3fffU) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
+{
+        return 0x00001200U;
+}
+static inline u32 fifo_replay_fault_buffer_get_r(void)
+{
+        return 0x00002a7cU;
+}
+static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
+{
+        return (v & 0x3fffU) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_put_r(void)
+{
+        return 0x00002a80U;
+}
+static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
+{
+        return (v & 0x3fffU) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_info_r(void)
+{
+        return 0x00002a84U;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_flush_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_flush_gp106.h
new file mode 100644
index 00000000..c4e1c32b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_flush_gp106.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_flush_gp106_h_
+#define _hw_flush_gp106_h_
+
+static inline u32 flush_l2_system_invalidate_r(void)
+{
+        return 0x00070004U;
+}
+static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_r(void)
+{
+        return 0x00070010U;
+}
+static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_r(void)
+{
+        return 0x0007000cU;
+}
+static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_r(void)
+{
+        return 0x00070000U;
+}
+static inline u32 flush_fb_flush_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_fb_flush_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
new file mode 100644
index 00000000..7d1fb075
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fuse_gp106_h_
+#define _hw_fuse_gp106_h_
+
+static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021c38U + i*4U;
+}
+static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021838U + i*4U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
+{
+        return 0x00021944U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
+{
+        return 0x00021948U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fuse_status_opt_fbio_r(void)
+{
+        return 0x00021c14U;
+}
+static inline u32 fuse_status_opt_fbio_data_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fuse_status_opt_fbio_data_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 fuse_status_opt_fbio_data_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
+{
+        return 0x00021d70U + i*4U;
+}
+static inline u32 fuse_status_opt_fbp_r(void)
+{
+        return 0x00021d38U;
+}
+static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fuse_vin_cal_fuse_rev_r(void)
+{
+        return 0x0002164cU;
+}
+static inline u32 fuse_vin_cal_fuse_rev_data_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fuse_vin_cal_gpc0_r(void)
+{
+        return 0x00021650U;
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_int_data_s(void)
+{
+        return 12U;
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_int_data_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_s(void)
+{
+        return 2U;
+}
+static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_v(u32 r)
+{
+        return (r >> 14U) & 0x3U;
+}
+static inline u32 fuse_vin_cal_gpc0_slope_int_data_s(void)
+{
+        return 4U;
+}
+static inline u32 fuse_vin_cal_gpc0_slope_int_data_v(u32 r)
+{
+        return (r >> 10U) & 0xfU;
+}
+static inline u32 fuse_vin_cal_gpc0_slope_frac_data_s(void)
+{
+        return 10U;
+}
+static inline u32 fuse_vin_cal_gpc0_slope_frac_data_v(u32 r)
+{
+        return (r >> 0U) & 0x3ffU;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_r(void)
+{
+        return 0x00021654U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_s(void)
+{
+        return 8U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_v(u32 r)
+{
+        return (r >> 14U) & 0xffU;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_s(void)
+{
+        return 2U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_v(u32 r)
+{
+        return (r >> 12U) & 0x3U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_s(void)
+{
+        return 1U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_v(u32 r)
+{
+        return (r >> 22U) & 0x1U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_s(void)
+{
+        return 1U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_v(u32 r)
+{
+        return (r >> 10U) & 0x1U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_s(void)
+{
+        return 10U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_v(u32 r)
+{
+        return (r >> 0U) & 0x3ffU;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_s(void)
+{
+        return 1U;
+}
+static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_v(u32 r)
+{
+        return (r >> 11U) & 0x1U;
+}
+static inline u32 fuse_vin_cal_gpc2_delta_r(void)
+{
+        return 0x00021658U;
+}
+static inline u32 fuse_vin_cal_gpc3_delta_r(void)
+{
+        return 0x0002165cU;
+}
+static inline u32 fuse_vin_cal_gpc4_delta_r(void)
+{
+        return 0x00021660U;
+}
+static inline u32 fuse_vin_cal_gpc5_delta_r(void)
+{
+        return 0x00021664U;
+}
+static inline u32 fuse_vin_cal_shared_delta_r(void)
+{
+        return 0x00021668U;
+}
+static inline u32 fuse_vin_cal_sram_delta_r(void)
+{
+        return 0x0002166cU;
+}
+static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_s(void)
+{
+        return 9U;
+}
+static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_v(u32 r)
+{
+        return (r >> 13U) & 0x1ffU;
+}
+static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_s(void)
+{
+        return 1U;
+}
+static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gc6_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gc6_gp106.h
new file mode 100644
index 00000000..91e9d7b3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gc6_gp106.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gc6_gp106_h_
+#define _hw_gc6_gp106_h_
+static inline u32 gc6_sci_strap_r(void)
+{
+        return 0x00010ebb0;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h
new file mode 100644
index 00000000..510dd5f2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h
@@ -0,0 +1,1275 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gmmu_gp106_h_
+#define _hw_gmmu_gp106_h_
+
+static inline u32 gmmu_new_pde_is_pte_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_is_pte_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_aperture_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_aperture_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_pde_address_sys_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_pde_address_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_vol_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_vol_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_pde_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_new_pde__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_dual_pde_is_pte_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_dual_pde__size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gmmu_new_pte__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_pte_valid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_valid_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_new_pte_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_privilege_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_privilege_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gmmu_new_pte_privilege_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_address_sys_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_pte_address_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_address_vid_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_pte_address_vid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_vol_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_vol_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_pte_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_aperture_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_pte_read_only_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_read_only_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gmmu_new_pte_comptagline_f(u32 v)
+{
+        return (v & 0x3ffffU) << 4U;
+}
+static inline u32 gmmu_new_pte_comptagline_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_new_pte_kind_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gmmu_new_pte_kind_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_new_pte_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_f(u32 v)
+{
+        return (v & 0xffU) << 4U;
+}
+static inline u32 gmmu_pte_kind_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_kind_invalid_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 gmmu_pte_kind_pitch_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gmmu_pte_kind_z16_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gmmu_pte_kind_z16_2c_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 gmmu_pte_kind_z16_2z_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 gmmu_pte_kind_z16_2cz_v(void)
+{
+        return 0x00000036U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
+{
+        return 0x00000037U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
+{
+        return 0x00000038U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
+{
+        return 0x00000039U;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
+{
+        return 0x0000005fU;
+}
+static inline u32 gmmu_pte_kind_z16_4cz_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gmmu_pte_kind_s8z24_v(void)
+{
+        return 0x00000011U;
+}
+static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
+{
+        return 0x00000012U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
+{
+        return 0x00000013U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
+{
+        return 0x00000014U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
+{
+        return 0x00000017U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
+{
+        return 0x00000019U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
+{
+        return 0x0000001aU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
+{
+        return 0x0000001bU;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
+{
+        return 0x0000001dU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
+{
+        return 0x0000001eU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
+{
+        return 0x0000001fU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
+{
+        return 0x00000021U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
+{
+        return 0x00000022U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
+{
+        return 0x00000023U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
+{
+        return 0x00000024U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
+{
+        return 0x00000026U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
+{
+        return 0x00000027U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
+{
+        return 0x00000029U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
+{
+        return 0x0000002eU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
+{
+        return 0x0000002fU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
+{
+        return 0x00000033U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
+{
+        return 0x00000034U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
+{
+        return 0x00000035U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
+{
+        return 0x0000003aU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
+{
+        return 0x0000003bU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
+{
+        return 0x0000003dU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
+{
+        return 0x0000003eU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
+{
+        return 0x0000003fU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
+{
+        return 0x00000041U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000042U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000043U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000044U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
+{
+        return 0x00000045U;
+}
+static inline u32 gmmu_pte_kind_z24s8_v(void)
+{
+        return 0x00000046U;
+}
+static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
+{
+        return 0x00000047U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
+{
+        return 0x00000048U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
+{
+        return 0x00000049U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
+{
+        return 0x0000004aU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
+{
+        return 0x0000004bU;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
+{
+        return 0x0000004dU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
+{
+        return 0x0000004eU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
+{
+        return 0x0000004fU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
+{
+        return 0x00000050U;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
+{
+        return 0x00000051U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
+{
+        return 0x00000052U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
+{
+        return 0x00000053U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
+{
+        return 0x00000054U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
+{
+        return 0x00000055U;
+}
+static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
+{
+        return 0x00000056U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
+{
+        return 0x00000057U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
+{
+        return 0x00000058U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
+{
+        return 0x00000059U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
+{
+        return 0x0000005aU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
+{
+        return 0x0000005bU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
+{
+        return 0x0000005cU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
+{
+        return 0x0000005dU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
+{
+        return 0x0000005eU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000063U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000064U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000065U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
+{
+        return 0x00000066U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
+{
+        return 0x00000067U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
+{
+        return 0x00000068U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
+{
+        return 0x00000069U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
+{
+        return 0x0000006aU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
+{
+        return 0x0000006fU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
+{
+        return 0x00000070U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
+{
+        return 0x00000071U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
+{
+        return 0x00000072U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
+{
+        return 0x00000073U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
+{
+        return 0x00000074U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
+{
+        return 0x00000075U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
+{
+        return 0x00000076U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000077U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000078U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000079U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
+{
+        return 0x0000007aU;
+}
+static inline u32 gmmu_pte_kind_zf32_v(void)
+{
+        return 0x0000007bU;
+}
+static inline u32 gmmu_pte_kind_zf32_1z_v(void)
+{
+        return 0x0000007cU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
+{
+        return 0x0000007dU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
+{
+        return 0x0000007eU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
+{
+        return 0x0000007fU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
+{
+        return 0x00000081U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
+{
+        return 0x00000082U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
+{
+        return 0x00000083U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
+{
+        return 0x00000084U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
+{
+        return 0x00000085U;
+}
+static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
+{
+        return 0x00000086U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
+{
+        return 0x00000087U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
+{
+        return 0x00000088U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
+{
+        return 0x00000089U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
+{
+        return 0x0000008aU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x0000008bU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x0000008cU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x0000008dU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x0000008eU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x0000008fU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x00000090U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x00000091U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x00000092U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000097U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000098U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000099U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x0000009aU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x0000009bU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x0000009cU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x0000009dU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x0000009eU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x0000009fU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000a1U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000a2U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000a3U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000a5U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000a6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x000000a7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x000000a9U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x000000aaU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x000000abU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x000000acU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x000000adU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x000000aeU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x000000b3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x000000b4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x000000b5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x000000b6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x000000b7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x000000b8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x000000b9U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x000000baU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x000000bbU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000bcU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000bdU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000beU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000bfU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000c1U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000c2U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
+{
+        return 0x000000c3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
+{
+        return 0x000000c4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
+{
+        return 0x000000c5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
+{
+        return 0x000000c6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
+{
+        return 0x000000c7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
+{
+        return 0x000000c8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
+{
+        return 0x000000ceU;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
+{
+        return 0x000000cfU;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
+{
+        return 0x000000d0U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
+{
+        return 0x000000d1U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
+{
+        return 0x000000d2U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
+{
+        return 0x000000d3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
+{
+        return 0x000000d4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
+{
+        return 0x000000d5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
+{
+        return 0x000000d6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
+{
+        return 0x000000d7U;
+}
+static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
+{
+        return 0x000000feU;
+}
+static inline u32 gmmu_pte_kind_c32_2c_v(void)
+{
+        return 0x000000d8U;
+}
+static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
+{
+        return 0x000000d9U;
+}
+static inline u32 gmmu_pte_kind_c32_2cba_v(void)
+{
+        return 0x000000daU;
+}
+static inline u32 gmmu_pte_kind_c32_2cra_v(void)
+{
+        return 0x000000dbU;
+}
+static inline u32 gmmu_pte_kind_c32_2bra_v(void)
+{
+        return 0x000000dcU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
+{
+        return 0x000000ddU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
+{
+        return 0x000000deU;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
+{
+        return 0x000000dfU;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
+{
+        return 0x000000e0U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
+{
+        return 0x000000e1U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
+{
+        return 0x000000e2U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
+{
+        return 0x000000e3U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
+{
+        return 0x0000002cU;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
+{
+        return 0x000000e4U;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
+{
+        return 0x000000e5U;
+}
+static inline u32 gmmu_pte_kind_c64_2c_v(void)
+{
+        return 0x000000e6U;
+}
+static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
+{
+        return 0x000000e7U;
+}
+static inline u32 gmmu_pte_kind_c64_2cba_v(void)
+{
+        return 0x000000e8U;
+}
+static inline u32 gmmu_pte_kind_c64_2cra_v(void)
+{
+        return 0x000000e9U;
+}
+static inline u32 gmmu_pte_kind_c64_2bra_v(void)
+{
+        return 0x000000eaU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
+{
+        return 0x000000ebU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
+{
+        return 0x000000edU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
+{
+        return 0x000000eeU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
+{
+        return 0x000000efU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
+{
+        return 0x000000f0U;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
+{
+        return 0x000000f1U;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
+{
+        return 0x0000002dU;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
+{
+        return 0x000000f2U;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
+{
+        return 0x000000f3U;
+}
+static inline u32 gmmu_pte_kind_c128_2c_v(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 gmmu_pte_kind_c128_2cr_v(void)
+{
+        return 0x000000f5U;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
+{
+        return 0x000000f6U;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
+{
+        return 0x000000f7U;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
+{
+        return 0x000000f9U;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
+{
+        return 0x000000faU;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
+{
+        return 0x000000fbU;
+}
+static inline u32 gmmu_pte_kind_x8c24_v(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
+{
+        return 0x000000fdU;
+}
+static inline u32 gmmu_pte_kind_smsked_message_v(void)
+{
+        return 0x000000caU;
+}
+static inline u32 gmmu_pte_kind_smhost_message_v(void)
+{
+        return 0x000000cbU;
+}
+static inline u32 gmmu_pte_kind_s8_v(void)
+{
+        return 0x0000002aU;
+}
+static inline u32 gmmu_pte_kind_s8_2s_v(void)
+{
+        return 0x0000002bU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
new file mode 100644
index 00000000..2da3ec41
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
@@ -0,0 +1,4111 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gr_gp106_h_
+#define _hw_gr_gp106_h_
+
+static inline u32 gr_intr_r(void)
+{
+        return 0x00400100U;
+}
+static inline u32 gr_intr_notify_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_notify_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_semaphore_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_semaphore_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_illegal_method_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_method_reset_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_notify_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_illegal_notify_reset_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 gr_intr_firmware_method_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_firmware_method_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_illegal_class_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_illegal_class_reset_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_fecs_error_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_fecs_error_reset_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_class_error_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_class_error_reset_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_exception_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_intr_exception_reset_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_fecs_intr_r(void)
+{
+        return 0x00400144U;
+}
+static inline u32 gr_class_error_r(void)
+{
+        return 0x00400110U;
+}
+static inline u32 gr_class_error_code_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_intr_nonstall_r(void)
+{
+        return 0x00400120U;
+}
+static inline u32 gr_intr_nonstall_trap_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_en_r(void)
+{
+        return 0x0040013cU;
+}
+static inline u32 gr_exception_r(void)
+{
+        return 0x00400108U;
+}
+static inline u32 gr_exception_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception_gpc_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 gr_exception_memfmt_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_exception_ds_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_exception1_r(void)
+{
+        return 0x00400118U;
+}
+static inline u32 gr_exception1_gpc_0_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_exception2_r(void)
+{
+        return 0x0040011cU;
+}
+static inline u32 gr_exception_en_r(void)
+{
+        return 0x00400138U;
+}
+static inline u32 gr_exception_en_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception1_en_r(void)
+{
+        return 0x00400130U;
+}
+static inline u32 gr_exception2_en_r(void)
+{
+        return 0x00400134U;
+}
+static inline u32 gr_gpfifo_ctl_r(void)
+{
+        return 0x00400500U;
+}
+static inline u32 gr_gpfifo_ctl_access_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpfifo_status_r(void)
+{
+        return 0x00400504U;
+}
+static inline u32 gr_trapped_addr_r(void)
+{
+        return 0x00400704U;
+}
+static inline u32 gr_trapped_addr_mthd_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 gr_trapped_addr_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_datahigh_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_priv_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_status_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_trapped_data_lo_r(void)
+{
+        return 0x00400708U;
+}
+static inline u32 gr_trapped_data_hi_r(void)
+{
+        return 0x0040070cU;
+}
+static inline u32 gr_trapped_data_mme_r(void)
+{
+        return 0x00400710U;
+}
+static inline u32 gr_trapped_data_mme_pc_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_status_r(void)
+{
+        return 0x00400700U;
+}
+static inline u32 gr_status_fe_method_upper_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_status_fe_gi_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 gr_status_mask_r(void)
+{
+        return 0x00400610U;
+}
+static inline u32 gr_status_1_r(void)
+{
+        return 0x00400604U;
+}
+static inline u32 gr_status_2_r(void)
+{
+        return 0x00400608U;
+}
+static inline u32 gr_engine_status_r(void)
+{
+        return 0x0040060cU;
+}
+static inline u32 gr_engine_status_value_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+        return 0x00410204U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+        return 0x00410208U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+        return 0x00502c94U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_activity_0_r(void)
+{
+        return 0x00400380U;
+}
+static inline u32 gr_activity_1_r(void)
+{
+        return 0x00400384U;
+}
+static inline u32 gr_activity_2_r(void)
+{
+        return 0x00400388U;
+}
+static inline u32 gr_activity_4_r(void)
+{
+        return 0x00400390U;
+}
+static inline u32 gr_activity_4_gpc0_s(void)
+{
+        return 3U;
+}
+static inline u32 gr_activity_4_gpc0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_activity_4_gpc0_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 gr_activity_4_gpc0_v(u32 r)
+{
+        return (r >> 0U) & 0x7U;
+}
+static inline u32 gr_activity_4_gpc0_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_activity_4_gpc0_preempted_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
+{
+        return 0x00501000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
+{
+        return 0x00419000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
+{
+        return 0x005046a4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
+{
+        return 0x00419ea4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_pri_sked_activity_r(void)
+{
+        return 0x00407054U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
+{
+        return 0x00502c80U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
+{
+        return 0x00502c84U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
+{
+        return 0x00502c88U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
+{
+        return 0x00502c8cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504500U;
+}
+static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504d00U;
+}
+static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00501d00U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
+{
+        return 0x0041ac80U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
+{
+        return 0x0041ac84U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
+{
+        return 0x0041ac88U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
+{
+        return 0x0041ac8cU;
+}
+static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041c500U;
+}
+static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041cd00U;
+}
+static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00419d00U;
+}
+static inline u32 gr_pri_be0_becs_be_activity0_r(void)
+{
+        return 0x00410200U;
+}
+static inline u32 gr_pri_be1_becs_be_activity0_r(void)
+{
+        return 0x00410600U;
+}
+static inline u32 gr_pri_bes_becs_be_activity0_r(void)
+{
+        return 0x00408a00U;
+}
+static inline u32 gr_pri_ds_mpipe_status_r(void)
+{
+        return 0x00405858U;
+}
+static inline u32 gr_pri_fe_go_idle_info_r(void)
+{
+        return 0x00404194U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
+{
+        return 0x00504238U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
+{
+        return 0x005046b8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
+{
+        return 0x005044a0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
+{
+        return 0x005046bcU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
+{
+        return 0x005046c0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
+{
+        return 0x005044a4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
+{
+        return 0x005042c4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_pri_be0_crop_status1_r(void)
+{
+        return 0x00410134U;
+}
+static inline u32 gr_pri_bes_crop_status1_r(void)
+{
+        return 0x00408934U;
+}
+static inline u32 gr_pri_be0_zrop_status_r(void)
+{
+        return 0x00410048U;
+}
+static inline u32 gr_pri_be0_zrop_status2_r(void)
+{
+        return 0x0041004cU;
+}
+static inline u32 gr_pri_bes_zrop_status_r(void)
+{
+        return 0x00408848U;
+}
+static inline u32 gr_pri_bes_zrop_status2_r(void)
+{
+        return 0x0040884cU;
+}
+static inline u32 gr_pipe_bundle_address_r(void)
+{
+        return 0x00400200U;
+}
+static inline u32 gr_pipe_bundle_address_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pipe_bundle_data_r(void)
+{
+        return 0x00400204U;
+}
+static inline u32 gr_pipe_bundle_config_r(void)
+{
+        return 0x00400208U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_hww_esr_r(void)
+{
+        return 0x00404000U;
+}
+static inline u32 gr_fe_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_fe_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_go_idle_timeout_r(void)
+{
+        return 0x00404154U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
+{
+        return 0x1800U;
+}
+static inline u32 gr_fe_object_table_r(u32 i)
+{
+        return 0x00404200U + i*4U;
+}
+static inline u32 gr_fe_object_table_nvclass_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_fe_tpc_fs_r(void)
+{
+        return 0x004041c4U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_r(void)
+{
+        return 0x00404488U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pri_mme_shadow_raw_data_r(void)
+{
+        return 0x0040448cU;
+}
+static inline u32 gr_mme_hww_esr_r(void)
+{
+        return 0x00404490U;
+}
+static inline u32 gr_mme_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_mme_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_memfmt_hww_esr_r(void)
+{
+        return 0x00404600U;
+}
+static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fecs_cpuctl_r(void)
+{
+        return 0x00409100U;
+}
+static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_cpuctl_alias_r(void)
+{
+        return 0x00409130U;
+}
+static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_dmactl_r(void)
+{
+        return 0x0040910cU;
+}
+static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_fecs_os_r(void)
+{
+        return 0x00409080U;
+}
+static inline u32 gr_fecs_idlestate_r(void)
+{
+        return 0x0040904cU;
+}
+static inline u32 gr_fecs_mailbox0_r(void)
+{
+        return 0x00409040U;
+}
+static inline u32 gr_fecs_mailbox1_r(void)
+{
+        return 0x00409044U;
+}
+static inline u32 gr_fecs_irqstat_r(void)
+{
+        return 0x00409008U;
+}
+static inline u32 gr_fecs_irqmode_r(void)
+{
+        return 0x0040900cU;
+}
+static inline u32 gr_fecs_irqmask_r(void)
+{
+        return 0x00409018U;
+}
+static inline u32 gr_fecs_irqdest_r(void)
+{
+        return 0x0040901cU;
+}
+static inline u32 gr_fecs_curctx_r(void)
+{
+        return 0x00409050U;
+}
+static inline u32 gr_fecs_nxtctx_r(void)
+{
+        return 0x00409054U;
+}
+static inline u32 gr_fecs_engctl_r(void)
+{
+        return 0x004090a4U;
+}
+static inline u32 gr_fecs_debug1_r(void)
+{
+        return 0x00409090U;
+}
+static inline u32 gr_fecs_debuginfo_r(void)
+{
+        return 0x00409094U;
+}
+static inline u32 gr_fecs_icd_cmd_r(void)
+{
+        return 0x00409200U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 gr_fecs_icd_rdata_r(void)
+{
+        return 0x0040920cU;
+}
+static inline u32 gr_fecs_imemc_r(u32 i)
+{
+        return 0x00409180U + i*16U;
+}
+static inline u32 gr_fecs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_imemd_r(u32 i)
+{
+        return 0x00409184U + i*16U;
+}
+static inline u32 gr_fecs_imemt_r(u32 i)
+{
+        return 0x00409188U + i*16U;
+}
+static inline u32 gr_fecs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_dmemc_r(u32 i)
+{
+        return 0x004091c0U + i*8U;
+}
+static inline u32 gr_fecs_dmemc_offs_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_v(u32 r)
+{
+        return (r >> 2U) & 0x3fU;
+}
+static inline u32 gr_fecs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_dmemd_r(u32 i)
+{
+        return 0x004091c4U + i*8U;
+}
+static inline u32 gr_fecs_dmatrfbase_r(void)
+{
+        return 0x00409110U;
+}
+static inline u32 gr_fecs_dmatrfmoffs_r(void)
+{
+        return 0x00409114U;
+}
+static inline u32 gr_fecs_dmatrffboffs_r(void)
+{
+        return 0x0040911cU;
+}
+static inline u32 gr_fecs_dmatrfcmd_r(void)
+{
+        return 0x00409118U;
+}
+static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_fecs_bootvec_r(void)
+{
+        return 0x00409104U;
+}
+static inline u32 gr_fecs_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_falcon_hwcfg_r(void)
+{
+        return 0x00409108U;
+}
+static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
+{
+        return 0x0041a108U;
+}
+static inline u32 gr_fecs_falcon_rm_r(void)
+{
+        return 0x00409084U;
+}
+static inline u32 gr_fecs_current_ctx_r(void)
+{
+        return 0x00409b00U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_current_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_current_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_current_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_method_data_r(void)
+{
+        return 0x00409500U;
+}
+static inline u32 gr_fecs_method_push_r(void)
+{
+        return 0x00409504U;
+}
+static inline u32 gr_fecs_method_push_adr_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
+{
+        return 0x00000038U;
+}
+static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
+{
+        return 0x00000039U;
+}
+static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
+{
+        return 0x21U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
+{
+        return 0x0000001aU;
+}
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_fecs_host_int_status_r(void)
+{
+        return 0x00409c18U;
+}
+static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 gr_fecs_host_int_clear_r(void)
+{
+        return 0x00409c20U;
+}
+static inline u32 gr_fecs_host_int_enable_r(void)
+{
+        return 0x00409c24U;
+}
+static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
+{
+        return 0x00409614U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
+{
+        return (r >> 10U) & 0x1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
+{
+        return 0x0040960cU;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x00409800U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
+{
+        return 0x004098c0U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
+{
+        return 0x00409840U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_fs_r(void)
+{
+        return 0x00409604U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_m(void)
+{
+        return 0x1fU << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_fecs_cfg_r(void)
+{
+        return 0x00409620U;
+}
+static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_fecs_rc_lanes_r(void)
+{
+        return 0x00409880U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_fecs_ctxsw_status_1_r(void)
+{
+        return 0x00409400U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_adr_r(void)
+{
+        return 0x00409a24U;
+}
+static inline u32 gr_fecs_new_ctx_r(void)
+{
+        return 0x00409b04U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_new_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_new_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_new_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_r(void)
+{
+        return 0x00409a0cU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_r(void)
+{
+        return 0x00409a10U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
+{
+        return 0x00409c00U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
+{
+        return 0x00502c04U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
+{
+        return 0x00502400U;
+}
+static inline u32 gr_fecs_ctxsw_idlestate_r(void)
+{
+        return 0x00409420U;
+}
+static inline u32 gr_fecs_feature_override_ecc_r(void)
+{
+        return 0x00409658U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
+{
+        return 0x00502420U;
+}
+static inline u32 gr_rstr2d_gpc_map0_r(void)
+{
+        return 0x0040780cU;
+}
+static inline u32 gr_rstr2d_gpc_map1_r(void)
+{
+        return 0x00407810U;
+}
+static inline u32 gr_rstr2d_gpc_map2_r(void)
+{
+        return 0x00407814U;
+}
+static inline u32 gr_rstr2d_gpc_map3_r(void)
+{
+        return 0x00407818U;
+}
+static inline u32 gr_rstr2d_gpc_map4_r(void)
+{
+        return 0x0040781cU;
+}
+static inline u32 gr_rstr2d_gpc_map5_r(void)
+{
+        return 0x00407820U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_r(void)
+{
+        return 0x004078bcU;
+}
+static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_hww_esr_r(void)
+{
+        return 0x00406018U;
+}
+static inline u32 gr_pd_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_pd_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00406028U + i*4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
+{
+        return (v & 0xfU) << 12U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
+{
+        return (v & 0xfU) << 24U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
+{
+        return (v & 0xfU) << 28U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_r(void)
+{
+        return 0x004064c0U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_r(void)
+{
+        return 0x004064c4U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
+{
+        return 0xffffU;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_r(void)
+{
+        return 0x004064c8U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
+{
+        return (v & 0x1fffU) << 0U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
+{
+        return 0x00000900U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
+{
+        return (v & 0x1fffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
+{
+        return 0x00000900U;
+}
+static inline u32 gr_pd_dist_skip_table_r(u32 i)
+{
+        return 0x004064d0U + i*4U;
+}
+static inline u32 gr_pd_dist_skip_table__size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gr_ds_debug_r(void)
+{
+        return 0x00405800U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 gr_ds_zbc_color_r_r(void)
+{
+        return 0x00405804U;
+}
+static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_g_r(void)
+{
+        return 0x00405808U;
+}
+static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_b_r(void)
+{
+        return 0x0040580cU;
+}
+static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_a_r(void)
+{
+        return 0x00405810U;
+}
+static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_r(void)
+{
+        return 0x00405814U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
+{
+        return (v & 0x7fU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gr_ds_zbc_z_r(void)
+{
+        return 0x00405818U;
+}
+static inline u32 gr_ds_zbc_z_val_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_ds_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_ds_zbc_z_val__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_ds_zbc_z_val__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_r(void)
+{
+        return 0x0040581cU;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_tbl_index_r(void)
+{
+        return 0x00405820U;
+}
+static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_r(void)
+{
+        return 0x00405824U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
+{
+        return 0x00405830U;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
+{
+        return 0x0040585cU;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_ds_hww_esr_r(void)
+{
+        return 0x00405840U;
+}
+static inline u32 gr_ds_hww_esr_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_esr_2_r(void)
+{
+        return 0x00405848U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_report_mask_r(void)
+{
+        return 0x00405844U;
+}
+static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_ds_hww_report_mask_2_r(void)
+{
+        return 0x0040584cU;
+}
+static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00405870U + i*4U;
+}
+static inline u32 gr_scc_bundle_cb_base_r(void)
+{
+        return 0x00408004U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_bundle_cb_size_r(void)
+{
+        return 0x00408008U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_pagepool_base_r(void)
+{
+        return 0x0040800cU;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_pagepool_r(void)
+{
+        return 0x00408010U;
+}
+static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
+{
+        return 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
+{
+        return 0x3ffU << 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
+{
+        return (r >> 10U) & 0x3ffU;
+}
+static inline u32 gr_scc_pagepool_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_init_r(void)
+{
+        return 0x0040802cU;
+}
+static inline u32 gr_scc_init_ram_trigger_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_scc_hww_esr_r(void)
+{
+        return 0x00408030U;
+}
+static inline u32 gr_scc_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_scc_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_sked_hww_esr_r(void)
+{
+        return 0x00407020U;
+}
+static inline u32 gr_sked_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_cwd_fs_r(void)
+{
+        return 0x00405b00U;
+}
+static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
+{
+        return 0x00405b60U + i*4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_cwd_sm_id_r(u32 i)
+{
+        return 0x00405ba0U + i*4U;
+}
+static inline u32 gr_cwd_sm_id__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpc0_fs_gpc_r(void)
+{
+        return 0x00502608U;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_gpc0_cfg_r(void)
+{
+        return 0x00502620U;
+}
+static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpccs_rc_lanes_r(void)
+{
+        return 0x00502880U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_rc_lane_size_r(void)
+{
+        return 0x00502910U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_s(void)
+{
+        return 24U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_zcull_fs_r(void)
+{
+        return 0x00500910U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_r(void)
+{
+        return 0x00500914U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
+{
+        return 0x00500918U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
+{
+        return 0x00800000U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
+{
+        return 0x00500920U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
+{
+        return 0x00500a04U + i*32U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
+{
+        return 0x00500c10U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
+{
+        return 0x00500c30U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
+{
+        return 0x00504088U;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
+{
+        return 0x00504698U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
+{
+        return 0x0050469cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
+{
+        return (r >> 8U) & 0xfffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
+{
+        return (r >> 20U) & 0xfffU;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
+{
+        return 0x00503018U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
+{
+        return 0x005030c0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
+{
+        return 0x3fffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
+{
+        return 0x00000320U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
+{
+        return 0x00000ba8U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
+{
+        return 0x005030f4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
+{
+        return 0x005030e4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
+{
+        return 0x005030f8U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
+{
+        return 0x005030f0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
+{
+        return 0x00000320U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
+{
+        return 0x00419b00U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
+{
+        return 0x00419b04U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
+{
+        return 21U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
+{
+        return (v & 0x1fffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
+{
+        return 0x1fffffU << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
+{
+        return (r >> 0U) & 0x1fffffU;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_r(void)
+{
+        return 0x0041a0acU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
+{
+        return (r >> 6U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_s(void)
+{
+        return 12U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_m(void)
+{
+        return 0xfffU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_gpccs_cpuctl_r(void)
+{
+        return 0x0041a100U;
+}
+static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_gpccs_dmactl_r(void)
+{
+        return 0x0041a10cU;
+}
+static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpccs_imemc_r(u32 i)
+{
+        return 0x0041a180U + i*16U;
+}
+static inline u32 gr_gpccs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_imemd_r(u32 i)
+{
+        return 0x0041a184U + i*16U;
+}
+static inline u32 gr_gpccs_imemt_r(u32 i)
+{
+        return 0x0041a188U + i*16U;
+}
+static inline u32 gr_gpccs_imemt__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_gpccs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpccs_dmemc_r(u32 i)
+{
+        return 0x0041a1c0U + i*8U;
+}
+static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_dmemd_r(u32 i)
+{
+        return 0x0041a1c4U + i*8U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x0041a800U + i*4U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
+{
+        return 0x00418e24U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
+{
+        return 0x00418e28U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
+{
+        return 11U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
+{
+        return 0x7ffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
+{
+        return (r >> 0U) & 0x7ffU;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
+{
+        return 0x30U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
+{
+        return 0x005001dcU;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
+{
+        return 0x00000de0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
+{
+        return 0x005001d8U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
+{
+        return 0x004181e4U;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
+{
+        return 0x0041befcU;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
+{
+        return 0x00418ea0U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
+{
+        return 0x3fffffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
+{
+        return 0x00418010U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
+{
+        return 0x0041804cU + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
+{
+        return 0x00418088U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
+{
+        return 0x004180c4U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
+{
+        return 0x00500100U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
+{
+        return 0x00418110U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
+{
+        return 0x0050014cU;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
+{
+        return 0x00418810U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_crstr_gpc_map0_r(void)
+{
+        return 0x00418b08U;
+}
+static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map1_r(void)
+{
+        return 0x00418b0cU;
+}
+static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map2_r(void)
+{
+        return 0x00418b10U;
+}
+static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map3_r(void)
+{
+        return 0x00418b14U;
+}
+static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map4_r(void)
+{
+        return 0x00418b18U;
+}
+static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map5_r(void)
+{
+        return 0x00418b1cU;
+}
+static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_map_table_cfg_r(void)
+{
+        return 0x00418bb8U;
+}
+static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
+{
+        return 0x00418980U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
+{
+        return 0x00418984U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
+{
+        return 0x00418988U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
+{
+        return 3U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
+{
+        return 0x7U << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
+{
+        return (r >> 28U) & 0x7U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
+{
+        return 0x0041898cU;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
+{
+        return 0x00418c6cU;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
+{
+        return 0x00419004U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_r(void)
+{
+        return 0x00419008U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
+{
+        return 0x0041980cU;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
+{
+        return 0x00419848U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
+{
+        return 0x00419c00U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
+{
+        return 0x00419c2cU;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00419e44U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00504644U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x00419e4cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x0050464cU;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
+{
+        return 0x00419d0cU;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
+{
+        return 0x0041ac94U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
+{
+        return 0x00504610U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
+{
+        return 0x00504614U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
+{
+        return 0x00504618U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00504624U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
+{
+        return 0x00504628U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
+{
+        return 0x00504634U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
+{
+        return 0x00504638U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00419e24U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_warp_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_sm_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
+{
+        return 0x0050460cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
+{
+        return 0x00419e50U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
+{
+        return 0x00504650U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
+{
+        return 0x00504224U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
+{
+        return 0x00504648U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
+{
+        return 0x00504770U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
+{
+        return 0x00419f70U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
+{
+        return 0x0050477cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
+{
+        return 0x00419f7cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
+{
+        return 0x0041be08U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
+{
+        return 0x0041bf00U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
+{
+        return 0x0041bf04U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
+{
+        return 0x0041bf08U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
+{
+        return 0x0041bf0cU;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
+{
+        return 0x0041bf10U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
+{
+        return 0x0041bf14U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
+{
+        return 0x0041bfd0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
+{
+        return (v & 0x7U) << 21U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 24U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
+{
+        return 0x0041bfd4U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
+{
+        return 0x0041bfe4U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 5U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 10U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 15U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 20U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 25U;
+}
+static inline u32 gr_bes_zrop_settings_r(void)
+{
+        return 0x00408850U;
+}
+static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_be0_crop_debug3_r(void)
+{
+        return 0x00410108U;
+}
+static inline u32 gr_bes_crop_debug3_r(void)
+{
+        return 0x00408908U;
+}
+static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_bes_crop_settings_r(void)
+{
+        return 0x00408958U;
+}
+static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gr_zcull_subregion_qty_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
+{
+        return 0x00504604U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
+{
+        return 0x00504608U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
+{
+        return 0x0050465cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
+{
+        return 0x00504660U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
+{
+        return 0x00504664U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
+{
+        return 0x00504668U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
+{
+        return 0x0050466cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
+{
+        return 0x00504658U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
+{
+        return 0x00504730U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
+{
+        return 0x00504734U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
+{
+        return 0x00504738U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
+{
+        return 0x0050473cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
+{
+        return 0x00504740U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
+{
+        return 0x00504744U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
+{
+        return 0x00504748U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
+{
+        return 0x0050474cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
+{
+        return 0x00504678U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
+{
+        return 0x00504694U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
+{
+        return 0x005046f0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
+{
+        return 0x00504700U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
+{
+        return 0x005046f4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
+{
+        return 0x00504704U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
+{
+        return 0x005046f8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
+{
+        return 0x00504708U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
+{
+        return 0x005046fcU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
+{
+        return 0x0050470cU;
+}
+static inline u32 gr_fe_pwr_mode_r(void)
+{
+        return 0x00404170U;
+}
+static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fe_pwr_mode_req_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_fe_pwr_mode_req_send_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fe_pwr_mode_req_done_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
+{
+        return 0x00418880U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
+{
+        return 0x3U << 3U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
+{
+        return 0x3U << 5U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
+{
+        return 0x00418890U;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
+{
+        return 0x00418894U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
+{
+        return 0x004188b0U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
+{
+        return 0x004188b4U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
+{
+        return 0x004188b8U;
+}
+static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
+{
+        return 0x004188acU;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
+{
+        return 0x00419e10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
+{
+        return 0x004041c0U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
+{
+        return 0x00419c84U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
+{
+        return 0x7U << 8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
+{
+        return 0x00419f78U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
+{
+        return 0x3U << 11U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_gpcs_tc_debug0_r(void)
+{
+        return 0x00418708U;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
+{
+        return 0x1ffU << 0U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h
new file mode 100644
index 00000000..e4e87aa8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h
@@ -0,0 +1,559 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ltc_gp106_h_
+#define _hw_ltc_gp106_h_
+
+static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+        return 0x00140518U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+        return 0x0017e318U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
+{
+        return 0x00140494U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
+{
+        return (r >> 16U) & 0x3U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
+{
+        return 0x0017e26cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
+{
+        return 0x0017e270U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
+{
+        return (v & 0x3ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
+{
+        return 0x0017e274U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
+{
+        return (v & 0x3ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
+{
+        return 0x0003ffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
+{
+        return 0x0017e278U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
+{
+        return (r >> 0U) & 0x3ffffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
+{
+        return 0x0017e27cU;
+}
+static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
+{
+        return 0x0017e000U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
+{
+        return 0x0017e280U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
+{
+        return (r >> 28U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
+{
+        return 0x0017e3f4U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
+{
+        return 0x0017e2acU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
+{
+        return 0x0017e338U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
+{
+        return 0x0017e33cU + i*4U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
+{
+        return 0x0017e34cU;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
+{
+        return 32U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
+{
+        return 0x0017e2b0U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
+{
+        return 0x0017e214U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
+{
+        return 0x00140214U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
+{
+        return 0x00142214U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+        return 0x0017e20cU;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+        return 0x0014040cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
+{
+        return 0x0014051cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x0017e2a0U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x0017e2a4U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001402a0U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001402a4U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001422a0U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001422a4U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
+{
+        return 0x0014058cU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h
new file mode 100644
index 00000000..349e2d7f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_mc_gp106_h_
+#define _hw_mc_gp106_h_
+
+static inline u32 mc_boot_0_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_boot_0_architecture_v(u32 r)
+{
+        return (r >> 24U) & 0x1fU;
+}
+static inline u32 mc_boot_0_implementation_v(u32 r)
+{
+        return (r >> 20U) & 0xfU;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 mc_intr_r(u32 i)
+{
+        return 0x00000100U + i*4U;
+}
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_intr_replayable_fault_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 mc_intr_pgraph_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_ltc_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 mc_intr_priv_ring_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 mc_intr_pbus_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_intr_en_r(u32 i)
+{
+        return 0x00000140U + i*4U;
+}
+static inline u32 mc_intr_en_set_r(u32 i)
+{
+        return 0x00000160U + i*4U;
+}
+static inline u32 mc_intr_en_clear_r(u32 i)
+{
+        return 0x00000180U + i*4U;
+}
+static inline u32 mc_enable_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 mc_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_enable_l2_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 mc_enable_pmedia_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pmedia_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 mc_enable_pmedia_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 mc_enable_pmedia_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 mc_enable_priv_ring_enabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 mc_enable_ce0_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 mc_enable_pfifo_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_enable_pgraph_enabled_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_enable_pwr_v(u32 r)
+{
+        return (r >> 13U) & 0x1U;
+}
+static inline u32 mc_enable_pwr_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_enable_pwr_enabled_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 mc_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_enable_ce2_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 mc_enable_ce2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 mc_enable_blg_enabled_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 mc_enable_perfmon_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 mc_intr_ltc_r(void)
+{
+        return 0x000001c0U;
+}
+static inline u32 mc_enable_pb_r(void)
+{
+        return 0x00000204U;
+}
+static inline u32 mc_enable_pb_0_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pb_0_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 mc_enable_pb_0_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 mc_enable_pb_0_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 mc_enable_pb_0_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 mc_elpg_enable_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 mc_elpg_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_elpg_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_elpg_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h
new file mode 100644
index 00000000..dad6317d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h
@@ -0,0 +1,527 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pbdma_gp106_h_
+#define _hw_pbdma_gp106_h_
+
+static inline u32 pbdma_gp_entry1_r(void)
+{
+        return 0x10000004U;
+}
+static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pbdma_gp_entry1_length_f(u32 v)
+{
+        return (v & 0x1fffffU) << 10U;
+}
+static inline u32 pbdma_gp_entry1_length_v(u32 r)
+{
+        return (r >> 10U) & 0x1fffffU;
+}
+static inline u32 pbdma_gp_base_r(u32 i)
+{
+        return 0x00040048U + i*8192U;
+}
+static inline u32 pbdma_gp_base__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pbdma_gp_base_offset_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 3U;
+}
+static inline u32 pbdma_gp_base_rsvd_s(void)
+{
+        return 3U;
+}
+static inline u32 pbdma_gp_base_hi_r(u32 i)
+{
+        return 0x0004004cU + i*8192U;
+}
+static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 pbdma_gp_fetch_r(u32 i)
+{
+        return 0x00040050U + i*8192U;
+}
+static inline u32 pbdma_gp_get_r(u32 i)
+{
+        return 0x00040014U + i*8192U;
+}
+static inline u32 pbdma_gp_put_r(u32 i)
+{
+        return 0x00040000U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_r(u32 i)
+{
+        return 0x00040054U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_hi_r(u32 i)
+{
+        return 0x00040058U + i*8192U;
+}
+static inline u32 pbdma_get_r(u32 i)
+{
+        return 0x00040018U + i*8192U;
+}
+static inline u32 pbdma_get_hi_r(u32 i)
+{
+        return 0x0004001cU + i*8192U;
+}
+static inline u32 pbdma_put_r(u32 i)
+{
+        return 0x0004005cU + i*8192U;
+}
+static inline u32 pbdma_put_hi_r(u32 i)
+{
+        return 0x00040060U + i*8192U;
+}
+static inline u32 pbdma_formats_r(u32 i)
+{
+        return 0x0004009cU + i*8192U;
+}
+static inline u32 pbdma_formats_gp_fermi0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_formats_pb_fermi1_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_formats_mp_fermi0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_r(u32 i)
+{
+        return 0x00040084U + i*8192U;
+}
+static inline u32 pbdma_pb_header_priv_user_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_method_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_subchannel_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_level_main_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_pb_header_type_inc_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_pb_header_type_non_inc_f(void)
+{
+        return 0x60000000U;
+}
+static inline u32 pbdma_hdr_shadow_r(u32 i)
+{
+        return 0x00040118U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_0_r(u32 i)
+{
+        return 0x00040110U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_1_r(u32 i)
+{
+        return 0x00040114U + i*8192U;
+}
+static inline u32 pbdma_subdevice_r(u32 i)
+{
+        return 0x00040094U + i*8192U;
+}
+static inline u32 pbdma_subdevice_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 pbdma_subdevice_status_active_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_method0_r(u32 i)
+{
+        return 0x000400c0U + i*8192U;
+}
+static inline u32 pbdma_method0_fifo_size_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pbdma_method0_addr_f(u32 v)
+{
+        return (v & 0xfffU) << 2U;
+}
+static inline u32 pbdma_method0_addr_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 pbdma_method0_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 pbdma_method0_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_method0_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_method1_r(u32 i)
+{
+        return 0x000400c8U + i*8192U;
+}
+static inline u32 pbdma_method2_r(u32 i)
+{
+        return 0x000400d0U + i*8192U;
+}
+static inline u32 pbdma_method3_r(u32 i)
+{
+        return 0x000400d8U + i*8192U;
+}
+static inline u32 pbdma_data0_r(u32 i)
+{
+        return 0x000400c4U + i*8192U;
+}
+static inline u32 pbdma_target_r(u32 i)
+{
+        return 0x000400acU + i*8192U;
+}
+static inline u32 pbdma_target_engine_sw_f(void)
+{
+        return 0x1fU;
+}
+static inline u32 pbdma_acquire_r(u32 i)
+{
+        return 0x00040030U + i*8192U;
+}
+static inline u32 pbdma_acquire_retry_man_2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_acquire_retry_exp_2_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_f(void)
+{
+        return 0x7800U;
+}
+static inline u32 pbdma_acquire_timeout_man_max_f(void)
+{
+        return 0x7fff8000U;
+}
+static inline u32 pbdma_acquire_timeout_en_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_status_r(u32 i)
+{
+        return 0x00040100U + i*8192U;
+}
+static inline u32 pbdma_channel_r(u32 i)
+{
+        return 0x00040120U + i*8192U;
+}
+static inline u32 pbdma_signature_r(u32 i)
+{
+        return 0x00040010U + i*8192U;
+}
+static inline u32 pbdma_signature_hw_valid_f(void)
+{
+        return 0xfaceU;
+}
+static inline u32 pbdma_signature_sw_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_r(u32 i)
+{
+        return 0x00040008U + i*8192U;
+}
+static inline u32 pbdma_userd_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pbdma_userd_addr_f(u32 v)
+{
+        return (v & 0x7fffffU) << 9U;
+}
+static inline u32 pbdma_userd_hi_r(u32 i)
+{
+        return 0x0004000cU + i*8192U;
+}
+static inline u32 pbdma_userd_hi_addr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_config_r(u32 i)
+{
+        return 0x000400f4U + i*8192U;
+}
+static inline u32 pbdma_config_auth_level_privileged_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_hce_ctrl_r(u32 i)
+{
+        return 0x000400e4U + i*8192U;
+}
+static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_r(u32 i)
+{
+        return 0x00040108U + i*8192U;
+}
+static inline u32 pbdma_intr_0_memreq_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pbdma_intr_0_memreq_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pbdma_intr_0_memflush_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_memop_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_intr_0_lbreq_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
+{
+        return 0x400U;
+}
+static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
+{
+        return 0x800U;
+}
+static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 pbdma_intr_0_gpptr_pending_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 pbdma_intr_0_gpentry_pending_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 pbdma_intr_0_pbptr_pending_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 pbdma_intr_0_pbentry_pending_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 pbdma_intr_0_method_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_intr_0_device_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 pbdma_intr_0_semaphore_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 pbdma_intr_0_acquire_pending_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 pbdma_intr_0_pri_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_intr_0_pbseg_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 pbdma_intr_0_signature_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+        return 0x00040148U + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_r(u32 i)
+{
+        return 0x0004010cU + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_en_1_r(u32 i)
+{
+        return 0x0004014cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_r(u32 i)
+{
+        return 0x0004013cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_udma_nop_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 pbdma_runlist_timeslice_r(u32 i)
+{
+        return 0x000400f8U + i*8192U;
+}
+static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
+{
+        return 0x3000U;
+}
+static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h
new file mode 100644
index 00000000..b0182789
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_perf_gp106_h_
+#define _hw_perf_gp106_h_
+
+static inline u32 perf_pmasys_control_r(void)
+{
+        return 0x001b4000U;
+}
+static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
+{
+        return 0x10U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
+{
+        return 0x20U;
+}
+static inline u32 perf_pmasys_mem_block_r(void)
+{
+        return 0x001b4070U;
+}
+static inline u32 perf_pmasys_mem_block_base_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 perf_pmasys_mem_block_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 perf_pmasys_mem_block_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_outbase_r(void)
+{
+        return 0x001b4074U;
+}
+static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_outbaseupper_r(void)
+{
+        return 0x001b4078U;
+}
+static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 perf_pmasys_outsize_r(void)
+{
+        return 0x001b407cU;
+}
+static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_mem_bytes_r(void)
+{
+        return 0x001b4084U;
+}
+static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_mem_bump_r(void)
+{
+        return 0x001b4088U;
+}
+static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_r(void)
+{
+        return 0x001b40a4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
+{
+        return 0x10U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h
new file mode 100644
index 00000000..7e33e716
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pram_gp106_h_
+#define _hw_pram_gp106_h_
+
+static inline u32 pram_data032_r(u32 i)
+{
+        return 0x00700000U + i*4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h
new file mode 100644
index 00000000..efdedc3b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringmaster_gp106_h_
+#define _hw_pri_ringmaster_gp106_h_
+
+static inline u32 pri_ringmaster_command_r(void)
+{
+        return 0x0012004cU;
+}
+static inline u32 pri_ringmaster_command_cmd_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 pri_ringmaster_command_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_command_data_r(void)
+{
+        return 0x00120048U;
+}
+static inline u32 pri_ringmaster_start_results_r(void)
+{
+        return 0x00120050U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pri_ringmaster_intr_status0_r(void)
+{
+        return 0x00120058U;
+}
+static inline u32 pri_ringmaster_intr_status1_r(void)
+{
+        return 0x0012005cU;
+}
+static inline u32 pri_ringmaster_global_ctl_r(void)
+{
+        return 0x00120060U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_enum_fbp_r(void)
+{
+        return 0x00120074U;
+}
+static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_gpc_r(void)
+{
+        return 0x00120078U;
+}
+static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_ltc_r(void)
+{
+        return 0x0012006cU;
+}
+static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h
new file mode 100644
index 00000000..711938d4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gp106_h_
+#define _hw_pri_ringstation_gpc_gp106_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300U + i*4U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
new file mode 100644
index 00000000..a3a1447d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_sys_gp106_h_
+#define _hw_pri_ringstation_sys_gp106_h_
+
+static inline u32 pri_ringstation_sys_master_config_r(u32 i)
+{
+        return 0x00122300U + i*4U;
+}
+static inline u32 pri_ringstation_sys_decode_config_r(void)
+{
+        return 0x00122204U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120U;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124U;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128U;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_proj_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_proj_gp106.h
new file mode 100644
index 00000000..be2111cc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_proj_gp106.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_proj_gp106_h_
+#define _hw_proj_gp106_h_
+
+static inline u32 proj_gpc_base_v(void)
+{
+        return 0x00500000U;
+}
+static inline u32 proj_gpc_shared_base_v(void)
+{
+        return 0x00418000U;
+}
+static inline u32 proj_gpc_stride_v(void)
+{
+        return 0x00008000U;
+}
+static inline u32 proj_ltc_stride_v(void)
+{
+        return 0x00002000U;
+}
+static inline u32 proj_lts_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_fbpa_base_v(void)
+{
+        return 0x00900000U;
+}
+static inline u32 proj_fbpa_shared_base_v(void)
+{
+        return 0x009a0000U;
+}
+static inline u32 proj_fbpa_stride_v(void)
+{
+        return 0x00004000U;
+}
+static inline u32 proj_ppc_in_gpc_base_v(void)
+{
+        return 0x00003000U;
+}
+static inline u32 proj_ppc_in_gpc_shared_base_v(void)
+{
+        return 0x00003e00U;
+}
+static inline u32 proj_ppc_in_gpc_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_rop_base_v(void)
+{
+        return 0x00410000U;
+}
+static inline u32 proj_rop_shared_base_v(void)
+{
+        return 0x00408800U;
+}
+static inline u32 proj_rop_stride_v(void)
+{
+        return 0x00000400U;
+}
+static inline u32 proj_tpc_in_gpc_base_v(void)
+{
+        return 0x00004000U;
+}
+static inline u32 proj_tpc_in_gpc_stride_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 proj_tpc_in_gpc_shared_base_v(void)
+{
+        return 0x00001800U;
+}
+static inline u32 proj_host_num_engines_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 proj_host_num_pbdma_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_fbps_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 proj_scal_litter_num_gpcs_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_scal_litter_num_zcull_banks_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 proj_scal_max_gpcs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 proj_scal_max_tpc_per_gpc_v(void)
+{
+        return 0x00000008U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h
new file mode 100644
index 00000000..b91c09ba
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h
@@ -0,0 +1,615 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_psec_gp106_h_
+#define _hw_psec_gp106_h_
+
+static inline u32 psec_falcon_irqsset_r(void)
+{
+        return 0x00087000U;
+}
+static inline u32 psec_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 psec_falcon_irqsclr_r(void)
+{
+        return 0x00087004U;
+}
+static inline u32 psec_falcon_irqstat_r(void)
+{
+        return 0x00087008U;
+}
+static inline u32 psec_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 psec_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 psec_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 psec_falcon_irqmode_r(void)
+{
+        return 0x0008700cU;
+}
+static inline u32 psec_falcon_irqmset_r(void)
+{
+        return 0x00087010U;
+}
+static inline u32 psec_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 psec_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 psec_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 psec_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 psec_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 psec_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 psec_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 psec_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 psec_falcon_irqmclr_r(void)
+{
+        return 0x00087014U;
+}
+static inline u32 psec_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 psec_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 psec_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 psec_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 psec_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 psec_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 psec_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 psec_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 psec_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 psec_falcon_irqmask_r(void)
+{
+        return 0x00087018U;
+}
+static inline u32 psec_falcon_irqdest_r(void)
+{
+        return 0x0008701cU;
+}
+static inline u32 psec_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 psec_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 psec_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 psec_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 psec_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 psec_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 psec_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 psec_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 psec_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 psec_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 psec_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 psec_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 psec_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 psec_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 psec_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 psec_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 psec_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 psec_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 psec_falcon_curctx_r(void)
+{
+        return 0x00087050U;
+}
+static inline u32 psec_falcon_nxtctx_r(void)
+{
+        return 0x00087054U;
+}
+static inline u32 psec_falcon_mailbox0_r(void)
+{
+        return 0x00087040U;
+}
+static inline u32 psec_falcon_mailbox1_r(void)
+{
+        return 0x00087044U;
+}
+static inline u32 psec_falcon_itfen_r(void)
+{
+        return 0x00087048U;
+}
+static inline u32 psec_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 psec_falcon_idlestate_r(void)
+{
+        return 0x0008704cU;
+}
+static inline u32 psec_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 psec_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 psec_falcon_os_r(void)
+{
+        return 0x00087080U;
+}
+static inline u32 psec_falcon_engctl_r(void)
+{
+        return 0x000870a4U;
+}
+static inline u32 psec_falcon_cpuctl_r(void)
+{
+        return 0x00087100U;
+}
+static inline u32 psec_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 psec_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 psec_falcon_cpuctl_alias_r(void)
+{
+        return 0x00087130U;
+}
+static inline u32 psec_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 psec_falcon_imemc_r(u32 i)
+{
+        return 0x00087180U + i*16U;
+}
+static inline u32 psec_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 psec_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 psec_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 psec_falcon_imemd_r(u32 i)
+{
+        return 0x00087184U + i*16U;
+}
+static inline u32 psec_falcon_imemt_r(u32 i)
+{
+        return 0x00087188U + i*16U;
+}
+static inline u32 psec_falcon_sctl_r(void)
+{
+        return 0x00087240U;
+}
+static inline u32 psec_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 psec_falcon_bootvec_r(void)
+{
+        return 0x00087104U;
+}
+static inline u32 psec_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 psec_falcon_dmactl_r(void)
+{
+        return 0x0008710cU;
+}
+static inline u32 psec_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 psec_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 psec_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 psec_falcon_hwcfg_r(void)
+{
+        return 0x00087108U;
+}
+static inline u32 psec_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 psec_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 psec_falcon_dmatrfbase_r(void)
+{
+        return 0x00087110U;
+}
+static inline u32 psec_falcon_dmatrfbase1_r(void)
+{
+        return 0x00087128U;
+}
+static inline u32 psec_falcon_dmatrfmoffs_r(void)
+{
+        return 0x00087114U;
+}
+static inline u32 psec_falcon_dmatrfcmd_r(void)
+{
+        return 0x00087118U;
+}
+static inline u32 psec_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 psec_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 psec_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 psec_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 psec_falcon_dmatrffboffs_r(void)
+{
+        return 0x0008711cU;
+}
+static inline u32 psec_falcon_exterraddr_r(void)
+{
+        return 0x00087168U;
+}
+static inline u32 psec_falcon_exterrstat_r(void)
+{
+        return 0x0008716cU;
+}
+static inline u32 psec_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 psec_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 psec_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_r(void)
+{
+        return 0x00087200U;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 psec_sec2_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 psec_sec2_falcon_icd_rdata_r(void)
+{
+        return 0x0008720cU;
+}
+static inline u32 psec_falcon_dmemc_r(u32 i)
+{
+        return 0x000871c0U + i*8U;
+}
+static inline u32 psec_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 psec_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 psec_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 psec_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 psec_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 psec_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 psec_falcon_dmemd_r(u32 i)
+{
+        return 0x000871c4U + i*8U;
+}
+static inline u32 psec_falcon_debug1_r(void)
+{
+        return 0x00087090U;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_s(void)
+{
+        return 1U;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 psec_falcon_debug1_ctxsw_mode_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 psec_fbif_transcfg_r(u32 i)
+{
+        return 0x00087600U + i*4U;
+}
+static inline u32 psec_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 psec_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1U;
+}
+static inline u32 psec_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 psec_fbif_transcfg_mem_type_s(void)
+{
+        return 1U;
+}
+static inline u32 psec_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 psec_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 psec_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 psec_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0U;
+}
+static inline u32 psec_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4U;
+}
+static inline u32 psec_falcon_engine_r(void)
+{
+        return 0x000873c0U;
+}
+static inline u32 psec_falcon_engine_reset_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 psec_falcon_engine_reset_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 psec_fbif_ctl_r(void)
+{
+        return 0x00087624U;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_disallow_f(void)
+{
+        return 0x0U;
+}
+static inline u32 psec_fbif_ctl_allow_phys_no_ctx_allow_f(void)
+{
+        return 0x80U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
new file mode 100644
index 00000000..a9fbbd10
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
@@ -0,0 +1,847 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pwr_gp106_h_
+#define _hw_pwr_gp106_h_
+
+static inline u32 pwr_falcon_irqsset_r(void)
+{
+        return 0x0010a000U;
+}
+static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqsclr_r(void)
+{
+        return 0x0010a004U;
+}
+static inline u32 pwr_falcon_irqstat_r(void)
+{
+        return 0x0010a008U;
+}
+static inline u32 pwr_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqmode_r(void)
+{
+        return 0x0010a00cU;
+}
+static inline u32 pwr_falcon_irqmset_r(void)
+{
+        return 0x0010a010U;
+}
+static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_r(void)
+{
+        return 0x0010a014U;
+}
+static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqmask_r(void)
+{
+        return 0x0010a018U;
+}
+static inline u32 pwr_falcon_irqdest_r(void)
+{
+        return 0x0010a01cU;
+}
+static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 pwr_falcon_curctx_r(void)
+{
+        return 0x0010a050U;
+}
+static inline u32 pwr_falcon_nxtctx_r(void)
+{
+        return 0x0010a054U;
+}
+static inline u32 pwr_falcon_mailbox0_r(void)
+{
+        return 0x0010a040U;
+}
+static inline u32 pwr_falcon_mailbox1_r(void)
+{
+        return 0x0010a044U;
+}
+static inline u32 pwr_falcon_itfen_r(void)
+{
+        return 0x0010a048U;
+}
+static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_r(void)
+{
+        return 0x0010a04cU;
+}
+static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 pwr_falcon_os_r(void)
+{
+        return 0x0010a080U;
+}
+static inline u32 pwr_falcon_engctl_r(void)
+{
+        return 0x0010a0a4U;
+}
+static inline u32 pwr_falcon_cpuctl_r(void)
+{
+        return 0x0010a100U;
+}
+static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 pwr_falcon_cpuctl_alias_r(void)
+{
+        return 0x0010a130U;
+}
+static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_pmu_scpctl_stat_r(void)
+{
+        return 0x0010ac08U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+        return 0x0010a180U + i*16U;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+        return 0x0010a184U + i*16U;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+        return 0x0010a188U + i*16U;
+}
+static inline u32 pwr_falcon_sctl_r(void)
+{
+        return 0x0010a240U;
+}
+static inline u32 pwr_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 pwr_falcon_bootvec_r(void)
+{
+        return 0x0010a104U;
+}
+static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_falcon_dmactl_r(void)
+{
+        return 0x0010a10cU;
+}
+static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_hwcfg_r(void)
+{
+        return 0x0010a108U;
+}
+static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_dmatrfbase_r(void)
+{
+        return 0x0010a110U;
+}
+static inline u32 pwr_falcon_dmatrfbase1_r(void)
+{
+        return 0x0010a128U;
+}
+static inline u32 pwr_falcon_dmatrfmoffs_r(void)
+{
+        return 0x0010a114U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_r(void)
+{
+        return 0x0010a118U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 pwr_falcon_dmatrffboffs_r(void)
+{
+        return 0x0010a11cU;
+}
+static inline u32 pwr_falcon_exterraddr_r(void)
+{
+        return 0x0010a168U;
+}
+static inline u32 pwr_falcon_exterrstat_r(void)
+{
+        return 0x0010a16cU;
+}
+static inline u32 pwr_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
+{
+        return 0x0010a200U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
+{
+        return 0x0010a20cU;
+}
+static inline u32 pwr_falcon_dmemc_r(u32 i)
+{
+        return 0x0010a1c0U + i*8U;
+}
+static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 pwr_falcon_dmemd_r(u32 i)
+{
+        return 0x0010a1c4U + i*8U;
+}
+static inline u32 pwr_pmu_new_instblk_r(void)
+{
+        return 0x0010a480U;
+}
+static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 pwr_pmu_mutex_id_r(void)
+{
+        return 0x0010a488U;
+}
+static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_id_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 pwr_pmu_mutex_id_release_r(void)
+{
+        return 0x0010a48cU;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_mutex_r(u32 i)
+{
+        return 0x0010a580U + i*4U;
+}
+static inline u32 pwr_pmu_mutex__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 pwr_pmu_mutex_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_queue_head_r(u32 i)
+{
+        return 0x0010a4a0U + i*4U;
+}
+static inline u32 pwr_pmu_queue_head__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_queue_head_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_head_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_queue_tail_r(u32 i)
+{
+        return 0x0010a4b0U + i*4U;
+}
+static inline u32 pwr_pmu_queue_tail__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_head_r(void)
+{
+        return 0x0010a4c8U;
+}
+static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_tail_r(void)
+{
+        return 0x0010a4ccU;
+}
+static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_idle_mask_r(u32 i)
+{
+        return 0x0010a504U + i*16U;
+}
+static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pwr_pmu_idle_count_r(u32 i)
+{
+        return 0x0010a508U + i*16U;
+}
+static inline u32 pwr_pmu_idle_count_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_count_value_v(u32 r)
+{
+        return (r >> 0U) & 0x7fffffffU;
+}
+static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
+{
+        return 0x0010a50cU + i*16U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
+{
+        return 0x0010a9f0U + i*8U;
+}
+static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
+{
+        return 0x0010a9f4U + i*8U;
+}
+static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
+{
+        return 0x0010aa30U + i*8U;
+}
+static inline u32 pwr_pmu_debug_r(u32 i)
+{
+        return 0x0010a5c0U + i*4U;
+}
+static inline u32 pwr_pmu_debug__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_mailbox_r(u32 i)
+{
+        return 0x0010a450U + i*4U;
+}
+static inline u32 pwr_pmu_mailbox__size_1_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 pwr_pmu_bar0_addr_r(void)
+{
+        return 0x0010a7a0U;
+}
+static inline u32 pwr_pmu_bar0_data_r(void)
+{
+        return 0x0010a7a4U;
+}
+static inline u32 pwr_pmu_bar0_ctl_r(void)
+{
+        return 0x0010a7acU;
+}
+static inline u32 pwr_pmu_bar0_timeout_r(void)
+{
+        return 0x0010a7a8U;
+}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+        return 0x0010a988U;
+}
+static inline u32 pwr_pmu_bar0_error_status_r(void)
+{
+        return 0x0010a7b0U;
+}
+static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
+{
+        return 0x0010a6c0U + i*4U;
+}
+static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
+{
+        return 0x0010a6e8U + i*4U;
+}
+static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
+{
+        return 0x0010a710U + i*4U;
+}
+static inline u32 pwr_pmu_pg_intren_r(u32 i)
+{
+        return 0x0010a760U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_r(u32 i)
+{
+        return 0x0010ae00U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_s(void)
+{
+        return 1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4U;
+}
+static inline u32 pwr_falcon_engine_r(void)
+{
+        return 0x0010a3c0U;
+}
+static inline u32 pwr_falcon_engine_reset_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_falcon_engine_reset_false_f(void)
+{
+        return 0x0U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h
new file mode 100644
index 00000000..3ae3f3bb
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h
@@ -0,0 +1,487 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ram_gp106_h_
+#define _hw_ram_gp106_h_
+
+static inline u32 ram_in_ramfc_s(void)
+{
+        return 4096U;
+}
+static inline u32 ram_in_ramfc_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_in_page_dir_base_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ram_in_page_dir_base_target_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 ram_in_page_dir_base_vol_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 ram_in_big_page_size_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 ram_in_big_page_size_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 ram_in_big_page_size_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_big_page_size_128kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_big_page_size_64kb_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ram_in_page_dir_base_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_page_dir_base_lo_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_hi_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ram_in_page_dir_base_hi_w(void)
+{
+        return 129U;
+}
+static inline u32 ram_in_adr_limit_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_adr_limit_lo_w(void)
+{
+        return 130U;
+}
+static inline u32 ram_in_adr_limit_hi_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ram_in_adr_limit_hi_w(void)
+{
+        return 131U;
+}
+static inline u32 ram_in_engine_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_engine_cs_wfi_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_engine_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_engine_cs_fg_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_engine_cs_fg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ram_in_gr_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_gr_wfi_target_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_mode_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
+{
+        return 133U;
+}
+static inline u32 ram_in_base_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ram_in_alloc_size_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ram_fc_size_val_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_fc_gp_put_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_userd_w(void)
+{
+        return 2U;
+}
+static inline u32 ram_fc_userd_hi_w(void)
+{
+        return 3U;
+}
+static inline u32 ram_fc_signature_w(void)
+{
+        return 4U;
+}
+static inline u32 ram_fc_gp_get_w(void)
+{
+        return 5U;
+}
+static inline u32 ram_fc_pb_get_w(void)
+{
+        return 6U;
+}
+static inline u32 ram_fc_pb_get_hi_w(void)
+{
+        return 7U;
+}
+static inline u32 ram_fc_pb_top_level_get_w(void)
+{
+        return 8U;
+}
+static inline u32 ram_fc_pb_top_level_get_hi_w(void)
+{
+        return 9U;
+}
+static inline u32 ram_fc_acquire_w(void)
+{
+        return 12U;
+}
+static inline u32 ram_fc_semaphorea_w(void)
+{
+        return 14U;
+}
+static inline u32 ram_fc_semaphoreb_w(void)
+{
+        return 15U;
+}
+static inline u32 ram_fc_semaphorec_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_fc_semaphored_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_fc_gp_base_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_fc_gp_base_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_fc_gp_fetch_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_fc_pb_fetch_w(void)
+{
+        return 21U;
+}
+static inline u32 ram_fc_pb_fetch_hi_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_fc_pb_put_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_fc_pb_put_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_fc_pb_header_w(void)
+{
+        return 33U;
+}
+static inline u32 ram_fc_pb_count_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_fc_subdevice_w(void)
+{
+        return 37U;
+}
+static inline u32 ram_fc_formats_w(void)
+{
+        return 39U;
+}
+static inline u32 ram_fc_target_w(void)
+{
+        return 43U;
+}
+static inline u32 ram_fc_hce_ctrl_w(void)
+{
+        return 57U;
+}
+static inline u32 ram_fc_chid_w(void)
+{
+        return 58U;
+}
+static inline u32 ram_fc_chid_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_fc_chid_id_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_config_w(void)
+{
+        return 61U;
+}
+static inline u32 ram_fc_runlist_timeslice_w(void)
+{
+        return 62U;
+}
+static inline u32 ram_userd_base_shift_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 ram_userd_chan_size_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_userd_put_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_userd_get_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_userd_ref_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_userd_put_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_userd_ref_threshold_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_userd_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_userd_get_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_userd_gp_get_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_userd_gp_put_w(void)
+{
+        return 35U;
+}
+static inline u32 ram_userd_gp_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_gp_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_rl_entry_size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+        return (v & 0xfU) << 14U;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+        return 0xc000U;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+        return (v & 0xffU) << 18U;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+        return (v & 0x3fU) << 26U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h
new file mode 100644
index 00000000..ee580326
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_therm_gp106_h_
+#define _hw_therm_gp106_h_
+
+static inline u32 therm_temp_sensor_tsense_r(void)
+{
+        return 0x00020460U;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_f(u32 v)
+{
+        return (v & 0x3fffU) << 3U;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_m(void)
+{
+        return 0x3fffU << 3U;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_v(u32 r)
+{
+        return (r >> 3U) & 0x3fffU;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_min_v(void)
+{
+        return 0x00003b00U;
+}
+static inline u32 therm_temp_sensor_tsense_fixed_point_max_v(void)
+{
+        return 0x000010e0U;
+}
+static inline u32 therm_temp_sensor_tsense_state_f(u32 v)
+{
+        return (v & 0x3U) << 29U;
+}
+static inline u32 therm_temp_sensor_tsense_state_m(void)
+{
+        return 0x3U << 29U;
+}
+static inline u32 therm_temp_sensor_tsense_state_v(u32 r)
+{
+        return (r >> 29U) & 0x3U;
+}
+static inline u32 therm_temp_sensor_tsense_state_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 therm_temp_sensor_tsense_state_shadow_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 therm_gate_ctrl_r(u32 i)
+{
+        return 0x00020200U + i*4U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_m(void)
+{
+        return 0x3U << 2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
+{
+        return 0x4U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
+{
+        return 0x1fU << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
+{
+        return (v & 0x7U) << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
+{
+        return 0x7U << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
+{
+        return 0xfU << 20U;
+}
+static inline u32 therm_fecs_idle_filter_r(void)
+{
+        return 0x00020288U;
+}
+static inline u32 therm_fecs_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_hubmmu_idle_filter_r(void)
+{
+        return 0x0002028cU;
+}
+static inline u32 therm_hubmmu_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h
new file mode 100644
index 00000000..7fd722f9
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_timer_gp106_h_
+#define _hw_timer_gp106_h_
+
+static inline u32 timer_pri_timeout_r(void)
+{
+        return 0x00009080U;
+}
+static inline u32 timer_pri_timeout_period_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 timer_pri_timeout_period_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 timer_pri_timeout_period_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 timer_pri_timeout_en_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 timer_pri_timeout_en_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 timer_pri_timeout_en_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 timer_pri_timeout_en_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 timer_pri_timeout_en_en_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 timer_pri_timeout_save_0_r(void)
+{
+        return 0x00009084U;
+}
+static inline u32 timer_pri_timeout_save_1_r(void)
+{
+        return 0x00009088U;
+}
+static inline u32 timer_pri_timeout_fecs_errcode_r(void)
+{
+        return 0x0000908cU;
+}
+static inline u32 timer_time_0_r(void)
+{
+        return 0x00009400U;
+}
+static inline u32 timer_time_1_r(void)
+{
+        return 0x00009410U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h
new file mode 100644
index 00000000..749f66ed
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_top_gp106_h_
+#define _hw_top_gp106_h_
+
+static inline u32 top_num_gpcs_r(void)
+{
+        return 0x00022430U;
+}
+static inline u32 top_num_gpcs_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_tpc_per_gpc_r(void)
+{
+        return 0x00022434U;
+}
+static inline u32 top_tpc_per_gpc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_fbps_r(void)
+{
+        return 0x00022438U;
+}
+static inline u32 top_num_fbps_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_fbpas_r(void)
+{
+        return 0x0002243cU;
+}
+static inline u32 top_num_fbpas_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_ltc_per_fbp_r(void)
+{
+        return 0x00022450U;
+}
+static inline u32 top_ltc_per_fbp_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_slices_per_ltc_r(void)
+{
+        return 0x0002245cU;
+}
+static inline u32 top_slices_per_ltc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_ltcs_r(void)
+{
+        return 0x00022454U;
+}
+static inline u32 top_device_info_r(u32 i)
+{
+        return 0x00022700U + i*4U;
+}
+static inline u32 top_device_info__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 top_device_info_chain_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 top_device_info_chain_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_engine_enum_v(u32 r)
+{
+        return (r >> 26U) & 0xfU;
+}
+static inline u32 top_device_info_runlist_enum_v(u32 r)
+{
+        return (r >> 21U) & 0xfU;
+}
+static inline u32 top_device_info_intr_enum_v(u32 r)
+{
+        return (r >> 15U) & 0x1fU;
+}
+static inline u32 top_device_info_reset_enum_v(u32 r)
+{
+        return (r >> 9U) & 0x1fU;
+}
+static inline u32 top_device_info_type_enum_v(u32 r)
+{
+        return (r >> 2U) & 0x1fffffffU;
+}
+static inline u32 top_device_info_type_enum_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_type_enum_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 top_device_info_type_enum_copy0_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_type_enum_copy0_f(void)
+{
+        return 0x4U;
+}
+static inline u32 top_device_info_type_enum_copy2_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_type_enum_copy2_f(void)
+{
+        return 0xcU;
+}
+static inline u32 top_device_info_type_enum_lce_v(void)
+{
+        return 0x00000013U;
+}
+static inline u32 top_device_info_type_enum_lce_f(void)
+{
+        return 0x4cU;
+}
+static inline u32 top_device_info_engine_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 top_device_info_runlist_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 top_device_info_intr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 top_device_info_reset_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_entry_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 top_device_info_entry_not_valid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_entry_enum_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 top_device_info_entry_engine_type_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_entry_data_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_data_type_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 top_device_info_data_type_enum2_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_data_inst_id_v(u32 r)
+{
+        return (r >> 26U) & 0xfU;
+}
+static inline u32 top_device_info_data_pri_base_v(u32 r)
+{
+        return (r >> 12U) & 0xfffU;
+}
+static inline u32 top_device_info_data_pri_base_align_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
+{
+        return (r >> 3U) & 0x1fU;
+}
+static inline u32 top_device_info_data_fault_id_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_data_fault_id_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_scratch1_r(void)
+{
+        return 0x0002240cU;
+}
+static inline u32 top_scratch1_devinit_completed_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h
new file mode 100644
index 00000000..cebb6d40
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_trim_gp106_h_
+#define _hw_trim_gp106_h_
+
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(void)
+{
+        return 0x00132924U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s(void)
+{
+        return 16U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s(void)
+{
+        return 1U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s(void)
+{
+        return 1U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(void)
+{
+        return 0x70000000U;
+}
+static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(void)
+{
+        return 0x00132928U;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(void)
+{
+        return 0x00132128U;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(void)
+{
+        return 0x0013212cU;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_r(void)
+{
+        return 0x001373c0U;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 trim_sys_clk_cntr_ncltcpll_cnt_r(void)
+{
+        return 0x001373c4U;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_r(void)
+{
+        return 0x001373b0U;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_clk_cntr_ncsyspll_cnt_r(void)
+{
+        return 0x001373b4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h
new file mode 100644
index 00000000..f6c843c5
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xp_gp106_h_
+#define _hw_xp_gp106_h_
+
+static inline u32 xp_dl_mgr_r(u32 i)
+{
+        return 0x0008b8c0U + i*4U;
+}
+static inline u32 xp_dl_mgr_safe_timing_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 xp_pl_link_config_r(u32 i)
+{
+        return 0x0008c040U + i*4U;
+}
+static inline u32 xp_pl_link_config_ltssm_status_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 xp_pl_link_config_ltssm_status_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_f(u32 v)
+{
+        return (v & 0x3U) << 18U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_m(void)
+{
+        return 0x3U << 18U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_m(void)
+{
+        return 0x7U << 20U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x1_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x2_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x4_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x8_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x16_v(void)
+{
+        return 0x00000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h
new file mode 100644
index 00000000..e61d13f3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xve_gp106_h_
+#define _hw_xve_gp106_h_
+
+static inline u32 xve_rom_ctrl_r(void)
+{
+        return 0x00000050U;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 xve_link_control_status_r(void)
+{
+        return 0x00000088U;
+}
+static inline u32 xve_link_control_status_link_speed_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 xve_link_control_status_link_speed_v(u32 r)
+{
+        return (r >> 16U) & 0xfU;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 xve_link_control_status_link_width_m(void)
+{
+        return 0x3fU << 20U;
+}
+static inline u32 xve_link_control_status_link_width_v(u32 r)
+{
+        return (r >> 20U) & 0x3fU;
+}
+static inline u32 xve_link_control_status_link_width_x1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 xve_link_control_status_link_width_x2_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 xve_link_control_status_link_width_x4_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 xve_link_control_status_link_width_x8_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 xve_link_control_status_link_width_x16_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 xve_priv_xv_r(void)
+{
+        return 0x00000150U;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 xve_cya_2_r(void)
+{
+        return 0x00000704U;
+}
+static inline u32 xve_reset_r(void)
+{
+        return 0x00000718U;
+}
+static inline u32 xve_reset_reset_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 xve_reset_gpu_on_sw_reset_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 xve_reset_counter_en_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 xve_reset_counter_val_f(u32 v)
+{
+        return (v & 0x7ffU) << 4U;
+}
+static inline u32 xve_reset_counter_val_m(void)
+{
+        return 0x7ffU << 4U;
+}
+static inline u32 xve_reset_counter_val_v(u32 r)
+{
+        return (r >> 4U) & 0x7ffU;
+}
+static inline u32 xve_reset_clock_on_sw_reset_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 xve_reset_clock_counter_en_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 xve_reset_clock_counter_val_f(u32 v)
+{
+        return (v & 0x7ffU) << 17U;
+}
+static inline u32 xve_reset_clock_counter_val_m(void)
+{
+        return 0x7ffU << 17U;
+}
+static inline u32 xve_reset_clock_counter_val_v(u32 r)
+{
+        return (r >> 17U) & 0x7ffU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
new file mode 100644
index 00000000..b06ea66d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_bus_gp10b_h_
+#define _hw_bus_gp10b_h_
+
+static inline u32 bus_bar0_window_r(void)
+{
+        return 0x00001700U;
+}
+static inline u32 bus_bar0_window_base_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 bus_bar0_window_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 bus_bar1_block_r(void)
+{
+        return 0x00001704U;
+}
+static inline u32 bus_bar1_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar1_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar1_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar2_block_r(void)
+{
+        return 0x00001714U;
+}
+static inline u32 bus_bar2_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar2_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar2_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar1_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bar2_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bind_status_r(void)
+{
+        return 0x00001710U;
+}
+static inline u32 bus_bind_status_bar1_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar1_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar1_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 bus_bind_status_bar2_pending_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar2_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar2_pending_busy_f(void)
+{
+        return 0x4U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 bus_intr_0_r(void)
+{
+        return 0x00001100U;
+}
+static inline u32 bus_intr_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 bus_intr_en_0_r(void)
+{
+        return 0x00001140U;
+}
+static inline u32 bus_intr_en_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_en_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_en_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
new file mode 100644
index 00000000..00879c11
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ccsr_gp10b_h_
+#define _hw_ccsr_gp10b_h_
+
+static inline u32 ccsr_channel_inst_r(u32 i)
+{
+        return 0x00800000U + i*8U;
+}
+static inline u32 ccsr_channel_inst__size_1_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ccsr_channel_inst_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 ccsr_channel_inst_bind_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_bind_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 ccsr_channel_r(u32 i)
+{
+        return 0x00800004U + i*8U;
+}
+static inline u32 ccsr_channel__size_1_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ccsr_channel_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ccsr_channel_enable_set_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 ccsr_channel_enable_set_true_f(void)
+{
+        return 0x400U;
+}
+static inline u32 ccsr_channel_enable_clr_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ccsr_channel_status_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
+{
+        return 0x100U;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
new file mode 100644
index 00000000..c2937710
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce_gp10b_h_
+#define _hw_ce_gp10b_h_
+
+static inline u32 ce_intr_status_r(u32 i)
+{
+        return 0x00104410U + i*128U;
+}
+static inline u32 ce_intr_status_blockpipe_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce_intr_status_blockpipe_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce_intr_status_launcherr_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ce_intr_status_launcherr_reset_f(void)
+{
+        return 0x4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
new file mode 100644
index 00000000..b214bdb3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
@@ -0,0 +1,487 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ctxsw_prog_gp10b_h_
+#define _hw_ctxsw_prog_gp10b_h_
+
+static inline u32 ctxsw_prog_fecs_header_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_main_image_patch_count_o(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ctxsw_prog_main_image_context_id_o(void)
+{
+        return 0x000000f0U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
+{
+        return 0x00000014U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
+{
+        return 0x00000018U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_o(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_main_image_pm_o(void)
+{
+        return 0x00000028U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
+{
+        return 0x7U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
+{
+        return 0x0000002cU;
+}
+static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
+{
+        return 0x000000d0U;
+}
+static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
+{
+        return 0x000000d4U;
+}
+static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
+{
+        return 0x000000d8U;
+}
+static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
+{
+        return 0x000000dcU;
+}
+static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
+{
+        return 0x600dc0deU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_local_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
+{
+        return 0xad0becabU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+        return 2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pmu_options_o(void)
+{
+        return 0x00000070U;
+}
+static inline u32 ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
+{
+        return 0x00000068U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
+{
+        return 0x00000084U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
+{
+        return 0x000000acU;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
+{
+        return 0x000000b0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
+{
+        return 0x000000b4U;
+}
+static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
+{
+        return 0x600dbeefU;
+}
+static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
+{
+        return 0x00000018U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
+{
+        return 0xffU << 24U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
+{
+        return (r >> 24U) & 0xffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
+{
+        return 0xa000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
+{
+        return 0xb000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
+{
+        return 0xc000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
+{
+        return 0xd000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
+{
+        return 0x5000000U;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
+{
+        return 0xff000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h
new file mode 100644
index 00000000..918f262b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h
@@ -0,0 +1,599 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_falcon_gp10b_h_
+#define _hw_falcon_gp10b_h_
+
+static inline u32 falcon_falcon_irqsset_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqsclr_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 falcon_falcon_irqstat_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 falcon_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqmode_r(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 falcon_falcon_irqmset_r(void)
+{
+        return 0x00000010U;
+}
+static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_r(void)
+{
+        return 0x00000014U;
+}
+static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqmask_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 falcon_falcon_irqdest_r(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 falcon_falcon_curctx_r(void)
+{
+        return 0x00000050U;
+}
+static inline u32 falcon_falcon_nxtctx_r(void)
+{
+        return 0x00000054U;
+}
+static inline u32 falcon_falcon_mailbox0_r(void)
+{
+        return 0x00000040U;
+}
+static inline u32 falcon_falcon_mailbox1_r(void)
+{
+        return 0x00000044U;
+}
+static inline u32 falcon_falcon_itfen_r(void)
+{
+        return 0x00000048U;
+}
+static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_r(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 falcon_falcon_os_r(void)
+{
+        return 0x00000080U;
+}
+static inline u32 falcon_falcon_engctl_r(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 falcon_falcon_cpuctl_r(void)
+{
+        return 0x00000100U;
+}
+static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_stopped_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_alias_r(void)
+{
+        return 0x00000130U;
+}
+static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_imemc_r(u32 i)
+{
+        return 0x00000180U + i*16U;
+}
+static inline u32 falcon_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_imemd_r(u32 i)
+{
+        return 0x00000184U + i*16U;
+}
+static inline u32 falcon_falcon_imemt_r(u32 i)
+{
+        return 0x00000188U + i*16U;
+}
+static inline u32 falcon_falcon_sctl_r(void)
+{
+        return 0x00000240U;
+}
+static inline u32 falcon_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 falcon_falcon_bootvec_r(void)
+{
+        return 0x00000104U;
+}
+static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 falcon_falcon_dmactl_r(void)
+{
+        return 0x0000010cU;
+}
+static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_hwcfg_r(void)
+{
+        return 0x00000108U;
+}
+static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_dmatrfbase_r(void)
+{
+        return 0x00000110U;
+}
+static inline u32 falcon_falcon_dmatrfbase1_r(void)
+{
+        return 0x00000128U;
+}
+static inline u32 falcon_falcon_dmatrfmoffs_r(void)
+{
+        return 0x00000114U;
+}
+static inline u32 falcon_falcon_imctl_debug_r(void)
+{
+        return 0x0000015cU;
+}
+static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 falcon_falcon_imstat_r(void)
+{
+        return 0x00000144U;
+}
+static inline u32 falcon_falcon_traceidx_r(void)
+{
+        return 0x00000148U;
+}
+static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 falcon_falcon_traceidx_idx_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 falcon_falcon_tracepc_r(void)
+{
+        return 0x0000014cU;
+}
+static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 falcon_falcon_dmatrfcmd_r(void)
+{
+        return 0x00000118U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 falcon_falcon_dmatrffboffs_r(void)
+{
+        return 0x0000011cU;
+}
+static inline u32 falcon_falcon_exterraddr_r(void)
+{
+        return 0x00000168U;
+}
+static inline u32 falcon_falcon_exterrstat_r(void)
+{
+        return 0x0000016cU;
+}
+static inline u32 falcon_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 falcon_falcon_icd_cmd_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 falcon_falcon_icd_rdata_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 falcon_falcon_dmemc_r(u32 i)
+{
+        return 0x000001c0U + i*8U;
+}
+static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 falcon_falcon_dmemd_r(u32 i)
+{
+        return 0x000001c4U + i*8U;
+}
+static inline u32 falcon_falcon_debug1_r(void)
+{
+        return 0x00000090U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
+{
+        return 1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 falcon_falcon_debuginfo_r(void)
+{
+        return 0x00000094U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
new file mode 100644
index 00000000..81a6f79c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
@@ -0,0 +1,487 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fb_gp10b_h_
+#define _hw_fb_gp10b_h_
+
+static inline u32 fb_fbhub_num_active_ltcs_r(void)
+{
+        return 0x00100800U;
+}
+static inline u32 fb_mmu_ctrl_r(void)
+{
+        return 0x00100c80U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
+{
+        return (r >> 11U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_priv_mmu_phy_secure_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 fb_mmu_invalidate_pdb_r(void)
+{
+        return 0x00100cb8U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_invalidate_r(void)
+{
+        return 0x00100cbcU;
+}
+static inline u32 fb_mmu_invalidate_all_va_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_invalidate_replay_s(void)
+{
+        return 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_f(u32 v)
+{
+        return (v & 0x7U) << 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_m(void)
+{
+        return 0x7U << 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_v(u32 r)
+{
+        return (r >> 3U) & 0x7U;
+}
+static inline u32 fb_mmu_invalidate_replay_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_replay_start_f(void)
+{
+        return 0x8U;
+}
+static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
+{
+        return 0x18U;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
+{
+        return 0x20U;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
+{
+        return 0x20U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 fb_mmu_invalidate_ack_s(void)
+{
+        return 2U;
+}
+static inline u32 fb_mmu_invalidate_ack_f(u32 v)
+{
+        return (v & 0x3U) << 7U;
+}
+static inline u32 fb_mmu_invalidate_ack_m(void)
+{
+        return 0x3U << 7U;
+}
+static inline u32 fb_mmu_invalidate_ack_v(u32 r)
+{
+        return (r >> 7U) & 0x3U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
+{
+        return 0x80U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
+{
+        return 6U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
+{
+        return (v & 0x3fU) << 9U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
+{
+        return 0x3fU << 9U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
+{
+        return (r >> 9U) & 0x3fU;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
+{
+        return 5U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
+{
+        return (v & 0x1fU) << 15U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
+{
+        return 0x1fU << 15U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
+{
+        return (r >> 15U) & 0x1fU;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
+{
+        return 3U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
+{
+        return 0x7U << 24U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
+{
+        return (r >> 24U) & 0x7U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
+{
+        return 0x5000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
+{
+        return 0x6000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
+{
+        return 0x7000000U;
+}
+static inline u32 fb_mmu_invalidate_trigger_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_debug_wr_r(void)
+{
+        return 0x00100cc8U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_s(void)
+{
+        return 2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_rd_r(void)
+{
+        return 0x00100cccU;
+}
+static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_rd_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_ctrl_r(void)
+{
+        return 0x00100cc4U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_vpr_info_r(void)
+{
+        return 0x00100cd0U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+        return 0x00100c10U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
new file mode 100644
index 00000000..71701626
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
@@ -0,0 +1,699 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fifo_gp10b_h_
+#define _hw_fifo_gp10b_h_
+
+static inline u32 fifo_bar1_base_r(void)
+{
+        return 0x00002254U;
+}
+static inline u32 fifo_bar1_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_bar1_base_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_bar1_base_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_runlist_base_r(void)
+{
+        return 0x00002270U;
+}
+static inline u32 fifo_runlist_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_runlist_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 fifo_runlist_r(void)
+{
+        return 0x00002274U;
+}
+static inline u32 fifo_runlist_engine_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 fifo_eng_runlist_base_r(u32 i)
+{
+        return 0x00002280U + i*8U;
+}
+static inline u32 fifo_eng_runlist_base__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_eng_runlist_r(u32 i)
+{
+        return 0x00002284U + i*8U;
+}
+static inline u32 fifo_eng_runlist__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_eng_runlist_length_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 fifo_eng_runlist_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_pb_timeslice_r(u32 i)
+{
+        return 0x00002350U + i*4U;
+}
+static inline u32 fifo_pb_timeslice_timeout_16_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fifo_pb_timeslice_timescale_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_pb_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_pbdma_map_r(u32 i)
+{
+        return 0x00002390U + i*4U;
+}
+static inline u32 fifo_intr_0_r(void)
+{
+        return 0x00002100U;
+}
+static inline u32 fifo_intr_0_bind_error_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_bind_error_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_sched_error_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_sched_error_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_chsw_error_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_chsw_error_reset_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_lb_error_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_lb_error_reset_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_intr_0_runlist_event_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fifo_intr_0_channel_intr_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fifo_intr_en_0_r(void)
+{
+        return 0x00002140U;
+}
+static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 fifo_intr_en_1_r(void)
+{
+        return 0x00002528U;
+}
+static inline u32 fifo_intr_bind_error_r(void)
+{
+        return 0x0000252cU;
+}
+static inline u32 fifo_intr_sched_error_r(void)
+{
+        return 0x0000254cU;
+}
+static inline u32 fifo_intr_sched_error_code_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 fifo_intr_chsw_error_r(void)
+{
+        return 0x0000256cU;
+}
+static inline u32 fifo_intr_mmu_fault_id_r(void)
+{
+        return 0x0000259cU;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
+{
+        return 0x00002800U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
+{
+        return 0x00002804U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
+{
+        return 0x00002808U + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
+{
+        return 0x0000280cU + i*16U;
+}
+static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 fifo_intr_mmu_fault_info_access_type_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
+{
+        return (r >> 8U) & 0x7fU;
+}
+static inline u32 fifo_intr_pbdma_id_r(void)
+{
+        return 0x000025a0U;
+}
+static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_intr_runlist_r(void)
+{
+        return 0x00002a00U;
+}
+static inline u32 fifo_fb_timeout_r(void)
+{
+        return 0x00002a04U;
+}
+static inline u32 fifo_fb_timeout_period_m(void)
+{
+        return 0x3fffffffU << 0U;
+}
+static inline u32 fifo_fb_timeout_period_max_f(void)
+{
+        return 0x3fffffffU;
+}
+static inline u32 fifo_error_sched_disable_r(void)
+{
+        return 0x0000262cU;
+}
+static inline u32 fifo_sched_disable_r(void)
+{
+        return 0x00002630U;
+}
+static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_runlist_m(u32 i)
+{
+        return 0x1U << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_preempt_r(void)
+{
+        return 0x00002634U;
+}
+static inline u32 fifo_preempt_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_preempt_type_channel_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_preempt_type_tsg_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_preempt_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_preempt_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_trigger_mmu_fault_r(u32 i)
+{
+        return 0x00002a30U + i*4U;
+}
+static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_engine_status_r(u32 i)
+{
+        return 0x00002640U + i*8U;
+}
+static inline u32 fifo_engine_status__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fifo_engine_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_engine_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_ctx_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_engine_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_engine_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_faulted_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fifo_engine_status_faulted_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_engine_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fifo_engine_status_engine_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_engine_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 fifo_pbdma_status_r(u32 i)
+{
+        return 0x00003080U + i*4U;
+}
+static inline u32 fifo_pbdma_status__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_pbdma_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_chsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_r(void)
+{
+        return 0x00002a70U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_hi_r(void)
+{
+        return 0x00002a74U;
+}
+static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_size_r(void)
+{
+        return 0x00002a78U;
+}
+static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 fifo_replay_fault_buffer_get_r(void)
+{
+        return 0x00002a7cU;
+}
+static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_put_r(void)
+{
+        return 0x00002a80U;
+}
+static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_info_r(void)
+{
+        return 0x00002a84U;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
new file mode 100644
index 00000000..ae6eabf1
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_flush_gp10b_h_
+#define _hw_flush_gp10b_h_
+
+static inline u32 flush_l2_system_invalidate_r(void)
+{
+        return 0x00070004U;
+}
+static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_r(void)
+{
+        return 0x00070010U;
+}
+static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_r(void)
+{
+        return 0x0007000cU;
+}
+static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_r(void)
+{
+        return 0x00070000U;
+}
+static inline u32 flush_fb_flush_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_fb_flush_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
new file mode 100644
index 00000000..29107fb8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fuse_gp10b_h_
+#define _hw_fuse_gp10b_h_
+
+static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021c38U + i*4U;
+}
+static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021838U + i*4U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
+{
+        return 0x00021944U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
+{
+        return 0x00021948U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fuse_status_opt_fbio_r(void)
+{
+        return 0x00021c14U;
+}
+static inline u32 fuse_status_opt_fbio_data_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fuse_status_opt_fbio_data_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 fuse_status_opt_fbio_data_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
+{
+        return 0x00021d70U + i*4U;
+}
+static inline u32 fuse_status_opt_fbp_r(void)
+{
+        return 0x00021d38U;
+}
+static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fuse_opt_ecc_en_r(void)
+{
+        return 0x00021228U;
+}
+static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
+{
+        return 0x000213f0U;
+}
+static inline u32 fuse_opt_sec_debug_en_r(void)
+{
+        return 0x00021218U;
+}
+static inline u32 fuse_opt_priv_sec_en_r(void)
+{
+        return 0x00021434U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
new file mode 100644
index 00000000..4702f575
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
@@ -0,0 +1,1283 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gmmu_gp10b_h_
+#define _hw_gmmu_gp10b_h_
+
+static inline u32 gmmu_new_pde_is_pte_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_is_pte_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_aperture_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_aperture_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_pde_address_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 8U;
+}
+static inline u32 gmmu_new_pde_address_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_vol_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_vol_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_pde_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_new_pde__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_dual_pde_is_pte_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 8U;
+}
+static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_dual_pde__size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gmmu_new_pte__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_pte_valid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_valid_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_new_pte_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_privilege_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_privilege_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gmmu_new_pte_privilege_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_address_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 8U;
+}
+static inline u32 gmmu_new_pte_address_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_address_vid_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_pte_address_vid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_vol_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_vol_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_pte_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_aperture_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_pte_read_only_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_read_only_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gmmu_new_pte_comptagline_f(u32 v)
+{
+        return (v & 0x3ffffU) << 4U;
+}
+static inline u32 gmmu_new_pte_comptagline_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_new_pte_kind_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gmmu_new_pte_kind_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_new_pte_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_f(u32 v)
+{
+        return (v & 0xffU) << 4U;
+}
+static inline u32 gmmu_pte_kind_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_kind_invalid_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 gmmu_pte_kind_pitch_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gmmu_pte_kind_z16_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gmmu_pte_kind_z16_2c_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 gmmu_pte_kind_z16_2z_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 gmmu_pte_kind_z16_2cz_v(void)
+{
+        return 0x00000036U;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
+{
+        return 0x00000037U;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
+{
+        return 0x00000038U;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
+{
+        return 0x00000039U;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
+{
+        return 0x0000005fU;
+}
+static inline u32 gmmu_pte_kind_z16_4cz_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gmmu_pte_kind_s8z24_v(void)
+{
+        return 0x00000011U;
+}
+static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
+{
+        return 0x00000012U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
+{
+        return 0x00000013U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
+{
+        return 0x00000014U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
+{
+        return 0x00000017U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
+{
+        return 0x00000019U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
+{
+        return 0x0000001aU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
+{
+        return 0x0000001bU;
+}
+static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
+{
+        return 0x0000001dU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
+{
+        return 0x0000001eU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
+{
+        return 0x0000001fU;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
+{
+        return 0x00000021U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
+{
+        return 0x00000022U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
+{
+        return 0x00000023U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
+{
+        return 0x00000024U;
+}
+static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
+{
+        return 0x00000026U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
+{
+        return 0x00000027U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
+{
+        return 0x00000029U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
+{
+        return 0x0000002eU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
+{
+        return 0x0000002fU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
+{
+        return 0x00000033U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
+{
+        return 0x00000034U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
+{
+        return 0x00000035U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
+{
+        return 0x0000003aU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
+{
+        return 0x0000003bU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
+{
+        return 0x0000003dU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
+{
+        return 0x0000003eU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
+{
+        return 0x0000003fU;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
+{
+        return 0x00000041U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000042U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000043U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000044U;
+}
+static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
+{
+        return 0x00000045U;
+}
+static inline u32 gmmu_pte_kind_z24s8_v(void)
+{
+        return 0x00000046U;
+}
+static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
+{
+        return 0x00000047U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
+{
+        return 0x00000048U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
+{
+        return 0x00000049U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
+{
+        return 0x0000004aU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
+{
+        return 0x0000004bU;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
+{
+        return 0x0000004dU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
+{
+        return 0x0000004eU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
+{
+        return 0x0000004fU;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
+{
+        return 0x00000050U;
+}
+static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
+{
+        return 0x00000051U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
+{
+        return 0x00000052U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
+{
+        return 0x00000053U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
+{
+        return 0x00000054U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
+{
+        return 0x00000055U;
+}
+static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
+{
+        return 0x00000056U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
+{
+        return 0x00000057U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
+{
+        return 0x00000058U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
+{
+        return 0x00000059U;
+}
+static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
+{
+        return 0x0000005aU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
+{
+        return 0x0000005bU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
+{
+        return 0x0000005cU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
+{
+        return 0x0000005dU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
+{
+        return 0x0000005eU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000063U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000064U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000065U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
+{
+        return 0x00000066U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
+{
+        return 0x00000067U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
+{
+        return 0x00000068U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
+{
+        return 0x00000069U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
+{
+        return 0x0000006aU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
+{
+        return 0x0000006fU;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
+{
+        return 0x00000070U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
+{
+        return 0x00000071U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
+{
+        return 0x00000072U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
+{
+        return 0x00000073U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
+{
+        return 0x00000074U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
+{
+        return 0x00000075U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
+{
+        return 0x00000076U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
+{
+        return 0x00000077U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
+{
+        return 0x00000078U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
+{
+        return 0x00000079U;
+}
+static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
+{
+        return 0x0000007aU;
+}
+static inline u32 gmmu_pte_kind_zf32_v(void)
+{
+        return 0x0000007bU;
+}
+static inline u32 gmmu_pte_kind_zf32_1z_v(void)
+{
+        return 0x0000007cU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
+{
+        return 0x0000007dU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
+{
+        return 0x0000007eU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
+{
+        return 0x0000007fU;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
+{
+        return 0x00000081U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
+{
+        return 0x00000082U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
+{
+        return 0x00000083U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
+{
+        return 0x00000084U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
+{
+        return 0x00000085U;
+}
+static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
+{
+        return 0x00000086U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
+{
+        return 0x00000087U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
+{
+        return 0x00000088U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
+{
+        return 0x00000089U;
+}
+static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
+{
+        return 0x0000008aU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x0000008bU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x0000008cU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x0000008dU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x0000008eU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x0000008fU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x00000090U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x00000091U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x00000092U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x00000097U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x00000098U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x00000099U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x0000009aU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x0000009bU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x0000009cU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x0000009dU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x0000009eU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x0000009fU;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000a1U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000a2U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000a3U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000a5U;
+}
+static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000a6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
+{
+        return 0x000000a7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
+{
+        return 0x000000a9U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
+{
+        return 0x000000aaU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
+{
+        return 0x000000abU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
+{
+        return 0x000000acU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
+{
+        return 0x000000adU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
+{
+        return 0x000000aeU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
+{
+        return 0x000000b3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
+{
+        return 0x000000b4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
+{
+        return 0x000000b5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
+{
+        return 0x000000b6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
+{
+        return 0x000000b7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
+{
+        return 0x000000b8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
+{
+        return 0x000000b9U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
+{
+        return 0x000000baU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
+{
+        return 0x000000bbU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
+{
+        return 0x000000bcU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
+{
+        return 0x000000bdU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
+{
+        return 0x000000beU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
+{
+        return 0x000000bfU;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
+{
+        return 0x000000c1U;
+}
+static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
+{
+        return 0x000000c2U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
+{
+        return 0x000000c3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
+{
+        return 0x000000c4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
+{
+        return 0x000000c5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
+{
+        return 0x000000c6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
+{
+        return 0x000000c7U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
+{
+        return 0x000000c8U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
+{
+        return 0x000000ceU;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
+{
+        return 0x000000cfU;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
+{
+        return 0x000000d0U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
+{
+        return 0x000000d1U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
+{
+        return 0x000000d2U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
+{
+        return 0x000000d3U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
+{
+        return 0x000000d4U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
+{
+        return 0x000000d5U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
+{
+        return 0x000000d6U;
+}
+static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
+{
+        return 0x000000d7U;
+}
+static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
+{
+        return 0x000000feU;
+}
+static inline u32 gmmu_pte_kind_c32_2c_v(void)
+{
+        return 0x000000d8U;
+}
+static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
+{
+        return 0x000000d9U;
+}
+static inline u32 gmmu_pte_kind_c32_2cba_v(void)
+{
+        return 0x000000daU;
+}
+static inline u32 gmmu_pte_kind_c32_2cra_v(void)
+{
+        return 0x000000dbU;
+}
+static inline u32 gmmu_pte_kind_c32_2bra_v(void)
+{
+        return 0x000000dcU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
+{
+        return 0x000000ddU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
+{
+        return 0x000000deU;
+}
+static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
+{
+        return 0x000000ccU;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
+{
+        return 0x000000dfU;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
+{
+        return 0x000000e0U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
+{
+        return 0x000000e1U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
+{
+        return 0x000000e2U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
+{
+        return 0x000000e3U;
+}
+static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
+{
+        return 0x0000002cU;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
+{
+        return 0x000000e4U;
+}
+static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
+{
+        return 0x000000e5U;
+}
+static inline u32 gmmu_pte_kind_c64_2c_v(void)
+{
+        return 0x000000e6U;
+}
+static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
+{
+        return 0x000000e7U;
+}
+static inline u32 gmmu_pte_kind_c64_2cba_v(void)
+{
+        return 0x000000e8U;
+}
+static inline u32 gmmu_pte_kind_c64_2cra_v(void)
+{
+        return 0x000000e9U;
+}
+static inline u32 gmmu_pte_kind_c64_2bra_v(void)
+{
+        return 0x000000eaU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
+{
+        return 0x000000ebU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
+{
+        return 0x000000cdU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
+{
+        return 0x000000edU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
+{
+        return 0x000000eeU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
+{
+        return 0x000000efU;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
+{
+        return 0x000000f0U;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
+{
+        return 0x000000f1U;
+}
+static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
+{
+        return 0x0000002dU;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
+{
+        return 0x000000f2U;
+}
+static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
+{
+        return 0x000000f3U;
+}
+static inline u32 gmmu_pte_kind_c128_2c_v(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 gmmu_pte_kind_c128_2cr_v(void)
+{
+        return 0x000000f5U;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
+{
+        return 0x000000f6U;
+}
+static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
+{
+        return 0x000000f7U;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
+{
+        return 0x000000f9U;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
+{
+        return 0x000000faU;
+}
+static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
+{
+        return 0x000000fbU;
+}
+static inline u32 gmmu_pte_kind_x8c24_v(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
+{
+        return 0x000000fdU;
+}
+static inline u32 gmmu_pte_kind_smsked_message_v(void)
+{
+        return 0x000000caU;
+}
+static inline u32 gmmu_pte_kind_smhost_message_v(void)
+{
+        return 0x000000cbU;
+}
+static inline u32 gmmu_pte_kind_s8_v(void)
+{
+        return 0x0000002aU;
+}
+static inline u32 gmmu_pte_kind_s8_2s_v(void)
+{
+        return 0x0000002bU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
new file mode 100644
index 00000000..51809112
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -0,0 +1,4363 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gr_gp10b_h_
+#define _hw_gr_gp10b_h_
+
+static inline u32 gr_intr_r(void)
+{
+        return 0x00400100U;
+}
+static inline u32 gr_intr_notify_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_notify_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_semaphore_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_semaphore_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_illegal_method_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_method_reset_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_notify_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_illegal_notify_reset_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 gr_intr_firmware_method_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_firmware_method_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_illegal_class_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_illegal_class_reset_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_fecs_error_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_fecs_error_reset_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_class_error_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_class_error_reset_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_exception_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_intr_exception_reset_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_fecs_intr_r(void)
+{
+        return 0x00400144U;
+}
+static inline u32 gr_class_error_r(void)
+{
+        return 0x00400110U;
+}
+static inline u32 gr_class_error_code_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_intr_nonstall_r(void)
+{
+        return 0x00400120U;
+}
+static inline u32 gr_intr_nonstall_trap_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_en_r(void)
+{
+        return 0x0040013cU;
+}
+static inline u32 gr_exception_r(void)
+{
+        return 0x00400108U;
+}
+static inline u32 gr_exception_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception_gpc_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 gr_exception_memfmt_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_exception_ds_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_exception_sked_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 gr_exception1_r(void)
+{
+        return 0x00400118U;
+}
+static inline u32 gr_exception1_gpc_0_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_exception2_r(void)
+{
+        return 0x0040011cU;
+}
+static inline u32 gr_exception_en_r(void)
+{
+        return 0x00400138U;
+}
+static inline u32 gr_exception_en_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception1_en_r(void)
+{
+        return 0x00400130U;
+}
+static inline u32 gr_exception2_en_r(void)
+{
+        return 0x00400134U;
+}
+static inline u32 gr_gpfifo_ctl_r(void)
+{
+        return 0x00400500U;
+}
+static inline u32 gr_gpfifo_ctl_access_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpfifo_status_r(void)
+{
+        return 0x00400504U;
+}
+static inline u32 gr_trapped_addr_r(void)
+{
+        return 0x00400704U;
+}
+static inline u32 gr_trapped_addr_mthd_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 gr_trapped_addr_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_datahigh_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_priv_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_status_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_trapped_data_lo_r(void)
+{
+        return 0x00400708U;
+}
+static inline u32 gr_trapped_data_hi_r(void)
+{
+        return 0x0040070cU;
+}
+static inline u32 gr_trapped_data_mme_r(void)
+{
+        return 0x00400710U;
+}
+static inline u32 gr_trapped_data_mme_pc_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_status_r(void)
+{
+        return 0x00400700U;
+}
+static inline u32 gr_status_fe_method_upper_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_status_fe_gi_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 gr_status_mask_r(void)
+{
+        return 0x00400610U;
+}
+static inline u32 gr_status_1_r(void)
+{
+        return 0x00400604U;
+}
+static inline u32 gr_status_2_r(void)
+{
+        return 0x00400608U;
+}
+static inline u32 gr_engine_status_r(void)
+{
+        return 0x0040060cU;
+}
+static inline u32 gr_engine_status_value_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+        return 0x00410204U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+        return 0x00410208U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+        return 0x00502c94U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_activity_0_r(void)
+{
+        return 0x00400380U;
+}
+static inline u32 gr_activity_1_r(void)
+{
+        return 0x00400384U;
+}
+static inline u32 gr_activity_2_r(void)
+{
+        return 0x00400388U;
+}
+static inline u32 gr_activity_4_r(void)
+{
+        return 0x00400390U;
+}
+static inline u32 gr_activity_4_gpc0_s(void)
+{
+        return 3U;
+}
+static inline u32 gr_activity_4_gpc0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_activity_4_gpc0_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 gr_activity_4_gpc0_v(u32 r)
+{
+        return (r >> 0U) & 0x7U;
+}
+static inline u32 gr_activity_4_gpc0_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_activity_4_gpc0_preempted_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
+{
+        return 0x00501000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
+{
+        return 0x00419000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
+{
+        return 0x005046a4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
+{
+        return 0x00419ea4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_pri_sked_activity_r(void)
+{
+        return 0x00407054U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
+{
+        return 0x00502c80U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
+{
+        return 0x00502c84U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
+{
+        return 0x00502c88U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
+{
+        return 0x00502c8cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504500U;
+}
+static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504d00U;
+}
+static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00501d00U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
+{
+        return 0x0041ac80U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
+{
+        return 0x0041ac84U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
+{
+        return 0x0041ac88U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
+{
+        return 0x0041ac8cU;
+}
+static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041c500U;
+}
+static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041cd00U;
+}
+static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00419d00U;
+}
+static inline u32 gr_pri_be0_becs_be_activity0_r(void)
+{
+        return 0x00410200U;
+}
+static inline u32 gr_pri_be1_becs_be_activity0_r(void)
+{
+        return 0x00410600U;
+}
+static inline u32 gr_pri_bes_becs_be_activity0_r(void)
+{
+        return 0x00408a00U;
+}
+static inline u32 gr_pri_ds_mpipe_status_r(void)
+{
+        return 0x00405858U;
+}
+static inline u32 gr_pri_fe_go_idle_info_r(void)
+{
+        return 0x00404194U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
+{
+        return 0x00504238U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
+{
+        return 0x005046b8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_b(void)
+{
+        return 4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_b(void)
+{
+        return 8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
+{
+        return 0x005044a0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
+{
+        return 0x005046bcU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
+{
+        return 0x005046c0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
+{
+        return 0x005044a4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
+{
+        return 0x005042c4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void)
+{
+        return 0x00504218U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void)
+{
+        return 0xffffU << 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void)
+{
+        return 0x005042ecU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void)
+{
+        return 0xffffU << 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 gr_pri_be0_crop_status1_r(void)
+{
+        return 0x00410134U;
+}
+static inline u32 gr_pri_bes_crop_status1_r(void)
+{
+        return 0x00408934U;
+}
+static inline u32 gr_pri_be0_zrop_status_r(void)
+{
+        return 0x00410048U;
+}
+static inline u32 gr_pri_be0_zrop_status2_r(void)
+{
+        return 0x0041004cU;
+}
+static inline u32 gr_pri_bes_zrop_status_r(void)
+{
+        return 0x00408848U;
+}
+static inline u32 gr_pri_bes_zrop_status2_r(void)
+{
+        return 0x0040884cU;
+}
+static inline u32 gr_pipe_bundle_address_r(void)
+{
+        return 0x00400200U;
+}
+static inline u32 gr_pipe_bundle_address_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pipe_bundle_data_r(void)
+{
+        return 0x00400204U;
+}
+static inline u32 gr_pipe_bundle_config_r(void)
+{
+        return 0x00400208U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_hww_esr_r(void)
+{
+        return 0x00404000U;
+}
+static inline u32 gr_fe_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_fe_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_go_idle_timeout_r(void)
+{
+        return 0x00404154U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
+{
+        return 0x7fffffffU;
+}
+static inline u32 gr_fe_object_table_r(u32 i)
+{
+        return 0x00404200U + i*4U;
+}
+static inline u32 gr_fe_object_table_nvclass_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_fe_tpc_fs_r(void)
+{
+        return 0x004041c4U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_r(void)
+{
+        return 0x00404488U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pri_mme_shadow_raw_data_r(void)
+{
+        return 0x0040448cU;
+}
+static inline u32 gr_mme_hww_esr_r(void)
+{
+        return 0x00404490U;
+}
+static inline u32 gr_mme_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_mme_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_memfmt_hww_esr_r(void)
+{
+        return 0x00404600U;
+}
+static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fecs_cpuctl_r(void)
+{
+        return 0x00409100U;
+}
+static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_cpuctl_alias_r(void)
+{
+        return 0x00409130U;
+}
+static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_dmactl_r(void)
+{
+        return 0x0040910cU;
+}
+static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_fecs_os_r(void)
+{
+        return 0x00409080U;
+}
+static inline u32 gr_fecs_idlestate_r(void)
+{
+        return 0x0040904cU;
+}
+static inline u32 gr_fecs_mailbox0_r(void)
+{
+        return 0x00409040U;
+}
+static inline u32 gr_fecs_mailbox1_r(void)
+{
+        return 0x00409044U;
+}
+static inline u32 gr_fecs_irqstat_r(void)
+{
+        return 0x00409008U;
+}
+static inline u32 gr_fecs_irqmode_r(void)
+{
+        return 0x0040900cU;
+}
+static inline u32 gr_fecs_irqmask_r(void)
+{
+        return 0x00409018U;
+}
+static inline u32 gr_fecs_irqdest_r(void)
+{
+        return 0x0040901cU;
+}
+static inline u32 gr_fecs_curctx_r(void)
+{
+        return 0x00409050U;
+}
+static inline u32 gr_fecs_nxtctx_r(void)
+{
+        return 0x00409054U;
+}
+static inline u32 gr_fecs_engctl_r(void)
+{
+        return 0x004090a4U;
+}
+static inline u32 gr_fecs_debug1_r(void)
+{
+        return 0x00409090U;
+}
+static inline u32 gr_fecs_debuginfo_r(void)
+{
+        return 0x00409094U;
+}
+static inline u32 gr_fecs_icd_cmd_r(void)
+{
+        return 0x00409200U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 gr_fecs_icd_rdata_r(void)
+{
+        return 0x0040920cU;
+}
+static inline u32 gr_fecs_imemc_r(u32 i)
+{
+        return 0x00409180U + i*16U;
+}
+static inline u32 gr_fecs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_imemd_r(u32 i)
+{
+        return 0x00409184U + i*16U;
+}
+static inline u32 gr_fecs_imemt_r(u32 i)
+{
+        return 0x00409188U + i*16U;
+}
+static inline u32 gr_fecs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_dmemc_r(u32 i)
+{
+        return 0x004091c0U + i*8U;
+}
+static inline u32 gr_fecs_dmemc_offs_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_v(u32 r)
+{
+        return (r >> 2U) & 0x3fU;
+}
+static inline u32 gr_fecs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_dmemd_r(u32 i)
+{
+        return 0x004091c4U + i*8U;
+}
+static inline u32 gr_fecs_dmatrfbase_r(void)
+{
+        return 0x00409110U;
+}
+static inline u32 gr_fecs_dmatrfmoffs_r(void)
+{
+        return 0x00409114U;
+}
+static inline u32 gr_fecs_dmatrffboffs_r(void)
+{
+        return 0x0040911cU;
+}
+static inline u32 gr_fecs_dmatrfcmd_r(void)
+{
+        return 0x00409118U;
+}
+static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_fecs_bootvec_r(void)
+{
+        return 0x00409104U;
+}
+static inline u32 gr_fecs_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_falcon_hwcfg_r(void)
+{
+        return 0x00409108U;
+}
+static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
+{
+        return 0x0041a108U;
+}
+static inline u32 gr_fecs_falcon_rm_r(void)
+{
+        return 0x00409084U;
+}
+static inline u32 gr_fecs_current_ctx_r(void)
+{
+        return 0x00409b00U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_current_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_current_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_current_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_method_data_r(void)
+{
+        return 0x00409500U;
+}
+static inline u32 gr_fecs_method_push_r(void)
+{
+        return 0x00409504U;
+}
+static inline u32 gr_fecs_method_push_adr_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
+{
+        return 0x00000038U;
+}
+static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
+{
+        return 0x00000039U;
+}
+static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
+{
+        return 0x21U;
+}
+static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void)
+{
+        return 0x0000003dU;
+}
+static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
+{
+        return 0x0000001aU;
+}
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void)
+{
+        return 0x0000003aU;
+}
+static inline u32 gr_fecs_host_int_status_r(void)
+{
+        return 0x00409c18U;
+}
+static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_host_int_clear_r(void)
+{
+        return 0x00409c20U;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fecs_host_int_enable_r(void)
+{
+        return 0x00409c24U;
+}
+static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
+{
+        return 0x00409614U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
+{
+        return (r >> 10U) & 0x1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
+{
+        return 0x0040960cU;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x00409800U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
+{
+        return 0x004098c0U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
+{
+        return 0x00409840U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_fs_r(void)
+{
+        return 0x00409604U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_m(void)
+{
+        return 0x1fU << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_fecs_cfg_r(void)
+{
+        return 0x00409620U;
+}
+static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_fecs_rc_lanes_r(void)
+{
+        return 0x00409880U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_fecs_ctxsw_status_1_r(void)
+{
+        return 0x00409400U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_adr_r(void)
+{
+        return 0x00409a24U;
+}
+static inline u32 gr_fecs_new_ctx_r(void)
+{
+        return 0x00409b04U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_new_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_new_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_new_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_r(void)
+{
+        return 0x00409a0cU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_r(void)
+{
+        return 0x00409a10U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
+{
+        return 0x00409c00U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
+{
+        return 0x00502c04U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
+{
+        return 0x00502400U;
+}
+static inline u32 gr_fecs_ctxsw_idlestate_r(void)
+{
+        return 0x00409420U;
+}
+static inline u32 gr_fecs_feature_override_ecc_r(void)
+{
+        return 0x00409658U;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r)
+{
+        return (r >> 11U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
+{
+        return 0x00502420U;
+}
+static inline u32 gr_rstr2d_gpc_map0_r(void)
+{
+        return 0x0040780cU;
+}
+static inline u32 gr_rstr2d_gpc_map1_r(void)
+{
+        return 0x00407810U;
+}
+static inline u32 gr_rstr2d_gpc_map2_r(void)
+{
+        return 0x00407814U;
+}
+static inline u32 gr_rstr2d_gpc_map3_r(void)
+{
+        return 0x00407818U;
+}
+static inline u32 gr_rstr2d_gpc_map4_r(void)
+{
+        return 0x0040781cU;
+}
+static inline u32 gr_rstr2d_gpc_map5_r(void)
+{
+        return 0x00407820U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_r(void)
+{
+        return 0x004078bcU;
+}
+static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_hww_esr_r(void)
+{
+        return 0x00406018U;
+}
+static inline u32 gr_pd_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_pd_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00406028U + i*4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
+{
+        return (v & 0xfU) << 12U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
+{
+        return (v & 0xfU) << 24U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
+{
+        return (v & 0xfU) << 28U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_r(void)
+{
+        return 0x004064c0U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_r(void)
+{
+        return 0x004064c4U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
+{
+        return 0xffffU;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_r(void)
+{
+        return 0x004064c8U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
+{
+        return (v & 0x1fffU) << 0U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
+{
+        return 0x000001c0U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
+{
+        return (v & 0x1fffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
+{
+        return 0x00000182U;
+}
+static inline u32 gr_pd_dist_skip_table_r(u32 i)
+{
+        return 0x004064d0U + i*4U;
+}
+static inline u32 gr_pd_dist_skip_table__size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gr_ds_debug_r(void)
+{
+        return 0x00405800U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 gr_ds_zbc_color_r_r(void)
+{
+        return 0x00405804U;
+}
+static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_g_r(void)
+{
+        return 0x00405808U;
+}
+static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_b_r(void)
+{
+        return 0x0040580cU;
+}
+static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_a_r(void)
+{
+        return 0x00405810U;
+}
+static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_r(void)
+{
+        return 0x00405814U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
+{
+        return (v & 0x7fU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gr_ds_zbc_z_r(void)
+{
+        return 0x00405818U;
+}
+static inline u32 gr_ds_zbc_z_val_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_ds_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_ds_zbc_z_val__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_ds_zbc_z_val__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_r(void)
+{
+        return 0x0040581cU;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_tbl_index_r(void)
+{
+        return 0x00405820U;
+}
+static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_r(void)
+{
+        return 0x00405824U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
+{
+        return 0x00405830U;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
+{
+        return 0x0040585cU;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_ds_hww_esr_r(void)
+{
+        return 0x00405840U;
+}
+static inline u32 gr_ds_hww_esr_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_esr_2_r(void)
+{
+        return 0x00405848U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_report_mask_r(void)
+{
+        return 0x00405844U;
+}
+static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_ds_hww_report_mask_2_r(void)
+{
+        return 0x0040584cU;
+}
+static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00405870U + i*4U;
+}
+static inline u32 gr_scc_bundle_cb_base_r(void)
+{
+        return 0x00408004U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_bundle_cb_size_r(void)
+{
+        return 0x00408008U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_pagepool_base_r(void)
+{
+        return 0x0040800cU;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_pagepool_r(void)
+{
+        return 0x00408010U;
+}
+static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
+{
+        return 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
+{
+        return 0x3ffU << 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
+{
+        return (r >> 10U) & 0x3ffU;
+}
+static inline u32 gr_scc_pagepool_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_init_r(void)
+{
+        return 0x0040802cU;
+}
+static inline u32 gr_scc_init_ram_trigger_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_scc_hww_esr_r(void)
+{
+        return 0x00408030U;
+}
+static inline u32 gr_scc_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_scc_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_sked_hww_esr_r(void)
+{
+        return 0x00407020U;
+}
+static inline u32 gr_sked_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_cwd_fs_r(void)
+{
+        return 0x00405b00U;
+}
+static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
+{
+        return 0x00405b60U + i*4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_cwd_sm_id_r(u32 i)
+{
+        return 0x00405ba0U + i*4U;
+}
+static inline u32 gr_cwd_sm_id__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpc0_fs_gpc_r(void)
+{
+        return 0x00502608U;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_gpc0_cfg_r(void)
+{
+        return 0x00502620U;
+}
+static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpccs_rc_lanes_r(void)
+{
+        return 0x00502880U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_rc_lane_size_r(void)
+{
+        return 0x00502910U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_s(void)
+{
+        return 24U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_zcull_fs_r(void)
+{
+        return 0x00500910U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_r(void)
+{
+        return 0x00500914U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
+{
+        return 0x00500918U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
+{
+        return 0x00800000U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
+{
+        return 0x00500920U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
+{
+        return 0x00500a04U + i*32U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
+{
+        return 0x00500c10U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
+{
+        return 0x00500c30U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
+{
+        return 0x00504088U;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
+{
+        return 0x00504698U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
+{
+        return 0x0050469cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
+{
+        return (r >> 8U) & 0xfffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
+{
+        return (r >> 20U) & 0xfffU;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
+{
+        return 0x00503018U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
+{
+        return 0x005030c0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
+{
+        return 0x3fffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
+{
+        return 0x00030000U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
+{
+        return 0x00030a00U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
+{
+        return 0x005030f4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
+{
+        return 0x005030e4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
+{
+        return 0x005030f8U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
+{
+        return 0x005030f0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
+{
+        return 0x00030000U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
+{
+        return 0x00419b00U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
+{
+        return 0x00419b04U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
+{
+        return 21U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
+{
+        return (v & 0x1fffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
+{
+        return 0x1fffffU << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
+{
+        return (r >> 0U) & 0x1fffffU;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void)
+{
+        return 0x00419a3cU;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpccs_falcon_addr_r(void)
+{
+        return 0x0041a0acU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
+{
+        return (r >> 6U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_s(void)
+{
+        return 12U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_m(void)
+{
+        return 0xfffU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_gpccs_cpuctl_r(void)
+{
+        return 0x0041a100U;
+}
+static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_gpccs_dmactl_r(void)
+{
+        return 0x0041a10cU;
+}
+static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpccs_imemc_r(u32 i)
+{
+        return 0x0041a180U + i*16U;
+}
+static inline u32 gr_gpccs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_imemd_r(u32 i)
+{
+        return 0x0041a184U + i*16U;
+}
+static inline u32 gr_gpccs_imemt_r(u32 i)
+{
+        return 0x0041a188U + i*16U;
+}
+static inline u32 gr_gpccs_imemt__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_gpccs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpccs_dmemc_r(u32 i)
+{
+        return 0x0041a1c0U + i*8U;
+}
+static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_dmemd_r(u32 i)
+{
+        return 0x0041a1c4U + i*8U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x0041a800U + i*4U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
+{
+        return 0x00418e24U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
+{
+        return 0x00418e28U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
+{
+        return 11U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
+{
+        return 0x7ffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
+{
+        return (r >> 0U) & 0x7ffU;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
+{
+        return 0x18U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
+{
+        return 0x00500ee4U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
+{
+        return 0x00000250U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
+{
+        return 0x00500ee0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
+{
+        return 0x00418eecU;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
+{
+        return 0x0041befcU;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
+{
+        return 0x00418ea0U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
+{
+        return 0x3fffffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
+{
+        return 0x00418010U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
+{
+        return 0x0041804cU + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
+{
+        return 0x00418088U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
+{
+        return 0x004180c4U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
+{
+        return 0x00500100U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
+{
+        return 0x00418110U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
+{
+        return 0x0050014cU;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
+{
+        return 0x00418810U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_crstr_gpc_map0_r(void)
+{
+        return 0x00418b08U;
+}
+static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map1_r(void)
+{
+        return 0x00418b0cU;
+}
+static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map2_r(void)
+{
+        return 0x00418b10U;
+}
+static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map3_r(void)
+{
+        return 0x00418b14U;
+}
+static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map4_r(void)
+{
+        return 0x00418b18U;
+}
+static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_gpc_map5_r(void)
+{
+        return 0x00418b1cU;
+}
+static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
+{
+        return (v & 0x7U) << 5U;
+}
+static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
+{
+        return (v & 0x7U) << 15U;
+}
+static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
+{
+        return (v & 0x7U) << 25U;
+}
+static inline u32 gr_crstr_map_table_cfg_r(void)
+{
+        return 0x00418bb8U;
+}
+static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
+{
+        return 0x00418980U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
+{
+        return 0x00418984U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
+{
+        return 0x00418988U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
+{
+        return 3U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
+{
+        return 0x7U << 28U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
+{
+        return (r >> 28U) & 0x7U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
+{
+        return 0x0041898cU;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
+{
+        return 0x00418c6cU;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
+{
+        return 0x00419004U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_r(void)
+{
+        return 0x00419008U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
+{
+        return 0x0041980cU;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
+{
+        return 0x00419848U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
+{
+        return 0x00419c00U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
+{
+        return 0x00419c2cU;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00419e44U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00504644U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x00419e4cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void)
+{
+        return 0x0050464cU;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
+{
+        return 0x00419d0cU;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
+{
+        return 0x0041ac94U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
+{
+        return 0x00504610U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
+{
+        return 0x00504614U;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
+{
+        return 0x00504618U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00504624U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
+{
+        return 0x00504628U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
+{
+        return 0x00504634U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
+{
+        return 0x00504638U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
+{
+        return 0x00419e24U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
+{
+        return 0x0050460cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
+{
+        return 0x00419e50U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
+{
+        return 0x00504650U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
+{
+        return 0x00504224U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
+{
+        return 0x00504648U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void)
+{
+        return 0x7U << 25U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
+{
+        return 0x00504654U;
+}
+static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
+{
+        return 0x00504770U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
+{
+        return 0x00419f70U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
+{
+        return 0x0050477cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
+{
+        return 0x00419f7cU;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
+{
+        return 0x0041be08U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
+{
+        return 0x0041bf00U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
+{
+        return 0x0041bf04U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
+{
+        return 0x0041bf08U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
+{
+        return 0x0041bf0cU;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
+{
+        return 0x0041bf10U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
+{
+        return 0x0041bf14U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
+{
+        return 0x0041bfd0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
+{
+        return (v & 0x7U) << 21U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 24U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
+{
+        return 0x0041bfd4U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
+{
+        return 0x0041bfe4U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 5U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 10U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 15U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 20U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
+{
+        return (v & 0x1fU) << 25U;
+}
+static inline u32 gr_bes_zrop_settings_r(void)
+{
+        return 0x00408850U;
+}
+static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_be0_crop_debug3_r(void)
+{
+        return 0x00410108U;
+}
+static inline u32 gr_bes_crop_debug3_r(void)
+{
+        return 0x00408908U;
+}
+static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_bes_crop_settings_r(void)
+{
+        return 0x00408958U;
+}
+static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gr_zcull_subregion_qty_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
+{
+        return 0x00504604U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
+{
+        return 0x00504608U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
+{
+        return 0x0050465cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
+{
+        return 0x00504660U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
+{
+        return 0x00504664U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
+{
+        return 0x00504668U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
+{
+        return 0x0050466cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
+{
+        return 0x00504658U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
+{
+        return 0x00504730U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
+{
+        return 0x00504734U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
+{
+        return 0x00504738U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
+{
+        return 0x0050473cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
+{
+        return 0x00504740U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
+{
+        return 0x00504744U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
+{
+        return 0x00504748U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
+{
+        return 0x0050474cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
+{
+        return 0x00504678U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
+{
+        return 0x00504694U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
+{
+        return 0x005046f0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
+{
+        return 0x00504700U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
+{
+        return 0x005046f4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
+{
+        return 0x00504704U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
+{
+        return 0x005046f8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
+{
+        return 0x00504708U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
+{
+        return 0x005046fcU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
+{
+        return 0x0050470cU;
+}
+static inline u32 gr_fe_pwr_mode_r(void)
+{
+        return 0x00404170U;
+}
+static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fe_pwr_mode_req_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_fe_pwr_mode_req_send_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fe_pwr_mode_req_done_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
+{
+        return 0x00418880U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
+{
+        return 0x3U << 3U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
+{
+        return 0x3U << 5U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
+{
+        return 0x00418890U;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
+{
+        return 0x00418894U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
+{
+        return 0x004188b0U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
+{
+        return 0x004188b4U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
+{
+        return 0x004188b8U;
+}
+static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
+{
+        return 0x004188acU;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
+{
+        return 0x00419e10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
+{
+        return 0x004041c0U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_debug_2_r(void)
+{
+        return 0x00400088U;
+}
+static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_m(void)
+{
+        return 0x1U << 23U;
+}
+static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_v(u32 r)
+{
+        return (r >> 23U) & 0x1U;
+}
+static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
+{
+        return 0x00419c84U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
+{
+        return 0x7U << 8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
+{
+        return 0x00419f78U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
+{
+        return 0x3U << 11U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_gpcs_tc_debug0_r(void)
+{
+        return 0x00418708U;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 gr_gpc0_prop_debug1_r(void)
+{
+        return 0x00500400U;
+}
+static inline u32 gr_gpc0_prop_debug1_czf_bypass_f(u32 v)
+{
+        return (v & 0x3U) << 14U;
+}
+static inline u32 gr_gpc0_prop_debug1_czf_bypass_m(void)
+{
+        return 0x3U << 14U;
+}
+static inline u32 gr_gpc0_prop_debug1_czf_bypass_init_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
new file mode 100644
index 00000000..721a48ae
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
@@ -0,0 +1,587 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ltc_gp10b_h_
+#define _hw_ltc_gp10b_h_
+
+static inline u32 ltc_pltcg_base_v(void)
+{
+        return 0x00140000U;
+}
+static inline u32 ltc_pltcg_extent_v(void)
+{
+        return 0x0017ffffU;
+}
+static inline u32 ltc_ltc0_ltss_v(void)
+{
+        return 0x00140200U;
+}
+static inline u32 ltc_ltc0_lts0_v(void)
+{
+        return 0x00140400U;
+}
+static inline u32 ltc_ltcs_ltss_v(void)
+{
+        return 0x0017e200U;
+}
+static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+        return 0x00140518U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+        return 0x0017e318U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
+{
+        return 0x00140494U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
+{
+        return (r >> 16U) & 0x3U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
+{
+        return 0x0017e26cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
+{
+        return 0x0017e270U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
+{
+        return (v & 0x3ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
+{
+        return 0x0017e274U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
+{
+        return (v & 0x3ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
+{
+        return 0x0003ffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
+{
+        return 0x0017e278U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
+{
+        return (r >> 0U) & 0x3ffffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
+{
+        return 0x0017e27cU;
+}
+static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
+{
+        return 0x0017e000U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
+{
+        return 0x0017e280U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
+{
+        return (r >> 28U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
+{
+        return 0x0017e3f4U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
+{
+        return 0x0017e2acU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
+{
+        return 0x0017e338U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
+{
+        return 0x0017e33cU + i*4U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
+{
+        return 0x0017e34cU;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
+{
+        return 32U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
+{
+        return 0x0017e2b0U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
+{
+        return 0x0017e214U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
+{
+        return 0x00140214U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
+{
+        return 0x00142214U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+        return 0x0017e20cU;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+        return 0x0014040cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
+{
+        return 0x0014051cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x0017e2a0U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x0017e2a4U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001402a0U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001402a4U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001422a0U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001422a4U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
+{
+        return 0x0014058cU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 ltc_ltca_g_axi_pctrl_r(void)
+{
+        return 0x00160000U;
+}
+static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
+{
+        return (v & 0xffU) << 2U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
new file mode 100644
index 00000000..dbf0ce35
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_mc_gp10b_h_
+#define _hw_mc_gp10b_h_
+
+static inline u32 mc_boot_0_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_boot_0_architecture_v(u32 r)
+{
+        return (r >> 24U) & 0x1fU;
+}
+static inline u32 mc_boot_0_implementation_v(u32 r)
+{
+        return (r >> 20U) & 0xfU;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 mc_intr_r(u32 i)
+{
+        return 0x00000100U + i*4U;
+}
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_intr_replayable_fault_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 mc_intr_pgraph_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_ltc_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 mc_intr_priv_ring_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 mc_intr_pbus_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_intr_en_r(u32 i)
+{
+        return 0x00000140U + i*4U;
+}
+static inline u32 mc_intr_en_set_r(u32 i)
+{
+        return 0x00000160U + i*4U;
+}
+static inline u32 mc_intr_en_clear_r(u32 i)
+{
+        return 0x00000180U + i*4U;
+}
+static inline u32 mc_enable_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 mc_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_enable_l2_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 mc_enable_pmedia_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pmedia_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 mc_enable_pmedia_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 mc_enable_pmedia_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 mc_enable_priv_ring_enabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 mc_enable_ce0_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 mc_enable_pfifo_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_enable_pgraph_enabled_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_enable_pwr_v(u32 r)
+{
+        return (r >> 13U) & 0x1U;
+}
+static inline u32 mc_enable_pwr_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_enable_pwr_enabled_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 mc_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_enable_ce2_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 mc_enable_ce2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 mc_enable_blg_enabled_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 mc_enable_perfmon_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 mc_intr_ltc_r(void)
+{
+        return 0x000001c0U;
+}
+static inline u32 mc_enable_pb_r(void)
+{
+        return 0x00000204U;
+}
+static inline u32 mc_enable_pb_0_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pb_0_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 mc_enable_pb_0_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 mc_enable_pb_0_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 mc_enable_pb_0_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 mc_elpg_enable_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 mc_elpg_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_elpg_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_elpg_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
new file mode 100644
index 00000000..4f45f824
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
@@ -0,0 +1,607 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pbdma_gp10b_h_
+#define _hw_pbdma_gp10b_h_
+
+static inline u32 pbdma_gp_entry1_r(void)
+{
+        return 0x10000004U;
+}
+static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pbdma_gp_entry1_length_f(u32 v)
+{
+        return (v & 0x1fffffU) << 10U;
+}
+static inline u32 pbdma_gp_entry1_length_v(u32 r)
+{
+        return (r >> 10U) & 0x1fffffU;
+}
+static inline u32 pbdma_gp_base_r(u32 i)
+{
+        return 0x00040048U + i*8192U;
+}
+static inline u32 pbdma_gp_base__size_1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pbdma_gp_base_offset_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 3U;
+}
+static inline u32 pbdma_gp_base_rsvd_s(void)
+{
+        return 3U;
+}
+static inline u32 pbdma_gp_base_hi_r(u32 i)
+{
+        return 0x0004004cU + i*8192U;
+}
+static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 pbdma_gp_fetch_r(u32 i)
+{
+        return 0x00040050U + i*8192U;
+}
+static inline u32 pbdma_gp_get_r(u32 i)
+{
+        return 0x00040014U + i*8192U;
+}
+static inline u32 pbdma_gp_put_r(u32 i)
+{
+        return 0x00040000U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_r(u32 i)
+{
+        return 0x00040054U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_hi_r(u32 i)
+{
+        return 0x00040058U + i*8192U;
+}
+static inline u32 pbdma_get_r(u32 i)
+{
+        return 0x00040018U + i*8192U;
+}
+static inline u32 pbdma_get_hi_r(u32 i)
+{
+        return 0x0004001cU + i*8192U;
+}
+static inline u32 pbdma_put_r(u32 i)
+{
+        return 0x0004005cU + i*8192U;
+}
+static inline u32 pbdma_put_hi_r(u32 i)
+{
+        return 0x00040060U + i*8192U;
+}
+static inline u32 pbdma_formats_r(u32 i)
+{
+        return 0x0004009cU + i*8192U;
+}
+static inline u32 pbdma_formats_gp_fermi0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_formats_pb_fermi1_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_formats_mp_fermi0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_r(u32 i)
+{
+        return 0x00040084U + i*8192U;
+}
+static inline u32 pbdma_pb_header_priv_user_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_method_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_subchannel_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_level_main_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_pb_header_type_inc_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_pb_header_type_non_inc_f(void)
+{
+        return 0x60000000U;
+}
+static inline u32 pbdma_hdr_shadow_r(u32 i)
+{
+        return 0x00040118U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_0_r(u32 i)
+{
+        return 0x00040110U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_1_r(u32 i)
+{
+        return 0x00040114U + i*8192U;
+}
+static inline u32 pbdma_subdevice_r(u32 i)
+{
+        return 0x00040094U + i*8192U;
+}
+static inline u32 pbdma_subdevice_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 pbdma_subdevice_status_active_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_method0_r(u32 i)
+{
+        return 0x000400c0U + i*8192U;
+}
+static inline u32 pbdma_method0_fifo_size_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pbdma_method0_addr_f(u32 v)
+{
+        return (v & 0xfffU) << 2U;
+}
+static inline u32 pbdma_method0_addr_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 pbdma_method0_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 pbdma_method0_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_method0_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_method1_r(u32 i)
+{
+        return 0x000400c8U + i*8192U;
+}
+static inline u32 pbdma_method2_r(u32 i)
+{
+        return 0x000400d0U + i*8192U;
+}
+static inline u32 pbdma_method3_r(u32 i)
+{
+        return 0x000400d8U + i*8192U;
+}
+static inline u32 pbdma_data0_r(u32 i)
+{
+        return 0x000400c4U + i*8192U;
+}
+static inline u32 pbdma_target_r(u32 i)
+{
+        return 0x000400acU + i*8192U;
+}
+static inline u32 pbdma_target_engine_sw_f(void)
+{
+        return 0x1fU;
+}
+static inline u32 pbdma_acquire_r(u32 i)
+{
+        return 0x00040030U + i*8192U;
+}
+static inline u32 pbdma_acquire_retry_man_2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_acquire_retry_exp_2_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
+{
+        return (v & 0xfU) << 11U;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_f(void)
+{
+        return 0x7800U;
+}
+static inline u32 pbdma_acquire_timeout_man_f(u32 v)
+{
+        return (v & 0xffffU) << 15U;
+}
+static inline u32 pbdma_acquire_timeout_man_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 pbdma_acquire_timeout_man_max_f(void)
+{
+        return 0x7fff8000U;
+}
+static inline u32 pbdma_acquire_timeout_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_acquire_timeout_en_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_status_r(u32 i)
+{
+        return 0x00040100U + i*8192U;
+}
+static inline u32 pbdma_channel_r(u32 i)
+{
+        return 0x00040120U + i*8192U;
+}
+static inline u32 pbdma_signature_r(u32 i)
+{
+        return 0x00040010U + i*8192U;
+}
+static inline u32 pbdma_signature_hw_valid_f(void)
+{
+        return 0xfaceU;
+}
+static inline u32 pbdma_signature_sw_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_r(u32 i)
+{
+        return 0x00040008U + i*8192U;
+}
+static inline u32 pbdma_userd_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pbdma_userd_addr_f(u32 v)
+{
+        return (v & 0x7fffffU) << 9U;
+}
+static inline u32 pbdma_userd_hi_r(u32 i)
+{
+        return 0x0004000cU + i*8192U;
+}
+static inline u32 pbdma_userd_hi_addr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_config_r(u32 i)
+{
+        return 0x000400f4U + i*8192U;
+}
+static inline u32 pbdma_config_auth_level_privileged_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_hce_ctrl_r(u32 i)
+{
+        return 0x000400e4U + i*8192U;
+}
+static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_r(u32 i)
+{
+        return 0x00040108U + i*8192U;
+}
+static inline u32 pbdma_intr_0_memreq_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pbdma_intr_0_memreq_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pbdma_intr_0_memflush_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_memop_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_intr_0_lbreq_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
+{
+        return 0x400U;
+}
+static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
+{
+        return 0x800U;
+}
+static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 pbdma_intr_0_gpptr_pending_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 pbdma_intr_0_gpentry_pending_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 pbdma_intr_0_pbptr_pending_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 pbdma_intr_0_pbentry_pending_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 pbdma_intr_0_method_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_intr_0_device_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 pbdma_intr_0_semaphore_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 pbdma_intr_0_acquire_pending_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 pbdma_intr_0_pri_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_intr_0_pbseg_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 pbdma_intr_0_signature_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+        return 0x00040148U + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_r(u32 i)
+{
+        return 0x0004010cU + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_en_1_r(u32 i)
+{
+        return 0x0004014cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_r(u32 i)
+{
+        return 0x0004013cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_udma_nop_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 pbdma_allowed_syncpoints_r(u32 i)
+{
+        return 0x000400e8U + i*8192U;
+}
+static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v)
+{
+        return (v & 0x7fffU) << 16U;
+}
+static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r)
+{
+        return (r >> 16U) & 0x7fffU;
+}
+static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v)
+{
+        return (v & 0x1U) << 15U;
+}
+static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
+{
+        return (v & 0x7fffU) << 0U;
+}
+static inline u32 pbdma_syncpointa_r(u32 i)
+{
+        return 0x000400a4U + i*8192U;
+}
+static inline u32 pbdma_syncpointa_payload_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pbdma_syncpointb_r(u32 i)
+{
+        return 0x000400a8U + i*8192U;
+}
+static inline u32 pbdma_syncpointb_op_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pbdma_syncpointb_op_wait_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
+{
+        return (r >> 8U) & 0xfffU;
+}
+static inline u32 pbdma_runlist_timeslice_r(u32 i)
+{
+        return 0x000400f8U + i*8192U;
+}
+static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
+{
+        return 0x3000U;
+}
+static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
new file mode 100644
index 00000000..aa0fafe7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_perf_gp10b_h_
+#define _hw_perf_gp10b_h_
+
+static inline u32 perf_pmasys_control_r(void)
+{
+        return 0x001b4000U;
+}
+static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
+{
+        return 0x10U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
+{
+        return 0x20U;
+}
+static inline u32 perf_pmasys_mem_block_r(void)
+{
+        return 0x001b4070U;
+}
+static inline u32 perf_pmasys_mem_block_base_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 perf_pmasys_mem_block_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 perf_pmasys_mem_block_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_outbase_r(void)
+{
+        return 0x001b4074U;
+}
+static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_outbaseupper_r(void)
+{
+        return 0x001b4078U;
+}
+static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 perf_pmasys_outsize_r(void)
+{
+        return 0x001b407cU;
+}
+static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_mem_bytes_r(void)
+{
+        return 0x001b4084U;
+}
+static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_mem_bump_r(void)
+{
+        return 0x001b4088U;
+}
+static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_r(void)
+{
+        return 0x001b40a4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
+{
+        return 0x10U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
new file mode 100644
index 00000000..aef0e693
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pram_gp10b_h_
+#define _hw_pram_gp10b_h_
+
+static inline u32 pram_data032_r(u32 i)
+{
+        return 0x00700000U + i*4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
new file mode 100644
index 00000000..03a3854e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringmaster_gp10b_h_
+#define _hw_pri_ringmaster_gp10b_h_
+
+static inline u32 pri_ringmaster_command_r(void)
+{
+        return 0x0012004cU;
+}
+static inline u32 pri_ringmaster_command_cmd_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 pri_ringmaster_command_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_command_data_r(void)
+{
+        return 0x00120048U;
+}
+static inline u32 pri_ringmaster_start_results_r(void)
+{
+        return 0x00120050U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pri_ringmaster_intr_status0_r(void)
+{
+        return 0x00120058U;
+}
+static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status1_r(void)
+{
+        return 0x0012005cU;
+}
+static inline u32 pri_ringmaster_global_ctl_r(void)
+{
+        return 0x00120060U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_enum_fbp_r(void)
+{
+        return 0x00120074U;
+}
+static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_gpc_r(void)
+{
+        return 0x00120078U;
+}
+static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_ltc_r(void)
+{
+        return 0x0012006cU;
+}
+static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
new file mode 100644
index 00000000..1bd5a0f7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gp10b_h_
+#define _hw_pri_ringstation_gpc_gp10b_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300U + i*4U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
new file mode 100644
index 00000000..c4d9ef1b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_sys_gp10b_h_
+#define _hw_pri_ringstation_sys_gp10b_h_
+
+static inline u32 pri_ringstation_sys_master_config_r(u32 i)
+{
+        return 0x00122300U + i*4U;
+}
+static inline u32 pri_ringstation_sys_decode_config_r(void)
+{
+        return 0x00122204U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120U;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124U;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128U;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h
new file mode 100644
index 00000000..f5d60beb
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_proj_gp10b_h_
+#define _hw_proj_gp10b_h_
+
+static inline u32 proj_gpc_base_v(void)
+{
+        return 0x00500000U;
+}
+static inline u32 proj_gpc_shared_base_v(void)
+{
+        return 0x00418000U;
+}
+static inline u32 proj_gpc_stride_v(void)
+{
+        return 0x00008000U;
+}
+static inline u32 proj_ltc_stride_v(void)
+{
+        return 0x00002000U;
+}
+static inline u32 proj_lts_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_fbpa_base_v(void)
+{
+        return 0x00900000U;
+}
+static inline u32 proj_fbpa_shared_base_v(void)
+{
+        return 0x009a0000U;
+}
+static inline u32 proj_fbpa_stride_v(void)
+{
+        return 0x00004000U;
+}
+static inline u32 proj_ppc_in_gpc_base_v(void)
+{
+        return 0x00003000U;
+}
+static inline u32 proj_ppc_in_gpc_shared_base_v(void)
+{
+        return 0x00003e00U;
+}
+static inline u32 proj_ppc_in_gpc_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_rop_base_v(void)
+{
+        return 0x00410000U;
+}
+static inline u32 proj_rop_shared_base_v(void)
+{
+        return 0x00408800U;
+}
+static inline u32 proj_rop_stride_v(void)
+{
+        return 0x00000400U;
+}
+static inline u32 proj_tpc_in_gpc_base_v(void)
+{
+        return 0x00004000U;
+}
+static inline u32 proj_tpc_in_gpc_stride_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 proj_tpc_in_gpc_shared_base_v(void)
+{
+        return 0x00001800U;
+}
+static inline u32 proj_host_num_engines_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_host_num_pbdma_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_fbps_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_gpcs_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_scal_litter_num_zcull_banks_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 proj_scal_max_gpcs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 proj_scal_max_tpc_per_gpc_v(void)
+{
+        return 0x00000008U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
new file mode 100644
index 00000000..73a5c45c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
@@ -0,0 +1,831 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pwr_gp10b_h_
+#define _hw_pwr_gp10b_h_
+
+static inline u32 pwr_falcon_irqsset_r(void)
+{
+        return 0x0010a000U;
+}
+static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqsclr_r(void)
+{
+        return 0x0010a004U;
+}
+static inline u32 pwr_falcon_irqstat_r(void)
+{
+        return 0x0010a008U;
+}
+static inline u32 pwr_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqmode_r(void)
+{
+        return 0x0010a00cU;
+}
+static inline u32 pwr_falcon_irqmset_r(void)
+{
+        return 0x0010a010U;
+}
+static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_r(void)
+{
+        return 0x0010a014U;
+}
+static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqmask_r(void)
+{
+        return 0x0010a018U;
+}
+static inline u32 pwr_falcon_irqdest_r(void)
+{
+        return 0x0010a01cU;
+}
+static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 pwr_falcon_curctx_r(void)
+{
+        return 0x0010a050U;
+}
+static inline u32 pwr_falcon_nxtctx_r(void)
+{
+        return 0x0010a054U;
+}
+static inline u32 pwr_falcon_mailbox0_r(void)
+{
+        return 0x0010a040U;
+}
+static inline u32 pwr_falcon_mailbox1_r(void)
+{
+        return 0x0010a044U;
+}
+static inline u32 pwr_falcon_itfen_r(void)
+{
+        return 0x0010a048U;
+}
+static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_r(void)
+{
+        return 0x0010a04cU;
+}
+static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 pwr_falcon_os_r(void)
+{
+        return 0x0010a080U;
+}
+static inline u32 pwr_falcon_engctl_r(void)
+{
+        return 0x0010a0a4U;
+}
+static inline u32 pwr_falcon_cpuctl_r(void)
+{
+        return 0x0010a100U;
+}
+static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 pwr_falcon_cpuctl_alias_r(void)
+{
+        return 0x0010a130U;
+}
+static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_pmu_scpctl_stat_r(void)
+{
+        return 0x0010ac08U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+        return 0x0010a180U + i*16U;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+        return 0x0010a184U + i*16U;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+        return 0x0010a188U + i*16U;
+}
+static inline u32 pwr_falcon_sctl_r(void)
+{
+        return 0x0010a240U;
+}
+static inline u32 pwr_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 pwr_falcon_bootvec_r(void)
+{
+        return 0x0010a104U;
+}
+static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_falcon_dmactl_r(void)
+{
+        return 0x0010a10cU;
+}
+static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_falcon_hwcfg_r(void)
+{
+        return 0x0010a108U;
+}
+static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_dmatrfbase_r(void)
+{
+        return 0x0010a110U;
+}
+static inline u32 pwr_falcon_dmatrfbase1_r(void)
+{
+        return 0x0010a128U;
+}
+static inline u32 pwr_falcon_dmatrfmoffs_r(void)
+{
+        return 0x0010a114U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_r(void)
+{
+        return 0x0010a118U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 pwr_falcon_dmatrffboffs_r(void)
+{
+        return 0x0010a11cU;
+}
+static inline u32 pwr_falcon_exterraddr_r(void)
+{
+        return 0x0010a168U;
+}
+static inline u32 pwr_falcon_exterrstat_r(void)
+{
+        return 0x0010a16cU;
+}
+static inline u32 pwr_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
+{
+        return 0x0010a200U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
+{
+        return 0x0010a20cU;
+}
+static inline u32 pwr_falcon_dmemc_r(u32 i)
+{
+        return 0x0010a1c0U + i*8U;
+}
+static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 pwr_falcon_dmemd_r(u32 i)
+{
+        return 0x0010a1c4U + i*8U;
+}
+static inline u32 pwr_pmu_new_instblk_r(void)
+{
+        return 0x0010a480U;
+}
+static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 pwr_pmu_mutex_id_r(void)
+{
+        return 0x0010a488U;
+}
+static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_id_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 pwr_pmu_mutex_id_release_r(void)
+{
+        return 0x0010a48cU;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_mutex_r(u32 i)
+{
+        return 0x0010a580U + i*4U;
+}
+static inline u32 pwr_pmu_mutex__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 pwr_pmu_mutex_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_queue_head_r(u32 i)
+{
+        return 0x0010a4a0U + i*4U;
+}
+static inline u32 pwr_pmu_queue_head__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_queue_head_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_head_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_queue_tail_r(u32 i)
+{
+        return 0x0010a4b0U + i*4U;
+}
+static inline u32 pwr_pmu_queue_tail__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_head_r(void)
+{
+        return 0x0010a4c8U;
+}
+static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_tail_r(void)
+{
+        return 0x0010a4ccU;
+}
+static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_idle_mask_r(u32 i)
+{
+        return 0x0010a504U + i*16U;
+}
+static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pwr_pmu_idle_count_r(u32 i)
+{
+        return 0x0010a508U + i*16U;
+}
+static inline u32 pwr_pmu_idle_count_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_count_value_v(u32 r)
+{
+        return (r >> 0U) & 0x7fffffffU;
+}
+static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
+{
+        return 0x0010a50cU + i*16U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
+{
+        return 0x0010a9f0U + i*8U;
+}
+static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
+{
+        return 0x0010a9f4U + i*8U;
+}
+static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
+{
+        return 0x0010aa30U + i*8U;
+}
+static inline u32 pwr_pmu_debug_r(u32 i)
+{
+        return 0x0010a5c0U + i*4U;
+}
+static inline u32 pwr_pmu_debug__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_mailbox_r(u32 i)
+{
+        return 0x0010a450U + i*4U;
+}
+static inline u32 pwr_pmu_mailbox__size_1_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 pwr_pmu_bar0_addr_r(void)
+{
+        return 0x0010a7a0U;
+}
+static inline u32 pwr_pmu_bar0_data_r(void)
+{
+        return 0x0010a7a4U;
+}
+static inline u32 pwr_pmu_bar0_ctl_r(void)
+{
+        return 0x0010a7acU;
+}
+static inline u32 pwr_pmu_bar0_timeout_r(void)
+{
+        return 0x0010a7a8U;
+}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+        return 0x0010a988U;
+}
+static inline u32 pwr_pmu_bar0_error_status_r(void)
+{
+        return 0x0010a7b0U;
+}
+static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
+{
+        return 0x0010a6c0U + i*4U;
+}
+static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
+{
+        return 0x0010a6e8U + i*4U;
+}
+static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
+{
+        return 0x0010a710U + i*4U;
+}
+static inline u32 pwr_pmu_pg_intren_r(u32 i)
+{
+        return 0x0010a760U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_r(u32 i)
+{
+        return 0x0010ae00U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_s(void)
+{
+        return 1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
new file mode 100644
index 00000000..a94fc0a2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ram_gp10b_h_
+#define _hw_ram_gp10b_h_
+
+static inline u32 ram_in_ramfc_s(void)
+{
+        return 4096U;
+}
+static inline u32 ram_in_ramfc_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_in_page_dir_base_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ram_in_page_dir_base_target_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 ram_in_page_dir_base_vol_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 ram_in_big_page_size_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 ram_in_big_page_size_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 ram_in_big_page_size_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_big_page_size_128kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_big_page_size_64kb_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ram_in_page_dir_base_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_page_dir_base_lo_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_page_dir_base_hi_w(void)
+{
+        return 129U;
+}
+static inline u32 ram_in_adr_limit_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_adr_limit_lo_w(void)
+{
+        return 130U;
+}
+static inline u32 ram_in_adr_limit_hi_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ram_in_adr_limit_hi_w(void)
+{
+        return 131U;
+}
+static inline u32 ram_in_engine_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_engine_cs_wfi_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_engine_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_engine_cs_fg_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_engine_cs_fg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ram_in_gr_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_gr_wfi_target_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_mode_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
+{
+        return 133U;
+}
+static inline u32 ram_in_base_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ram_in_alloc_size_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ram_fc_size_val_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_fc_gp_put_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_userd_w(void)
+{
+        return 2U;
+}
+static inline u32 ram_fc_userd_hi_w(void)
+{
+        return 3U;
+}
+static inline u32 ram_fc_signature_w(void)
+{
+        return 4U;
+}
+static inline u32 ram_fc_gp_get_w(void)
+{
+        return 5U;
+}
+static inline u32 ram_fc_pb_get_w(void)
+{
+        return 6U;
+}
+static inline u32 ram_fc_pb_get_hi_w(void)
+{
+        return 7U;
+}
+static inline u32 ram_fc_pb_top_level_get_w(void)
+{
+        return 8U;
+}
+static inline u32 ram_fc_pb_top_level_get_hi_w(void)
+{
+        return 9U;
+}
+static inline u32 ram_fc_acquire_w(void)
+{
+        return 12U;
+}
+static inline u32 ram_fc_semaphorea_w(void)
+{
+        return 14U;
+}
+static inline u32 ram_fc_semaphoreb_w(void)
+{
+        return 15U;
+}
+static inline u32 ram_fc_semaphorec_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_fc_semaphored_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_fc_gp_base_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_fc_gp_base_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_fc_gp_fetch_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_fc_pb_fetch_w(void)
+{
+        return 21U;
+}
+static inline u32 ram_fc_pb_fetch_hi_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_fc_pb_put_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_fc_pb_put_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_fc_pb_header_w(void)
+{
+        return 33U;
+}
+static inline u32 ram_fc_pb_count_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_fc_subdevice_w(void)
+{
+        return 37U;
+}
+static inline u32 ram_fc_formats_w(void)
+{
+        return 39U;
+}
+static inline u32 ram_fc_allowed_syncpoints_w(void)
+{
+        return 58U;
+}
+static inline u32 ram_fc_syncpointa_w(void)
+{
+        return 41U;
+}
+static inline u32 ram_fc_syncpointb_w(void)
+{
+        return 42U;
+}
+static inline u32 ram_fc_target_w(void)
+{
+        return 43U;
+}
+static inline u32 ram_fc_hce_ctrl_w(void)
+{
+        return 57U;
+}
+static inline u32 ram_fc_chid_w(void)
+{
+        return 58U;
+}
+static inline u32 ram_fc_chid_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_fc_chid_id_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_config_w(void)
+{
+        return 61U;
+}
+static inline u32 ram_fc_runlist_timeslice_w(void)
+{
+        return 62U;
+}
+static inline u32 ram_userd_base_shift_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 ram_userd_chan_size_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_userd_put_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_userd_get_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_userd_ref_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_userd_put_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_userd_ref_threshold_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_userd_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_userd_get_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_userd_gp_get_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_userd_gp_put_w(void)
+{
+        return 35U;
+}
+static inline u32 ram_userd_gp_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_gp_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_rl_entry_size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+        return (v & 0xfU) << 14U;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+        return 0xc000U;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+        return (v & 0xffU) << 18U;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+        return (v & 0x3fU) << 26U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
new file mode 100644
index 00000000..49fb7180
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
@@ -0,0 +1,415 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_therm_gp10b_h_
+#define _hw_therm_gp10b_h_
+
+static inline u32 therm_use_a_r(void)
+{
+        return 0x00020798U;
+}
+static inline u32 therm_use_a_ext_therm_0_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_use_a_ext_therm_1_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_use_a_ext_therm_2_enable_f(void)
+{
+        return 0x4U;
+}
+static inline u32 therm_evt_ext_therm_0_r(void)
+{
+        return 0x00020700U;
+}
+static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 24U;
+}
+static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
+{
+        return (v & 0x3U) << 30U;
+}
+static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 therm_evt_ext_therm_1_r(void)
+{
+        return 0x00020704U;
+}
+static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 24U;
+}
+static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
+{
+        return (v & 0x3U) << 30U;
+}
+static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 therm_evt_ext_therm_2_r(void)
+{
+        return 0x00020708U;
+}
+static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 24U;
+}
+static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
+{
+        return (v & 0x3U) << 30U;
+}
+static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 therm_weight_1_r(void)
+{
+        return 0x00020024U;
+}
+static inline u32 therm_config1_r(void)
+{
+        return 0x00020050U;
+}
+static inline u32 therm_config2_r(void)
+{
+        return 0x00020130U;
+}
+static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 therm_config2_grad_enable_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 therm_gate_ctrl_r(u32 i)
+{
+        return 0x00020200U + i*4U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_m(void)
+{
+        return 0x3U << 2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
+{
+        return 0x4U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_m(void)
+{
+        return 0x3U << 4U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
+{
+        return 0x10U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
+{
+        return 0x20U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
+{
+        return 0x1fU << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
+{
+        return (v & 0x7U) << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
+{
+        return 0x7U << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
+{
+        return 0xfU << 20U;
+}
+static inline u32 therm_fecs_idle_filter_r(void)
+{
+        return 0x00020288U;
+}
+static inline u32 therm_fecs_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_hubmmu_idle_filter_r(void)
+{
+        return 0x0002028cU;
+}
+static inline u32 therm_hubmmu_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_clk_slowdown_r(u32 i)
+{
+        return 0x00020160U + i*4U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 16U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_m(void)
+{
+        return 0x3fU << 16U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
+{
+        return (r >> 16U) & 0x3fU;
+}
+static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_grad_stepping_table_r(u32 i)
+{
+        return 0x000202c8U + i*4U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
+{
+        return 0x6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
+{
+        return 0xeU;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
+{
+        return (v & 0x3fU) << 12U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
+{
+        return 0x3fU << 12U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
+{
+        return (v & 0x3fU) << 18U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
+{
+        return 0x3fU << 18U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
+{
+        return (v & 0x3fU) << 24U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
+{
+        return 0x3fU << 24U;
+}
+static inline u32 therm_grad_stepping0_r(void)
+{
+        return 0x000202c0U;
+}
+static inline u32 therm_grad_stepping0_feature_s(void)
+{
+        return 1U;
+}
+static inline u32 therm_grad_stepping0_feature_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 therm_grad_stepping0_feature_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 therm_grad_stepping0_feature_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 therm_grad_stepping0_feature_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_grad_stepping1_r(void)
+{
+        return 0x000202c4U;
+}
+static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 therm_clk_timing_r(u32 i)
+{
+        return 0x000203c0U + i*4U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
+{
+        return 0x10000U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
new file mode 100644
index 00000000..db752648
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_timer_gp10b_h_
+#define _hw_timer_gp10b_h_
+
+static inline u32 timer_pri_timeout_r(void)
+{
+        return 0x00009080U;
+}
+static inline u32 timer_pri_timeout_period_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 timer_pri_timeout_period_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 timer_pri_timeout_period_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 timer_pri_timeout_en_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 timer_pri_timeout_en_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 timer_pri_timeout_en_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 timer_pri_timeout_en_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 timer_pri_timeout_en_en_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 timer_pri_timeout_save_0_r(void)
+{
+        return 0x00009084U;
+}
+static inline u32 timer_pri_timeout_save_1_r(void)
+{
+        return 0x00009088U;
+}
+static inline u32 timer_pri_timeout_fecs_errcode_r(void)
+{
+        return 0x0000908cU;
+}
+static inline u32 timer_time_0_r(void)
+{
+        return 0x00009400U;
+}
+static inline u32 timer_time_1_r(void)
+{
+        return 0x00009410U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h
new file mode 100644
index 00000000..8d336077
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_top_gp10b_h_
+#define _hw_top_gp10b_h_
+
+static inline u32 top_num_gpcs_r(void)
+{
+        return 0x00022430U;
+}
+static inline u32 top_num_gpcs_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_tpc_per_gpc_r(void)
+{
+        return 0x00022434U;
+}
+static inline u32 top_tpc_per_gpc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_fbps_r(void)
+{
+        return 0x00022438U;
+}
+static inline u32 top_num_fbps_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_ltc_per_fbp_r(void)
+{
+        return 0x00022450U;
+}
+static inline u32 top_ltc_per_fbp_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_slices_per_ltc_r(void)
+{
+        return 0x0002245cU;
+}
+static inline u32 top_slices_per_ltc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_ltcs_r(void)
+{
+        return 0x00022454U;
+}
+static inline u32 top_device_info_r(u32 i)
+{
+        return 0x00022700U + i*4U;
+}
+static inline u32 top_device_info__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 top_device_info_chain_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 top_device_info_chain_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_engine_enum_v(u32 r)
+{
+        return (r >> 26U) & 0xfU;
+}
+static inline u32 top_device_info_runlist_enum_v(u32 r)
+{
+        return (r >> 21U) & 0xfU;
+}
+static inline u32 top_device_info_intr_enum_v(u32 r)
+{
+        return (r >> 15U) & 0x1fU;
+}
+static inline u32 top_device_info_reset_enum_v(u32 r)
+{
+        return (r >> 9U) & 0x1fU;
+}
+static inline u32 top_device_info_type_enum_v(u32 r)
+{
+        return (r >> 2U) & 0x1fffffffU;
+}
+static inline u32 top_device_info_type_enum_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_type_enum_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 top_device_info_type_enum_copy2_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_type_enum_copy2_f(void)
+{
+        return 0xcU;
+}
+static inline u32 top_device_info_type_enum_lce_v(void)
+{
+        return 0x00000013U;
+}
+static inline u32 top_device_info_type_enum_lce_f(void)
+{
+        return 0x4cU;
+}
+static inline u32 top_device_info_engine_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 top_device_info_runlist_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 top_device_info_intr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 top_device_info_reset_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_entry_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 top_device_info_entry_not_valid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_entry_enum_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 top_device_info_entry_engine_type_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 top_device_info_entry_data_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_data_type_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 top_device_info_data_type_enum2_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_data_inst_id_v(u32 r)
+{
+        return (r >> 26U) & 0xfU;
+}
+static inline u32 top_device_info_data_pri_base_v(u32 r)
+{
+        return (r >> 12U) & 0xfffU;
+}
+static inline u32 top_device_info_data_pri_base_align_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
+{
+        return (r >> 3U) & 0x1fU;
+}
+static inline u32 top_device_info_data_fault_id_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_data_fault_id_valid_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/io.h b/drivers/gpu/nvgpu/include/nvgpu/io.h
new file mode 100644
index 00000000..94ae8f95
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/io.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_IO_H__
+#define __NVGPU_IO_H__
+
+#include <nvgpu/types.h>
+#ifdef CONFIG_TEGRA_19x_GPU
+#include <nvgpu/io_t19x.h>
+#endif
+
+/* Legacy defines - should be removed once everybody uses nvgpu_* */
+#define gk20a_writel nvgpu_writel
+#define gk20a_readl nvgpu_readl
+#define gk20a_writel_check nvgpu_writel_check
+#define gk20a_bar1_writel nvgpu_bar1_writel
+#define gk20a_bar1_readl nvgpu_bar1_readl
+#define gk20a_io_exists nvgpu_io_exists
+#define gk20a_io_valid_reg nvgpu_io_valid_reg
+
+struct gk20a;
+
+void nvgpu_writel(struct gk20a *g, u32 r, u32 v);
+u32 nvgpu_readl(struct gk20a *g, u32 r);
+void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v);
+void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v);
+u32 nvgpu_bar1_readl(struct gk20a *g, u32 b);
+bool nvgpu_io_exists(struct gk20a *g);
+bool nvgpu_io_valid_reg(struct gk20a *g, u32 r);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/kmem.h b/drivers/gpu/nvgpu/include/nvgpu/kmem.h
new file mode 100644
index 00000000..fef837cf
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/kmem.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_KMEM_H__
+#define __NVGPU_KMEM_H__
+
+#include <nvgpu/types.h>
+
+/*
+ * Incase this isn't defined already.
+ */
+#ifndef _THIS_IP_
+#define _THIS_IP_  ({ __label__ __here; __here: (unsigned long)&&__here; })
+#endif
+
+struct gk20a;
+
+/*
+ * When there's other implementations make sure they are included instead of
+ * Linux when not compiling on Linux!
+ */
+#ifdef __KERNEL__
+#include <nvgpu/linux/kmem.h>
+#else
+#include <nvgpu_rmos/include/kmem.h>
+#endif
+
+/**
+ * DOC: Kmem cache support
+ *
+ * In Linux there is support for the notion of a kmem_cache. It gives better
+ * memory usage characteristics for lots of allocations of the same size. Think
+ * structs that get allocated over and over. Normal kmalloc() type routines
+ * typically round to the next power-of-2 since that's easy.
+ *
+ * But if we know the size ahead of time the packing for the allocations can be
+ * much better. This is the benefit of a slab allocator. This type hides the
+ * underlying kmem_cache (or absense thereof).
+ */
+struct nvgpu_kmem_cache;
+
+#ifdef CONFIG_NVGPU_TRACK_MEM_USAGE
+/*
+ * Uncomment this if you want to enable stack traces in the memory profiling.
+ * Since this is a fairly high overhead operation and is only necessary for
+ * debugging actual bugs it's left here for developers to enable.
+ */
+/* #define __NVGPU_SAVE_KALLOC_STACK_TRACES */
+
+/*
+ * Defined per-OS.
+ */
+struct nvgpu_mem_alloc_tracker;
+#endif
+
+
+/**
+ * nvgpu_kmem_cache_create - create an nvgpu kernel memory cache.
+ *
+ * @g           The GPU driver struct using this cache.
+ * @size        Size of the object allocated by the cache.
+ *
+ * This cache can be used to allocate objects of size @size. Common usage would
+ * be for a struct that gets allocated a lot. In that case @size should be
+ * sizeof(struct my_struct).
+ *
+ * A given implementation of this need not do anything special. The allocation
+ * routines can simply be passed on to nvgpu_kzalloc() if desired so packing
+ * and alignment of the structs cannot be assumed.
+ */
+struct nvgpu_kmem_cache *nvgpu_kmem_cache_create(struct gk20a *g, size_t size);
+
+/**
+ * nvgpu_kmem_cache_destroy - destroy a cache created by
+ *                            nvgpu_kmem_cache_create().
+ *
+ * @cache       The cache to destroy.
+ */
+void nvgpu_kmem_cache_destroy(struct nvgpu_kmem_cache *cache);
+
+/**
+ * nvgpu_kmem_cache_alloc - Allocate an object from the cache
+ *
+ * @cache       The cache to alloc from.
+ */
+void *nvgpu_kmem_cache_alloc(struct nvgpu_kmem_cache *cache);
+
+/**
+ * nvgpu_kmem_cache_free - Free an object back to a cache
+ *
+ * @cache       The cache to return the object to.
+ * @ptr         Pointer to the object to free.
+ */
+void nvgpu_kmem_cache_free(struct nvgpu_kmem_cache *cache, void *ptr);
+
+/**
+ * nvgpu_kmalloc - Allocate from the kernel's allocator.
+ *
+ * @g:          Current GPU.
+ * @size:       Size of the allocation.
+ *
+ * Allocate a chunk of system memory from the kernel. Allocations larger than 1
+ * page may fail even when there may appear to be enough memory.
+ *
+ * This function may sleep so cannot be used in IRQs.
+ */
+#define nvgpu_kmalloc(g, size)          __nvgpu_kmalloc(g, size, _THIS_IP_)
+
+/**
+ * nvgpu_kzalloc - Allocate from the kernel's allocator.
+ *
+ * @g:          Current GPU.
+ * @size:       Size of the allocation.
+ *
+ * Identical to nvgpu_kalloc() except the memory will be zeroed before being
+ * returned.
+ */
+#define nvgpu_kzalloc(g, size)          __nvgpu_kzalloc(g, size, _THIS_IP_)
+
+/**
+ * nvgpu_kcalloc - Allocate from the kernel's allocator.
+ *
+ * @g:          Current GPU.
+ * @n:          Number of objects.
+ * @size:       Size of each object.
+ *
+ * Identical to nvgpu_kalloc() except the size of the memory chunk returned is
+ * @n * @size.
+ */
+#define nvgpu_kcalloc(g, n, size)       __nvgpu_kcalloc(g, n, size, _THIS_IP_)
+
+/**
+ * nvgpu_vmalloc - Allocate memory and return a map to it.
+ *
+ * @g:          Current GPU.
+ * @size:       Size of the allocation.
+ *
+ * Allocate some memory and return a pointer to a virtual memory mapping of
+ * that memory in the kernel's virtual address space. The underlying physical
+ * memory is not guaranteed to be contiguous (and indeed likely isn't). This
+ * allows for much larger allocations to be done without worrying about as much
+ * about physical memory fragmentation.
+ *
+ * This function may sleep.
+ */
+#define nvgpu_vmalloc(g, size)          __nvgpu_vmalloc(g, size, _THIS_IP_)
+
+/**
+ * nvgpu_vzalloc - Allocate memory and return a map to it.
+ *
+ * @g:          Current GPU.
+ * @size:       Size of the allocation.
+ *
+ * Identical to nvgpu_vmalloc() except this will return zero'ed memory.
+ */
+#define nvgpu_vzalloc(g, size)          __nvgpu_vzalloc(g, size, _THIS_IP_)
+
+/**
+ * nvgpu_kfree - Frees an alloc from nvgpu_kmalloc, nvgpu_kzalloc,
+ *               nvgpu_kcalloc.
+ *
+ * @g:          Current GPU.
+ * @addr:       Address of object to free.
+ */
+#define nvgpu_kfree(g, addr)            __nvgpu_kfree(g, addr)
+
+/**
+ * nvgpu_vfree - Frees an alloc from nvgpu_vmalloc, nvgpu_vzalloc.
+ *
+ * @g:          Current GPU.
+ * @addr:       Address of object to free.
+ */
+#define nvgpu_vfree(g, addr)            __nvgpu_vfree(g, addr)
+
+#define kmem_dbg(g, fmt, args...)               \
+        nvgpu_log(g, gpu_dbg_kmem, fmt, ##args)
+
+/**
+ * nvgpu_kmem_init - Initialize the kmem tracking stuff.
+ *
+ *@g: The driver to init.
+ *
+ * Returns non-zero on failure.
+ */
+int nvgpu_kmem_init(struct gk20a *g);
+
+/**
+ * nvgpu_kmem_fini - Finalize the kmem tracking code
+ *
+ * @g     - The GPU.
+ * @flags - Flags that control operation of this finalization.
+ *
+ * Cleanup resources used by nvgpu_kmem. Available flags for cleanup are:
+ *
+ *   %NVGPU_KMEM_FINI_DO_NOTHING
+ *   %NVGPU_KMEM_FINI_FORCE_CLEANUP
+ *   %NVGPU_KMEM_FINI_DUMP_ALLOCS
+ *   %NVGPU_KMEM_FINI_WARN
+ *   %NVGPU_KMEM_FINI_BUG
+ *
+ * %NVGPU_KMEM_FINI_DO_NOTHING will be overridden by anything else specified.
+ * Put another way don't just add %NVGPU_KMEM_FINI_DO_NOTHING and expect that
+ * to suppress other flags from doing anything.
+ */
+void nvgpu_kmem_fini(struct gk20a *g, int flags);
+
+/*
+ * These will simply be ignored if CONFIG_NVGPU_TRACK_MEM_USAGE is not defined.
+ */
+#define NVGPU_KMEM_FINI_DO_NOTHING              0
+#define NVGPU_KMEM_FINI_FORCE_CLEANUP           (1 << 0)
+#define NVGPU_KMEM_FINI_DUMP_ALLOCS             (1 << 1)
+#define NVGPU_KMEM_FINI_WARN                    (1 << 2)
+#define NVGPU_KMEM_FINI_BUG                     (1 << 3)
+
+/*
+ * Implemented by the OS interface.
+ */
+void *__nvgpu_big_alloc(struct gk20a *g, size_t size, bool clear);
+
+/**
+ * nvgpu_big_malloc - Pick virtual or physical alloc based on @size
+ *
+ * @g - The GPU.
+ * @size - Size of the allocation.
+ *
+ * On some platforms (i.e Linux) it is possible to allocate memory directly
+ * mapped into the kernel's address space (kmalloc) or allocate discontiguous
+ * pages which are then mapped into a special kernel address range. Each type
+ * of allocation has pros and cons. kmalloc() for instance lets you allocate
+ * small buffers more space efficiently but vmalloc() allows you to successfully
+ * allocate much larger buffers without worrying about fragmentation as much
+ * (but will allocate in multiples of page size).
+ *
+ * This function aims to provide the right allocation for when buffers are of
+ * variable size. In some cases the code doesn't know ahead of time if the
+ * buffer is going to be big or small so this does the check for you and
+ * provides the right type of memory allocation.
+ *
+ * Returns a pointer to a virtual address range that the kernel can access or
+ * %NULL on failure.
+ */
+static inline void *nvgpu_big_malloc(struct gk20a *g, size_t size)
+{
+        return __nvgpu_big_alloc(g, size, false);
+}
+
+/**
+ * nvgpu_big_malloc - Pick virtual or physical alloc based on @size
+ *
+ * @g - The GPU.
+ * @size - Size of the allocation.
+ *
+ * Zeroed memory version of nvgpu_big_malloc().
+ */
+static inline void *nvgpu_big_zalloc(struct gk20a *g, size_t size)
+{
+        return __nvgpu_big_alloc(g, size, true);
+}
+
+/**
+ * nvgpu_big_free - Free and alloc from nvgpu_big_zalloc() or
+ *                  nvgpu_big_malloc().
+ * @g - The GPU.
+ * @p - A pointer allocated by nvgpu_big_zalloc() or nvgpu_big_malloc().
+ */
+void nvgpu_big_free(struct gk20a *g, void *p);
+
+#endif /* __NVGPU_KMEM_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/kref.h b/drivers/gpu/nvgpu/include/nvgpu/kref.h
new file mode 100644
index 00000000..72b21ec4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/kref.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The following structure is used for reference counting of objects in nvgpu.
+ */
+#ifndef __NVGPU_KREF_H__
+#define __NVGPU_KREF_H__
+
+#include <nvgpu/atomic.h>
+
+struct nvgpu_ref {
+        nvgpu_atomic_t refcount;
+};
+
+/*
+ * Initialize object.
+ * @ref: the nvgpu_ref object to initialize
+ */
+static inline void nvgpu_ref_init(struct nvgpu_ref *ref)
+{
+        nvgpu_atomic_set(&ref->refcount, 1);
+}
+
+/*
+ * Increment reference count for the object
+ * @ref: the nvgpu_ref object
+ */
+static inline void nvgpu_ref_get(struct nvgpu_ref *ref)
+{
+        nvgpu_atomic_inc(&ref->refcount);
+}
+
+/*
+ * Decrement reference count for the object and call release() if it becomes
+ * zero.
+ * @ref: the nvgpu_ref object
+ * @release: pointer to the function that would be invoked to clean up the
+ *      object when the reference count becomes zero, i.e. the last
+ *      reference corresponding to this object is removed.
+ * Return 1 if object was removed, otherwise return 0. The user should not
+ * make any assumptions about the status of the object in the memory when
+ * the function returns 0 and should only use it to know that there are no
+ * further references to this object.
+ */
+static inline int nvgpu_ref_put(struct nvgpu_ref *ref,
+                void (*release)(struct nvgpu_ref *r))
+{
+        if (nvgpu_atomic_sub_and_test(1, &ref->refcount)) {
+                if (release != NULL)
+                        release(ref);
+                return 1;
+        }
+        return 0;
+}
+
+/*
+ * Increment reference count for the object unless it is zero.
+ * @ref: the nvgpu_ref object
+ * Return non-zero if the increment succeeds, Otherwise return 0.
+ */
+static inline int __must_check nvgpu_ref_get_unless_zero(struct nvgpu_ref *ref)
+{
+        return nvgpu_atomic_add_unless(&ref->refcount, 1, 0);
+}
+
+#endif /* __NVGPU_KREF_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h
new file mode 100644
index 00000000..0734672e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVGPU_ATOMIC_LINUX_H__
+#define __NVGPU_ATOMIC_LINUX_H__
+
+#ifdef __KERNEL__
+#include <linux/atomic.h>
+#endif
+
+typedef struct nvgpu_atomic {
+  atomic_t atomic_var;
+} nvgpu_atomic_t;
+
+typedef struct nvgpu_atomic64 {
+  atomic64_t atomic_var;
+} nvgpu_atomic64_t;
+
+#define __nvgpu_atomic_init(i)  { ATOMIC_INIT(i) }
+#define __nvgpu_atomic64_init(i)        { ATOMIC64_INIT(i) }
+
+static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i)
+{
+        atomic_set(&v->atomic_var, i);
+}
+
+static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v)
+{
+        return atomic_read(&v->atomic_var);
+}
+
+static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v)
+{
+        atomic_inc(&v->atomic_var);
+}
+
+static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v)
+{
+        return atomic_inc_return(&v->atomic_var);
+}
+
+static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v)
+{
+        atomic_dec(&v->atomic_var);
+}
+
+static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v)
+{
+        return atomic_dec_return(&v->atomic_var);
+}
+
+static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new)
+{
+        return atomic_cmpxchg(&v->atomic_var, old, new);
+}
+
+static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new)
+{
+        return atomic_xchg(&v->atomic_var, new);
+}
+
+static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v)
+{
+        return atomic_inc_and_test(&v->atomic_var);
+}
+
+static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v)
+{
+        return atomic_dec_and_test(&v->atomic_var);
+}
+
+static inline bool __nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v)
+{
+        return atomic_sub_and_test(i, &v->atomic_var);
+}
+
+static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v)
+{
+        return atomic_add_return(i, &v->atomic_var);
+}
+
+static inline int __nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u)
+{
+        return atomic_add_unless(&v->atomic_var, a, u);
+}
+
+static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i)
+{
+        atomic64_set(&v->atomic_var, i);
+}
+
+static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v)
+{
+        return atomic64_read(&v->atomic_var);
+}
+
+static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v)
+{
+        atomic64_add(x, &v->atomic_var);
+}
+
+static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v)
+{
+        atomic64_inc(&v->atomic_var);
+}
+
+static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v)
+{
+        return atomic64_inc_return(&v->atomic_var);
+}
+
+static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v)
+{
+        atomic64_dec(&v->atomic_var);
+}
+
+static inline void __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v)
+{
+        atomic64_dec_return(&v->atomic_var);
+}
+
+static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v,
+                                        long old, long new)
+{
+        return atomic64_cmpxchg(&v->atomic_var, old, new);
+}
+
+static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v)
+{
+        atomic64_sub(x, &v->atomic_var);
+}
+
+static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v)
+{
+        return atomic64_sub_return(x, &v->atomic_var);
+}
+#endif /*__NVGPU_ATOMIC_LINUX_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/barrier.h b/drivers/gpu/nvgpu/include/nvgpu/linux/barrier.h
new file mode 100644
index 00000000..b20f9462
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/barrier.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_BARRIER_LINUX_H__
+#define __NVGPU_BARRIER_LINUX_H__
+
+#include <asm/barrier.h>
+
+#define __nvgpu_mb()    mb()
+#define __nvgpu_rmb()   rmb()
+#define __nvgpu_wmb()   wmb()
+
+#define __nvgpu_smp_mb()        smp_mb()
+#define __nvgpu_smp_rmb()       smp_rmb()
+#define __nvgpu_smp_wmb()       smp_wmb()
+
+#define __nvgpu_read_barrier_depends()  read_barrier_depends()
+#define __nvgpu_smp_read_barrier_depends()      smp_read_barrier_depends()
+
+#define __NV_ACCESS_ONCE(x)     ACCESS_ONCE(x)
+
+#endif /* __NVGPU_BARRIER_LINUX_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/cond.h b/drivers/gpu/nvgpu/include/nvgpu/linux/cond.h
new file mode 100644
index 00000000..01ca5291
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/cond.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_COND_LINUX_H__
+#define __NVGPU_COND_LINUX_H__
+
+#include <linux/wait.h>
+
+struct nvgpu_cond {
+        bool initialized;
+        wait_queue_head_t wq;
+};
+
+/**
+ * NVGPU_COND_WAIT - Wait for a condition to be true
+ *
+ * @c - The condition variable to sleep on
+ * @condition - The condition that needs to be true
+ * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait
+ *
+ * Wait for a condition to become true. Returns -ETIMEOUT if
+ * the wait timed out with condition false.
+ */
+#define NVGPU_COND_WAIT(c, condition, timeout_ms) \
+({\
+        int ret = 0; \
+        long _timeout_ms = timeout_ms;\
+        if (_timeout_ms > 0) { \
+                long _ret = wait_event_timeout((c)->wq, condition, \
+                                                 msecs_to_jiffies(_timeout_ms)); \
+                if (_ret == 0) \
+                        ret = -ETIMEDOUT; \
+        } else { \
+                wait_event((c)->wq, condition); \
+        } \
+        ret;\
+})
+
+/**
+ * NVGPU_COND_WAIT_INTERRUPTIBLE - Wait for a condition to be true
+ *
+ * @c - The condition variable to sleep on
+ * @condition - The condition that needs to be true
+ * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait
+ *
+ * Wait for a condition to become true. Returns -ETIMEOUT if
+ * the wait timed out with condition false or -ERESTARTSYS on
+ * signal.
+ */
+#define NVGPU_COND_WAIT_INTERRUPTIBLE(c, condition, timeout_ms) \
+({ \
+        int ret = 0; \
+        long _timeout_ms = timeout_ms;\
+        if (_timeout_ms > 0) { \
+                long _ret = wait_event_interruptible_timeout((c)->wq, condition, \
+                                                 msecs_to_jiffies(_timeout_ms)); \
+                if (_ret == 0) \
+                        ret = -ETIMEDOUT; \
+                else if (_ret == -ERESTARTSYS) \
+                        ret = -ERESTARTSYS; \
+        } else { \
+                wait_event_interruptible((c)->wq, condition); \
+        } \
+        ret; \
+})
+
+#endif /* __NVGPU_LOCK_LINUX_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/dma.h b/drivers/gpu/nvgpu/include/nvgpu/linux/dma.h
new file mode 100644
index 00000000..342b278e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/dma.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_LINUX_DMA_H__
+#define __NVGPU_LINUX_DMA_H__
+
+/**
+ * Functions used internally for building the backing SGTs for nvgpu_mems.
+ */
+
+
+int nvgpu_get_sgtable_attrs(struct gk20a *g, struct sg_table **sgt,
+                      void *cpuva, u64 iova,
+                      size_t size, unsigned long flags);
+
+int nvgpu_get_sgtable(struct gk20a *g, struct sg_table **sgt,
+                      void *cpuva, u64 iova, size_t size);
+
+int nvgpu_get_sgtable_from_pages(struct gk20a *g, struct sg_table **sgt,
+                                 struct page **pages, u64 iova,
+                                 size_t size);
+
+void nvgpu_free_sgtable(struct gk20a *g, struct sg_table **sgt);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/kmem.h b/drivers/gpu/nvgpu/include/nvgpu/linux/kmem.h
new file mode 100644
index 00000000..611854f2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/kmem.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_KMEM_LINUX_H__
+#define __NVGPU_KMEM_LINUX_H__
+
+struct gk20a;
+struct device;
+
+#ifdef CONFIG_NVGPU_TRACK_MEM_USAGE
+void *__nvgpu_track_vmalloc(struct gk20a *g, unsigned long size,
+                            unsigned long ip);
+void *__nvgpu_track_vzalloc(struct gk20a *g, unsigned long size,
+                            unsigned long ip);
+void *__nvgpu_track_kmalloc(struct gk20a *g, size_t size, unsigned long ip);
+void *__nvgpu_track_kzalloc(struct gk20a *g, size_t size, unsigned long ip);
+void *__nvgpu_track_kcalloc(struct gk20a *g, size_t n, size_t size,
+                            unsigned long ip);
+void  __nvgpu_track_vfree(struct gk20a *g, void *addr);
+void  __nvgpu_track_kfree(struct gk20a *g, void *addr);
+#endif
+
+/**
+ * DOC: Linux pass through kmem implementation.
+ *
+ * These are the Linux implementations of the various kmem functions defined by
+ * nvgpu. This should not be included directly - instead include <nvgpu/kmem.h>.
+ */
+void *__nvgpu_kmalloc(struct gk20a *g, size_t size, unsigned long ip);
+void *__nvgpu_kzalloc(struct gk20a *g, size_t size, unsigned long ip);
+void *__nvgpu_kcalloc(struct gk20a *g, size_t n, size_t size, unsigned long ip);
+void *__nvgpu_vmalloc(struct gk20a *g, unsigned long size, unsigned long ip);
+void *__nvgpu_vzalloc(struct gk20a *g, unsigned long size, unsigned long ip);
+void __nvgpu_kfree(struct gk20a *g, void *addr);
+void __nvgpu_vfree(struct gk20a *g, void *addr);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/lock.h b/drivers/gpu/nvgpu/include/nvgpu/linux/lock.h
new file mode 100644
index 00000000..fbf26e9d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/lock.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef NVGPU_LOCK_LINUX_H
+#define NVGPU_LOCK_LINUX_H
+
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+
+struct nvgpu_mutex {
+        struct mutex mutex;
+};
+struct nvgpu_spinlock {
+        spinlock_t spinlock;
+};
+struct nvgpu_raw_spinlock {
+        raw_spinlock_t spinlock;
+};
+
+static inline int nvgpu_mutex_init(struct nvgpu_mutex *mutex)
+{
+        mutex_init(&mutex->mutex);
+        return 0;
+};
+static inline void nvgpu_mutex_acquire(struct nvgpu_mutex *mutex)
+{
+        mutex_lock(&mutex->mutex);
+};
+static inline void nvgpu_mutex_release(struct nvgpu_mutex *mutex)
+{
+        mutex_unlock(&mutex->mutex);
+};
+static inline int nvgpu_mutex_tryacquire(struct nvgpu_mutex *mutex)
+{
+        return mutex_trylock(&mutex->mutex);
+};
+static inline void nvgpu_mutex_destroy(struct nvgpu_mutex *mutex)
+{
+        mutex_destroy(&mutex->mutex);
+};
+
+static inline void nvgpu_spinlock_init(struct nvgpu_spinlock *spinlock)
+{
+        spin_lock_init(&spinlock->spinlock);
+};
+static inline void nvgpu_spinlock_acquire(struct nvgpu_spinlock *spinlock)
+{
+        spin_lock(&spinlock->spinlock);
+};
+static inline void nvgpu_spinlock_release(struct nvgpu_spinlock *spinlock)
+{
+        spin_unlock(&spinlock->spinlock);
+};
+
+static inline void nvgpu_raw_spinlock_init(struct nvgpu_raw_spinlock *spinlock)
+{
+        raw_spin_lock_init(&spinlock->spinlock);
+};
+static inline void nvgpu_raw_spinlock_acquire(struct nvgpu_raw_spinlock *spinlock)
+{
+        raw_spin_lock(&spinlock->spinlock);
+};
+static inline void nvgpu_raw_spinlock_release(struct nvgpu_raw_spinlock *spinlock)
+{
+        raw_spin_unlock(&spinlock->spinlock);
+};
+
+#endif /* NVGPU_LOCK_LINUX_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/linux/nvgpu_mem.h
new file mode 100644
index 00000000..e5f5031a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/nvgpu_mem.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_LINUX_NVGPU_MEM_H__
+#define __NVGPU_LINUX_NVGPU_MEM_H__
+
+struct page;
+struct sg_table;
+struct scatterlist;
+struct nvgpu_sgt;
+
+struct gk20a;
+struct nvgpu_mem;
+struct nvgpu_gmmu_attrs;
+
+struct nvgpu_mem_priv {
+        struct page **pages;
+        struct sg_table *sgt;
+        unsigned long flags;
+};
+
+u64 nvgpu_mem_get_addr_sgl(struct gk20a *g, struct scatterlist *sgl);
+struct nvgpu_sgt *nvgpu_mem_linux_sgt_create(struct gk20a *g,
+                                           struct sg_table *sgt);
+void nvgpu_mem_linux_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt);
+struct nvgpu_sgt *nvgpu_linux_sgt_create(struct gk20a *g,
+                                           struct sg_table *sgt);
+/**
+ * __nvgpu_mem_create_from_pages - Create an nvgpu_mem from physical pages.
+ *
+ * @g        - The GPU.
+ * @dest     - nvgpu_mem to initialize.
+ * @pages    - A list of page pointers.
+ * @nr_pages - The number of pages in @pages.
+ *
+ * Create a new nvgpu_mem struct from a pre-existing list of physical pages. The
+ * pages need not be contiguous (the underlying scatter gather list will help
+ * with that). However, note, this API will explicitly make it so that the GMMU
+ * mapping code bypasses SMMU access for the passed pages. This allows one to
+ * make mem_descs that describe MMIO regions or other non-DRAM things.
+ *
+ * This only works for SYSMEM (or other things like SYSMEM - basically just not
+ * VIDMEM). Also, this API is only available for Linux as it heavily depends on
+ * the notion of struct %page.
+ *
+ * The resulting nvgpu_mem should be released with the nvgpu_dma_free() or the
+ * nvgpu_dma_unmap_free() function depending on whether or not the resulting
+ * nvgpu_mem has been mapped. The underlying pages themselves must be cleaned up
+ * by the caller of this API.
+ *
+ * Returns 0 on success, or a relevant error otherwise.
+ */
+int __nvgpu_mem_create_from_pages(struct gk20a *g, struct nvgpu_mem *dest,
+                                  struct page **pages, int nr_pages);
+
+/**
+ * __nvgpu_mem_create_from_phys - Create an nvgpu_mem from physical mem.
+ *
+ * @g        - The GPU.
+ * @dest     - nvgpu_mem to initialize.
+ * @src_phys - start address of physical mem
+ * @nr_pages - The number of pages in phys.
+ *
+ * Create a new nvgpu_mem struct from a physical memory aperure. The physical
+ * memory aperture needs to be contiguous for requested @nr_pages. This API
+ * only works for SYSMEM.
+ *
+ * The resulting nvgpu_mem should be released with the nvgpu_dma_free() or the
+ * nvgpu_dma_unmap_free() function depending on whether or not the resulting
+ * nvgpu_mem has been mapped.
+ *
+ * Returns 0 on success, or a relevant error otherwise.
+ */
+int __nvgpu_mem_create_from_phys(struct gk20a *g, struct nvgpu_mem *dest,
+                                  u64 src_phys, int nr_pages);
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/rwsem.h b/drivers/gpu/nvgpu/include/nvgpu/linux/rwsem.h
new file mode 100644
index 00000000..7d073d39
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/rwsem.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_RWSEM_LINUX_H__
+#define __NVGPU_RWSEM_LINUX_H__
+
+#include <linux/rwsem.h>
+
+struct nvgpu_rwsem {
+        struct rw_semaphore rwsem;
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/thread.h b/drivers/gpu/nvgpu/include/nvgpu/linux/thread.h
new file mode 100644
index 00000000..1355319c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/thread.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_THREAD_LINUX_H__
+#define __NVGPU_THREAD_LINUX_H__
+
+struct task_struct;
+
+struct nvgpu_thread {
+        struct task_struct *task;
+        bool running;
+        int (*fn)(void *);
+        void *data;
+};
+
+#endif /* __NVGPU_THREAD_LINUX_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/vidmem.h b/drivers/gpu/nvgpu/include/nvgpu/linux/vidmem.h
new file mode 100644
index 00000000..ec02faec
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/vidmem.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __NVGPU_LINUX_VIDMEM_H__
+#define __NVGPU_LINUX_VIDMEM_H__
+
+#include <nvgpu/types.h>
+
+struct dma_buf;
+
+struct gk20a;
+
+#ifdef CONFIG_GK20A_VIDMEM
+
+struct gk20a *nvgpu_vidmem_buf_owner(struct dma_buf *dmabuf);
+int nvgpu_vidmem_export_linux(struct gk20a *g, size_t bytes);
+
+void nvgpu_vidmem_set_page_alloc(struct scatterlist *sgl, u64 addr);
+struct nvgpu_page_alloc *nvgpu_vidmem_get_page_alloc(struct scatterlist *sgl);
+
+int nvgpu_vidmem_buf_access_memory(struct gk20a *g, struct dma_buf *dmabuf,
+                void *buffer, u64 offset, u64 size, u32 cmd);
+
+#else /* !CONFIG_GK20A_VIDMEM */
+
+static inline struct gk20a *nvgpu_vidmem_buf_owner(struct dma_buf *dmabuf)
+{
+        return NULL;
+}
+
+static inline int nvgpu_vidmem_export_linux(struct gk20a *g, size_t bytes)
+{
+        return -ENOSYS;
+}
+
+static inline void nvgpu_vidmem_set_page_alloc(struct scatterlist *sgl,
+                                               u64 addr)
+{
+}
+
+static inline struct nvgpu_page_alloc *nvgpu_vidmem_get_page_alloc(
+        struct scatterlist *sgl)
+{
+        return NULL;
+}
+
+static inline int nvgpu_vidmem_buf_access_memory(struct gk20a *g,
+                                                 struct dma_buf *dmabuf,
+                                                 void *buffer, u64 offset,
+                                                 u64 size, u32 cmd)
+{
+        return -ENOSYS;
+}
+
+#endif
+
+
+struct nvgpu_vidmem_linux {
+        struct dma_buf  *dmabuf;
+        void            *dmabuf_priv;
+        void            (*dmabuf_priv_delete)(void *);
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/vm.h b/drivers/gpu/nvgpu/include/nvgpu/linux/vm.h
new file mode 100644
index 00000000..d9f082af
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/linux/vm.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __COMMON_LINUX_VM_PRIV_H__
+#define __COMMON_LINUX_VM_PRIV_H__
+
+#include <nvgpu/types.h>
+
+#include <asm/cacheflush.h>
+
+/*
+ * Couple of places explicitly flush caches still. Any DMA buffer we allocate
+ * from within the GPU is writecombine and as a result does not need this but
+ * there seem to be exceptions.
+ */
+#ifdef CONFIG_ARM64
+#define outer_flush_range(a, b)
+#define __cpuc_flush_dcache_area __flush_dcache_area
+#endif
+
+struct sg_table;
+struct dma_buf;
+struct device;
+
+struct vm_gk20a;
+struct vm_gk20a_mapping_batch;
+struct nvgpu_vm_area;
+
+struct nvgpu_os_buffer {
+        struct dma_buf *dmabuf;
+        struct device *dev;
+};
+
+struct nvgpu_mapped_buf_priv {
+        struct dma_buf *dmabuf;
+        struct sg_table *sgt;
+};
+
+/* NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set */
+int nvgpu_vm_map_linux(struct vm_gk20a *vm,
+                       struct dma_buf *dmabuf,
+                       u64 offset_align,
+                       u32 flags,
+                       s16 compr_kind,
+                       s16 incompr_kind,
+                       int rw_flag,
+                       u64 buffer_offset,
+                       u64 mapping_size,
+                       struct vm_gk20a_mapping_batch *mapping_batch,
+                       u64 *gpu_va);
+
+/*
+ * Notes:
+ * - Batch may be NULL if map op is not part of a batch.
+ * - NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL must be set
+ */
+int nvgpu_vm_map_buffer(struct vm_gk20a *vm,
+                        int dmabuf_fd,
+                        u64 *offset_align,
+                        u32 flags, /* NVGPU_AS_MAP_BUFFER_FLAGS_ */
+                        s16 compr_kind,
+                        s16 incompr_kind,
+                        u64 buffer_offset,
+                        u64 mapping_size,
+                        struct vm_gk20a_mapping_batch *batch);
+
+/* find buffer corresponding to va */
+int nvgpu_vm_find_buf(struct vm_gk20a *vm, u64 gpu_va,
+                      struct dma_buf **dmabuf,
+                      u64 *offset);
+
+enum nvgpu_aperture gk20a_dmabuf_aperture(struct gk20a *g,
+                                          struct dma_buf *dmabuf);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/list.h b/drivers/gpu/nvgpu/include/nvgpu/list.h
new file mode 100644
index 00000000..a7e13cab
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/list.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_LIST_H
+#define NVGPU_LIST_H
+
+struct nvgpu_list_node {
+        struct nvgpu_list_node *prev;
+        struct nvgpu_list_node *next;
+};
+
+static inline void nvgpu_init_list_node(struct nvgpu_list_node *node)
+{
+        node->prev = node;
+        node->next = node;
+}
+
+static inline void nvgpu_list_add(struct nvgpu_list_node *new_node, struct nvgpu_list_node *head)
+{
+        new_node->next = head->next;
+        new_node->next->prev = new_node;
+        new_node->prev = head;
+        head->next = new_node;
+}
+
+static inline void nvgpu_list_add_tail(struct nvgpu_list_node *new_node, struct nvgpu_list_node *head)
+{
+        new_node->prev = head->prev;
+        new_node->prev->next = new_node;
+        new_node->next = head;
+        head->prev = new_node;
+}
+
+static inline void nvgpu_list_del(struct nvgpu_list_node *node)
+{
+        node->prev->next = node->next;
+        node->next->prev = node->prev;
+        nvgpu_init_list_node(node);
+}
+
+static inline int nvgpu_list_empty(struct nvgpu_list_node *head)
+{
+        return head->next == head;
+}
+
+static inline void nvgpu_list_move(struct nvgpu_list_node *node, struct nvgpu_list_node *head)
+{
+        nvgpu_list_del(node);
+        nvgpu_list_add(node, head);
+}
+
+static inline void nvgpu_list_replace_init(struct nvgpu_list_node *old_node, struct nvgpu_list_node *new_node)
+{
+        new_node->next = old_node->next;
+        new_node->next->prev = new_node;
+        new_node->prev = old_node->prev;
+        new_node->prev->next = new_node;
+        nvgpu_init_list_node(old_node);
+}
+
+#define nvgpu_list_entry(ptr, type, member)     \
+        type ## _from_ ## member(ptr)
+
+#define nvgpu_list_next_entry(pos, type, member)        \
+        nvgpu_list_entry((pos)->member.next, type, member)
+
+#define nvgpu_list_first_entry(ptr, type, member)       \
+        nvgpu_list_entry((ptr)->next, type, member)
+
+#define nvgpu_list_last_entry(ptr, type, member)        \
+        nvgpu_list_entry((ptr)->prev, type, member)
+
+#define nvgpu_list_for_each_entry(pos, head, type, member)      \
+        for (pos = nvgpu_list_first_entry(head, type, member);  \
+                &pos->member != (head);                         \
+                pos = nvgpu_list_next_entry(pos, type, member))
+
+#define nvgpu_list_for_each_entry_safe(pos, n, head, type, member)      \
+        for (pos = nvgpu_list_first_entry(head, type, member),          \
+                        n = nvgpu_list_next_entry(pos, type, member);   \
+                &pos->member != (head);                                 \
+                pos = n, n = nvgpu_list_next_entry(n, type, member))
+
+#endif /* NVGPU_LIST_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/lock.h b/drivers/gpu/nvgpu/include/nvgpu/lock.h
new file mode 100644
index 00000000..bccded57
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/lock.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_LOCK_H
+#define NVGPU_LOCK_H
+
+#ifdef __KERNEL__
+#include <nvgpu/linux/lock.h>
+#else
+#include <nvgpu_rmos/include/lock.h>
+#endif
+
+/*
+ * struct nvgpu_mutex
+ *
+ * Should be implemented per-OS in a separate library
+ * But implementation should adhere to mutex implementation
+ * as specified in Linux Documentation
+ */
+struct nvgpu_mutex;
+
+/*
+ * struct nvgpu_spinlock
+ *
+ * Should be implemented per-OS in a separate library
+ * But implementation should adhere to spinlock implementation
+ * as specified in Linux Documentation
+ */
+struct nvgpu_spinlock;
+
+/*
+ * struct nvgpu_raw_spinlock
+ *
+ * Should be implemented per-OS in a separate library
+ * But implementation should adhere to raw_spinlock implementation
+ * as specified in Linux Documentation
+ */
+struct nvgpu_raw_spinlock;
+
+int nvgpu_mutex_init(struct nvgpu_mutex *mutex);
+void nvgpu_mutex_acquire(struct nvgpu_mutex *mutex);
+void nvgpu_mutex_release(struct nvgpu_mutex *mutex);
+int nvgpu_mutex_tryacquire(struct nvgpu_mutex *mutex);
+void nvgpu_mutex_destroy(struct nvgpu_mutex *mutex);
+
+void nvgpu_spinlock_init(struct nvgpu_spinlock *spinlock);
+void nvgpu_spinlock_acquire(struct nvgpu_spinlock *spinlock);
+void nvgpu_spinlock_release(struct nvgpu_spinlock *spinlock);
+
+void nvgpu_raw_spinlock_init(struct nvgpu_raw_spinlock *spinlock);
+void nvgpu_raw_spinlock_acquire(struct nvgpu_raw_spinlock *spinlock);
+void nvgpu_raw_spinlock_release(struct nvgpu_raw_spinlock *spinlock);
+
+#endif /* NVGPU_LOCK_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log.h b/drivers/gpu/nvgpu/include/nvgpu/log.h
new file mode 100644
index 00000000..65f86198
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/log.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_DEBUGGING_H__
+#define __NVGPU_DEBUGGING_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/bitops.h>
+
+struct gk20a;
+
+enum nvgpu_log_type {
+        NVGPU_ERROR,
+        NVGPU_WARNING,
+        NVGPU_DEBUG,
+        NVGPU_INFO,
+};
+
+/*
+ * Each OS must implement these functions. They handle the OS specific nuances
+ * of printing data to a UART, log, whatever.
+ */
+__attribute__((format (printf, 5, 6)))
+void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
+                     enum nvgpu_log_type type, const char *fmt, ...);
+
+__attribute__((format (printf, 5, 6)))
+void __nvgpu_log_dbg(struct gk20a *g, u32 log_mask,
+                     const char *func_name, int line,
+                     const char *fmt, ...);
+
+/*
+ * Use this define to set a default mask.
+ */
+#define NVGPU_DEFAULT_DBG_MASK          (0)
+
+enum nvgpu_log_categories {
+        gpu_dbg_info       = BIT(0),    /* Lightly verbose info. */
+        gpu_dbg_fn         = BIT(1),    /* Function name tracing. */
+        gpu_dbg_reg        = BIT(2),    /* Register accesses; very verbose. */
+        gpu_dbg_pte        = BIT(3),    /* GMMU PTEs. */
+        gpu_dbg_intr       = BIT(4),    /* Interrupts. */
+        gpu_dbg_pmu        = BIT(5),    /* gk20a pmu. */
+        gpu_dbg_clk        = BIT(6),    /* gk20a clk. */
+        gpu_dbg_map        = BIT(7),    /* Memory mappings. */
+        gpu_dbg_map_v      = BIT(8),    /* Verbose mem mappings. */
+        gpu_dbg_gpu_dbg    = BIT(9),    /* GPU debugger/profiler. */
+        gpu_dbg_cde        = BIT(10),   /* cde info messages. */
+        gpu_dbg_cde_ctx    = BIT(11),   /* cde context usage messages. */
+        gpu_dbg_ctxsw      = BIT(12),   /* ctxsw tracing. */
+        gpu_dbg_sched      = BIT(13),   /* Sched control tracing. */
+        gpu_dbg_sema       = BIT(14),   /* Semaphore debugging. */
+        gpu_dbg_sema_v     = BIT(15),   /* Verbose semaphore debugging. */
+        gpu_dbg_pmu_pstate = BIT(16),   /* p state controlled by pmu. */
+        gpu_dbg_xv         = BIT(17),   /* XVE debugging. */
+        gpu_dbg_shutdown   = BIT(18),   /* GPU shutdown tracing. */
+        gpu_dbg_kmem       = BIT(19),   /* Kmem tracking debugging. */
+        gpu_dbg_pd_cache   = BIT(20),   /* PD cache traces. */
+        gpu_dbg_alloc      = BIT(21),   /* Allocator debugging. */
+        gpu_dbg_dma        = BIT(22),   /* DMA allocation prints. */
+        gpu_dbg_sgl        = BIT(23),   /* SGL related traces. */
+        gpu_dbg_vidmem     = BIT(24),   /* VIDMEM tracing. */
+        gpu_dbg_mem        = BIT(31),   /* memory accesses; very verbose. */
+};
+
+/**
+ * nvgpu_log_mask_enabled - Check if logging is enabled
+ *
+ * @g        - The GPU.
+ * @log_mask - The mask the check against.
+ *
+ * Check if, given the passed mask, logging would actually happen. This is
+ * useful for avoiding calling the logging function many times when we know that
+ * said prints would not happen. For example for-loops of log statements in
+ * critical paths.
+ */
+int nvgpu_log_mask_enabled(struct gk20a *g, u32 log_mask);
+
+/**
+ * nvgpu_log - Print a debug message
+ *
+ * @g        - The GPU.
+ * @log_mask - A mask defining when the print should happen. See enum
+ *             %nvgpu_log_categories.
+ * @fmt      - A format string (printf style).
+ * @arg...   - Arguments for the format string.
+ *
+ * Print a message if the log_mask matches the enabled debugging.
+ */
+#define nvgpu_log(g, log_mask, fmt, arg...)                             \
+        __nvgpu_log_dbg(g, log_mask, __func__, __LINE__, fmt, ##arg)
+
+/**
+ * nvgpu_err - Print an error
+ *
+ * @g        - The GPU.
+ * @fmt      - A format string (printf style).
+ * @arg...   - Arguments for the format string.
+ *
+ * Uncondtionally print an error message.
+ */
+#define nvgpu_err(g, fmt, arg...)                                       \
+        __nvgpu_log_msg(g, __func__, __LINE__, NVGPU_ERROR, fmt, ##arg)
+
+/**
+ * nvgpu_err - Print a warning
+ *
+ * @g        - The GPU.
+ * @fmt      - A format string (printf style).
+ * @arg...   - Arguments for the format string.
+ *
+ * Uncondtionally print a warming message.
+ */
+#define nvgpu_warn(g, fmt, arg...)                                      \
+        __nvgpu_log_msg(g, __func__, __LINE__, NVGPU_WARNING, fmt, ##arg)
+
+/**
+ * nvgpu_info - Print an info message
+ *
+ * @g        - The GPU.
+ * @fmt      - A format string (printf style).
+ * @arg...   - Arguments for the format string.
+ *
+ * Unconditionally print an information message.
+ */
+#define nvgpu_info(g, fmt, arg...)                                      \
+        __nvgpu_log_msg(g, __func__, __LINE__, NVGPU_INFO, fmt, ##arg)
+
+/*
+ * Some convenience macros.
+ */
+#define nvgpu_log_fn(g, fmt, arg...)    nvgpu_log(g, gpu_dbg_fn, fmt, ##arg)
+#define nvgpu_log_info(g, fmt, arg...)  nvgpu_log(g, gpu_dbg_info, fmt, ##arg)
+
+/******************************************************************************
+ * The old legacy debugging API minus some parts that are unnecessary.        *
+ * Please, please, please do not use this!!! This is still around to aid      *
+ * transitioning to the new API.                                              *
+ *                                                                            *
+ * This changes up the print formats to be closer to the new APIs formats.    *
+ * Also it removes the dev_warn() and dev_err() usage. Those arguments are    *
+ * ignored now.                                                               *
+ ******************************************************************************/
+
+/*
+ * This exist for backwards compatibility with the old debug/logging API. If you
+ * want ftrace support use the new API!
+ */
+extern u32 nvgpu_dbg_mask;
+
+#define gk20a_dbg(log_mask, fmt, arg...)                                \
+        do {                                                            \
+                if (((log_mask) & nvgpu_dbg_mask) != 0)                 \
+                        __nvgpu_log_msg(NULL, __func__, __LINE__,       \
+                                        NVGPU_DEBUG, fmt "\n", ##arg);  \
+        } while (0)
+
+/*
+ * Some convenience macros.
+ */
+#define gk20a_dbg_fn(fmt, arg...)       gk20a_dbg(gpu_dbg_fn, fmt, ##arg)
+#define gk20a_dbg_info(fmt, arg...)     gk20a_dbg(gpu_dbg_info, fmt, ##arg)
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log2.h b/drivers/gpu/nvgpu/include/nvgpu/log2.h
new file mode 100644
index 00000000..827162f8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/log2.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_LOG2_H__
+#define __NVGPU_LOG2_H__
+
+#ifdef __KERNEL__
+#include <linux/log2.h>
+#endif
+
+#endif /* __NVGPU_LOG2_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/ltc.h
new file mode 100644
index 00000000..60aa5424
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/ltc.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_LTC_H__
+#define __NVGPU_LTC_H__
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+int nvgpu_init_ltc_support(struct gk20a *g);
+void nvgpu_ltc_sync_enabled(struct gk20a *g);
+int nvgpu_ltc_alloc_cbc(struct gk20a *g, size_t compbit_backing_size);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h
new file mode 100644
index 00000000..9882b31e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h
@@ -0,0 +1,222 @@
+/*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_MM_H__
+#define __NVGPU_MM_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/cond.h>
+#include <nvgpu/thread.h>
+#include <nvgpu/lock.h>
+#include <nvgpu/atomic.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/allocator.h>
+#include <nvgpu/list.h>
+
+struct gk20a;
+struct vm_gk20a;
+struct nvgpu_mem;
+struct nvgpu_pd_cache;
+
+#define FAULT_TYPE_NUM          2       /* replay and nonreplay faults */
+
+struct mmu_fault_info {
+        u64     inst_ptr;
+        u32     inst_aperture;
+        u64     fault_addr;
+        u32     fault_addr_aperture;
+        u32     timestamp_lo;
+        u32     timestamp_hi;
+        u32     mmu_engine_id;
+        u32     gpc_id;
+        u32     client_type;
+        u32     client_id;
+        u32     fault_type;
+        u32     access_type;
+        u32     protected_mode;
+        u32     replayable_fault;
+        u32     replay_fault_en;
+        u32     valid;
+        u32     faulted_pbdma;
+        u32     faulted_engine;
+        u32     faulted_subid;
+        u32     chid;
+        struct channel_gk20a *refch;
+        const char *client_type_desc;
+        const char *fault_type_desc;
+        const char *client_id_desc;
+};
+
+enum nvgpu_flush_op {
+        NVGPU_FLUSH_DEFAULT,
+        NVGPU_FLUSH_FB,
+        NVGPU_FLUSH_L2_INV,
+        NVGPU_FLUSH_L2_FLUSH,
+        NVGPU_FLUSH_CBC_CLEAN,
+};
+
+struct mm_gk20a {
+        struct gk20a *g;
+
+        /* GPU VA default sizes address spaces for channels */
+        struct {
+                u64 user_size;   /* userspace-visible GPU VA region */
+                u64 kernel_size; /* kernel-only GPU VA region */
+        } channel;
+
+        struct {
+                u32 aperture_size;
+                struct vm_gk20a *vm;
+                struct nvgpu_mem inst_block;
+        } bar1;
+
+        struct {
+                u32 aperture_size;
+                struct vm_gk20a *vm;
+                struct nvgpu_mem inst_block;
+        } bar2;
+
+        struct {
+                u32 aperture_size;
+                struct vm_gk20a *vm;
+                struct nvgpu_mem inst_block;
+        } pmu;
+
+        struct {
+                /* using pmu vm currently */
+                struct nvgpu_mem inst_block;
+        } hwpm;
+
+        struct {
+                struct vm_gk20a *vm;
+                struct nvgpu_mem inst_block;
+        } perfbuf;
+
+        struct {
+                struct vm_gk20a *vm;
+        } cde;
+
+        struct {
+                struct vm_gk20a *vm;
+        } ce;
+
+        struct nvgpu_pd_cache *pd_cache;
+
+        struct nvgpu_mutex l2_op_lock;
+        struct nvgpu_mutex tlb_lock;
+        struct nvgpu_mutex priv_lock;
+
+        struct nvgpu_mem bar2_desc;
+
+#ifdef CONFIG_TEGRA_19x_GPU
+        struct nvgpu_mem hw_fault_buf[FAULT_TYPE_NUM];
+        unsigned int hw_fault_buf_status[FAULT_TYPE_NUM];
+        struct mmu_fault_info *fault_info[FAULT_TYPE_NUM];
+        struct nvgpu_mutex hub_isr_mutex;
+        u32    hub_intr_types;
+#endif
+        /*
+         * Separate function to cleanup the CE since it requires a channel to
+         * be closed which must happen before fifo cleanup.
+         */
+        void (*remove_ce_support)(struct mm_gk20a *mm);
+        void (*remove_support)(struct mm_gk20a *mm);
+        bool sw_ready;
+        int physical_bits;
+        bool use_full_comp_tag_line;
+        bool ltc_enabled_current;
+        bool ltc_enabled_target;
+        bool bypass_smmu;
+        bool disable_bigpage;
+        bool has_physical_mode;
+
+        struct nvgpu_mem sysmem_flush;
+
+        u32 pramin_window;
+        struct nvgpu_spinlock pramin_window_lock;
+        bool force_pramin; /* via debugfs */
+
+        struct {
+                size_t size;
+                u64 base;
+                size_t bootstrap_size;
+                u64 bootstrap_base;
+
+                struct nvgpu_allocator allocator;
+                struct nvgpu_allocator bootstrap_allocator;
+
+                u32 ce_ctx_id;
+                volatile bool cleared;
+                struct nvgpu_mutex first_clear_mutex;
+
+                struct nvgpu_list_node clear_list_head;
+                struct nvgpu_mutex clear_list_mutex;
+
+                struct nvgpu_cond clearing_thread_cond;
+                struct nvgpu_thread clearing_thread;
+                struct nvgpu_mutex clearing_thread_lock;
+                nvgpu_atomic_t pause_count;
+
+                nvgpu_atomic64_t bytes_pending;
+        } vidmem;
+};
+
+#define gk20a_from_mm(mm) ((mm)->g)
+#define gk20a_from_vm(vm) ((vm)->mm->g)
+
+static inline int bar1_aperture_size_mb_gk20a(void)
+{
+        return 16; /* 16MB is more than enough atm. */
+}
+
+/* The maximum GPU VA range supported */
+#define NV_GMMU_VA_RANGE          38
+
+/* The default userspace-visible GPU VA size */
+#define NV_MM_DEFAULT_USER_SIZE   (1ULL << 37)
+
+/* The default kernel-reserved GPU VA size */
+#define NV_MM_DEFAULT_KERNEL_SIZE (1ULL << 32)
+
+/*
+ * When not using unified address spaces, the bottom 56GB of the space are used
+ * for small pages, and the remaining high memory is used for large pages.
+ */
+static inline u64 __nv_gmmu_va_small_page_limit(void)
+{
+        return ((u64)SZ_1G * 56);
+}
+
+enum gmmu_pgsz_gk20a __get_pte_size_fixed_map(struct vm_gk20a *vm,
+                                              u64 base, u64 size);
+enum gmmu_pgsz_gk20a __get_pte_size(struct vm_gk20a *vm, u64 base, u64 size);
+
+void nvgpu_init_mm_ce_context(struct gk20a *g);
+int nvgpu_init_mm_support(struct gk20a *g);
+int nvgpu_init_mm_setup_hw(struct gk20a *g);
+
+u64 nvgpu_inst_block_addr(struct gk20a *g, struct nvgpu_mem *mem);
+void nvgpu_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
+
+int nvgpu_mm_suspend(struct gk20a *g);
+u32 nvgpu_mm_get_default_big_page_size(struct gk20a *g);
+u32 nvgpu_mm_get_available_big_page_sizes(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h
new file mode 100644
index 00000000..50e8c8f1
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_COMMON_H
+#define NVGPU_COMMON_H
+
+struct gk20a;
+struct class;
+
+int nvgpu_probe(struct gk20a *g,
+                const char *debugfs_symlink,
+                const char *interface_name,
+                struct class *class);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
new file mode 100644
index 00000000..2b8b7015
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_NVGPU_MEM_H__
+#define __NVGPU_NVGPU_MEM_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/list.h>
+
+#ifdef __KERNEL__
+#include <nvgpu/linux/nvgpu_mem.h>
+#else
+#include <nvgpu_rmos/include/nvgpu_mem.h>
+#endif
+
+struct page;
+struct sg_table;
+struct nvgpu_sgt;
+
+struct gk20a;
+struct nvgpu_allocator;
+struct nvgpu_gmmu_attrs;
+struct nvgpu_page_alloc;
+
+#define NVGPU_MEM_DMA_ERROR             (~0ULL)
+
+/*
+ * Real location of a buffer - nvgpu_aperture_mask() will deduce what will be
+ * told to the gpu about the aperture, but this flag designates where the
+ * memory actually was allocated from.
+ */
+enum nvgpu_aperture {
+        APERTURE_INVALID = 0, /* unallocated or N/A */
+        APERTURE_SYSMEM,
+        APERTURE_VIDMEM
+};
+
+struct nvgpu_sgt_ops {
+        void *(*sgl_next)(void *sgl);
+        u64   (*sgl_phys)(void *sgl);
+        u64   (*sgl_dma)(void *sgl);
+        u64   (*sgl_length)(void *sgl);
+        u64   (*sgl_gpu_addr)(struct gk20a *g, void *sgl,
+                              struct nvgpu_gmmu_attrs *attrs);
+        /*
+         * If left NULL then iommuable is assumed to be false.
+         */
+        bool  (*sgt_iommuable)(struct gk20a *g, struct nvgpu_sgt *sgt);
+
+        /*
+         * Note: this operates on the whole SGT not a specific SGL entry.
+         */
+        void  (*sgt_free)(struct gk20a *g, struct nvgpu_sgt *sgt);
+};
+
+/*
+ * Scatter gather table: this is a list of scatter list entries and the ops for
+ * interacting with those entries.
+ */
+struct nvgpu_sgt {
+        /*
+         * Ops for interacting with the underlying scatter gather list entries.
+         */
+        const struct nvgpu_sgt_ops *ops;
+
+        /*
+         * The first node in the scatter gather list.
+         */
+        void *sgl;
+};
+
+/*
+ * This struct holds the necessary information for describing a struct
+ * nvgpu_mem's scatter gather list.
+ *
+ * Not all nvgpu_sgt's use this particular implementation. Nor is a given OS
+ * required to use this at all.
+ */
+struct nvgpu_mem_sgl {
+        /*
+         * Internally this is implemented as a singly linked list.
+         */
+        struct nvgpu_mem_sgl    *next;
+
+        /*
+         * There is both a phys address and a DMA address since some systems,
+         * for example ones with an IOMMU, may see these as different addresses.
+         */
+        u64                      phys;
+        u64                      dma;
+        u64                      length;
+};
+
+/*
+ * Iterate over the SGL entries in an SGT.
+ */
+#define nvgpu_sgt_for_each_sgl(__sgl__, __sgt__)                \
+        for ((__sgl__) = (__sgt__)->sgl;                        \
+             (__sgl__) != NULL;                                 \
+             (__sgl__) = nvgpu_sgt_get_next(__sgt__, __sgl__))
+
+struct nvgpu_mem {
+        /*
+         * Populated for all nvgpu_mem structs - vidmem or system.
+         */
+        enum nvgpu_aperture                      aperture;
+        size_t                                   size;
+        size_t                                   aligned_size;
+        u64                                      gpu_va;
+        bool                                     skip_wmb;
+
+        /*
+         * Set when a nvgpu_mem struct is not a "real" nvgpu_mem struct. Instead
+         * the struct is just a copy of another nvgpu_mem struct.
+         */
+#define NVGPU_MEM_FLAG_SHADOW_COPY               (1 << 0)
+
+        /*
+         * Specify that the GVA mapping is a fixed mapping - that is the caller
+         * chose the GPU VA, not the GMMU mapping function. Only relevant for
+         * VIDMEM.
+         */
+#define NVGPU_MEM_FLAG_FIXED                     (1 << 1)
+
+        /*
+         * Set for user generated VIDMEM allocations. This triggers a special
+         * cleanup path that clears the vidmem on free. Given that the VIDMEM is
+         * zeroed on boot this means that all user vidmem allocations are
+         * therefor zeroed (to prevent leaking information in VIDMEM buffers).
+         */
+#define NVGPU_MEM_FLAG_USER_MEM                  (1 << 2)
+
+        /*
+         * Internal flag that specifies this struct has not been made with DMA
+         * memory and as a result should not try to use the DMA routines for
+         * freeing the backing memory.
+         *
+         * However, this will not stop the DMA API from freeing other parts of
+         * nvgpu_mem in a system specific way.
+         */
+#define __NVGPU_MEM_FLAG_NO_DMA                  (1 << 3)
+        unsigned long                            mem_flags;
+
+        /*
+         * Only populated for a sysmem allocation.
+         */
+        void                                    *cpu_va;
+
+        /*
+         * Fields only populated for vidmem allocations.
+         */
+        struct nvgpu_page_alloc                 *vidmem_alloc;
+        struct nvgpu_allocator                  *allocator;
+        struct nvgpu_list_node                   clear_list_entry;
+
+        /*
+         * This is defined by the system specific header. It can be empty if
+         * there's no system specific stuff for a given system.
+         */
+        struct nvgpu_mem_priv                    priv;
+};
+
+static inline struct nvgpu_mem *
+nvgpu_mem_from_clear_list_entry(struct nvgpu_list_node *node)
+{
+        return (struct nvgpu_mem *)
+                ((uintptr_t)node - offsetof(struct nvgpu_mem,
+                                            clear_list_entry));
+};
+
+static inline const char *nvgpu_aperture_str(enum nvgpu_aperture aperture)
+{
+        switch (aperture) {
+                case APERTURE_INVALID: return "INVAL";
+                case APERTURE_SYSMEM:  return "SYSMEM";
+                case APERTURE_VIDMEM:  return "VIDMEM";
+        };
+        return "UNKNOWN";
+}
+
+/*
+ * Returns true if the passed nvgpu_mem has been allocated (i.e it's valid for
+ * subsequent use).
+ */
+static inline bool nvgpu_mem_is_valid(struct nvgpu_mem *mem)
+{
+        /*
+         * Internally the DMA APIs must set/unset the aperture flag when
+         * allocating/freeing the buffer. So check that to see if the *mem
+         * has been allocated or not.
+         *
+         * This relies on mem_descs being zeroed before being initialized since
+         * APERTURE_INVALID is equal to 0.
+         */
+        return mem->aperture != APERTURE_INVALID;
+
+}
+
+/*
+ * Create a nvgpu_sgt of the default implementation
+ */
+struct nvgpu_sgt *nvgpu_sgt_create(struct gk20a *g);
+
+/**
+ * nvgpu_mem_sgt_create_from_mem - Create a scatter list from an nvgpu_mem.
+ *
+ * @g   - The GPU.
+ * @mem - The source memory allocation to use.
+ *
+ * Create a scatter gather table from the passed @mem struct. This list lets the
+ * calling code iterate across each chunk of a DMA allocation for when that DMA
+ * allocation is not completely contiguous.
+ */
+struct nvgpu_sgt *nvgpu_sgt_create_from_mem(struct gk20a *g,
+                                            struct nvgpu_mem *mem);
+
+void *nvgpu_sgt_get_next(struct nvgpu_sgt *sgt, void *sgl);
+u64 nvgpu_sgt_get_phys(struct nvgpu_sgt *sgt, void *sgl);
+u64 nvgpu_sgt_get_dma(struct nvgpu_sgt *sgt, void *sgl);
+u64 nvgpu_sgt_get_length(struct nvgpu_sgt *sgt, void *sgl);
+u64 nvgpu_sgt_get_gpu_addr(struct gk20a *g, struct nvgpu_sgt *sgt, void *sgl,
+                           struct nvgpu_gmmu_attrs *attrs);
+void nvgpu_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt);
+
+bool nvgpu_sgt_iommuable(struct gk20a *g, struct nvgpu_sgt *sgt);
+u64 nvgpu_sgt_alignment(struct gk20a *g, struct nvgpu_sgt *sgt);
+
+/**
+ * nvgpu_mem_create_from_mem - Create a new nvgpu_mem struct from an old one.
+ *
+ * @g          - The GPU.
+ * @dest       - Destination nvgpu_mem to hold resulting memory description.
+ * @src        - Source memory. Must be valid.
+ * @start_page - Starting page to use.
+ * @nr_pages   - Number of pages to place in the new nvgpu_mem.
+ *
+ * Create a new nvgpu_mem struct describing a subsection of the @src nvgpu_mem.
+ * This will create an nvpgu_mem object starting at @start_page and is @nr_pages
+ * long. This currently only works on SYSMEM nvgpu_mems. If this is called on a
+ * VIDMEM nvgpu_mem then this will return an error.
+ *
+ * There is a _major_ caveat to this API: if the source buffer is freed before
+ * the copy is freed then the copy will become invalid. This is a result from
+ * how typical DMA APIs work: we can't call free on the buffer multiple times.
+ * Nor can we call free on parts of a buffer. Thus the only way to ensure that
+ * the entire buffer is actually freed is to call free once on the source
+ * buffer. Since these nvgpu_mem structs are not ref-counted in anyway it is up
+ * to the caller of this API to _ensure_ that the resulting nvgpu_mem buffer
+ * from this API is freed before the source buffer. Otherwise there can and will
+ * be memory corruption.
+ *
+ * The resulting nvgpu_mem should be released with the nvgpu_dma_free() or the
+ * nvgpu_dma_unmap_free() function depending on whether or not the resulting
+ * nvgpu_mem has been mapped.
+ *
+ * This will return 0 on success. An error is returned if the resulting
+ * nvgpu_mem would not make sense or if a new scatter gather table cannot be
+ * created.
+ */
+int nvgpu_mem_create_from_mem(struct gk20a *g,
+                              struct nvgpu_mem *dest, struct nvgpu_mem *src,
+                              int start_page, int nr_pages);
+
+/*
+ * Really free a vidmem buffer. There's a fair amount of work involved in
+ * freeing vidmem buffers in the DMA API. This handles none of that - it only
+ * frees the underlying vidmem specific structures used in vidmem buffers.
+ *
+ * This is implemented in the OS specific code. If it's not necessary it can
+ * be a noop. But the symbol must at least be present.
+ */
+void __nvgpu_mem_free_vidmem_alloc(struct gk20a *g, struct nvgpu_mem *vidmem);
+
+/*
+ * Buffer accessors - wrap between begin() and end() if there is no permanent
+ * kernel mapping for this buffer.
+ */
+
+int nvgpu_mem_begin(struct gk20a *g, struct nvgpu_mem *mem);
+/* nop for null mem, like with free() or vunmap() */
+void nvgpu_mem_end(struct gk20a *g, struct nvgpu_mem *mem);
+
+/* word-indexed offset */
+u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w);
+/* byte offset (32b-aligned) */
+u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset);
+/* memcpy to cpu, offset and size in bytes (32b-aligned) */
+void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
+                void *dest, u32 size);
+
+/* word-indexed offset */
+void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data);
+/* byte offset (32b-aligned) */
+void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data);
+/* memcpy from cpu, offset and size in bytes (32b-aligned) */
+void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
+                void *src, u32 size);
+/* size and offset in bytes (32b-aligned), filled with the constant byte c */
+void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
+                u32 c, u32 size);
+
+u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem);
+u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem);
+
+u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture,
+                u32 sysmem_mask, u32 vidmem_mask);
+u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem,
+                u32 sysmem_mask, u32 vidmem_mask);
+
+u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost.h
new file mode 100644
index 00000000..536b248a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_NVHOST_H__
+#define __NVGPU_NVHOST_H__
+
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+
+struct nvgpu_nvhost_dev;
+struct gk20a;
+struct sync_pt;
+struct sync_fence;
+struct timespec;
+
+int nvgpu_get_nvhost_dev(struct gk20a *g);
+void nvgpu_free_nvhost_dev(struct gk20a *g);
+
+int nvgpu_nvhost_module_busy_ext(struct nvgpu_nvhost_dev *nvhost_dev);
+void nvgpu_nvhost_module_idle_ext(struct nvgpu_nvhost_dev *nvhost_dev);
+
+void nvgpu_nvhost_debug_dump_device(struct nvgpu_nvhost_dev *nvhost_dev);
+
+int nvgpu_nvhost_syncpt_is_expired_ext(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id, u32 thresh);
+int nvgpu_nvhost_syncpt_wait_timeout_ext(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id, u32 thresh, u32 timeout, u32 *value, struct timespec *ts);
+
+u32 nvgpu_nvhost_syncpt_incr_max_ext(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id, u32 incrs);
+void nvgpu_nvhost_syncpt_set_min_eq_max_ext(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id);
+int nvgpu_nvhost_syncpt_read_ext_check(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id, u32 *val);
+
+int nvgpu_nvhost_intr_register_notifier(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id, u32 thresh, void (*callback)(void *, int), void *private_data);
+
+const char *nvgpu_nvhost_syncpt_get_name(struct nvgpu_nvhost_dev *nvhost_dev,
+        int id);
+bool nvgpu_nvhost_syncpt_is_valid_pt_ext(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id);
+void nvgpu_nvhost_syncpt_put_ref_ext(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id);
+u32 nvgpu_nvhost_get_syncpt_host_managed(struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 param,
+        const char *syncpt_name);
+
+int nvgpu_nvhost_create_symlink(struct gk20a *g);
+void nvgpu_nvhost_remove_symlink(struct gk20a *g);
+
+#ifdef CONFIG_SYNC
+u32 nvgpu_nvhost_sync_pt_id(struct sync_pt *pt);
+u32 nvgpu_nvhost_sync_pt_thresh(struct sync_pt *pt);
+int nvgpu_nvhost_sync_num_pts(struct sync_fence *fence);
+
+struct sync_fence *nvgpu_nvhost_sync_fdget(int fd);
+struct sync_fence *nvgpu_nvhost_sync_create_fence(
+        struct nvgpu_nvhost_dev *nvhost_dev,
+        u32 id, u32 thresh, u32 num_pts, const char *name);
+#endif /* CONFIG_SYNC */
+#endif /* CONFIG_TEGRA_GK20A_NVHOST */
+#endif /* __NVGPU_NVHOST_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/page_allocator.h b/drivers/gpu/nvgpu/include/nvgpu/page_allocator.h
new file mode 100644
index 00000000..a6e02058
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/page_allocator.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef PAGE_ALLOCATOR_PRIV_H
+#define PAGE_ALLOCATOR_PRIV_H
+
+#include <nvgpu/allocator.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/kmem.h>
+#include <nvgpu/list.h>
+#include <nvgpu/rbtree.h>
+
+struct nvgpu_allocator;
+
+/*
+ * This allocator implements the ability to do SLAB style allocation since the
+ * GPU has two page sizes available - 4k and 64k/128k. When the default
+ * granularity is the large page size (64k/128k) small allocations become very
+ * space inefficient. This is most notable in PDE and PTE blocks which are 4k
+ * in size.
+ *
+ * Thus we need the ability to suballocate in 64k pages. The way we do this for
+ * the GPU is as follows. We have several buckets for sub-64K allocations:
+ *
+ *   B0 - 4k
+ *   B1 - 8k
+ *   B3 - 16k
+ *   B4 - 32k
+ *   B5 - 64k (for when large pages are 128k)
+ *
+ * When an allocation comes in for less than the large page size (from now on
+ * assumed to be 64k) the allocation is satisfied by one of the buckets.
+ */
+struct page_alloc_slab {
+        struct nvgpu_list_node empty;
+        struct nvgpu_list_node partial;
+        struct nvgpu_list_node full;
+
+        int nr_empty;
+        int nr_partial;
+        int nr_full;
+
+        u32 slab_size;
+};
+
+enum slab_page_state {
+        SP_EMPTY,
+        SP_PARTIAL,
+        SP_FULL,
+        SP_NONE
+};
+
+struct page_alloc_slab_page {
+        unsigned long bitmap;
+        u64 page_addr;
+        u32 slab_size;
+
+        u32 nr_objects;
+        u32 nr_objects_alloced;
+
+        enum slab_page_state state;
+
+        struct page_alloc_slab *owner;
+        struct nvgpu_list_node list_entry;
+};
+
+static inline struct page_alloc_slab_page *
+page_alloc_slab_page_from_list_entry(struct nvgpu_list_node *node)
+{
+        return (struct page_alloc_slab_page *)
+        ((uintptr_t)node - offsetof(struct page_alloc_slab_page, list_entry));
+};
+
+/*
+ * Struct to handle internal management of page allocation. It holds a list
+ * of the chunks of pages that make up the overall allocation - much like a
+ * scatter gather table.
+ */
+struct nvgpu_page_alloc {
+        /*
+         * nvgpu_sgt for describing the actual allocation. Convenient for
+         * GMMU mapping.
+         */
+        struct nvgpu_sgt sgt;
+
+        int nr_chunks;
+        u64 length;
+
+        /*
+         * Only useful for the RB tree - since the alloc may have discontiguous
+         * pages the base is essentially irrelevant except for the fact that it
+         * is guarenteed to be unique.
+         */
+        u64 base;
+
+        struct nvgpu_rbtree_node tree_entry;
+
+        /*
+         * Set if this is a slab alloc. Points back to the slab page that owns
+         * this particular allocation. nr_chunks will always be 1 if this is
+         * set.
+         */
+        struct page_alloc_slab_page *slab_page;
+};
+
+static inline struct nvgpu_page_alloc *
+nvgpu_page_alloc_from_rbtree_node(struct nvgpu_rbtree_node *node)
+{
+        return (struct nvgpu_page_alloc *)
+              ((uintptr_t)node - offsetof(struct nvgpu_page_alloc, tree_entry));
+};
+
+struct nvgpu_page_allocator {
+        struct nvgpu_allocator *owner;  /* Owner of this allocator. */
+
+        /*
+         * Use a buddy allocator to manage the allocation of the underlying
+         * pages. This lets us abstract the discontiguous allocation handling
+         * out of the annoyingly complicated buddy allocator.
+         */
+        struct nvgpu_allocator source_allocator;
+
+        /*
+         * Page params.
+         */
+        u64 base;
+        u64 length;
+        u64 page_size;
+        u32 page_shift;
+
+        struct nvgpu_rbtree_node *allocs;       /* Outstanding allocations. */
+
+        struct page_alloc_slab *slabs;
+        int nr_slabs;
+
+        struct nvgpu_kmem_cache *alloc_cache;
+        struct nvgpu_kmem_cache *slab_page_cache;
+
+        u64 flags;
+
+        /*
+         * Stat tracking.
+         */
+        u64 nr_allocs;
+        u64 nr_frees;
+        u64 nr_fixed_allocs;
+        u64 nr_fixed_frees;
+        u64 nr_slab_allocs;
+        u64 nr_slab_frees;
+        u64 pages_alloced;
+        u64 pages_freed;
+};
+
+static inline struct nvgpu_page_allocator *page_allocator(
+        struct nvgpu_allocator *a)
+{
+        return (struct nvgpu_page_allocator *)(a)->priv;
+}
+
+static inline struct nvgpu_allocator *palloc_owner(
+        struct nvgpu_page_allocator *a)
+{
+        return a->owner;
+}
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
new file mode 100644
index 00000000..045bf34c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
@@ -0,0 +1,465 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_PMU_H__
+#define __NVGPU_PMU_H__
+
+#include <nvgpu/kmem.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/allocator.h>
+#include <nvgpu/lock.h>
+#include <nvgpu/cond.h>
+#include <nvgpu/thread.h>
+#include <nvgpu/nvgpu_common.h>
+#include <nvgpu/flcnif_cmn.h>
+#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
+
+#define nvgpu_pmu_dbg(g, fmt, args...) \
+        nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
+
+/* defined by pmu hw spec */
+#define GK20A_PMU_VA_SIZE               (512 * 1024 * 1024)
+#define GK20A_PMU_UCODE_SIZE_MAX        (256 * 1024)
+#define GK20A_PMU_SEQ_BUF_SIZE          4096
+
+#define GK20A_PMU_TRACE_BUFSIZE         0x4000    /* 4K */
+#define GK20A_PMU_DMEM_BLKSIZE2         8
+
+#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R  6
+#define PMU_MODE_MISMATCH_STATUS_VAL        0xDEADDEAD
+
+/* Falcon Register index */
+#define PMU_FALCON_REG_R0               (0)
+#define PMU_FALCON_REG_R1               (1)
+#define PMU_FALCON_REG_R2               (2)
+#define PMU_FALCON_REG_R3               (3)
+#define PMU_FALCON_REG_R4               (4)
+#define PMU_FALCON_REG_R5               (5)
+#define PMU_FALCON_REG_R6               (6)
+#define PMU_FALCON_REG_R7               (7)
+#define PMU_FALCON_REG_R8               (8)
+#define PMU_FALCON_REG_R9               (9)
+#define PMU_FALCON_REG_R10              (10)
+#define PMU_FALCON_REG_R11              (11)
+#define PMU_FALCON_REG_R12              (12)
+#define PMU_FALCON_REG_R13              (13)
+#define PMU_FALCON_REG_R14              (14)
+#define PMU_FALCON_REG_R15              (15)
+#define PMU_FALCON_REG_IV0              (16)
+#define PMU_FALCON_REG_IV1              (17)
+#define PMU_FALCON_REG_UNDEFINED        (18)
+#define PMU_FALCON_REG_EV               (19)
+#define PMU_FALCON_REG_SP               (20)
+#define PMU_FALCON_REG_PC               (21)
+#define PMU_FALCON_REG_IMB              (22)
+#define PMU_FALCON_REG_DMB              (23)
+#define PMU_FALCON_REG_CSW              (24)
+#define PMU_FALCON_REG_CCR              (25)
+#define PMU_FALCON_REG_SEC              (26)
+#define PMU_FALCON_REG_CTX              (27)
+#define PMU_FALCON_REG_EXCI             (28)
+#define PMU_FALCON_REG_RSVD0    (29)
+#define PMU_FALCON_REG_RSVD1    (30)
+#define PMU_FALCON_REG_RSVD2    (31)
+#define PMU_FALCON_REG_SIZE             (32)
+
+/* Choices for pmu_state */
+#define PMU_STATE_OFF                   0 /* PMU is off */
+#define PMU_STATE_STARTING              1 /* PMU is on, but not booted */
+#define PMU_STATE_INIT_RECEIVED         2 /* PMU init message received */
+#define PMU_STATE_ELPG_BOOTING          3 /* PMU is booting */
+#define PMU_STATE_ELPG_BOOTED           4 /* ELPG is initialized */
+#define PMU_STATE_LOADING_PG_BUF        5 /* Loading PG buf */
+#define PMU_STATE_LOADING_ZBC           6 /* Loading ZBC buf */
+#define PMU_STATE_STARTED               7 /* Fully unitialized */
+#define PMU_STATE_EXIT                  8 /* Exit PMU state machine */
+
+#define GK20A_PMU_UCODE_NB_MAX_OVERLAY      32
+#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH  64
+
+#define PMU_MAX_NUM_SEQUENCES           (256)
+#define PMU_SEQ_BIT_SHIFT               (5)
+#define PMU_SEQ_TBL_SIZE        \
+                (PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT)
+
+#define PMU_INVALID_SEQ_DESC            (~0)
+
+enum {
+        GK20A_PMU_DMAIDX_UCODE          = 0,
+        GK20A_PMU_DMAIDX_VIRT           = 1,
+        GK20A_PMU_DMAIDX_PHYS_VID       = 2,
+        GK20A_PMU_DMAIDX_PHYS_SYS_COH   = 3,
+        GK20A_PMU_DMAIDX_PHYS_SYS_NCOH  = 4,
+        GK20A_PMU_DMAIDX_RSVD           = 5,
+        GK20A_PMU_DMAIDX_PELPG          = 6,
+        GK20A_PMU_DMAIDX_END            = 7
+};
+
+enum {
+        PMU_SEQ_STATE_FREE = 0,
+        PMU_SEQ_STATE_PENDING,
+        PMU_SEQ_STATE_USED,
+        PMU_SEQ_STATE_CANCELLED
+};
+
+/*PG defines used by nvpgu-pmu*/
+#define PMU_PG_IDLE_THRESHOLD_SIM               1000
+#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM  4000000
+/* TBD: QT or else ? */
+#define PMU_PG_IDLE_THRESHOLD                   15000
+#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD      1000000
+
+#define PMU_PG_LPWR_FEATURE_RPPG 0x0
+#define PMU_PG_LPWR_FEATURE_MSCG 0x1
+
+#define PMU_MSCG_DISABLED 0
+#define PMU_MSCG_ENABLED 1
+
+/* Default Sampling Period of AELPG */
+#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US                    (1000000)
+
+/* Default values of APCTRL parameters */
+#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US                   (100)
+#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US                 (10000)
+#define APCTRL_POWER_BREAKEVEN_DEFAULT_US                       (2000)
+#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT                    (200)
+
+typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32,
+        u32);
+
+struct pmu_payload {
+        struct {
+                void *buf;
+                u32 offset;
+                u32 size;
+                u32 fb_size;
+        } in, out;
+};
+
+struct pmu_ucode_desc {
+        u32 descriptor_size;
+        u32 image_size;
+        u32 tools_version;
+        u32 app_version;
+        char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
+        u32 bootloader_start_offset;
+        u32 bootloader_size;
+        u32 bootloader_imem_offset;
+        u32 bootloader_entry_point;
+        u32 app_start_offset;
+        u32 app_size;
+        u32 app_imem_offset;
+        u32 app_imem_entry;
+        u32 app_dmem_offset;
+        /* Offset from appStartOffset */
+        u32 app_resident_code_offset;
+        /* Exact size of the resident code
+         * ( potentially contains CRC inside at the end )
+         */
+        u32 app_resident_code_size;
+        /* Offset from appStartOffset */
+        u32 app_resident_data_offset;
+        /* Exact size of the resident code
+         * ( potentially contains CRC inside at the end )
+         */
+        u32 app_resident_data_size;
+        u32 nb_overlays;
+        struct {u32 start; u32 size; } load_ovl[GK20A_PMU_UCODE_NB_MAX_OVERLAY];
+        u32 compressed;
+};
+
+struct pmu_ucode_desc_v1 {
+        u32 descriptor_size;
+        u32 image_size;
+        u32 tools_version;
+        u32 app_version;
+        char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
+        u32 bootloader_start_offset;
+        u32 bootloader_size;
+        u32 bootloader_imem_offset;
+        u32 bootloader_entry_point;
+        u32 app_start_offset;
+        u32 app_size;
+        u32 app_imem_offset;
+        u32 app_imem_entry;
+        u32 app_dmem_offset;
+        u32 app_resident_code_offset;
+        u32 app_resident_code_size;
+        u32 app_resident_data_offset;
+        u32 app_resident_data_size;
+        u32 nb_imem_overlays;
+        u32 nb_dmem_overlays;
+        struct {u32 start; u32 size; } load_ovl[64];
+        u32 compressed;
+};
+
+struct pmu_queue {
+
+        /* used by hw, for BIOS/SMI queue */
+        u32 mutex_id;
+        u32 mutex_lock;
+        /* used by sw, for LPQ/HPQ queue */
+        struct nvgpu_mutex mutex;
+
+        /* current write position */
+        u32 position;
+        /* physical dmem offset where this queue begins */
+        u32 offset;
+        /* logical queue identifier */
+        u32 id;
+        /* physical queue index */
+        u32 index;
+        /* in bytes */
+        u32 size;
+
+        /* open-flag */
+        u32 oflag;
+        bool opened; /* opened implies locked */
+};
+
+struct pmu_mutex {
+        u32 id;
+        u32 index;
+        u32 ref_cnt;
+};
+
+struct pmu_sequence {
+        u8 id;
+        u32 state;
+        u32 desc;
+        struct pmu_msg *msg;
+        union {
+                struct pmu_allocation_v0 in_v0;
+                struct pmu_allocation_v1 in_v1;
+                struct pmu_allocation_v2 in_v2;
+                struct pmu_allocation_v3 in_v3;
+        };
+        struct nvgpu_mem *in_mem;
+        union {
+                struct pmu_allocation_v0 out_v0;
+                struct pmu_allocation_v1 out_v1;
+                struct pmu_allocation_v2 out_v2;
+                struct pmu_allocation_v3 out_v3;
+        };
+        struct nvgpu_mem *out_mem;
+        u8 *out_payload;
+        pmu_callback callback;
+        void *cb_params;
+};
+
+struct nvgpu_pg_init {
+        bool state_change;
+        struct nvgpu_cond wq;
+        struct nvgpu_thread state_task;
+};
+
+struct nvgpu_pmu {
+        struct gk20a *g;
+        struct nvgpu_falcon *flcn;
+
+        union {
+                struct pmu_ucode_desc *desc;
+                struct pmu_ucode_desc_v1 *desc_v1;
+        };
+        struct nvgpu_mem ucode;
+
+        struct nvgpu_mem pg_buf;
+
+        /* TBD: remove this if ZBC seq is fixed */
+        struct nvgpu_mem seq_buf;
+        struct nvgpu_mem trace_buf;
+        bool buf_loaded;
+
+        struct pmu_sha1_gid gid_info;
+
+        struct pmu_queue queue[PMU_QUEUE_COUNT];
+
+        struct pmu_sequence *seq;
+        unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE];
+        u32 next_seq_desc;
+
+        struct pmu_mutex *mutex;
+        u32 mutex_cnt;
+
+        struct nvgpu_mutex pmu_copy_lock;
+        struct nvgpu_mutex pmu_seq_lock;
+
+        struct nvgpu_allocator dmem;
+
+        u32 *ucode_image;
+        bool pmu_ready;
+
+        u32 zbc_save_done;
+
+        u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE];
+
+        u32 elpg_stat;
+
+        u32 mscg_stat;
+        u32 mscg_transition_state;
+
+        int pmu_state;
+
+#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC        1 /* msec */
+        struct nvgpu_pg_init pg_init;
+        struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */
+        struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */
+        /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */
+        int elpg_refcnt;
+
+        union {
+                struct pmu_perfmon_counter_v2 perfmon_counter_v2;
+                struct pmu_perfmon_counter_v0 perfmon_counter_v0;
+        };
+        u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM];
+
+        bool initialized;
+
+        void (*remove_support)(struct nvgpu_pmu *pmu);
+        bool sw_ready;
+        bool perfmon_ready;
+
+        u32 sample_buffer;
+        u32 load_shadow;
+        u32 load_avg;
+
+        struct nvgpu_mutex isr_mutex;
+        bool isr_enabled;
+
+        bool zbc_ready;
+        union {
+                struct pmu_cmdline_args_v0 args_v0;
+                struct pmu_cmdline_args_v1 args_v1;
+                struct pmu_cmdline_args_v2 args_v2;
+                struct pmu_cmdline_args_v3 args_v3;
+                struct pmu_cmdline_args_v4 args_v4;
+                struct pmu_cmdline_args_v5 args_v5;
+                struct pmu_cmdline_args_v6 args_v6;
+        };
+        unsigned long perfmon_events_cnt;
+        bool perfmon_sampling_enabled;
+        u8 pmu_mode; /*Added for GM20b, and ACR*/
+        u32 falcon_id;
+        u32 aelpg_param[5];
+        u32 override_done;
+
+        struct nvgpu_firmware *fw;
+};
+
+struct pmu_surface {
+        struct nvgpu_mem vidmem_desc;
+        struct nvgpu_mem sysmem_desc;
+        struct flcn_mem_desc_v0 params;
+};
+
+/*PG defines used by nvpgu-pmu*/
+struct pmu_pg_stats_data {
+        u32 gating_cnt;
+        u32 ingating_time;
+        u32 ungating_time;
+        u32 avg_entry_latency_us;
+        u32 avg_exit_latency_us;
+};
+
+/* PMU IPC Methods */
+void nvgpu_pmu_seq_init(struct nvgpu_pmu *pmu);
+
+int nvgpu_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
+int nvgpu_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
+
+int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id,
+        union pmu_init_msg_pmu *init);
+bool nvgpu_pmu_queue_is_empty(struct nvgpu_pmu *pmu, struct pmu_queue *queue);
+
+/* send a cmd to pmu */
+int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
+                struct pmu_msg *msg, struct pmu_payload *payload,
+                u32 queue_id, pmu_callback callback, void *cb_param,
+                u32 *seq_desc, unsigned long timeout);
+
+int nvgpu_pmu_process_message(struct nvgpu_pmu *pmu);
+
+/* perfmon */
+int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu);
+int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu);
+int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu);
+int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu,
+        struct pmu_perfmon_msg *msg);
+int nvgpu_pmu_load_norm(struct gk20a *g, u32 *load);
+int nvgpu_pmu_load_update(struct gk20a *g);
+void nvgpu_pmu_reset_load_counters(struct gk20a *g);
+void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
+                u32 *total_cycles);
+
+int nvgpu_pmu_handle_therm_event(struct nvgpu_pmu *pmu,
+                        struct nv_pmu_therm_msg *msg);
+
+/* PMU init */
+int nvgpu_init_pmu_support(struct gk20a *g);
+int nvgpu_pmu_destroy(struct gk20a *g);
+int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu,
+        struct pmu_msg *msg);
+
+void nvgpu_pmu_state_change(struct gk20a *g, u32 pmu_state,
+        bool post_change_event);
+
+/* NVGPU-PMU MEM alloc */
+void nvgpu_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem);
+void nvgpu_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
+                struct flcn_mem_desc_v0 *fb);
+int nvgpu_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
+                u32 size);
+int nvgpu_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
+                u32 size);
+
+/* PMU F/W support */
+int nvgpu_init_pmu_fw_support(struct nvgpu_pmu *pmu);
+int nvgpu_pmu_prepare_ns_ucode_blob(struct gk20a *g);
+
+/* PG init*/
+int nvgpu_pmu_init_powergating(struct gk20a *g);
+int nvgpu_pmu_init_bind_fecs(struct gk20a *g);
+void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g);
+
+/* PMU reset */
+int nvgpu_pmu_reset(struct gk20a *g);
+
+/* PG enable/disable */
+int nvgpu_pmu_enable_elpg(struct gk20a *g);
+int nvgpu_pmu_disable_elpg(struct gk20a *g);
+int nvgpu_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg);
+
+int nvgpu_pmu_get_pg_stats(struct gk20a *g, u32 pg_engine_id,
+        struct pmu_pg_stats_data *pg_stat_data);
+
+/* AELPG */
+int nvgpu_aelpg_init(struct gk20a *g);
+int nvgpu_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id);
+int nvgpu_pmu_ap_send_command(struct gk20a *g,
+                union pmu_ap_cmd *p_ap_cmd, bool b_block);
+
+/* PMU debug */
+void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
+void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
+bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos);
+
+#endif /* __NVGPU_PMU_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
new file mode 100644
index 00000000..2d31207f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFACR_H_
+#define _GPMUIFACR_H_
+
+/* ACR Commands/Message structures */
+
+enum {
+        PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0,
+        PMU_ACR_CMD_ID_BOOTSTRAP_FALCON,
+        PMU_ACR_CMD_ID_RESERVED,
+        PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS,
+};
+
+/*
+ * Initializes the WPR region details
+ */
+struct pmu_acr_cmd_init_wpr_details {
+        u8  cmd_type;
+        u32 regionid;
+        u32 wproffset;
+
+};
+
+/*
+ * falcon ID to bootstrap
+ */
+struct pmu_acr_cmd_bootstrap_falcon {
+        u8 cmd_type;
+        u32 flags;
+        u32 falconid;
+};
+
+/*
+ * falcon ID to bootstrap
+ */
+struct pmu_acr_cmd_bootstrap_multiple_falcons {
+        u8 cmd_type;
+        u32 flags;
+        u32 falconidmask;
+        u32 usevamask;
+        struct falc_u64 wprvirtualbase;
+};
+
+#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO  1
+#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0
+
+
+struct pmu_acr_cmd {
+        union {
+                u8 cmd_type;
+                struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon;
+                struct pmu_acr_cmd_init_wpr_details init_wpr;
+                struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons;
+        };
+};
+
+/* acr messages */
+
+/*
+ * returns the WPR region init information
+ */
+#define PMU_ACR_MSG_ID_INIT_WPR_REGION   0
+
+/*
+ * Returns the Bootstrapped falcon ID to RM
+ */
+#define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON  1
+
+/*
+ * Returns the WPR init status
+ */
+#define PMU_ACR_SUCCESS                  0
+#define PMU_ACR_ERROR                    1
+
+/*
+ * PMU notifies about bootstrap status of falcon
+ */
+struct pmu_acr_msg_bootstrap_falcon {
+        u8 msg_type;
+        union {
+                u32 errorcode;
+                u32 falconid;
+        };
+};
+
+struct pmu_acr_msg {
+        union {
+                u8 msg_type;
+                struct pmu_acr_msg_bootstrap_falcon acrmsg;
+        };
+};
+
+#endif /* _GPMUIFACR_H_ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h
new file mode 100644
index 00000000..e4f6d5c4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFAP_H_
+#define _GPMUIFAP_H_
+
+/* PMU Command/Message Interfaces for Adaptive Power */
+/* Macro to get Histogram index */
+#define PMU_AP_HISTOGRAM(idx)           (idx)
+#define PMU_AP_HISTOGRAM_CONT           (4)
+
+/* Total number of histogram bins */
+#define PMU_AP_CFG_HISTOGRAM_BIN_N      (16)
+
+/* Mapping between Idle counters and histograms */
+#define PMU_AP_IDLE_MASK_HIST_IDX_0             (2)
+#define PMU_AP_IDLE_MASK_HIST_IDX_1             (3)
+#define PMU_AP_IDLE_MASK_HIST_IDX_2             (5)
+#define PMU_AP_IDLE_MASK_HIST_IDX_3             (6)
+
+
+/* Mapping between AP_CTRLs and Histograms */
+#define PMU_AP_HISTOGRAM_IDX_GRAPHICS   (PMU_AP_HISTOGRAM(1))
+
+/* Mapping between AP_CTRLs and Idle counters */
+#define PMU_AP_IDLE_MASK_GRAPHICS       (PMU_AP_IDLE_MASK_HIST_IDX_1)
+
+/* Adaptive Power Controls (AP_CTRL) */
+enum {
+        PMU_AP_CTRL_ID_GRAPHICS = 0x0,
+        PMU_AP_CTRL_ID_MAX,
+};
+
+/* AP_CTRL Statistics */
+struct pmu_ap_ctrl_stat {
+        /*
+         * Represents whether AP is active or not
+         */
+        u8      b_active;
+
+        /* Idle filter represented by histogram bin index */
+        u8      idle_filter_x;
+        u8      rsvd[2];
+
+        /* Total predicted power saving cycles. */
+        s32     power_saving_h_cycles;
+
+        /* Counts how many times AP gave us -ve power benefits. */
+        u32     bad_decision_count;
+
+        /*
+         * Number of times ap structure needs to skip AP iterations
+         * KICK_CTRL from kernel updates this parameter.
+         */
+        u32     skip_count;
+        u8      bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
+};
+
+/* Parameters initialized by INITn APCTRL command */
+struct pmu_ap_ctrl_init_params {
+        /* Minimum idle filter value in Us */
+        u32     min_idle_filter_us;
+
+        /*
+         * Minimum Targeted Saving in Us. AP will update idle thresholds only
+         * if power saving achieved by updating idle thresholds is greater than
+         * Minimum targeted saving.
+         */
+        u32     min_target_saving_us;
+
+        /* Minimum targeted residency of power feature in Us */
+        u32     power_break_even_us;
+
+        /*
+         * Maximum number of allowed power feature cycles per sample.
+         *
+         * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
+         * AKA pgPerSampleMax in original algorithm.
+         */
+        u32     cycles_per_sample_max;
+};
+
+/* AP Commands/Message structures */
+
+/*
+ * Structure for Generic AP Commands
+ */
+struct pmu_ap_cmd_common {
+        u8      cmd_type;
+        u16     cmd_id;
+};
+
+/*
+ * Structure for INIT AP command
+ */
+struct pmu_ap_cmd_init {
+        u8      cmd_type;
+        u16     cmd_id;
+        u8      rsvd;
+        u32     pg_sampling_period_us;
+};
+
+/*
+ * Structure for Enable/Disable ApCtrl Commands
+ */
+struct pmu_ap_cmd_enable_ctrl {
+        u8      cmd_type;
+        u16     cmd_id;
+
+        u8      ctrl_id;
+};
+
+struct pmu_ap_cmd_disable_ctrl {
+        u8      cmd_type;
+        u16     cmd_id;
+
+        u8      ctrl_id;
+};
+
+/*
+ * Structure for INIT command
+ */
+struct pmu_ap_cmd_init_ctrl {
+        u8                              cmd_type;
+        u16                             cmd_id;
+        u8                              ctrl_id;
+        struct pmu_ap_ctrl_init_params  params;
+};
+
+struct pmu_ap_cmd_init_and_enable_ctrl {
+        u8                              cmd_type;
+        u16                             cmd_id;
+        u8                              ctrl_id;
+        struct pmu_ap_ctrl_init_params  params;
+};
+
+/*
+ * Structure for KICK_CTRL command
+ */
+struct pmu_ap_cmd_kick_ctrl {
+        u8      cmd_type;
+        u16     cmd_id;
+        u8      ctrl_id;
+
+        u32     skip_count;
+};
+
+/*
+ * Structure for PARAM command
+ */
+struct pmu_ap_cmd_param {
+        u8      cmd_type;
+        u16     cmd_id;
+        u8      ctrl_id;
+
+        u32     data;
+};
+
+/*
+ * Defines for AP commands
+ */
+enum {
+        PMU_AP_CMD_ID_INIT = 0x0,
+        PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
+        PMU_AP_CMD_ID_ENABLE_CTRL,
+        PMU_AP_CMD_ID_DISABLE_CTRL,
+        PMU_AP_CMD_ID_KICK_CTRL,
+};
+
+/*
+ * AP Command
+ */
+union pmu_ap_cmd {
+        u8                                      cmd_type;
+        struct pmu_ap_cmd_common                cmn;
+        struct pmu_ap_cmd_init                  init;
+        struct pmu_ap_cmd_init_and_enable_ctrl  init_and_enable_ctrl;
+        struct pmu_ap_cmd_enable_ctrl           enable_ctrl;
+        struct pmu_ap_cmd_disable_ctrl          disable_ctrl;
+        struct pmu_ap_cmd_kick_ctrl             kick_ctrl;
+};
+
+/*
+ * Structure for generic AP Message
+ */
+struct pmu_ap_msg_common {
+        u8      msg_type;
+        u16     msg_id;
+};
+
+/*
+ * Structure for INIT_ACK Message
+ */
+struct pmu_ap_msg_init_ack {
+        u8      msg_type;
+        u16     msg_id;
+        u8      ctrl_id;
+        u32     stats_dmem_offset;
+};
+
+/*
+ * Defines for AP messages
+ */
+enum {
+        PMU_AP_MSG_ID_INIT_ACK = 0x0,
+};
+
+/*
+ * AP Message
+ */
+union pmu_ap_msg {
+        u8                              msg_type;
+        struct pmu_ap_msg_common        cmn;
+        struct pmu_ap_msg_init_ack      init_ack;
+};
+
+/*
+ * Adaptive Power Controller
+ */
+struct ap_ctrl {
+        u32                     stats_dmem_offset;
+        u32                     disable_reason_mask;
+        struct pmu_ap_ctrl_stat stat_cache;
+        u8                      b_ready;
+};
+
+/*
+ * Adaptive Power structure
+ *
+ * ap structure provides generic infrastructure to make any power feature
+ * adaptive.
+ */
+struct pmu_ap {
+        u32                     supported_mask;
+        struct ap_ctrl          ap_ctrl[PMU_AP_CTRL_ID_MAX];
+};
+
+#endif /* _GPMUIFAP_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
new file mode 100644
index 00000000..f39e7b6c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFCMN_H_
+#define _GPMUIFCMN_H_
+
+/*
+ * Defines the logical queue IDs that must be used when submitting
+ * commands to the PMU
+ */
+/* write by sw, read by pmu, protected by sw mutex lock */
+#define PMU_COMMAND_QUEUE_HPQ           0
+/* write by sw, read by pmu, protected by sw mutex lock */
+#define PMU_COMMAND_QUEUE_LPQ           1
+/* read/write by sw/hw, protected by hw pmu mutex, id = 2 */
+#define PMU_COMMAND_QUEUE_BIOS          2
+/* read/write by sw/hw, protected by hw pmu mutex, id = 3 */
+#define PMU_COMMAND_QUEUE_SMI           3
+/* write by pmu, read by sw, accessed by interrupt handler, no lock */
+#define PMU_MESSAGE_QUEUE               4
+#define PMU_QUEUE_COUNT                 5
+
+#define PMU_IS_COMMAND_QUEUE(id)        \
+                ((id)  < PMU_MESSAGE_QUEUE)
+
+#define PMU_IS_SW_COMMAND_QUEUE(id)     \
+                (((id) == PMU_COMMAND_QUEUE_HPQ) || \
+                 ((id) == PMU_COMMAND_QUEUE_LPQ))
+
+#define  PMU_IS_MESSAGE_QUEUE(id)       \
+                ((id) == PMU_MESSAGE_QUEUE)
+
+enum {
+        OFLAG_READ = 0,
+        OFLAG_WRITE
+};
+
+#define QUEUE_SET               (true)
+#define QUEUE_GET               (false)
+
+#define QUEUE_ALIGNMENT         (4)
+
+/* An enumeration containing all valid logical mutex identifiers */
+enum {
+        PMU_MUTEX_ID_RSVD1 = 0,
+        PMU_MUTEX_ID_GPUSER,
+        PMU_MUTEX_ID_QUEUE_BIOS,
+        PMU_MUTEX_ID_QUEUE_SMI,
+        PMU_MUTEX_ID_GPMUTEX,
+        PMU_MUTEX_ID_I2C,
+        PMU_MUTEX_ID_RMLOCK,
+        PMU_MUTEX_ID_MSGBOX,
+        PMU_MUTEX_ID_FIFO,
+        PMU_MUTEX_ID_PG,
+        PMU_MUTEX_ID_GR,
+        PMU_MUTEX_ID_CLK,
+        PMU_MUTEX_ID_RSVD6,
+        PMU_MUTEX_ID_RSVD7,
+        PMU_MUTEX_ID_RSVD8,
+        PMU_MUTEX_ID_RSVD9,
+        PMU_MUTEX_ID_INVALID
+};
+
+#define PMU_MUTEX_ID_IS_VALID(id)       \
+                ((id) < PMU_MUTEX_ID_INVALID)
+
+#define PMU_INVALID_MUTEX_OWNER_ID      (0)
+
+/*
+ * The PMU's frame-buffer interface block has several slots/indices
+ * which can be bound to support DMA to various surfaces in memory
+ */
+enum {
+        PMU_DMAIDX_UCODE         = 0,
+        PMU_DMAIDX_VIRT          = 1,
+        PMU_DMAIDX_PHYS_VID      = 2,
+        PMU_DMAIDX_PHYS_SYS_COH  = 3,
+        PMU_DMAIDX_PHYS_SYS_NCOH = 4,
+        PMU_DMAIDX_RSVD          = 5,
+        PMU_DMAIDX_PELPG         = 6,
+        PMU_DMAIDX_END           = 7
+};
+
+/*
+ * Falcon PMU DMA's minimum size in bytes.
+ */
+#define PMU_DMA_MIN_READ_SIZE_BYTES             16
+#define PMU_DMA_MIN_WRITE_SIZE_BYTES    4
+
+#define PMU_FB_COPY_RW_ALIGNMENT        \
+        ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \
+        PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES)
+
+/*
+ * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned
+ * data structures to issue DMA read/write operations.
+ */
+#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size)           \
+union name##_aligned {                                   \
+                struct name data;                        \
+                u8 pad[ALIGN_UP(sizeof(struct name),     \
+                (PMU_FB_COPY_RW_ALIGNMENT))];            \
+}
+
+#define NV_PMU_MAKE_ALIGNED_UNION(name, size)            \
+union name##_aligned {                                   \
+                union name data;                         \
+                u8 pad[ALIGN_UP(sizeof(union name),      \
+                (PMU_FB_COPY_RW_ALIGNMENT))];            \
+}
+
+#endif /* _GPMUIFCMN_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
new file mode 100644
index 00000000..f8c15324
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFPERFMON_H_
+#define _GPMUIFPERFMON_H_
+
+/*perfmon task defines*/
+
+#define PMU_DOMAIN_GROUP_PSTATE         0
+#define PMU_DOMAIN_GROUP_GPC2CLK        1
+#define PMU_DOMAIN_GROUP_NUM            2
+
+#define PMU_PERFMON_FLAG_ENABLE_INCREASE        (0x00000001)
+#define PMU_PERFMON_FLAG_ENABLE_DECREASE        (0x00000002)
+#define PMU_PERFMON_FLAG_CLEAR_PREV             (0x00000004)
+
+enum pmu_perfmon_cmd_start_fields {
+        COUNTER_ALLOC
+};
+
+enum {
+        PMU_PERFMON_CMD_ID_START = 0,
+        PMU_PERFMON_CMD_ID_STOP  = 1,
+        PMU_PERFMON_CMD_ID_INIT  = 2
+};
+
+struct pmu_perfmon_counter_v0 {
+        u8 index;
+        u8 flags;
+        u8 group_id;
+        u8 valid;
+        u16 upper_threshold; /* units of 0.01% */
+        u16 lower_threshold; /* units of 0.01% */
+};
+
+struct pmu_perfmon_counter_v2 {
+        u8 index;
+        u8 flags;
+        u8 group_id;
+        u8 valid;
+        u16 upper_threshold; /* units of 0.01% */
+        u16 lower_threshold; /* units of 0.01% */
+        u32 scale;
+};
+
+struct pmu_perfmon_cmd_start_v3 {
+        u8 cmd_type;
+        u8 group_id;
+        u8 state_id;
+        u8 flags;
+        struct pmu_allocation_v3 counter_alloc;
+};
+
+struct pmu_perfmon_cmd_start_v2 {
+        u8 cmd_type;
+        u8 group_id;
+        u8 state_id;
+        u8 flags;
+        struct pmu_allocation_v2 counter_alloc;
+};
+
+struct pmu_perfmon_cmd_start_v1 {
+        u8 cmd_type;
+        u8 group_id;
+        u8 state_id;
+        u8 flags;
+        struct pmu_allocation_v1 counter_alloc;
+};
+
+struct pmu_perfmon_cmd_start_v0 {
+        u8 cmd_type;
+        u8 group_id;
+        u8 state_id;
+        u8 flags;
+        struct pmu_allocation_v0 counter_alloc;
+};
+
+struct pmu_perfmon_cmd_stop {
+        u8 cmd_type;
+};
+
+struct pmu_perfmon_cmd_init_v3 {
+        u8 cmd_type;
+        u8 to_decrease_count;
+        u8 base_counter_id;
+        u32 sample_period_us;
+        struct pmu_allocation_v3 counter_alloc;
+        u8 num_counters;
+        u8 samples_in_moving_avg;
+        u16 sample_buffer;
+};
+
+struct pmu_perfmon_cmd_init_v2 {
+        u8 cmd_type;
+        u8 to_decrease_count;
+        u8 base_counter_id;
+        u32 sample_period_us;
+        struct pmu_allocation_v2 counter_alloc;
+        u8 num_counters;
+        u8 samples_in_moving_avg;
+        u16 sample_buffer;
+};
+
+struct pmu_perfmon_cmd_init_v1 {
+        u8 cmd_type;
+        u8 to_decrease_count;
+        u8 base_counter_id;
+        u32 sample_period_us;
+        struct pmu_allocation_v1 counter_alloc;
+        u8 num_counters;
+        u8 samples_in_moving_avg;
+        u16 sample_buffer;
+};
+
+struct pmu_perfmon_cmd_init_v0 {
+        u8 cmd_type;
+        u8 to_decrease_count;
+        u8 base_counter_id;
+        u32 sample_period_us;
+        struct pmu_allocation_v0 counter_alloc;
+        u8 num_counters;
+        u8 samples_in_moving_avg;
+        u16 sample_buffer;
+};
+
+struct pmu_perfmon_cmd {
+        union {
+                u8 cmd_type;
+                struct pmu_perfmon_cmd_start_v0 start_v0;
+                struct pmu_perfmon_cmd_start_v1 start_v1;
+                struct pmu_perfmon_cmd_start_v2 start_v2;
+                struct pmu_perfmon_cmd_start_v3 start_v3;
+                struct pmu_perfmon_cmd_stop stop;
+                struct pmu_perfmon_cmd_init_v0 init_v0;
+                struct pmu_perfmon_cmd_init_v1 init_v1;
+                struct pmu_perfmon_cmd_init_v2 init_v2;
+                struct pmu_perfmon_cmd_init_v3 init_v3;
+        };
+};
+
+struct pmu_zbc_cmd {
+        u8 cmd_type;
+        u8 pad;
+        u16 entry_mask;
+};
+
+/* PERFMON MSG */
+enum {
+        PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
+        PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
+        PMU_PERFMON_MSG_ID_INIT_EVENT     = 2,
+        PMU_PERFMON_MSG_ID_ACK            = 3
+};
+
+struct pmu_perfmon_msg_generic {
+        u8 msg_type;
+        u8 state_id;
+        u8 group_id;
+        u8 data;
+};
+
+struct pmu_perfmon_msg {
+        union {
+                u8 msg_type;
+                struct pmu_perfmon_msg_generic gen;
+        };
+};
+
+#endif /* _GPMUIFPERFMON_H_ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
new file mode 100644
index 00000000..b1077821
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFPG_H_
+#define _GPMUIFPG_H_
+
+#include "gpmuif_ap.h"
+#include "gpmuif_pg_rppg.h"
+
+/*PG defines*/
+
+/* Identifier for each PG */
+#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000)
+#define PMU_PG_ELPG_ENGINE_ID_MS       (0x00000004)
+#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005)
+#define PMU_PG_ELPG_ENGINE_MAX    PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
+
+/* PG message */
+enum {
+        PMU_PG_ELPG_MSG_INIT_ACK,
+        PMU_PG_ELPG_MSG_DISALLOW_ACK,
+        PMU_PG_ELPG_MSG_ALLOW_ACK,
+        PMU_PG_ELPG_MSG_FREEZE_ACK,
+        PMU_PG_ELPG_MSG_FREEZE_ABORT,
+        PMU_PG_ELPG_MSG_UNFREEZE_ACK,
+};
+
+struct pmu_pg_msg_elpg_msg {
+        u8 msg_type;
+        u8 engine_id;
+        u16 msg;
+};
+
+enum {
+        PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
+};
+
+struct pmu_pg_msg_stat {
+        u8 msg_type;
+        u8 engine_id;
+        u16 sub_msg_id;
+        u32 data;
+};
+
+enum {
+        PMU_PG_MSG_ENG_BUF_LOADED,
+        PMU_PG_MSG_ENG_BUF_UNLOADED,
+        PMU_PG_MSG_ENG_BUF_FAILED,
+};
+
+struct pmu_pg_msg_eng_buf_stat {
+        u8 msg_type;
+        u8 engine_id;
+        u8 buf_idx;
+        u8 status;
+};
+
+struct pmu_pg_msg {
+        union {
+                u8 msg_type;
+                struct pmu_pg_msg_elpg_msg elpg_msg;
+                struct pmu_pg_msg_stat stat;
+                struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
+                /* TBD: other pg messages */
+                union pmu_ap_msg ap_msg;
+                struct nv_pmu_rppg_msg rppg_msg;
+        };
+};
+
+/* PG commands */
+enum {
+        PMU_PG_ELPG_CMD_INIT,
+        PMU_PG_ELPG_CMD_DISALLOW,
+        PMU_PG_ELPG_CMD_ALLOW,
+        PMU_PG_ELPG_CMD_FREEZE,
+        PMU_PG_ELPG_CMD_UNFREEZE,
+};
+
+enum {
+        PMU_PG_CMD_ID_ELPG_CMD = 0,
+        PMU_PG_CMD_ID_ENG_BUF_LOAD,
+        PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
+        PMU_PG_CMD_ID_PG_STAT,
+        PMU_PG_CMD_ID_PG_LOG_INIT,
+        PMU_PG_CMD_ID_PG_LOG_FLUSH,
+        PMU_PG_CMD_ID_PG_PARAM,
+        PMU_PG_CMD_ID_ELPG_INIT,
+        PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
+        PMU_PG_CMD_ID_ELPG_ABORT_POLL,
+        PMU_PG_CMD_ID_ELPG_PWR_UP,
+        PMU_PG_CMD_ID_ELPG_DISALLOW,
+        PMU_PG_CMD_ID_ELPG_ALLOW,
+        PMU_PG_CMD_ID_AP,
+        RM_PMU_PG_CMD_ID_PSI,
+        RM_PMU_PG_CMD_ID_CG,
+        PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
+        PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
+        PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
+        PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
+        PMU_PMU_PG_CMD_ID_RPPG = 0x24,
+};
+
+enum {
+        PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
+};
+
+#define PMU_PG_PARAM_CMD_GR_INIT_PARAM  0x0
+#define PMU_PG_PARAM_CMD_MS_INIT_PARAM  0x01
+#define PMU_PG_PARAM_CMD_MCLK_CHANGE  0x04
+#define PMU_PG_PARAM_CMD_POST_INIT  0x06
+#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE  0x07
+
+#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
+#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED  (1 << 2)
+#define PMU_PG_FEATURE_GR_RPPG_ENABLED          (1 << 3)
+
+#define NVGPU_PMU_GR_FEATURE_MASK_RPPG  (1 << 3)
+#define NVGPU_PMU_GR_FEATURE_MASK_ALL   \
+        (       \
+                NVGPU_PMU_GR_FEATURE_MASK_RPPG   \
+        )
+
+#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING  (1 << 0)
+#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR        (1 << 1)
+#define NVGPU_PMU_MS_FEATURE_MASK_RPPG          (1 << 8)
+#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING   (1 << 5)
+
+#define NVGPU_PMU_MS_FEATURE_MASK_ALL   \
+        (       \
+                NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING  |\
+                NVGPU_PMU_MS_FEATURE_MASK_SW_ASR        |\
+                NVGPU_PMU_MS_FEATURE_MASK_RPPG          |\
+                NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING   \
+        )
+
+
+struct pmu_pg_cmd_elpg_cmd {
+        u8 cmd_type;
+        u8 engine_id;
+        u16 cmd;
+};
+
+struct pmu_pg_cmd_eng_buf_load_v0 {
+        u8 cmd_type;
+        u8 engine_id;
+        u8 buf_idx;
+        u8 pad;
+        u16 buf_size;
+        u32 dma_base;
+        u8 dma_offset;
+        u8 dma_idx;
+};
+
+struct pmu_pg_cmd_eng_buf_load_v1 {
+        u8 cmd_type;
+        u8 engine_id;
+        u8 buf_idx;
+        u8 pad;
+        struct flcn_mem_desc {
+                struct falc_u64 dma_addr;
+                u16 dma_size;
+                u8 dma_idx;
+        } dma_desc;
+};
+
+struct pmu_pg_cmd_eng_buf_load_v2 {
+        u8 cmd_type;
+        u8 engine_id;
+        u8 buf_idx;
+        u8 pad;
+        struct flcn_mem_desc_v0 dma_desc;
+};
+
+struct pmu_pg_cmd_gr_init_param {
+        u8 cmd_type;
+        u16 sub_cmd_id;
+        u8 featuremask;
+};
+
+struct pmu_pg_cmd_gr_init_param_v1 {
+        u8 cmd_type;
+        u16 sub_cmd_id;
+        u32 featuremask;
+};
+
+struct pmu_pg_cmd_sub_feature_mask_update {
+        u8 cmd_type;
+        u16 sub_cmd_id;
+        u8 ctrl_id;
+        u32 enabled_mask;
+};
+
+struct pmu_pg_cmd_ms_init_param {
+        u8 cmd_type;
+        u16 cmd_id;
+        u8 psi;
+        u8 idle_flipped_test_enabled;
+        u16 psiSettleTimeUs;
+        u8 rsvd[2];
+        u32 support_mask;
+        u32 abort_timeout_us;
+};
+
+struct pmu_pg_cmd_mclk_change {
+        u8 cmd_type;
+        u16 cmd_id;
+        u8 rsvd;
+        u32 data;
+};
+
+#define PG_VOLT_RAIL_IDX_MAX 2
+
+struct pmu_pg_volt_rail {
+        u8    volt_rail_idx;
+        u8    sleep_volt_dev_idx;
+        u8    sleep_vfe_idx;
+        u32   sleep_voltage_uv;
+        u32   therm_vid0_cache;
+        u32   therm_vid1_cache;
+};
+
+struct pmu_pg_cmd_post_init_param {
+        u8 cmd_type;
+        u16 cmd_id;
+        struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
+};
+
+struct pmu_pg_cmd_stat {
+        u8 cmd_type;
+        u8 engine_id;
+        u16 sub_cmd_id;
+        u32 data;
+};
+
+struct pmu_pg_cmd {
+        union {
+                u8 cmd_type;
+                struct pmu_pg_cmd_elpg_cmd elpg_cmd;
+                struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
+                struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
+                struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
+                struct pmu_pg_cmd_stat stat;
+                struct pmu_pg_cmd_gr_init_param gr_init_param;
+                struct pmu_pg_cmd_gr_init_param_v1 gr_init_param_v1;
+                struct pmu_pg_cmd_ms_init_param ms_init_param;
+                struct pmu_pg_cmd_mclk_change mclk_change;
+                struct pmu_pg_cmd_post_init_param post_init;
+                /* TBD: other pg commands */
+                union pmu_ap_cmd ap_cmd;
+                struct nv_pmu_rppg_cmd rppg_cmd;
+                struct pmu_pg_cmd_sub_feature_mask_update sf_mask_update;
+        };
+};
+
+/* Statistics structure for PG features */
+struct pmu_pg_stats_v2 {
+        u32 entry_count;
+        u32 exit_count;
+        u32 abort_count;
+        u32 detection_count;
+        u32 prevention_activate_count;
+        u32 prevention_deactivate_count;
+        u32 powered_up_time_us;
+        u32 entry_latency_us;
+        u32 exit_latency_us;
+        u32 resident_time_us;
+        u32 entry_latency_avg_us;
+        u32 exit_latency_avg_us;
+        u32 entry_latency_max_us;
+        u32 exit_latency_max_us;
+        u32 total_sleep_time_us;
+        u32 total_non_sleep_time_us;
+};
+
+struct pmu_pg_stats_v1 {
+        /* Number of time PMU successfully engaged sleep state */
+        u32 entry_count;
+        /* Number of time PMU exit sleep state */
+        u32 exit_count;
+        /* Number of time PMU aborted in entry sequence */
+        u32 abort_count;
+        /*
+        * Time for which GPU was neither in Sleep state not
+        * executing sleep sequence.
+        */
+        u32 poweredup_timeus;
+        /* Entry and exit latency of current sleep cycle */
+        u32 entry_latency_us;
+        u32 exitlatencyus;
+        /* Resident time for current sleep cycle. */
+        u32 resident_timeus;
+        /* Rolling average entry and exit latencies */
+        u32 entrylatency_avgus;
+        u32 exitlatency_avgus;
+        /* Max entry and exit latencies */
+        u32 entrylatency_maxus;
+        u32 exitlatency_maxus;
+        /* Total time spent in sleep and non-sleep state */
+        u32 total_sleep_timeus;
+        u32 total_nonsleep_timeus;
+};
+
+struct pmu_pg_stats {
+        u64 pg_entry_start_timestamp;
+        u64 pg_ingating_start_timestamp;
+        u64 pg_exit_start_timestamp;
+        u64 pg_ungating_start_timestamp;
+        u32 pg_avg_entry_time_us;
+        u32 pg_ingating_cnt;
+        u32 pg_ingating_time_us;
+        u32 pg_avg_exit_time_us;
+        u32 pg_ungating_count;
+        u32 pg_ungating_time_us;
+        u32 pg_gating_cnt;
+        u32 pg_gating_deny_cnt;
+};
+
+#endif /* _GPMUIFPG_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h
new file mode 100644
index 00000000..26d38ccb
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFRPPG_H_
+#define _GPMUIFRPPG_H_
+
+#define NV_PMU_RPPG_CTRL_ID_GR    (0x0000)
+#define NV_PMU_RPPG_CTRL_ID_MS    (0x0001)
+#define NV_PMU_RPPG_CTRL_ID_DI    (0x0002)
+#define NV_PMU_RPPG_CTRL_ID_MAX   (0x0003)
+
+#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL  (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\
+        BIT(NV_PMU_RPPG_CTRL_ID_MS) |\
+        BIT(NV_PMU_RPPG_CTRL_ID_DI))
+
+#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0
+
+enum {
+        NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0,
+        NV_PMU_RPPG_DOMAIN_ID_NON_GFX,
+};
+
+struct nv_pmu_rppg_ctrl_stats {
+        u32 entry_count;
+        u32 exit_count;
+};
+
+struct nv_pmu_rppg_cmd_common {
+        u8 cmd_type;
+        u8 cmd_id;
+};
+
+struct nv_pmu_rppg_cmd_init {
+        u8 cmd_type;
+        u8 cmd_id;
+};
+
+struct nv_pmu_rppg_cmd_init_ctrl {
+        u8 cmd_type;
+        u8 cmd_id;
+        u8 ctrl_id;
+        u8 domain_id;
+};
+
+struct nv_pmu_rppg_cmd_stats_reset {
+        u8 cmd_type;
+        u8 cmd_id;
+        u8 ctrl_id;
+};
+
+struct nv_pmu_rppg_cmd {
+        union {
+                u8 cmd_type;
+                struct nv_pmu_rppg_cmd_common cmn;
+                struct nv_pmu_rppg_cmd_init init;
+                struct nv_pmu_rppg_cmd_init_ctrl init_ctrl;
+                struct nv_pmu_rppg_cmd_stats_reset stats_reset;
+        };
+};
+
+enum {
+        NV_PMU_RPPG_CMD_ID_INIT = 0x0,
+        NV_PMU_RPPG_CMD_ID_INIT_CTRL,
+        NV_PMU_RPPG_CMD_ID_STATS_RESET,
+};
+
+
+struct nv_pmu_rppg_msg_common {
+        u8 msg_type;
+        u8 msg_id;
+};
+
+struct nv_pmu_rppg_msg_init_ctrl_ack {
+        u8 msg_type;
+        u8 msg_id;
+        u8 ctrl_id;
+        u32 stats_dmem_offset;
+};
+
+struct nv_pmu_rppg_msg {
+        union {
+                u8 msg_type;
+                struct nv_pmu_rppg_msg_common cmn;
+                struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack;
+        };
+};
+
+enum {
+        NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0,
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
new file mode 100644
index 00000000..91ef1bda
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFPMU_H_
+#define _GPMUIFPMU_H_
+
+#include <nvgpu/flcnif_cmn.h>
+#include "gpmuif_cmn.h"
+
+/* Make sure size of this structure is a multiple of 4 bytes */
+struct pmu_cmdline_args_v0 {
+        u32 cpu_freq_hz;
+        u32 falc_trace_size;
+        u32 falc_trace_dma_base;
+        u32 falc_trace_dma_idx;
+        struct pmu_mem_v0 gc6_ctx;
+};
+
+struct pmu_cmdline_args_v1 {
+        u32 cpu_freq_hz;
+        u32 falc_trace_size;
+        u32 falc_trace_dma_base;
+        u32 falc_trace_dma_idx;
+        u8 secure_mode;
+        struct pmu_mem_v1 gc6_ctx;
+};
+
+struct pmu_cmdline_args_v2 {
+        u32 cpu_freq_hz;
+        u32 falc_trace_size;
+        u32 falc_trace_dma_base;
+        u32 falc_trace_dma_idx;
+        u8 secure_mode;
+        u8 raise_priv_sec;
+        struct pmu_mem_v1 gc6_ctx;
+};
+
+struct pmu_cmdline_args_v3 {
+        u32 reserved;
+        u32 cpu_freq_hz;
+        u32 falc_trace_size;
+        u32 falc_trace_dma_base;
+        u32 falc_trace_dma_idx;
+        u8 secure_mode;
+        u8 raise_priv_sec;
+        struct pmu_mem_v1 gc6_ctx;
+};
+
+struct pmu_cmdline_args_v4 {
+        u32 reserved;
+        u32 cpu_freq_hz;
+        u32 falc_trace_size;
+        struct falc_dma_addr dma_addr;
+        u32 falc_trace_dma_idx;
+        u8 secure_mode;
+        u8 raise_priv_sec;
+        struct pmu_mem_desc_v0 gc6_ctx;
+        u8 pad;
+};
+
+struct pmu_cmdline_args_v5 {
+        u32 cpu_freq_hz;
+        struct flcn_mem_desc_v0 trace_buf;
+        u8 secure_mode;
+        u8 raise_priv_sec;
+        struct flcn_mem_desc_v0 gc6_ctx;
+        struct flcn_mem_desc_v0 init_data_dma_info;
+        u32 dummy;
+};
+
+struct pmu_cmdline_args_v6 {
+        u32 cpu_freq_hz;
+        struct flcn_mem_desc_v0 trace_buf;
+        u8 secure_mode;
+        u8 raise_priv_sec;
+        struct flcn_mem_desc_v0 gc6_ctx;
+        struct flcn_mem_desc_v0 gc6_bsod_ctx;
+        struct flcn_mem_desc_v0 init_data_dma_info;
+        u32 dummy;
+};
+
+/* GPU ID */
+#define PMU_SHA1_GID_SIGNATURE          0xA7C66AD2
+#define PMU_SHA1_GID_SIGNATURE_SIZE     4
+
+#define PMU_SHA1_GID_SIZE       16
+
+struct pmu_sha1_gid {
+        bool valid;
+        u8 gid[PMU_SHA1_GID_SIZE];
+};
+
+struct pmu_sha1_gid_data {
+        u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE];
+        u8 gid[PMU_SHA1_GID_SIZE];
+};
+
+/* PMU INIT MSG */
+enum {
+        PMU_INIT_MSG_TYPE_PMU_INIT = 0,
+};
+
+struct pmu_init_msg_pmu_v0 {
+        u8 msg_type;
+        u8 pad;
+
+        struct {
+                u16 size;
+                u16 offset;
+                u8  index;
+                u8  pad;
+        } queue_info[PMU_QUEUE_COUNT];
+
+        u16 sw_managed_area_offset;
+        u16 sw_managed_area_size;
+};
+
+struct pmu_init_msg_pmu_v1 {
+        u8 msg_type;
+        u8 pad;
+        u16  os_debug_entry_point;
+
+        struct {
+                u16 size;
+                u16 offset;
+                u8  index;
+                u8  pad;
+        } queue_info[PMU_QUEUE_COUNT];
+
+        u16 sw_managed_area_offset;
+        u16 sw_managed_area_size;
+};
+struct pmu_init_msg_pmu_v2 {
+        u8 msg_type;
+        u8 pad;
+        u16  os_debug_entry_point;
+
+        struct {
+                u16 size;
+                u16 offset;
+                u8  index;
+                u8  pad;
+        } queue_info[PMU_QUEUE_COUNT];
+
+        u16 sw_managed_area_offset;
+        u16 sw_managed_area_size;
+        u8 dummy[18];
+};
+
+#define PMU_QUEUE_COUNT_FOR_V4 5
+#define PMU_QUEUE_COUNT_FOR_V3 3
+#define PMU_QUEUE_HPQ_IDX_FOR_V3 0
+#define PMU_QUEUE_LPQ_IDX_FOR_V3 1
+#define PMU_QUEUE_MSG_IDX_FOR_V3 2
+#define PMU_QUEUE_MSG_IDX_FOR_V4 4
+struct pmu_init_msg_pmu_v3 {
+        u8 msg_type;
+        u8  queue_index[PMU_QUEUE_COUNT_FOR_V3];
+        u16 queue_size[PMU_QUEUE_COUNT_FOR_V3];
+        u16 queue_offset;
+
+        u16 sw_managed_area_offset;
+        u16 sw_managed_area_size;
+
+        u16  os_debug_entry_point;
+
+        u8 dummy[18];
+};
+
+struct pmu_init_msg_pmu_v4 {
+        u8 msg_type;
+        u8  queue_index[PMU_QUEUE_COUNT_FOR_V4];
+        u16 queue_size[PMU_QUEUE_COUNT_FOR_V4];
+        u16 queue_offset;
+
+        u16 sw_managed_area_offset;
+        u16 sw_managed_area_size;
+
+        u16  os_debug_entry_point;
+
+        u8 dummy[18];
+};
+
+union pmu_init_msg_pmu {
+        struct pmu_init_msg_pmu_v0 v0;
+        struct pmu_init_msg_pmu_v1 v1;
+        struct pmu_init_msg_pmu_v2 v2;
+        struct pmu_init_msg_pmu_v3 v3;
+        struct pmu_init_msg_pmu_v4 v4;
+};
+
+struct pmu_init_msg {
+        union {
+                u8 msg_type;
+                struct pmu_init_msg_pmu_v1 pmu_init_v1;
+                struct pmu_init_msg_pmu_v0 pmu_init_v0;
+                struct pmu_init_msg_pmu_v2 pmu_init_v2;
+                struct pmu_init_msg_pmu_v3 pmu_init_v3;
+                struct pmu_init_msg_pmu_v4 pmu_init_v4;
+        };
+};
+
+/* robust channel (RC) messages */
+enum {
+        PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0,
+};
+
+struct pmu_rc_msg_unhandled_cmd {
+        u8 msg_type;
+        u8 unit_id;
+};
+
+struct pmu_rc_msg {
+        u8 msg_type;
+        struct pmu_rc_msg_unhandled_cmd unhandled_cmd;
+};
+
+#endif /* _GPMUIFPMU_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h
new file mode 100644
index 00000000..9934d3fd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFBIOS_H_
+#define _GPMUIFBIOS_H_
+
+struct nv_pmu_bios_vfield_register_segment_super {
+        u8 type;
+        u8 low_bit;
+        u8 high_bit;
+};
+
+struct nv_pmu_bios_vfield_register_segment_reg {
+        struct nv_pmu_bios_vfield_register_segment_super super;
+        u32 addr;
+};
+
+struct nv_pmu_bios_vfield_register_segment_index_reg {
+        struct nv_pmu_bios_vfield_register_segment_super super;
+        u32 addr;
+        u32 reg_index;
+        u32 index;
+};
+
+union nv_pmu_bios_vfield_register_segment {
+        struct nv_pmu_bios_vfield_register_segment_super super;
+        struct nv_pmu_bios_vfield_register_segment_reg reg;
+        struct nv_pmu_bios_vfield_register_segment_index_reg index_reg;
+};
+
+
+#endif /* _GPMUIFBIOS_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h
new file mode 100644
index 00000000..ee5dfd06
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h
@@ -0,0 +1,204 @@
+/*
+* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+#ifndef _GPMUIFBOARDOBJ_H_
+#define _GPMUIFBOARDOBJ_H_
+
+#include <nvgpu/flcnif_cmn.h>
+#include "ctrl/ctrlboardobj.h"
+
+/*
+ * Base structure describing a BOARDOBJ for communication between Kernel and
+ * PMU.
+ */
+struct nv_pmu_boardobj {
+        u8 type;
+};
+
+/*
+ * Base structure describing a BOARDOBJ for Query interface between Kernel and
+ * PMU.
+ */
+struct nv_pmu_boardobj_query {
+        u8 type;
+};
+
+/*
+ * Virtual base structure describing a BOARDOBJGRP interface between Kernel and
+ * PMU.
+ */
+struct nv_pmu_boardobjgrp_super {
+        u8 type;
+        u8 class_id;
+        u8 obj_slots;
+        u8 rsvd;
+};
+
+struct nv_pmu_boardobjgrp {
+        struct nv_pmu_boardobjgrp_super super;
+        u32 obj_mask;
+};
+
+struct nv_pmu_boardobjgrp_e32 {
+        struct nv_pmu_boardobjgrp_super super;
+        struct ctrl_boardobjgrp_mask_e32 obj_mask;
+};
+
+struct nv_pmu_boardobjgrp_e255 {
+        struct nv_pmu_boardobjgrp_super super;
+        struct ctrl_boardobjgrp_mask_e255 obj_mask;
+};
+
+struct nv_pmu_boardobj_cmd_grp_payload {
+        struct pmu_allocation_v3 dmem_buf;
+        struct flcn_mem_desc_v0 fb;
+        u8 hdr_size;
+        u8 entry_size;
+};
+
+struct nv_pmu_boardobj_cmd_grp {
+        u8 cmd_type;
+        u8 pad[2];
+        u8 class_id;
+        struct nv_pmu_boardobj_cmd_grp_payload grp;
+};
+
+#define NV_PMU_BOARDOBJ_GRP_ALLOC_OFFSET                                       \
+        (NV_OFFSETOF(NV_PMU_BOARDOBJ_CMD_GRP, grp))
+
+struct nv_pmu_boardobj_cmd {
+        union {
+                u8 cmd_type;
+                struct nv_pmu_boardobj_cmd_grp grp;
+                struct nv_pmu_boardobj_cmd_grp grp_set;
+                struct nv_pmu_boardobj_cmd_grp grp_get_status;
+        };
+};
+
+struct nv_pmu_boardobj_msg_grp {
+        u8 msg_type;
+        bool b_success;
+        flcn_status flcn_status;
+        u8 class_id;
+};
+
+struct nv_pmu_boardobj_msg {
+        union {
+                u8 msg_type;
+                struct nv_pmu_boardobj_msg_grp grp;
+                struct nv_pmu_boardobj_msg_grp grp_set;
+                struct nv_pmu_boardobj_msg_grp grp_get_status;
+        };
+};
+
+/*
+* Macro generating structures describing classes which implement
+* NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface.
+*
+* @para    _eng    Name of implementing engine in which this structure is
+* found.
+* @param   _class  Class ID of Objects within Board Object Group.
+* @param   _slots  Max number of elements this group can contain.
+*/
+#define NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, _slots)                     \
+        NV_PMU_MAKE_ALIGNED_STRUCT(                                            \
+        nv_pmu_##_eng##_##_class##_boardobjgrp_set_header, one_structure);     \
+        NV_PMU_MAKE_ALIGNED_UNION(                                             \
+        nv_pmu_##_eng##_##_class##_boardobj_set_union, one_union);             \
+        struct nv_pmu_##_eng##_##_class##_boardobj_grp_set {                   \
+        union nv_pmu_##_eng##_##_class##_boardobjgrp_set_header_aligned  hdr;        \
+        union nv_pmu_##_eng##_##_class##_boardobj_set_union_aligned objects[(_slots)];\
+        }
+
+/*
+* Macro generating structures describing classes which implement
+* NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface.
+*
+* @para    _eng    Name of implementing engine in which this structure is
+* found.
+* @param   _class  Class ID of Objects within Board Object Group.
+*/
+#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(_eng, _class)                         \
+        NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class,                             \
+        CTRL_BOARDOBJGRP_E32_MAX_OBJECTS)
+
+/*
+* Macro generating structures describing classes which implement
+* NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface.
+*
+* @para    _eng    Name of implementing engine in which this structure is
+* found.
+* @param   _class  Class ID of Objects within Board Object Group.
+*/
+#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(_eng, _class)                        \
+        NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class,                             \
+        CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)
+
+/*
+* Macro generating structures for querying dynamic state for classes which
+* implement NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS
+* interface.
+*
+* @para    _eng    Name of implementing engine in which this structure is
+* found.
+* @param   _class  Class ID of Objects within Board Object Group.
+* @param   _slots  Max number of elements this group can contain.
+*/
+#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, _slots)              \
+        NV_PMU_MAKE_ALIGNED_STRUCT(                                            \
+        nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header, struct);     \
+        NV_PMU_MAKE_ALIGNED_UNION(                                             \
+        nv_pmu_##_eng##_##_class##_boardobj_get_status_union, union);          \
+        struct  nv_pmu_##_eng##_##_class##_boardobj_grp_get_status {           \
+        union nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header_aligned \
+        hdr;                                                                   \
+        union nv_pmu_##_eng##_##_class##_boardobj_get_status_union_aligned     \
+        objects[(_slots)];                                                     \
+        }
+
+/*
+* Macro generating structures for querying dynamic state for classes which
+* implement NV_PMU_BOARDOBJGRP_E32  via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS
+* interface.
+*
+* @para    _eng    Name of implementing engine in which this structure is
+* found.
+* @param   _class  Class ID of Objects within Board Object Group.
+*/
+#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(_eng, _class)                  \
+        NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class,                      \
+        CTRL_BOARDOBJGRP_E32_MAX_OBJECTS)
+
+/*
+* Macro generating structures for querying dynamic state for classes which
+* implement NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS
+* interface.
+*
+* @para    _eng    Name of implementing engine in which this structure is
+* found.
+* @param   _class  Class ID of Objects within Board Object Group.
+*/
+#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(_eng, _class)                 \
+        NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class,                      \
+        CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)
+
+
+#endif /*  _GPMUIFBOARDOBJ_H_ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
new file mode 100644
index 00000000..2ea0c548
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
@@ -0,0 +1,464 @@
+/*
+* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef _GPMUIFCLK_H_
+#define _GPMUIFCLK_H_
+
+#include "ctrl/ctrlboardobj.h"
+#include "ctrl/ctrlvolt.h"
+#include "ctrl/ctrlperf.h"
+#include "ctrl/ctrlclk.h"
+#include "gpmuifboardobj.h"
+#include "gpmuifvolt.h"
+#include <nvgpu/flcnif_cmn.h>
+
+enum nv_pmu_clk_clkwhich {
+        clkwhich_mclk           = 5,
+        clkwhich_dispclk        = 7,
+        clkwhich_gpc2clk        = 17,
+        clkwhich_xbar2clk       = 19,
+        clkwhich_sys2clk        = 20,
+        clkwhich_hub2clk        = 21,
+        clkwhich_pwrclk         = 24,
+        clkwhich_nvdclk         = 25,
+        clkwhich_pciegenclk     = 31,
+};
+
+/*
+ * Enumeration of BOARDOBJGRP class IDs within OBJCLK.  Used as "classId"
+ * argument for communications between Kernel and PMU via the various generic
+ * BOARDOBJGRP interfaces.
+ */
+#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN                          0x00
+#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG                            0x01
+#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE                          0x02
+#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE                          0x03
+#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT                        0x04
+#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER                 0x05
+
+/*!
+* CLK_DOMAIN BOARDOBJGRP Header structure.  Describes global state about the
+* CLK_DOMAIN feature.
+*/
+struct nv_pmu_clk_clk_domain_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+        u32 vbios_domains;
+        struct ctrl_boardobjgrp_mask_e32 master_domains_mask;
+        u16 cntr_sampling_periodms;
+        bool b_override_o_v_o_c;
+        bool b_debug_mode;
+        bool b_enforce_vf_monotonicity;
+        bool b_enforce_vf_smoothening;
+        u8 volt_rails_max;
+        struct ctrl_clk_clk_delta deltas;
+};
+
+struct nv_pmu_clk_clk_domain_boardobj_set {
+        struct nv_pmu_boardobj super;
+        enum nv_pmu_clk_clkwhich domain;
+        u32 api_domain;
+        u8 perf_domain_grp_idx;
+};
+
+struct nv_pmu_clk_clk_domain_3x_boardobj_set {
+        struct nv_pmu_clk_clk_domain_boardobj_set super;
+        bool b_noise_aware_capable;
+};
+
+struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set {
+        struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
+        u16 freq_mhz;
+};
+
+struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set {
+        struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
+        u8 clk_prog_idx_first;
+        u8 clk_prog_idx_last;
+        u8 noise_unaware_ordering_index;
+        u8 noise_aware_ordering_index;
+        bool b_force_noise_unaware_ordering;
+        int factory_offset_khz;
+        short freq_delta_min_mhz;
+        short freq_delta_max_mhz;
+        struct ctrl_clk_clk_delta deltas;
+};
+
+struct nv_pmu_clk_clk_domain_3x_master_boardobj_set {
+        struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
+        u32 slave_idxs_mask;
+};
+
+struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
+        struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
+        u8 master_idx;
+};
+
+union nv_pmu_clk_clk_domain_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_clk_clk_domain_boardobj_set super;
+        struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x;
+        struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed;
+        struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog;
+        struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master;
+        struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain);
+
+struct nv_pmu_clk_clk_prog_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e255 super;
+        u8 slave_entry_count;
+        u8 vf_entry_count;
+};
+
+struct nv_pmu_clk_clk_prog_boardobj_set {
+        struct nv_pmu_boardobj super;
+};
+
+struct nv_pmu_clk_clk_prog_1x_boardobj_set {
+        struct nv_pmu_clk_clk_prog_boardobj_set super;
+        u8 source;
+        u16 freq_max_mhz;
+        union ctrl_clk_clk_prog_1x_source_data source_data;
+};
+
+struct nv_pmu_clk_clk_prog_1x_master_boardobj_set {
+        struct nv_pmu_clk_clk_prog_1x_boardobj_set super;
+        bool b_o_c_o_v_enabled;
+        struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[
+                CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES];
+        union ctrl_clk_clk_prog_1x_master_source_data source_data;
+        struct ctrl_clk_clk_delta deltas;
+};
+
+struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set {
+        struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super;
+        struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[
+                CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES];
+};
+
+struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set {
+        struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super;
+        struct ctrl_clk_clk_prog_1x_master_table_slave_entry
+        slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES];
+};
+
+union nv_pmu_clk_clk_prog_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_clk_clk_prog_boardobj_set super;
+        struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x;
+        struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master;
+        struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio;
+        struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog);
+
+struct nv_pmu_clk_lut_device_desc {
+        u8 vselect_mode;
+        u16 hysteresis_threshold;
+};
+
+struct nv_pmu_clk_regime_desc {
+        u8 regime_id;
+        u16 fixed_freq_regime_limit_mhz;
+};
+
+struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+        struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask;
+        u32 lut_step_size_uv;
+        u32 lut_min_voltage_uv;
+        u8 lut_num_entries;
+        u16 max_min_freq_mhz;
+};
+
+struct nv_pmu_clk_clk_fll_device_boardobj_set {
+        struct nv_pmu_boardobj super;
+        u8 id;
+        u8 mdiv;
+        u8 vin_idx_logic;
+        u8 vin_idx_sram;
+        u8 rail_idx_for_lut;
+        u16 input_freq_mhz;
+        u32 clk_domain;
+        struct nv_pmu_clk_lut_device_desc lut_device;
+        struct nv_pmu_clk_regime_desc regime_desc;
+        u8 min_freq_vfe_idx;
+        u8 freq_ctrl_idx;
+        struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask;
+};
+
+union nv_pmu_clk_clk_fll_device_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_clk_clk_fll_device_boardobj_set super;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device);
+
+struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+        bool b_vin_is_disable_allowed;
+};
+
+struct nv_pmu_clk_clk_vin_device_boardobj_set {
+        struct nv_pmu_boardobj super;
+        u8 id;
+        u8 volt_domain;
+        u32 slope;
+        u32 intercept;
+        u32 flls_shared_mask;
+};
+
+union nv_pmu_clk_clk_vin_device_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_clk_clk_vin_device_boardobj_set super;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device);
+
+struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e255 super;
+};
+
+struct nv_pmu_clk_clk_vf_point_boardobj_set {
+        struct nv_pmu_boardobj super;
+        u8 vfe_equ_idx;
+        u8 volt_rail_idx;
+};
+
+struct nv_pmu_clk_clk_vf_point_freq_boardobj_set {
+        struct nv_pmu_clk_clk_vf_point_boardobj_set super;
+        u16 freq_mhz;
+        int volt_delta_uv;
+};
+
+struct nv_pmu_clk_clk_vf_point_volt_boardobj_set {
+        struct nv_pmu_clk_clk_vf_point_boardobj_set super;
+        u32 source_voltage_uv;
+        int freq_delta_khz;
+};
+
+union nv_pmu_clk_clk_vf_point_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_clk_clk_vf_point_boardobj_set super;
+        struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq;
+        struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point);
+
+struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e255 super;
+};
+
+struct nv_pmu_clk_clk_vf_point_boardobj_get_status {
+        struct nv_pmu_boardobj super;
+        struct ctrl_clk_vf_pair pair;
+};
+
+struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status {
+        struct nv_pmu_clk_clk_vf_point_boardobj_get_status super;
+        u16 vf_gain_value;
+};
+
+union nv_pmu_clk_clk_vf_point_boardobj_get_status_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_clk_clk_vf_point_boardobj_get_status super;
+        struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point);
+
+#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS                                  (12)
+
+struct nv_pmu_clk_clk_domain_list {
+        u8 num_domains;
+        struct ctrl_clk_clk_domain_list_item clk_domains[
+                NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
+};
+
+struct nv_pmu_clk_vf_change_inject {
+        u8 flags;
+        struct nv_pmu_clk_clk_domain_list clk_list;
+        struct nv_pmu_volt_volt_rail_list volt_list;
+};
+
+#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN                              (0x00000002)
+#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES       (0x00000001)
+
+struct nv_pmu_clk_load_payload_freq_controllers {
+        struct ctrl_boardobjgrp_mask_e32 load_mask;
+};
+
+struct nv_pmu_clk_load {
+        u8 feature;
+        u32 action_mask;
+        union {
+                struct nv_pmu_clk_load_payload_freq_controllers freq_controllers;
+        } payload;
+};
+/* CLK_FREQ_CONTROLLER */
+#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003)
+
+#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO  (0x00000000)
+#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002)
+
+struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32  super;
+        u32 sampling_period_ms;
+        u8 volt_policy_idx;
+};
+
+struct nv_pmu_clk_clk_freq_controller_boardobj_set {
+        struct nv_pmu_boardobj super;
+        u8   controller_id;
+        u8   parts_freq_mode;
+        bool bdisable;
+        u32  clk_domain;
+        s16  freq_cap_noise_unaware_vmin_above;
+        s16  freq_cap_noise_unaware_vmin_below;
+        s16  freq_hyst_pos_mhz;
+        s16  freq_hyst_neg_mhz;
+};
+
+struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set {
+        struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
+        s32 prop_gain;
+        s32 integ_gain;
+        s32 integ_decay;
+        s32 volt_delta_min;
+        s32 volt_delta_max;
+        u8  slowdown_pct_min;
+        bool bpoison;
+};
+
+union nv_pmu_clk_clk_freq_controller_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
+        struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller);
+
+/* CLK CMD ID definitions.  */
+#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET                          (0x00000000)
+#define NV_PMU_CLK_CMD_ID_RPC                                       (0x00000001)
+#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS                   (0x00000002)
+
+#define NV_PMU_CLK_RPC_ID_LOAD                                      (0x00000002)
+#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT                      (0x00000001)
+
+struct nv_pmu_clk_cmd_rpc {
+        u8 cmd_type;
+        u8 pad[3];
+        struct nv_pmu_allocation request;
+};
+
+#define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET                                        \
+        (offsetof(struct nv_pmu_clk_cmd_rpc, request))
+
+struct nv_pmu_clk_cmd {
+        union {
+                u8 cmd_type;
+                struct nv_pmu_boardobj_cmd_grp grp_set;
+                struct nv_pmu_clk_cmd_rpc rpc;
+                struct nv_pmu_boardobj_cmd_grp grp_get_status;
+        };
+};
+
+struct nv_pmu_clk_rpc {
+        u8 function;
+        bool b_supported;
+        bool b_success;
+        flcn_status flcn_status;
+        union {
+                struct nv_pmu_clk_vf_change_inject clk_vf_change_inject;
+                struct nv_pmu_clk_load clk_load;
+        } params;
+};
+
+/* CLK MSG ID definitions */
+#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET                          (0x00000000)
+#define NV_PMU_CLK_MSG_ID_RPC                                       (0x00000001)
+#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS                   (0x00000002)
+
+struct nv_pmu_clk_msg_rpc {
+        u8 msg_type;
+        u8 rsvd[3];
+        struct nv_pmu_allocation response;
+};
+
+#define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET       \
+        offsetof(struct nv_pmu_clk_msg_rpc, response)
+
+struct nv_pmu_clk_msg {
+        union {
+                u8 msg_type;
+                struct nv_pmu_boardobj_msg_grp grp_set;
+                struct nv_pmu_clk_msg_rpc rpc;
+                struct nv_pmu_boardobj_msg_grp grp_get_status;
+        };
+};
+
+struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_clk_clk_vin_device_boardobj_get_status {
+        struct nv_pmu_boardobj_query super;
+        u32 actual_voltage_uv;
+        u32 corrected_voltage_uv;
+        u8 sampled_code;
+        u8 override_code;
+};
+
+union nv_pmu_clk_clk_vin_device_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_clk_clk_vin_device_boardobj_get_status super;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device);
+
+struct nv_pmu_clk_lut_vf_entry {
+        u32 entry;
+};
+
+struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_clk_clk_fll_device_boardobj_get_status {
+        struct nv_pmu_boardobj_query super;
+        u8 current_regime_id;
+        u16 min_freq_mhz;
+        struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)];
+};
+
+union nv_pmu_clk_clk_fll_device_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_clk_clk_fll_device_boardobj_get_status super;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device);
+
+#endif /*_GPMUIFCLK_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h
new file mode 100644
index 00000000..83d08afc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFPERF_H_
+#define _GPMUIFPERF_H_
+
+#include "gpmuifvolt.h"
+#include "gpmuifperfvfe.h"
+
+/*
+* Enumeration of BOARDOBJGRP class IDs within OBJPERF.  Used as "classId"
+* argument for communications between Kernel and PMU via the various generic
+* BOARDOBJGRP interfaces.
+*/
+#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR                            0x00
+#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU                            0x01
+
+#define NV_PMU_PERF_CMD_ID_RPC                                   (0x00000002)
+#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET                      (0x00000003)
+#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS               (0x00000004)
+
+struct nv_pmu_perf_cmd_set_object {
+        u8 cmd_type;
+        u8 pad[2];
+        u8 object_type;
+        struct nv_pmu_allocation object;
+};
+
+#define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET                            \
+        (offsetof(struct nv_pmu_perf_cmd_set_object, object))
+
+/* RPC IDs */
+#define NV_PMU_PERF_RPC_ID_VFE_LOAD                                 (0x00000001)
+
+/*!
+* Command requesting execution of the perf RPC.
+*/
+struct nv_pmu_perf_cmd_rpc {
+        u8 cmd_type;
+        u8 pad[3];
+        struct nv_pmu_allocation request;
+};
+
+#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET       \
+        offsetof(struct nv_pmu_perf_cmd_rpc, request)
+
+/*!
+* Simply a union of all specific PERF commands. Forms the general packet
+* exchanged between the Kernel and PMU when sending and receiving PERF commands
+* (respectively).
+*/
+struct nv_pmu_perf_cmd {
+        union {
+        u8 cmd_type;
+        struct nv_pmu_perf_cmd_set_object set_object;
+        struct nv_pmu_boardobj_cmd_grp grp_set;
+        struct nv_pmu_boardobj_cmd_grp grp_get_status;
+        };
+};
+
+/*!
+* Defines the data structure used to invoke PMU perf RPCs. Same structure is
+* used to return the result of the RPC execution.
+*/
+struct nv_pmu_perf_rpc {
+        u8 function;
+        bool b_supported;
+        bool b_success;
+        flcn_status flcn_status;
+        union {
+                struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval;
+                struct nv_pmu_perf_rpc_vfe_load vfe_load;
+        } params;
+};
+
+
+/* PERF Message-type Definitions */
+#define NV_PMU_PERF_MSG_ID_RPC                                      (0x00000003)
+#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET                         (0x00000004)
+#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS                  (0x00000006)
+#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK                             (0x00000005)
+
+/*!
+* Message carrying the result of the perf RPC execution.
+*/
+struct nv_pmu_perf_msg_rpc {
+        u8 msg_type;
+        u8 rsvd[3];
+        struct nv_pmu_allocation response;
+};
+
+#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET       \
+        (offsetof(struct nv_pmu_perf_msg_rpc, response))
+
+/*!
+* Simply a union of all specific PERF messages. Forms the general packet
+* exchanged between the Kernel and PMU when sending and receiving PERF messages
+* (respectively).
+*/
+struct nv_pmu_perf_msg {
+        union {
+                u8 msg_type;
+                struct nv_pmu_perf_msg_rpc rpc;
+                struct nv_pmu_boardobj_msg_grp grp_set;
+        };
+};
+
+#endif  /* _GPMUIFPERF_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h
new file mode 100644
index 00000000..18568a4d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GPMUIFPERFVFE_H_
+#define _GPMUIFPERFVFE_H_
+
+#include "gpmuifbios.h"
+#include "gpmuifboardobj.h"
+
+#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT                      0x03
+#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX                             2
+#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX                             16
+#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX                        1
+
+struct nv_pmu_perf_vfe_var_value {
+        u8 var_type;
+        u8 reserved[3];
+        u32 var_value;
+};
+
+union nv_pmu_perf_vfe_equ_result {
+        u32 freq_m_hz;
+        u32 voltu_v;
+        u32 vf_gain;
+        int volt_deltau_v;
+};
+
+struct nv_pmu_perf_rpc_vfe_equ_eval {
+        u8 equ_idx;
+        u8 var_count;
+        u8 output_type;
+        struct nv_pmu_perf_vfe_var_value var_values[
+                NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX];
+        union nv_pmu_perf_vfe_equ_result result;
+};
+
+struct nv_pmu_perf_rpc_vfe_load {
+        bool b_load;
+};
+
+struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_perf_vfe_var_get_status_super {
+        struct nv_pmu_boardobj_query board_obj;
+};
+
+struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status {
+        struct nv_pmu_perf_vfe_var_get_status_super super;
+        u32 fuse_value_integer;
+        u32 fuse_value_hw_integer;
+        u8 fuse_version;
+        bool b_version_check_failed;
+};
+
+union nv_pmu_perf_vfe_var_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_perf_vfe_var_get_status_super super;
+        struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var);
+
+struct nv_pmu_vfe_var {
+        struct nv_pmu_boardobj super;
+        u32 out_range_min;
+        u32 out_range_max;
+};
+
+struct nv_pmu_vfe_var_derived {
+        struct nv_pmu_vfe_var super;
+};
+
+struct nv_pmu_vfe_var_derived_product {
+        struct nv_pmu_vfe_var_derived super;
+        u8 var_idx0;
+        u8 var_idx1;
+};
+
+struct nv_pmu_vfe_var_derived_sum {
+        struct nv_pmu_vfe_var_derived super;
+        u8 var_idx0;
+        u8 var_idx1;
+};
+
+struct nv_pmu_vfe_var_single {
+        struct nv_pmu_vfe_var super;
+        u8 override_type;
+        u32 override_value;
+};
+
+struct nv_pmu_vfe_var_single_frequency {
+        struct nv_pmu_vfe_var_single super;
+};
+
+struct nv_pmu_vfe_var_single_sensed {
+        struct nv_pmu_vfe_var_single super;
+};
+
+struct nv_pmu_vfe_var_single_sensed_fuse_info {
+        u8 segment_count;
+        union nv_pmu_bios_vfield_register_segment segments[
+                NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX];
+};
+
+struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info {
+        struct nv_pmu_vfe_var_single_sensed_fuse_info fuse;
+        u32 fuse_val_default;
+        int hw_correction_scale;
+        int hw_correction_offset;
+        u8 v_field_id;
+};
+
+struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info {
+        struct nv_pmu_vfe_var_single_sensed_fuse_info fuse;
+        u8 ver_expected;
+        bool b_ver_check;
+        bool b_use_default_on_ver_check_fail;
+        u8 v_field_id_ver;
+};
+
+struct nv_pmu_vfe_var_single_sensed_fuse_override_info {
+        u32 fuse_val_override;
+        bool b_fuse_regkey_override;
+};
+
+struct nv_pmu_vfe_var_single_sensed_fuse {
+        struct nv_pmu_vfe_var_single_sensed super;
+        struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info;
+        struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info;
+        struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info;
+};
+
+struct nv_pmu_vfe_var_single_sensed_temp {
+        struct nv_pmu_vfe_var_single_sensed super;
+        u8 therm_channel_index;
+        int temp_hysteresis_positive;
+        int temp_hysteresis_negative;
+        int temp_default;
+};
+
+struct nv_pmu_vfe_var_single_voltage {
+        struct nv_pmu_vfe_var_single super;
+};
+
+struct nv_pmu_perf_vfe_var_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+        u8 polling_periodms;
+};
+
+union nv_pmu_perf_vfe_var_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_vfe_var var;
+        struct nv_pmu_vfe_var_derived var_derived;
+        struct nv_pmu_vfe_var_derived_product var_derived_product;
+        struct nv_pmu_vfe_var_derived_sum var_derived_sum;
+        struct nv_pmu_vfe_var_single var_single;
+        struct nv_pmu_vfe_var_single_frequency var_single_frequiency;
+        struct nv_pmu_vfe_var_single_sensed var_single_sensed;
+        struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse;
+        struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp;
+        struct nv_pmu_vfe_var_single_voltage var_single_voltage;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var);
+
+struct nv_pmu_vfe_equ {
+        struct nv_pmu_boardobj super;
+        u8 var_idx;
+        u8 equ_idx_next;
+        u8 output_type;
+        u32 out_range_min;
+        u32 out_range_max;
+};
+
+struct nv_pmu_vfe_equ_compare {
+        struct nv_pmu_vfe_equ super;
+        u8 func_id;
+        u8 equ_idx_true;
+        u8 equ_idx_false;
+        u32 criteria;
+};
+
+struct nv_pmu_vfe_equ_minmax {
+        struct nv_pmu_vfe_equ super;
+        bool b_max;
+        u8 equ_idx0;
+        u8 equ_idx1;
+};
+
+struct nv_pmu_vfe_equ_quadratic {
+        struct nv_pmu_vfe_equ super;
+        u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT];
+};
+
+struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e255 super;
+};
+
+union nv_pmu_perf_vfe_equ_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_vfe_equ equ;
+        struct nv_pmu_vfe_equ_compare equ_comapre;
+        struct nv_pmu_vfe_equ_minmax equ_minmax;
+        struct nv_pmu_vfe_equ_quadratic equ_quadratic;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ);
+
+#endif  /* _GPMUIFPERFVFE_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h
new file mode 100644
index 00000000..4ac86092
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h
@@ -0,0 +1,443 @@
+/*
+* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef _GPMUIFPMGR_H_
+#define _GPMUIFPMGR_H_
+
+#include "ctrl/ctrlpmgr.h"
+#include "gpmuifboardobj.h"
+#include <nvgpu/flcnif_cmn.h>
+
+struct nv_pmu_pmgr_i2c_device_desc {
+        struct nv_pmu_boardobj super;
+        u8 dcb_index;
+        u16 i2c_address;
+        u32 i2c_flags;
+        u8 i2c_port;
+};
+
+#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES                      (32)
+
+struct nv_pmu_pmgr_i2c_device_desc_table {
+        u32 dev_mask;
+        struct nv_pmu_pmgr_i2c_device_desc
+        devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES];
+};
+
+struct nv_pmu_pmgr_pwr_device_desc {
+        struct nv_pmu_boardobj super;
+        u32 power_corr_factor;
+};
+
+#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM                              0x03
+
+struct nv_pmu_pmgr_pwr_device_desc_ina3221 {
+        struct nv_pmu_pmgr_pwr_device_desc super;
+        u8 i2c_dev_idx;
+        struct ctrl_pmgr_pwr_device_info_rshunt
+                r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM];
+        u16 configuration;
+        u16 mask_enable;
+        u32 event_mask;
+        u16 curr_correct_m;
+        s16 curr_correct_b;
+};
+
+union nv_pmu_pmgr_pwr_device_desc_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_pmgr_pwr_device_desc pwr_dev;
+        struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221;
+};
+
+struct nv_pmu_pmgr_pwr_device_ba_info {
+        bool b_initialized_and_used;
+};
+
+struct nv_pmu_pmgr_pwr_device_desc_table_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+        struct nv_pmu_pmgr_pwr_device_ba_info ba_info;
+};
+
+NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header,
+                sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header));
+NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union,
+                sizeof(union nv_pmu_pmgr_pwr_device_desc_union));
+
+struct nv_pmu_pmgr_pwr_device_desc_table {
+        union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr;
+        union nv_pmu_pmgr_pwr_device_desc_union_aligned
+        devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES];
+};
+
+union nv_pmu_pmgr_pwr_device_dmem_size {
+        union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr;
+        union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device;
+};
+
+struct nv_pmu_pmgr_pwr_channel {
+        struct nv_pmu_boardobj super;
+        u8 pwr_rail;
+        u8 ch_idx;
+        u32 volt_fixedu_v;
+        u32 pwr_corr_slope;
+        s32 pwr_corr_offsetm_w;
+        u32 curr_corr_slope;
+        s32 curr_corr_offsetm_a;
+        u32 dependent_ch_mask;
+};
+
+#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS                                  16
+
+#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS                           16
+
+struct nv_pmu_pmgr_pwr_channel_sensor {
+        struct nv_pmu_pmgr_pwr_channel super;
+        u8 pwr_dev_idx;
+        u8 pwr_dev_prov_idx;
+};
+
+struct nv_pmu_pmgr_pwr_channel_pmu_compactible {
+        u8 pmu_compactible_data[56];
+};
+
+union nv_pmu_pmgr_pwr_channel_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_pmgr_pwr_channel pwr_channel;
+        struct nv_pmu_pmgr_pwr_channel_sensor sensor;
+        struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel;
+};
+
+#define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING                             0x02
+
+struct nv_pmu_pmgr_pwr_monitor_pstate {
+        u32 hw_channel_mask;
+};
+
+union nv_pmu_pmgr_pwr_monitor_type_specific {
+        struct nv_pmu_pmgr_pwr_monitor_pstate pstate;
+};
+
+struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible {
+        u8 pmu_compactible_data[28];
+};
+
+union nv_pmu_pmgr_pwr_chrelationship_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship;
+};
+
+struct nv_pmu_pmgr_pwr_channel_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+        u8 type;
+        union nv_pmu_pmgr_pwr_monitor_type_specific type_specific;
+        u8 sample_count;
+        u16 sampling_periodms;
+        u16 sampling_period_low_powerms;
+        u32 total_gpu_power_channel_mask;
+        u32 physical_channel_mask;
+};
+
+struct nv_pmu_pmgr_pwr_chrelationship_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header,
+                sizeof(struct nv_pmu_pmgr_pwr_channel_header));
+NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header,
+                sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header));
+NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union,
+                sizeof(union nv_pmu_pmgr_pwr_chrelationship_union));
+NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union,
+                sizeof(union nv_pmu_pmgr_pwr_channel_union));
+
+struct nv_pmu_pmgr_pwr_channel_desc {
+        union nv_pmu_pmgr_pwr_channel_header_aligned hdr;
+        union nv_pmu_pmgr_pwr_channel_union_aligned
+        channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS];
+};
+
+struct nv_pmu_pmgr_pwr_chrelationship_desc {
+        union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr;
+        union nv_pmu_pmgr_pwr_chrelationship_union_aligned
+        ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS];
+};
+
+union nv_pmu_pmgr_pwr_monitor_dmem_size {
+        union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr;
+        union nv_pmu_pmgr_pwr_channel_union_aligned channel;
+        union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr;
+        union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels;
+};
+
+struct nv_pmu_pmgr_pwr_monitor_pack {
+        struct nv_pmu_pmgr_pwr_channel_desc channels;
+        struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels;
+};
+
+#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES                                   32
+
+#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS                       32
+
+struct nv_pmu_pmgr_pwr_policy {
+        struct nv_pmu_boardobj super;
+        u8 ch_idx;
+        u8 num_limit_inputs;
+        u8 limit_unit;
+        u8 sample_mult;
+        u32 limit_curr;
+        u32 limit_min;
+        u32 limit_max;
+        struct ctrl_pmgr_pwr_policy_info_integral integral;
+        enum ctrl_pmgr_pwr_policy_filter_type filter_type;
+        union ctrl_pmgr_pwr_policy_filter_param filter_param;
+};
+
+struct nv_pmu_pmgr_pwr_policy_hw_threshold {
+        struct nv_pmu_pmgr_pwr_policy super;
+        u8 threshold_idx;
+        u8 low_threshold_idx;
+        bool b_use_low_threshold;
+        u16 low_threshold_value;
+};
+
+struct nv_pmu_pmgr_pwr_policy_sw_threshold {
+        struct nv_pmu_pmgr_pwr_policy super;
+        u8 threshold_idx;
+        u8 low_threshold_idx;
+        bool b_use_low_threshold;
+        u16 low_threshold_value;
+        u8 event_id;
+};
+
+struct nv_pmu_pmgr_pwr_policy_pmu_compactible {
+        u8 pmu_compactible_data[68];
+};
+
+union nv_pmu_pmgr_pwr_policy_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_pmgr_pwr_policy pwr_policy;
+        struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold;
+        struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold;
+        struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy;
+};
+
+struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible {
+        u8 pmu_compactible_data[24];
+};
+
+union nv_pmu_pmgr_pwr_policy_relationship_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship;
+};
+
+struct nv_pmu_pmgr_pwr_violation_pmu_compactible {
+        u8 pmu_compactible_data[16];
+};
+
+union nv_pmu_pmgr_pwr_violation_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation;
+};
+
+#define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X                    0x30
+
+NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union,
+                sizeof(union nv_pmu_pmgr_pwr_policy_union));
+NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union,
+                sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union));
+
+#define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2
+
+struct nv_pmu_perf_domain_group_limits
+{
+        u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS];
+} ;
+
+#define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT                    0x6
+
+struct nv_pmu_pmgr_pwr_policy_desc_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+        u8 version;
+        bool b_enabled;
+        u8 low_sampling_mult;
+        u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES];
+        u16 base_sample_period;
+        u16 min_client_sample_period;
+        u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT];
+        struct nv_pmu_perf_domain_group_limits global_ceiling;
+};
+
+NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header ,
+                sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header ));
+
+struct nv_pmu_pmgr_pwr_policyrel_desc_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header,
+                sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header));
+
+struct nv_pmu_pmgr_pwr_violation_desc_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header,
+                sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header));
+NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union,
+                sizeof(union nv_pmu_pmgr_pwr_violation_union));
+
+struct nv_pmu_pmgr_pwr_policy_desc {
+        union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr;
+        union nv_pmu_pmgr_pwr_policy_union_aligned
+        policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES];
+};
+
+struct nv_pmu_pmgr_pwr_policyrel_desc {
+        union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr;
+        union nv_pmu_pmgr_pwr_policy_relationship_union_aligned
+        policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS];
+};
+
+struct nv_pmu_pmgr_pwr_violation_desc {
+        union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr;
+        union nv_pmu_pmgr_pwr_violation_union_aligned
+        violations[CTRL_PMGR_PWR_VIOLATION_MAX];
+};
+
+union nv_pmu_pmgr_pwr_policy_dmem_size {
+        union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr;
+        union nv_pmu_pmgr_pwr_policy_union_aligned policy;
+        union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr;
+        union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels;
+        union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr;
+        union nv_pmu_pmgr_pwr_violation_union_aligned violation;
+};
+
+struct nv_pmu_pmgr_pwr_policy_pack {
+        struct nv_pmu_pmgr_pwr_policy_desc policies;
+        struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels;
+        struct nv_pmu_pmgr_pwr_violation_desc violations;
+};
+
+#define NV_PMU_PMGR_CMD_ID_SET_OBJECT                              (0x00000000)
+
+#define NV_PMU_PMGR_MSG_ID_QUERY                                   (0x00000002)
+
+#define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY                       (0x00000001)
+
+#define NV_PMU_PMGR_CMD_ID_LOAD                                    (0x00000006)
+
+#define NV_PMU_PMGR_CMD_ID_UNLOAD                                  (0x00000007)
+
+struct nv_pmu_pmgr_cmd_set_object {
+        u8 cmd_type;
+        u8 pad[2];
+        u8 object_type;
+        struct nv_pmu_allocation object;
+};
+
+#define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET                              (0x04)
+
+#define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE                   (0x00000000)
+
+#define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE                   (0x00000001)
+
+#define NV_PMU_PMGR_OBJECT_PWR_MONITOR                             (0x00000002)
+
+#define NV_PMU_PMGR_OBJECT_PWR_POLICY                              (0x00000005)
+
+struct nv_pmu_pmgr_pwr_devices_query_payload {
+        struct {
+                u32 powerm_w;
+                u32 voltageu_v;
+                u32 currentm_a;
+        } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES];
+};
+
+struct nv_pmu_pmgr_cmd_pwr_devices_query {
+        u8 cmd_type;
+        u8 pad[3];
+        u32 dev_mask;
+        struct nv_pmu_allocation payload;
+};
+
+#define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET                        (0x08)
+
+struct nv_pmu_pmgr_cmd_load {
+        u8 cmd_type;
+};
+
+struct nv_pmu_pmgr_cmd_unload {
+        u8 cmd_type;
+};
+
+struct nv_pmu_pmgr_cmd {
+        union {
+                u8 cmd_type;
+                struct nv_pmu_pmgr_cmd_set_object set_object;
+                struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query;
+                struct nv_pmu_pmgr_cmd_load load;
+                struct nv_pmu_pmgr_cmd_unload unload;
+        };
+};
+
+#define NV_PMU_PMGR_MSG_ID_SET_OBJECT                              (0x00000000)
+
+#define NV_PMU_PMGR_MSG_ID_LOAD                                    (0x00000004)
+
+#define NV_PMU_PMGR_MSG_ID_UNLOAD                                  (0x00000005)
+
+struct nv_pmu_pmgr_msg_set_object {
+        u8 msg_type;
+        bool b_success;
+        flcn_status flcnstatus;
+        u8 object_type;
+};
+
+struct nv_pmu_pmgr_msg_query {
+        u8 msg_type;
+        bool b_success;
+        flcn_status flcnstatus;
+        u8 cmd_type;
+};
+
+struct nv_pmu_pmgr_msg_load {
+        u8 msg_type;
+        bool b_success;
+        flcn_status flcnstatus;
+};
+
+struct nv_pmu_pmgr_msg_unload {
+        u8 msg_type;
+};
+
+struct nv_pmu_pmgr_msg {
+        union {
+                u8 msg_type;
+                struct nv_pmu_pmgr_msg_set_object set_object;
+                struct nv_pmu_pmgr_msg_query query;
+                struct nv_pmu_pmgr_msg_load load;
+                struct nv_pmu_pmgr_msg_unload unload;
+        };
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h
new file mode 100644
index 00000000..fadad61e
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h
@@ -0,0 +1,82 @@
+/*
+* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+#ifndef _GPMUIFSEQ_H_
+#define _GPMUIFSEQ_H_
+
+#include <nvgpu/flcnif_cmn.h>
+
+#define PMU_UNIT_SEQ            (0x02)
+
+/*!
+* @file   gpmuifseq.h
+* @brief  PMU Command/Message Interfaces - Sequencer
+*/
+
+/*!
+* Defines the identifiers various high-level types of sequencer commands.
+*
+* _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT
+*/
+enum {
+        NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0,
+};
+
+struct nv_pmu_seq_cmd_run_script {
+        u8 cmd_type;
+        u8 pad[3];
+        struct pmu_allocation_v3 script_alloc;
+        struct pmu_allocation_v3 reg_alloc;
+};
+
+#define NV_PMU_SEQ_CMD_ALLOC_OFFSET              4
+
+#define NV_PMU_SEQ_MSG_ALLOC_OFFSET                                         \
+        (NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE)
+
+struct nv_pmu_seq_cmd {
+        struct pmu_hdr hdr;
+        union {
+                u8 cmd_type;
+                struct nv_pmu_seq_cmd_run_script run_script;
+        };
+};
+
+enum {
+        NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0,
+};
+
+struct nv_pmu_seq_msg_run_script {
+        u8 msg_type;
+        u8 error_code;
+        u16 error_pc;
+        u32 timeout_stat;
+};
+
+struct nv_pmu_seq_msg {
+        struct pmu_hdr hdr;
+        union {
+                u8 msg_type;
+                struct nv_pmu_seq_msg_run_script run_script;
+        };
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h
new file mode 100644
index 00000000..2caf9c9d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h
@@ -0,0 +1,102 @@
+/*
+* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef _GPMUIFTHERM_H_
+#define _GPMUIFTHERM_H_
+
+#include <nvgpu/flcnif_cmn.h>
+
+#define NV_PMU_THERM_CMD_ID_RPC                                      0x00000002
+#define NV_PMU_THERM_MSG_ID_RPC                                      0x00000002
+#define NV_PMU_THERM_RPC_ID_SLCT                                     0x00000000
+#define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET                   0x00000006
+#define NV_PMU_THERM_EVENT_THERMAL_1                                 0x00000004
+#define NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION                 0x00000001
+#define NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE      0x00000001
+#define NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION           0x00000001
+
+struct nv_pmu_therm_rpc_slct_event_temp_th_set {
+        s32 temp_threshold;
+        u8 event_id;
+        flcn_status flcn_stat;
+};
+
+struct nv_pmu_therm_rpc_slct {
+        u32 mask_enabled;
+        flcn_status flcn_stat;
+};
+
+struct nv_pmu_therm_rpc {
+        u8 function;
+        bool b_supported;
+        union {
+                struct nv_pmu_therm_rpc_slct slct;
+                struct nv_pmu_therm_rpc_slct_event_temp_th_set slct_event_temp_th_set;
+        } params;
+};
+
+struct nv_pmu_therm_cmd_rpc {
+        u8 cmd_type;
+        u8 pad[3];
+        struct nv_pmu_allocation request;
+};
+
+struct nv_pmu_therm_cmd_hw_slowdown_notification {
+        u8 cmd_type;
+        u8 request;
+};
+
+#define NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET       \
+        offsetof(struct nv_pmu_therm_cmd_rpc, request)
+
+struct nv_pmu_therm_cmd {
+        union {
+                u8 cmd_type;
+                struct nv_pmu_therm_cmd_rpc rpc;
+                struct nv_pmu_therm_cmd_hw_slowdown_notification hw_slct_notification;
+        };
+};
+
+struct nv_pmu_therm_msg_rpc {
+        u8 msg_type;
+        u8 rsvd[3];
+        struct nv_pmu_allocation response;
+};
+
+struct nv_pmu_therm_msg_event_hw_slowdown_notification {
+        u8 msg_type;
+        u32 mask;
+};
+
+#define NV_PMU_THERM_MSG_RPC_ALLOC_OFFSET       \
+        offsetof(struct nv_pmu_therm_msg_rpc, response)
+
+struct nv_pmu_therm_msg {
+        union {
+                u8 msg_type;
+                struct nv_pmu_therm_msg_rpc rpc;
+                struct nv_pmu_therm_msg_event_hw_slowdown_notification hw_slct_msg;
+        };
+};
+
+#endif
+
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h
new file mode 100644
index 00000000..994cd5b7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h
@@ -0,0 +1,83 @@
+/*
+* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef _GPMUIFTHERMSENSOR_H_
+#define _GPMUIFTHERMSENSOR_H_
+
+#include "ctrl/ctrltherm.h"
+#include "gpmuifboardobj.h"
+#include <nvgpu/flcnif_cmn.h>
+
+#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE      0x00
+#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL     0x01
+
+#define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET                         0x0000000B
+#define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET                        0x00000008
+
+struct nv_pmu_therm_therm_device_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_therm_therm_device_boardobj_set {
+        struct nv_pmu_boardobj super;
+};
+
+struct nv_pmu_therm_therm_device_i2c_boardobj_set {
+        struct nv_pmu_therm_therm_device_boardobj_set super;
+        u8 i2c_dev_idx;
+};
+
+union nv_pmu_therm_therm_device_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_therm_therm_device_boardobj_set therm_device;
+        struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device);
+
+struct nv_pmu_therm_therm_channel_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_therm_therm_channel_boardobj_set {
+        struct nv_pmu_boardobj super;
+        s16 scaling;
+        s16 offset;
+        s32 temp_min;
+        s32 temp_max;
+};
+
+struct nv_pmu_therm_therm_channel_device_boardobj_set {
+        struct nv_pmu_therm_therm_channel_boardobj_set super;
+        u8 therm_dev_idx;
+        u8 therm_dev_prov_idx;
+};
+
+union nv_pmu_therm_therm_channel_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_therm_therm_channel_boardobj_set therm_channel;
+        struct nv_pmu_therm_therm_channel_device_boardobj_set device;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h
new file mode 100644
index 00000000..c3d540cc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h
@@ -0,0 +1,335 @@
+/*
+* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+#ifndef _GPMUIFVOLT_H_
+#define _GPMUIFVOLT_H_
+
+#include "gpmuifboardobj.h"
+#include <nvgpu/flcnif_cmn.h>
+#include "ctrl/ctrlvolt.h"
+
+#define NV_PMU_VOLT_VALUE_0V_IN_UV      (0)
+
+/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */
+
+#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL              0x00
+#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE    0x01
+#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY    0x02
+
+
+struct nv_pmu_volt_volt_rail_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_rail_boardobj_set {
+
+        struct nv_pmu_boardobj super;
+        u8 rel_limit_vfe_equ_idx;
+        u8 alt_rel_limit_vfe_equ_idx;
+        u8 ov_limit_vfe_equ_idx;
+        u8 vmin_limit_vfe_equ_idx;
+        u8 volt_margin_limit_vfe_equ_idx;
+        u8 pwr_equ_idx;
+        u8 volt_dev_idx_default;
+        struct ctrl_boardobjgrp_mask_e32 volt_dev_mask;
+        s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
+};
+
+union nv_pmu_volt_volt_rail_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_volt_volt_rail_boardobj_set super;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail);
+
+/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */
+
+struct nv_pmu_volt_volt_device_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_device_boardobj_set {
+        struct nv_pmu_boardobj super;
+        u32 switch_delay_us;
+        u32 voltage_min_uv;
+        u32 voltage_max_uv;
+        u32 volt_step_uv;
+};
+
+struct nv_pmu_volt_volt_device_vid_boardobj_set {
+        struct nv_pmu_volt_volt_device_boardobj_set super;
+        s32 voltage_base_uv;
+        s32 voltage_offset_scale_uv;
+        u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES];
+        u8 vsel_mask;
+};
+
+struct nv_pmu_volt_volt_device_pwm_boardobj_set {
+        struct nv_pmu_volt_volt_device_boardobj_set super;
+        u32 raw_period;
+        s32 voltage_base_uv;
+        s32 voltage_offset_scale_uv;
+        enum nv_pmu_pmgr_pwm_source pwm_source;
+};
+
+union nv_pmu_volt_volt_device_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_volt_volt_device_boardobj_set super;
+        struct nv_pmu_volt_volt_device_vid_boardobj_set vid;
+        struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device);
+
+/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */
+struct nv_pmu_volt_volt_policy_boardobjgrp_set_header {
+
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_policy_boardobj_set {
+        struct nv_pmu_boardobj super;
+};
+struct nv_pmu_volt_volt_policy_sr_boardobj_set {
+        struct nv_pmu_volt_volt_policy_boardobj_set super;
+        u8 rail_idx;
+};
+
+struct nv_pmu_volt_volt_policy_splt_r_boardobj_set {
+        struct nv_pmu_volt_volt_policy_boardobj_set super;
+        u8 rail_idx_master;
+        u8 rail_idx_slave;
+        u8 delta_min_vfe_equ_idx;
+        u8 delta_max_vfe_equ_idx;
+        s32 offset_delta_min_uv;
+        s32 offset_delta_max_uv;
+};
+
+struct nv_pmu_volt_volt_policy_srms_boardobj_set {
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
+        u16 inter_switch_delayus;
+};
+
+/* sr - > single_rail */
+struct nv_pmu_volt_volt_policy_srss_boardobj_set {
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
+};
+
+union nv_pmu_volt_volt_policy_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_volt_volt_policy_boardobj_set super;
+        struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail;
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail;
+        struct nv_pmu_volt_volt_policy_srms_boardobj_set
+                        split_rail_m_s;
+        struct nv_pmu_volt_volt_policy_srss_boardobj_set
+                        split_rail_s_s;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy);
+
+/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */
+struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_rail_boardobj_get_status {
+        struct nv_pmu_boardobj_query super;
+        u32 curr_volt_defaultu_v;
+        u32 rel_limitu_v;
+        u32 alt_rel_limitu_v;
+        u32 ov_limitu_v;
+        u32 max_limitu_v;
+        u32 vmin_limitu_v;
+        s32 volt_margin_limitu_v;
+        u32 rsvd;
+};
+
+union nv_pmu_volt_volt_rail_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_volt_volt_rail_boardobj_get_status super;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail);
+
+/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */
+struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_device_boardobj_get_status {
+        struct nv_pmu_boardobj_query super;
+};
+
+union nv_pmu_volt_volt_device_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_volt_volt_device_boardobj_get_status super;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device);
+
+/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */
+struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_policy_boardobj_get_status {
+        struct nv_pmu_boardobj_query super;
+        u32 offset_volt_requ_v;
+        u32 offset_volt_curru_v;
+};
+
+struct nv_pmu_volt_volt_policy_sr_boardobj_get_status {
+        struct nv_pmu_volt_volt_policy_boardobj_get_status super;
+        u32 curr_voltu_v;
+};
+
+struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status {
+        struct nv_pmu_volt_volt_policy_boardobj_get_status super;
+        s32 delta_minu_v;
+        s32 delta_maxu_v;
+        s32 orig_delta_minu_v;
+        s32 orig_delta_maxu_v;
+        u32 curr_volt_masteru_v;
+        u32 curr_volt_slaveu_v;
+        bool b_violation;
+};
+
+/* srms -> split_rail_multi_step */
+struct nv_pmu_volt_volt_policy_srms_boardobj_get_status {
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
+};
+
+/* srss -> split_rail_single_step */
+struct nv_pmu_volt_volt_policy_srss_boardobj_get_status {
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
+};
+
+union nv_pmu_volt_volt_policy_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_volt_volt_policy_boardobj_get_status super;
+        struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail;
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail;
+        struct nv_pmu_volt_volt_policy_srms_boardobj_get_status
+                        split_rail_m_s;
+        struct nv_pmu_volt_volt_policy_srss_boardobj_get_status
+                        split_rail_s_s;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy);
+
+struct nv_pmu_volt_policy_voltage_data {
+        u8 policy_idx;
+        struct ctrl_perf_volt_rail_list
+        rail_list;
+};
+
+struct nv_pmu_volt_rail_get_voltage {
+        u8 rail_idx;
+        u32 voltage_uv;
+};
+
+struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin {
+        u8 num_rails;
+        struct ctrl_volt_volt_rail_list
+        rail_list;
+};
+
+#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET     (0x00000000)
+#define NV_PMU_VOLT_CMD_ID_RPC                          (0x00000001)
+#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS      (0x00000002)
+#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004)
+
+/*!
+* PMU VOLT RPC calls.
+*/
+#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000)
+#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE      (0x00000002)
+#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE        (0x00000003)
+
+struct nv_pmu_volt_cmd_rpc {
+        u8 cmd_type;
+        u8 pad[3];
+        struct nv_pmu_allocation request;
+};
+
+#define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET        \
+        offsetof(struct nv_pmu_volt_cmd_rpc, request)
+
+struct nv_pmu_volt_cmd {
+        union {
+                u8 cmd_type;
+                struct nv_pmu_boardobj_cmd_grp grp_set;
+                struct nv_pmu_volt_cmd_rpc rpc;
+                struct nv_pmu_boardobj_cmd_grp grp_get_status;
+        };
+};
+
+struct nv_pmu_volt_rpc {
+        u8 function;
+        bool b_supported;
+        bool b_success;
+        flcn_status flcn_status;
+        union {
+                struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data;
+                struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage;
+                struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin
+                        volt_rail_set_noise_unaware_vmin;
+        } params;
+};
+
+/*!
+* VOLT MSG ID definitions
+*/
+#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET     (0x00000000)
+#define NV_PMU_VOLT_MSG_ID_RPC                          (0x00000001)
+#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS      (0x00000002)
+
+/*!
+* Message carrying the result of the VOLT RPC execution.
+*/
+struct nv_pmu_volt_msg_rpc {
+        u8 msg_type;
+        u8 rsvd[3];
+        struct nv_pmu_allocation response;
+};
+
+#define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET        \
+                offsetof(struct nv_pmu_volt_msg_rpc, response)
+
+struct nv_pmu_volt_msg {
+        union {
+                u8 msg_type;
+                struct nv_pmu_boardobj_msg_grp grp_set;
+                struct nv_pmu_volt_msg_rpc rpc;
+                struct nv_pmu_boardobj_msg_grp grp_get_status;
+        };
+};
+
+#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS         (2)
+
+struct nv_pmu_volt_volt_rail_list {
+        u8 num_rails;
+        struct ctrl_perf_volt_rail_list_item
+        rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
+};
+
+#endif  /* _GPMUIFVOLT_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
new file mode 100644
index 00000000..fea6326a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _NVGPUGPMUCMDIF_H_
+#define _NVGPUGPMUCMDIF_H_
+
+#include <nvgpu/flcnif_cmn.h>
+#include "gpmuif_cmn.h"
+#include "gpmuif_pmu.h"
+#include "gpmuif_ap.h"
+#include "gpmuif_pg.h"
+#include "gpmuif_perfmon.h"
+#include "gpmuif_acr.h"
+#include "gpmuifboardobj.h"
+#include "gpmuifclk.h"
+#include "gpmuifperf.h"
+#include "gpmuifperfvfe.h"
+#include "gpmuifpmgr.h"
+#include "gpmuifvolt.h"
+#include "gpmuiftherm.h"
+#include "gpmuifthermsensor.h"
+#include "gpmuifseq.h"
+
+struct pmu_cmd {
+        struct pmu_hdr hdr;
+        union {
+                struct pmu_perfmon_cmd perfmon;
+                struct pmu_pg_cmd pg;
+                struct pmu_zbc_cmd zbc;
+                struct pmu_acr_cmd acr;
+                struct nv_pmu_boardobj_cmd boardobj;
+                struct nv_pmu_perf_cmd perf;
+                struct nv_pmu_volt_cmd volt;
+                struct nv_pmu_clk_cmd clk;
+                struct nv_pmu_pmgr_cmd pmgr;
+                struct nv_pmu_therm_cmd therm;
+        } cmd;
+};
+
+struct pmu_msg {
+        struct pmu_hdr hdr;
+        union {
+                struct pmu_init_msg init;
+                struct pmu_perfmon_msg perfmon;
+                struct pmu_pg_msg pg;
+                struct pmu_rc_msg rc;
+                struct pmu_acr_msg acr;
+                struct nv_pmu_boardobj_msg boardobj;
+                struct nv_pmu_perf_msg perf;
+                struct nv_pmu_volt_msg volt;
+                struct nv_pmu_clk_msg clk;
+                struct nv_pmu_pmgr_msg pmgr;
+                struct nv_pmu_therm_msg therm;
+        } msg;
+};
+
+#define PMU_UNIT_REWIND         (0x00)
+#define PMU_UNIT_PG                     (0x03)
+#define PMU_UNIT_INIT           (0x07)
+#define PMU_UNIT_ACR            (0x0A)
+#define PMU_UNIT_PERFMON_T18X   (0x11)
+#define PMU_UNIT_PERFMON        (0x12)
+#define PMU_UNIT_PERF           (0x13)
+#define PMU_UNIT_RC                     (0x1F)
+#define PMU_UNIT_FECS_MEM_OVERRIDE      (0x1E)
+#define PMU_UNIT_CLK    (0x0D)
+#define PMU_UNIT_THERM  (0x14)
+#define PMU_UNIT_PMGR   (0x18)
+#define PMU_UNIT_VOLT   (0x0E)
+
+#define PMU_UNIT_END            (0x23)
+#define PMU_UNIT_INVALID        (0xFF)
+
+#define PMU_UNIT_TEST_START     (0xFE)
+#define PMU_UNIT_END_SIM        (0xFF)
+#define PMU_UNIT_TEST_END       (0xFF)
+
+#define PMU_UNIT_ID_IS_VALID(id)                \
+                (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START))
+
+#endif /* _NVGPUGPMUCMDIF_H_*/
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pramin.h b/drivers/gpu/nvgpu/include/nvgpu/pramin.h
new file mode 100644
index 00000000..33702bc8
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pramin.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_PRAMIN_H__
+#define __NVGPU_PRAMIN_H__
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct mm_gk20a;
+struct nvgpu_mem;
+
+/*
+ * This typedef is for functions that get called during the access_batched()
+ * operation.
+ */
+typedef void (*pramin_access_batch_fn)(struct gk20a *g, u32 start, u32 words,
+                                       u32 **arg);
+
+void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem,
+                                 u32 offset, u32 size,
+                                 pramin_access_batch_fn loop, u32 **arg);
+
+void nvgpu_init_pramin(struct mm_gk20a *mm);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/rbtree.h b/drivers/gpu/nvgpu/include/nvgpu/rbtree.h
new file mode 100644
index 00000000..25740863
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/rbtree.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_RBTREE_H__
+#define __NVGPU_RBTREE_H__
+
+#include <nvgpu/types.h>
+
+struct nvgpu_rbtree_node {
+        u64 key_start;
+        u64 key_end;
+
+        bool is_red; /* !IsRed == IsBlack */
+
+        struct nvgpu_rbtree_node *parent;
+        struct nvgpu_rbtree_node *left;
+        struct nvgpu_rbtree_node *right;
+};
+
+/**
+ * nvgpu_rbtree_insert - insert a new node into rbtree
+ *
+ * @new_node    Pointer to new node.
+ * @root        Pointer to root of tree
+ *
+ * Nodes with duplicate key_start and overlapping ranges
+ * are not allowed
+ */
+void nvgpu_rbtree_insert(struct nvgpu_rbtree_node *new_node,
+                    struct nvgpu_rbtree_node **root);
+
+/**
+ * nvgpu_rbtree_unlink - delete a node from rbtree
+ *
+ * @node        Pointer to node to be deleted
+ * @root        Pointer to root of tree
+ */
+void nvgpu_rbtree_unlink(struct nvgpu_rbtree_node *node,
+                    struct nvgpu_rbtree_node **root);
+
+/**
+ * nvgpu_rbtree_search - search a given key in rbtree
+ *
+ * @key_start   Key to be searched in rbtree
+ * @node        Node pointer to be returned
+ * @root        Pointer to root of tree
+ *
+ * This API will match given key against key_start of each node
+ * In case of a hit, node points to a node with given key
+ * In case of a miss, node is NULL
+ */
+void nvgpu_rbtree_search(u64 key_start, struct nvgpu_rbtree_node **node,
+                             struct nvgpu_rbtree_node *root);
+
+/**
+ * nvgpu_rbtree_range_search - search a node with key falling in range
+ *
+ * @key         Key to be searched in rbtree
+ * @node        Node pointer to be returned
+ * @root        Pointer to root of tree
+ *
+ * This API will match given key and find a node where key value
+ * falls within range of {start, end} keys
+ * In case of a hit, node points to a node with given key
+ * In case of a miss, node is NULL
+ */
+void nvgpu_rbtree_range_search(u64 key,
+                               struct nvgpu_rbtree_node **node,
+                               struct nvgpu_rbtree_node *root);
+
+/**
+ * nvgpu_rbtree_less_than_search - search a node with key lesser than given key
+ *
+ * @key_start   Key to be searched in rbtree
+ * @node        Node pointer to be returned
+ * @root        Pointer to root of tree
+ *
+ * This API will match given key and find a node with highest
+ * key value lesser than given key
+ * In case of a hit, node points to a node with given key
+ * In case of a miss, node is NULL
+ */
+void nvgpu_rbtree_less_than_search(u64 key_start,
+                               struct nvgpu_rbtree_node **node,
+                               struct nvgpu_rbtree_node *root);
+
+/**
+ * nvgpu_rbtree_enum_start - enumerate tree starting at the node with specified value
+ *
+ * @key_start   Key value to begin enumeration from
+ * @node        Pointer to first node in the tree
+ * @root        Pointer to root of tree
+ *
+ * This API returns node pointer pointing to first node in the rbtree
+ */
+void nvgpu_rbtree_enum_start(u64 key_start,
+                        struct nvgpu_rbtree_node **node,
+                        struct nvgpu_rbtree_node *root);
+
+/**
+ * nvgpu_rbtree_enum_next - find next node in enumeration
+ *
+ * @node        Pointer to next node in the tree
+ * @root        Pointer to root of tree
+ *
+ * This API returns node pointer pointing to next node in the rbtree
+ */
+void nvgpu_rbtree_enum_next(struct nvgpu_rbtree_node **node,
+                       struct nvgpu_rbtree_node *root);
+
+#endif /* __NVGPU_RBTREE_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/rwsem.h b/drivers/gpu/nvgpu/include/nvgpu/rwsem.h
new file mode 100644
index 00000000..0366ceff
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/rwsem.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_RWSEM_H__
+#define __NVGPU_RWSEM_H__
+
+#ifdef __KERNEL__
+#include <nvgpu/linux/rwsem.h>
+#else
+#include <nvgpu_rmos/include/rwsem.h>
+#endif
+
+/*
+ * struct nvgpu_rwsem
+ *
+ * Should be implemented per-OS in a separate library
+ * But implementation should adhere to rw_semaphore implementation
+ * as specified in Linux Documentation
+ */
+struct nvgpu_rwsem;
+
+void nvgpu_rwsem_init(struct nvgpu_rwsem *rwsem);
+void nvgpu_rwsem_up_read(struct nvgpu_rwsem *rwsem);
+void nvgpu_rwsem_down_read(struct nvgpu_rwsem *rwsem);
+void nvgpu_rwsem_up_write(struct nvgpu_rwsem *rwsem);
+void nvgpu_rwsem_down_write(struct nvgpu_rwsem *rwsem);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h
new file mode 100644
index 00000000..d36a3270
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SEMAPHORE_GK20A_H
+#define SEMAPHORE_GK20A_H
+
+#include <nvgpu/log.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/atomic.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/kref.h>
+#include <nvgpu/list.h>
+#include <nvgpu/nvgpu_mem.h>
+
+#include "gk20a/gk20a.h"
+#include "gk20a/mm_gk20a.h"
+#include "gk20a/channel_gk20a.h"
+
+#define gpu_sema_dbg(g, fmt, args...)           \
+        nvgpu_log(g, gpu_dbg_sema, fmt, ##args)
+#define gpu_sema_verbose_dbg(g, fmt, args...)   \
+        nvgpu_log(g, gpu_dbg_sema_v, fmt, ##args)
+
+/*
+ * Max number of channels that can be used is 512. This of course needs to be
+ * fixed to be dynamic but still fast.
+ */
+#define SEMAPHORE_POOL_COUNT            512
+#define SEMAPHORE_SIZE                  16
+#define SEMAPHORE_SEA_GROWTH_RATE       32
+
+struct nvgpu_semaphore_sea;
+
+/*
+ * Underlying semaphore data structure. This semaphore can be shared amongst
+ * other semaphore instances.
+ */
+struct nvgpu_semaphore_int {
+        int idx;                        /* Semaphore index. */
+        u32 offset;                     /* Offset into the pool. */
+        nvgpu_atomic_t next_value;      /* Next available value. */
+        u32 nr_incrs;                   /* Number of increments programmed. */
+        struct nvgpu_semaphore_pool *p; /* Pool that owns this sema. */
+        struct channel_gk20a *ch;       /* Channel that owns this sema. */
+        struct nvgpu_list_node hw_sema_list;    /* List of HW semaphores. */
+};
+
+static inline struct nvgpu_semaphore_int *
+nvgpu_semaphore_int_from_hw_sema_list(struct nvgpu_list_node *node)
+{
+        return (struct nvgpu_semaphore_int *)
+         ((uintptr_t)node - offsetof(struct nvgpu_semaphore_int, hw_sema_list));
+};
+
+/*
+ * A semaphore which the rest of the driver actually uses. This consists of a
+ * pointer to a real semaphore and a value to wait for. This allows one physical
+ * semaphore to be shared among an essentially infinite number of submits.
+ */
+struct nvgpu_semaphore {
+        struct nvgpu_semaphore_int *hw_sema;
+
+        nvgpu_atomic_t value;
+        int incremented;
+
+        struct nvgpu_ref ref;
+};
+
+/*
+ * A semaphore pool. Each address space will own exactly one of these.
+ */
+struct nvgpu_semaphore_pool {
+        struct nvgpu_list_node pool_list_entry; /* Node for list of pools. */
+        u64 gpu_va;                             /* GPU access to the pool. */
+        u64 gpu_va_ro;                          /* GPU access to the pool. */
+        int page_idx;                           /* Index into sea bitmap. */
+
+        struct nvgpu_list_node hw_semas;        /* List of HW semas. */
+        DECLARE_BITMAP(semas_alloced, PAGE_SIZE / SEMAPHORE_SIZE);
+
+        struct nvgpu_semaphore_sea *sema_sea;   /* Sea that owns this pool. */
+
+        struct nvgpu_mutex pool_lock;
+
+        /*
+         * This is the address spaces's personal RW table. Other channels will
+         * ultimately map this page as RO. This is a sub-nvgpu_mem from the
+         * sea's mem.
+         */
+        struct nvgpu_mem rw_mem;
+
+        int mapped;
+
+        /*
+         * Sometimes a channel can be released before other channels are
+         * done waiting on it. This ref count ensures that the pool doesn't
+         * go away until all semaphores using this pool are cleaned up first.
+         */
+        struct nvgpu_ref ref;
+};
+
+static inline struct nvgpu_semaphore_pool *
+nvgpu_semaphore_pool_from_pool_list_entry(struct nvgpu_list_node *node)
+{
+        return (struct nvgpu_semaphore_pool *)
+                ((uintptr_t)node -
+                offsetof(struct nvgpu_semaphore_pool, pool_list_entry));
+};
+
+/*
+ * A sea of semaphores pools. Each pool is owned by a single VM. Since multiple
+ * channels can share a VM each channel gets it's own HW semaphore from the
+ * pool. Channels then allocate regular semaphores - basically just a value that
+ * signifies when a particular job is done.
+ */
+struct nvgpu_semaphore_sea {
+        struct nvgpu_list_node pool_list;       /* List of pools in this sea. */
+        struct gk20a *gk20a;
+
+        size_t size;                    /* Number of pages available. */
+        u64 gpu_va;                     /* GPU virtual address of sema sea. */
+        u64 map_size;                   /* Size of the mapping. */
+
+        /*
+         * TODO:
+         * List of pages that we use to back the pools. The number of pages
+         * can grow dynamically since allocating 512 pages for all channels at
+         * once would be a tremendous waste.
+         */
+        int page_count;                 /* Pages allocated to pools. */
+
+        /*
+         * The read-only memory for the entire semaphore sea. Each semaphore
+         * pool needs a sub-nvgpu_mem that will be mapped as RW in its address
+         * space. This sea_mem cannot be freed until all semaphore_pools have
+         * been freed.
+         */
+        struct nvgpu_mem sea_mem;
+
+        /*
+         * Can't use a regular allocator here since the full range of pools are
+         * not always allocated. Instead just use a bitmap.
+         */
+        DECLARE_BITMAP(pools_alloced, SEMAPHORE_POOL_COUNT);
+
+        struct nvgpu_mutex sea_lock;            /* Lock alloc/free calls. */
+};
+
+/*
+ * Semaphore sea functions.
+ */
+struct nvgpu_semaphore_sea *nvgpu_semaphore_sea_create(struct gk20a *gk20a);
+void nvgpu_semaphore_sea_destroy(struct gk20a *g);
+int nvgpu_semaphore_sea_map(struct nvgpu_semaphore_pool *sea,
+                            struct vm_gk20a *vm);
+void nvgpu_semaphore_sea_unmap(struct nvgpu_semaphore_pool *sea,
+                               struct vm_gk20a *vm);
+struct nvgpu_semaphore_sea *nvgpu_semaphore_get_sea(struct gk20a *g);
+
+/*
+ * Semaphore pool functions.
+ */
+struct nvgpu_semaphore_pool *nvgpu_semaphore_pool_alloc(
+        struct nvgpu_semaphore_sea *sea);
+int nvgpu_semaphore_pool_map(struct nvgpu_semaphore_pool *pool,
+                             struct vm_gk20a *vm);
+void nvgpu_semaphore_pool_unmap(struct nvgpu_semaphore_pool *pool,
+                                struct vm_gk20a *vm);
+u64 __nvgpu_semaphore_pool_gpu_va(struct nvgpu_semaphore_pool *p, bool global);
+void nvgpu_semaphore_pool_get(struct nvgpu_semaphore_pool *p);
+void nvgpu_semaphore_pool_put(struct nvgpu_semaphore_pool *p);
+
+/*
+ * Semaphore functions.
+ */
+struct nvgpu_semaphore *nvgpu_semaphore_alloc(struct channel_gk20a *ch);
+void nvgpu_semaphore_put(struct nvgpu_semaphore *s);
+void nvgpu_semaphore_get(struct nvgpu_semaphore *s);
+void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch);
+
+/*
+ * Return the address of a specific semaphore.
+ *
+ * Don't call this on a semaphore you don't own - the VA returned will make no
+ * sense in your specific channel's VM.
+ */
+static inline u64 nvgpu_semaphore_gpu_rw_va(struct nvgpu_semaphore *s)
+{
+        return __nvgpu_semaphore_pool_gpu_va(s->hw_sema->p, false) +
+                s->hw_sema->offset;
+}
+
+/*
+ * Get the global RO address for the semaphore. Can be called on any semaphore
+ * regardless of whether you own it.
+ */
+static inline u64 nvgpu_semaphore_gpu_ro_va(struct nvgpu_semaphore *s)
+{
+        return __nvgpu_semaphore_pool_gpu_va(s->hw_sema->p, true) +
+                s->hw_sema->offset;
+}
+
+static inline u64 nvgpu_hw_sema_addr(struct nvgpu_semaphore_int *hw_sema)
+{
+        return __nvgpu_semaphore_pool_gpu_va(hw_sema->p, true) +
+                hw_sema->offset;
+}
+
+static inline u32 __nvgpu_semaphore_read(struct nvgpu_semaphore_int *hw_sema)
+{
+        return nvgpu_mem_rd(hw_sema->ch->g,
+                            &hw_sema->p->rw_mem, hw_sema->offset);
+}
+
+/*
+ * Read the underlying value from a semaphore.
+ */
+static inline u32 nvgpu_semaphore_read(struct nvgpu_semaphore *s)
+{
+        return __nvgpu_semaphore_read(s->hw_sema);
+}
+
+/*
+ * TODO: handle wrap around... Hmm, how to do this?
+ */
+static inline bool nvgpu_semaphore_is_released(struct nvgpu_semaphore *s)
+{
+        u32 sema_val = nvgpu_semaphore_read(s);
+
+        /*
+         * If the underlying semaphore value is greater than or equal to
+         * the value of the semaphore then the semaphore has been signaled
+         * (a.k.a. released).
+         */
+        return (int)sema_val >= nvgpu_atomic_read(&s->value);
+}
+
+static inline bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s)
+{
+        return !nvgpu_semaphore_is_released(s);
+}
+
+static inline u32 nvgpu_semaphore_get_value(struct nvgpu_semaphore *s)
+{
+        return (u32)nvgpu_atomic_read(&s->value);
+}
+
+static inline u32 nvgpu_semaphore_next_value(struct nvgpu_semaphore *s)
+{
+        return (u32)nvgpu_atomic_read(&s->hw_sema->next_value);
+}
+
+/*
+ * If @force is set then this will not wait for the underlying semaphore to
+ * catch up to the passed semaphore.
+ */
+static inline void __nvgpu_semaphore_release(struct nvgpu_semaphore *s,
+                                             bool force)
+{
+        struct nvgpu_semaphore_int *hw_sema = s->hw_sema;
+        u32 current_val;
+        u32 val = nvgpu_semaphore_get_value(s);
+        int attempts = 0;
+
+        /*
+         * Wait until the sema value is 1 less than the write value. That
+         * way this function is essentially an increment.
+         *
+         * TODO: tune the wait a little better.
+         */
+        while ((current_val = nvgpu_semaphore_read(s)) < (val - 1)) {
+                if (force)
+                        break;
+                nvgpu_msleep(100);
+                attempts += 1;
+                if (attempts > 100) {
+                        WARN(1, "Stall on sema release!");
+                        return;
+                }
+        }
+
+        /*
+         * If the semaphore has already passed the value we would write then
+         * this is really just a NO-OP.
+         */
+        if (current_val >= val)
+                return;
+
+        nvgpu_mem_wr(hw_sema->ch->g, &hw_sema->p->rw_mem, hw_sema->offset, val);
+
+        gpu_sema_verbose_dbg(hw_sema->p->sema_sea->gk20a,
+                             "(c=%d) WRITE %u", hw_sema->ch->chid, val);
+}
+
+static inline void nvgpu_semaphore_release(struct nvgpu_semaphore *s)
+{
+        __nvgpu_semaphore_release(s, false);
+}
+
+/*
+ * Configure a software based increment on this semaphore. This is useful for
+ * when we want the GPU to wait on a SW event before processing a channel.
+ * Another way to describe this is when the GPU needs to wait on a SW pre-fence.
+ * The pre-fence signals SW which in turn calls nvgpu_semaphore_release() which
+ * then allows the GPU to continue.
+ *
+ * Also used to prep a semaphore for an INCR by the GPU.
+ */
+static inline void nvgpu_semaphore_incr(struct nvgpu_semaphore *s)
+{
+        BUG_ON(s->incremented);
+
+        nvgpu_atomic_set(&s->value, nvgpu_atomic_add_return(1, &s->hw_sema->next_value));
+        s->incremented = 1;
+
+        gpu_sema_verbose_dbg(s->hw_sema->p->sema_sea->gk20a,
+                             "INCR sema for c=%d (%u)",
+                             s->hw_sema->ch->chid,
+                             nvgpu_semaphore_next_value(s));
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/soc.h b/drivers/gpu/nvgpu/include/nvgpu/soc.h
new file mode 100644
index 00000000..5001f27f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/soc.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_SOC_H__
+#define __NVGPU_SOC_H__
+
+struct gk20a;
+
+bool nvgpu_platform_is_silicon(struct gk20a *g);
+bool nvgpu_platform_is_simulation(struct gk20a *g);
+bool nvgpu_platform_is_fpga(struct gk20a *g);
+bool nvgpu_is_hypervisor_mode(struct gk20a *g);
+bool nvgpu_is_bpmp_running(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/sort.h b/drivers/gpu/nvgpu/include/nvgpu/sort.h
new file mode 100644
index 00000000..51d1dcf3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/sort.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_SORT_H__
+#define __NVGPU_SORT_H__
+
+#ifdef __KERNEL__
+#include <linux/sort.h>
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/thread.h b/drivers/gpu/nvgpu/include/nvgpu/thread.h
new file mode 100644
index 00000000..79df9cda
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/thread.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_THREAD_H__
+#define __NVGPU_THREAD_H__
+
+#ifdef __KERNEL__
+#include <nvgpu/linux/thread.h>
+#else
+#include <nvgpu_rmos/include/thread.h>
+#endif
+
+/**
+ * nvgpu_thread_create - Create and run a new thread.
+ *
+ * @thread - thread structure to use
+ * @data - data to pass to threadfn
+ * @threadfn - Thread function
+ * @name - name of the thread
+ *
+ * Create a thread and run threadfn in it. The thread stays alive as long as
+ * threadfn is running. As soon as threadfn returns the thread is destroyed.
+ *
+ * threadfn needs to continuously poll nvgpu_thread_should_stop() to determine
+ * if it should exit.
+ */
+int nvgpu_thread_create(struct nvgpu_thread *thread,
+                void *data,
+                int (*threadfn)(void *data), const char *name);
+
+/**
+ * nvgpu_thread_stop - Destroy or request to destroy a thread
+ *
+ * @thread - thread to stop
+ *
+ * Request a thread to stop by setting nvgpu_thread_should_stop() to
+ * true and wait for thread to exit.
+ */
+void nvgpu_thread_stop(struct nvgpu_thread *thread);
+
+/**
+ * nvgpu_thread_should_stop - Query if thread should stop
+ *
+ * @thread
+ *
+ * Return true if thread should exit. Can be run only in the thread's own
+ * context and with the thread as parameter.
+ */
+bool nvgpu_thread_should_stop(struct nvgpu_thread *thread);
+
+/**
+ * nvgpu_thread_is_running - Query if thread is running
+ *
+ * @thread
+ *
+ * Return true if thread is started.
+ */
+bool nvgpu_thread_is_running(struct nvgpu_thread *thread);
+
+#endif /* __NVGPU_THREAD_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/timers.h b/drivers/gpu/nvgpu/include/nvgpu/timers.h
new file mode 100644
index 00000000..b0df29b6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/timers.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_TIMERS_H__
+#define __NVGPU_TIMERS_H__
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+/*
+ * struct nvgpu_timeout - define a timeout.
+ *
+ * There are two types of timer suported:
+ *
+ *   o  NVGPU_TIMER_CPU_TIMER
+ *        Timer uses the CPU to measure the timeout.
+ *
+ *   o  NVGPU_TIMER_RETRY_TIMER
+ *        Instead of measuring a time limit keep track of the number of times
+ *        something has been attempted. After said limit, "expire" the timer.
+ *
+ * Available flags:
+ *
+ *   o  NVGPU_TIMER_NO_PRE_SI
+ *        By default when the system is not running on silicon the timeout
+ *        code will ignore the requested timeout. Specifying this flag will
+ *        override that behavior and honor the timeout regardless of platform.
+ *
+ *   o  NVGPU_TIMER_SILENT_TIMEOUT
+ *        Do not print any messages on timeout. Normally a simple message is
+ *        printed that specifies where the timeout occurred.
+ */
+struct nvgpu_timeout {
+        struct gk20a            *g;
+
+        unsigned int             flags;
+
+        union {
+                s64              time;
+                struct {
+                        u32      max;
+                        u32      attempted;
+                } retries;
+        };
+};
+
+/*
+ * Bit 0 specifies the type of timer: CPU or retry.
+ */
+#define NVGPU_TIMER_CPU_TIMER           (0x0)
+#define NVGPU_TIMER_RETRY_TIMER         (0x1)
+
+/*
+ * Bits 1 through 7 are reserved; bits 8 and up are flags:
+ */
+#define NVGPU_TIMER_NO_PRE_SI           (0x1 << 8)
+#define NVGPU_TIMER_SILENT_TIMEOUT      (0x1 << 9)
+
+#define NVGPU_TIMER_FLAG_MASK           (NVGPU_TIMER_RETRY_TIMER |      \
+                                         NVGPU_TIMER_NO_PRE_SI |        \
+                                         NVGPU_TIMER_SILENT_TIMEOUT)
+
+int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout,
+                       u32 duration, unsigned long flags);
+int nvgpu_timeout_peek_expired(struct nvgpu_timeout *timeout);
+
+#define nvgpu_timeout_expired(__timeout)                                \
+        __nvgpu_timeout_expired_msg(__timeout, (void *)_THIS_IP_, "")
+
+#define nvgpu_timeout_expired_msg(__timeout, fmt, args...)              \
+        __nvgpu_timeout_expired_msg(__timeout, (void *)_THIS_IP_,       \
+                                    fmt, ##args)
+
+/*
+ * Don't use this directly.
+ */
+int __nvgpu_timeout_expired_msg(struct nvgpu_timeout *timeout,
+                              void *caller, const char *fmt, ...);
+
+
+/*
+ * Waits and delays.
+ */
+void nvgpu_msleep(unsigned int msecs);
+void nvgpu_usleep_range(unsigned int min_us, unsigned int max_us);
+void nvgpu_udelay(unsigned int usecs);
+
+/*
+ * Timekeeping.
+ */
+s64 nvgpu_current_time_ms(void);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/types.h b/drivers/gpu/nvgpu/include/nvgpu/types.h
new file mode 100644
index 00000000..8425c25d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/types.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_TYPES_H__
+#define __NVGPU_TYPES_H__
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <nvgpu_rmos/include/types.h>
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/unit.h b/drivers/gpu/nvgpu/include/nvgpu/unit.h
new file mode 100644
index 00000000..ea929916
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/unit.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_UNITS_H__
+#define __NVGPU_UNITS_H__
+
+/*
+ * Enumeration of all units intended to be used by any HAL that requires
+ * unit as parameter.
+ *
+ * Units are added to the enumeration as needed, so it is not complete.
+ */
+enum nvgpu_unit {
+        NVGPU_UNIT_FIFO,
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vm.h
new file mode 100644
index 00000000..0092fa28
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vm.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_VM_VGPU_H__
+#define __NVGPU_VM_VGPU_H__
+
+#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
+int  vgpu_vm_init(struct gk20a *g, struct vm_gk20a *vm);
+void vgpu_vm_remove(struct vm_gk20a *vm);
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vidmem.h b/drivers/gpu/nvgpu/include/nvgpu/vidmem.h
new file mode 100644
index 00000000..62c970d3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/vidmem.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_VIDMEM_H__
+#define __NVGPU_VIDMEM_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/errno.h>
+#include <nvgpu/nvgpu_mem.h>
+
+struct work_struct;
+
+struct gk20a;
+struct mm_gk20a;
+struct nvgpu_mem;
+
+struct nvgpu_vidmem_buf {
+        /*
+         * Must be a pointer since control of this mem is passed over to the
+         * vidmem background clearing thread when the vidmem buf is freed.
+         */
+        struct nvgpu_mem        *mem;
+
+        struct gk20a            *g;
+
+        /*
+         * Filled in by each OS - this holds the necessary data to export this
+         * buffer to userspace. This will eventually be replaced by a struct
+         * which shall be defined in the OS specific vidmem.h header file.
+         */
+        void                    *priv;
+};
+
+#if defined(CONFIG_GK20A_VIDMEM)
+
+/**
+ * nvgpu_vidmem_user_alloc - Allocates a vidmem buffer for userspace
+ *
+ * @g     - The GPU.
+ * @bytes - Size of the buffer in bytes.
+ *
+ * Allocate a generic (OS agnostic) vidmem buffer. This does not allocate the OS
+ * specific interfacing for userspace sharing. Instead is is expected that the
+ * OS specific code will allocate that OS specific data and add it to this
+ * buffer.
+ *
+ * The buffer allocated here is intended to use used by userspace, hence the
+ * extra struct over nvgpu_mem. If a vidmem buffer is needed by the kernel
+ * driver only then a simple nvgpu_dma_alloc_vid() or the like is sufficient.
+ *
+ * Returns a pointer to a vidmem buffer on success, 0 otherwise.
+ */
+struct nvgpu_vidmem_buf *nvgpu_vidmem_user_alloc(struct gk20a *g, size_t bytes);
+
+void nvgpu_vidmem_buf_free(struct gk20a *g, struct nvgpu_vidmem_buf *buf);
+
+int nvgpu_vidmem_clear_list_enqueue(struct gk20a *g, struct nvgpu_mem *mem);
+
+bool nvgpu_addr_is_vidmem_page_alloc(u64 addr);
+int nvgpu_vidmem_get_space(struct gk20a *g, u64 *space);
+
+void nvgpu_vidmem_destroy(struct gk20a *g);
+int nvgpu_vidmem_init(struct mm_gk20a *mm);
+
+int nvgpu_vidmem_clear(struct gk20a *g, struct nvgpu_mem *mem);
+
+void nvgpu_vidmem_thread_pause_sync(struct mm_gk20a *mm);
+void nvgpu_vidmem_thread_unpause(struct mm_gk20a *mm);
+
+#else /* !defined(CONFIG_GK20A_VIDMEM) */
+
+/*
+ * When VIDMEM support is not present this interface is used.
+ */
+
+static inline bool nvgpu_addr_is_vidmem_page_alloc(u64 addr)
+{
+        return false;
+}
+
+static inline int nvgpu_vidmem_buf_alloc(struct gk20a *g, size_t bytes)
+{
+        return -ENOSYS;
+}
+
+static inline void nvgpu_vidmem_buf_free(struct gk20a *g,
+                                         struct nvgpu_vidmem_buf *buf)
+{
+}
+
+static inline int nvgpu_vidmem_get_space(struct gk20a *g, u64 *space)
+{
+        return -ENOSYS;
+}
+
+static inline void nvgpu_vidmem_destroy(struct gk20a *g)
+{
+}
+
+static inline int nvgpu_vidmem_init(struct mm_gk20a *mm)
+{
+        return 0;
+}
+
+static inline int nvgpu_vidmem_clear_all(struct gk20a *g)
+{
+        return -ENOSYS;
+}
+
+static inline int nvgpu_vidmem_clear(struct gk20a *g,
+                                              struct nvgpu_mem *mem)
+{
+        return -ENOSYS;
+}
+
+static inline void nvgpu_vidmem_thread_pause_sync(struct mm_gk20a *mm)
+{
+}
+
+static inline void nvgpu_vidmem_thread_unpause(struct mm_gk20a *mm)
+{
+}
+
+#endif /* !defined(CONFIG_GK20A_VIDMEM) */
+
+/*
+ * Simple macro for VIDMEM debugging.
+ */
+#define vidmem_dbg(g, fmt, args...)                     \
+        nvgpu_log(g, gpu_dbg_vidmem, fmt, ##args);      \
+
+#endif /* __NVGPU_VIDMEM_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h
new file mode 100644
index 00000000..c0a4124c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_VM_H__
+#define __NVGPU_VM_H__
+
+#include <nvgpu/kref.h>
+#include <nvgpu/list.h>
+#include <nvgpu/rbtree.h>
+#include <nvgpu/types.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/allocator.h>
+
+struct dma_buf;
+
+struct vm_gk20a;
+struct nvgpu_vm_area;
+struct gk20a_comptag_allocator;
+
+/*
+ * Defined by each OS. Allows the common VM code do things to the OS specific
+ * buffer structures.
+ */
+struct nvgpu_os_buffer;
+
+#ifdef __KERNEL__
+#include <nvgpu/linux/vm.h>
+#else
+/* QNX include goes here. */
+#include <nvgpu_rmos/include/vm.h>
+#endif
+
+/**
+ * This header contains the OS agnostic APIs for dealing with VMs. Most of the
+ * VM implementation is system specific - it must translate from a platform's
+ * representation of DMA'able memory to our nvgpu_mem notion.
+ *
+ * However, some stuff is platform agnostic. VM ref-counting and the VM struct
+ * itself are platform agnostic. Also, the initialization and destruction of
+ * VMs is the same across all platforms (for now).
+ *
+ * VM Architecture:
+ * ----------------
+ *
+ *   The VM managment in nvgpu is split up as follows: a vm_gk20a struct which
+ * defines an address space. Each address space is a set of page tables and a
+ * GPU Virtual Address (GVA) allocator. Any number of channels may bind to a VM.
+ *
+ *     +----+  +----+     +----+     +-----+     +-----+
+ *     | C1 |  | C2 | ... | Cn |     | VM1 | ... | VMn |
+ *     +-+--+  +-+--+     +-+--+     +--+--+     +--+--+
+ *       |       |          |           |           |
+ *       |       |          +----->-----+           |
+ *       |       +---------------->-----+           |
+ *       +------------------------>-----------------+
+ *
+ *   Each VM also manages a set of mapped buffers (struct nvgpu_mapped_buf)
+ * which corresponds to _user space_ buffers which have been mapped into this VM.
+ * Kernel space mappings (created by nvgpu_gmmu_map()) are not tracked by VMs.
+ * This may be an architectural bug, but for now it seems to be OK. VMs can be
+ * closed in various ways - refs counts hitting zero, direct calls to the remove
+ * routine, etc. Note: this is going to change. VM cleanup is going to be
+ * homogonized around ref-counts. When a VM is closed all mapped buffers in the
+ * VM are unmapped from the GMMU. This means that those mappings will no longer
+ * be valid and any subsequent access by the GPU will fault. That means one must
+ * ensure the VM is not in use before closing it.
+ *
+ *   VMs may also contain VM areas (struct nvgpu_vm_area) which are created for
+ * the purpose of sparse and/or fixed mappings. If userspace wishes to create a
+ * fixed mapping it must first create a VM area - either with a fixed address or
+ * not. VM areas are reserved - other mapping operations will not use the space.
+ * Userspace may then create fixed mappings within that VM area.
+ */
+
+/* map/unmap batch state */
+struct vm_gk20a_mapping_batch {
+        bool gpu_l2_flushed;
+        bool need_tlb_invalidate;
+};
+
+struct nvgpu_mapped_buf {
+        struct vm_gk20a *vm;
+        struct nvgpu_vm_area *vm_area;
+
+        struct nvgpu_ref ref;
+
+        struct nvgpu_rbtree_node node;
+        struct nvgpu_list_node buffer_list;
+        u64 addr;
+        u64 size;
+
+        u32 pgsz_idx;
+
+        u32 flags;
+        u32 kind;
+        bool va_allocated;
+
+        /*
+         * Separate from the nvgpu_os_buffer struct to clearly distinguish
+         * lifetime. A nvgpu_mapped_buf_priv will _always_ be wrapped by a
+         * struct nvgpu_mapped_buf; however, there are times when a struct
+         * nvgpu_os_buffer would be separate. This aims to prevent dangerous
+         * usage of container_of() or the like in OS code.
+         */
+        struct nvgpu_mapped_buf_priv os_priv;
+};
+
+static inline struct nvgpu_mapped_buf *
+nvgpu_mapped_buf_from_buffer_list(struct nvgpu_list_node *node)
+{
+        return (struct nvgpu_mapped_buf *)
+                ((uintptr_t)node - offsetof(struct nvgpu_mapped_buf,
+                                            buffer_list));
+}
+
+static inline struct nvgpu_mapped_buf *
+mapped_buffer_from_rbtree_node(struct nvgpu_rbtree_node *node)
+{
+        return (struct nvgpu_mapped_buf *)
+                  ((uintptr_t)node - offsetof(struct nvgpu_mapped_buf, node));
+}
+
+struct vm_gk20a {
+        struct mm_gk20a *mm;
+        struct gk20a_as_share *as_share; /* as_share this represents */
+        char name[20];
+
+        u64 va_start;
+        u64 va_limit;
+
+        int num_user_mapped_buffers;
+
+        bool big_pages;   /* enable large page support */
+        bool enable_ctag;
+
+        u32 big_page_size;
+
+        bool userspace_managed;
+
+        const struct gk20a_mmu_level *mmu_levels;
+
+        struct nvgpu_ref ref;
+
+        struct nvgpu_mutex update_gmmu_lock;
+
+        struct nvgpu_gmmu_pd pdb;
+
+        /*
+         * These structs define the address spaces. In some cases it's possible
+         * to merge address spaces (user and user_lp) and in other cases it's
+         * not. vma[] allows the code to be agnostic to this by always using
+         * address spaces through this pointer array.
+         */
+        struct nvgpu_allocator *vma[gmmu_nr_page_sizes];
+        struct nvgpu_allocator kernel;
+        struct nvgpu_allocator user;
+        struct nvgpu_allocator user_lp;
+
+        struct nvgpu_rbtree_node *mapped_buffers;
+
+        struct nvgpu_list_node vm_area_list;
+
+#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
+        u64 handle;
+#endif
+        u32 gmmu_page_sizes[gmmu_nr_page_sizes];
+
+        /* if non-NULL, kref_put will use this batch when
+           unmapping. Must hold vm->update_gmmu_lock. */
+        struct vm_gk20a_mapping_batch *kref_put_batch;
+
+        /*
+         * Each address space needs to have a semaphore pool.
+         */
+        struct nvgpu_semaphore_pool *sema_pool;
+
+        /*
+         * Create sync point read only map for sync point range.
+         * Channels sharing same vm will also share same sync point ro map
+         */
+        u64 syncpt_ro_map_gpu_va;
+};
+
+void nvgpu_vm_get(struct vm_gk20a *vm);
+void nvgpu_vm_put(struct vm_gk20a *vm);
+
+int vm_aspace_id(struct vm_gk20a *vm);
+int nvgpu_big_pages_possible(struct vm_gk20a *vm, u64 base, u64 size);
+
+/* batching eliminates redundant cache flushes and invalidates */
+void nvgpu_vm_mapping_batch_start(struct vm_gk20a_mapping_batch *batch);
+void nvgpu_vm_mapping_batch_finish(
+        struct vm_gk20a *vm, struct vm_gk20a_mapping_batch *batch);
+/* called when holding vm->update_gmmu_lock */
+void nvgpu_vm_mapping_batch_finish_locked(
+        struct vm_gk20a *vm, struct vm_gk20a_mapping_batch *batch);
+
+/* get reference to all currently mapped buffers */
+int nvgpu_vm_get_buffers(struct vm_gk20a *vm,
+                         struct nvgpu_mapped_buf ***mapped_buffers,
+                         int *num_buffers);
+/* put references on the given buffers */
+void nvgpu_vm_put_buffers(struct vm_gk20a *vm,
+                          struct nvgpu_mapped_buf **mapped_buffers,
+                          int num_buffers);
+
+struct nvgpu_mapped_buf *nvgpu_vm_find_mapping(struct vm_gk20a *vm,
+                                               struct nvgpu_os_buffer *os_buf,
+                                               u64 map_addr,
+                                               u32 flags,
+                                               int kind);
+
+struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm,
+                                      struct nvgpu_os_buffer *os_buf,
+                                      struct nvgpu_sgt *sgt,
+                                      u64 map_addr,
+                                      u64 map_size,
+                                      u64 phys_offset,
+                                      int rw,
+                                      u32 flags,
+                                      s16 compr_kind,
+                                      s16 incompr_kind,
+                                      struct vm_gk20a_mapping_batch *batch,
+                                      enum nvgpu_aperture aperture);
+
+void nvgpu_vm_unmap(struct vm_gk20a *vm, u64 offset,
+                    struct vm_gk20a_mapping_batch *batch);
+
+/*
+ * Implemented by each OS. Called from within the core VM code to handle OS
+ * specific components of an nvgpu_mapped_buf.
+ */
+void nvgpu_vm_unmap_system(struct nvgpu_mapped_buf *mapped_buffer);
+
+/*
+ * Don't use this outside of the core VM code!
+ */
+void __nvgpu_vm_unmap_ref(struct nvgpu_ref *ref);
+
+u64 nvgpu_os_buf_get_size(struct nvgpu_os_buffer *os_buf);
+
+/*
+ * These all require the VM update lock to be held.
+ */
+struct nvgpu_mapped_buf *__nvgpu_vm_find_mapped_buf(
+        struct vm_gk20a *vm, u64 addr);
+struct nvgpu_mapped_buf *__nvgpu_vm_find_mapped_buf_range(
+        struct vm_gk20a *vm, u64 addr);
+struct nvgpu_mapped_buf *__nvgpu_vm_find_mapped_buf_less_than(
+        struct vm_gk20a *vm, u64 addr);
+
+int nvgpu_insert_mapped_buf(struct vm_gk20a *vm,
+                            struct nvgpu_mapped_buf *mapped_buffer);
+void nvgpu_remove_mapped_buf(struct vm_gk20a *vm,
+                             struct nvgpu_mapped_buf *mapped_buffer);
+
+struct vm_gk20a *nvgpu_vm_init(struct gk20a *g,
+                               u32 big_page_size,
+                               u64 low_hole,
+                               u64 kernel_reserved,
+                               u64 aperture_size,
+                               bool big_pages,
+                               bool userspace_managed,
+                               char *name);
+
+/*
+ * These are private to the VM code but are unfortunately used by the vgpu code.
+ * It appears to be used for an optimization in reducing the number of server
+ * requests to the vgpu server. Basically the vgpu implementation of
+ * map_global_ctx_buffers() sends a bunch of VA ranges over to the RM server.
+ * Ideally the RM server can just batch mappings but until such a time this
+ * will be used by the vgpu code.
+ */
+u64 __nvgpu_vm_alloc_va(struct vm_gk20a *vm, u64 size,
+                        enum gmmu_pgsz_gk20a pgsz_idx);
+int __nvgpu_vm_free_va(struct vm_gk20a *vm, u64 addr,
+                       enum gmmu_pgsz_gk20a pgsz_idx);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm_area.h b/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
new file mode 100644
index 00000000..7fc77b29
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm_area.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_VM_AREA_H__
+#define __NVGPU_VM_AREA_H__
+
+#include <nvgpu/list.h>
+#include <nvgpu/types.h>
+
+struct vm_gk20a;
+struct gk20a_as_share;
+struct nvgpu_as_alloc_space_args;
+struct nvgpu_as_free_space_args;
+
+struct nvgpu_vm_area {
+        /*
+         * Entry into the list of VM areas owned by a VM.
+         */
+        struct nvgpu_list_node vm_area_list;
+
+        /*
+         * List of buffers mapped into this vm_area.
+         */
+        struct nvgpu_list_node buffer_list_head;
+
+        u32 flags;
+        u32 pgsz_idx;
+        u64 addr;
+        u64 size;
+        bool sparse;
+};
+
+static inline struct nvgpu_vm_area *
+nvgpu_vm_area_from_vm_area_list(struct nvgpu_list_node *node)
+{
+        return (struct nvgpu_vm_area *)
+                ((uintptr_t)node - offsetof(struct nvgpu_vm_area,
+                                            vm_area_list));
+};
+
+int nvgpu_vm_area_alloc(struct vm_gk20a *vm, u32 pages, u32 page_size,
+                        u64 *addr, u32 flags);
+int nvgpu_vm_area_free(struct vm_gk20a *vm, u64 addr);
+
+struct nvgpu_vm_area *nvgpu_vm_area_find(struct vm_gk20a *vm, u64 addr);
+int nvgpu_vm_area_validate_buffer(struct vm_gk20a *vm,
+                                  u64 map_offset, u64 map_size, int pgsz_idx,
+                                  struct nvgpu_vm_area **pvm_area);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/xve.h b/drivers/gpu/nvgpu/include/nvgpu/xve.h
new file mode 100644
index 00000000..1c47e1c5
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/xve.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVGPU_XVE_H__
+#define __NVGPU_XVE_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/log2.h>
+
+/*
+ * For the available speeds bitmap.
+ */
+#define GPU_XVE_SPEED_2P5       (1 << 0)
+#define GPU_XVE_SPEED_5P0       (1 << 1)
+#define GPU_XVE_SPEED_8P0       (1 << 2)
+#define GPU_XVE_NR_SPEEDS       3
+
+#define GPU_XVE_SPEED_MASK      (GPU_XVE_SPEED_2P5 |    \
+                                 GPU_XVE_SPEED_5P0 |    \
+                                 GPU_XVE_SPEED_8P0)
+
+/*
+ * The HW uses a 2 bit field where speed is defined by a number:
+ *
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2
+ *   NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3
+ *
+ * This isn't ideal for a bitmap with available speeds. So the external
+ * APIs think about speeds as a bit in a bitmap and this function converts
+ * from those bits to the actual HW speed setting.
+ *
+ * @speed_bit must have only 1 bit set and must be one of the 3 available
+ * HW speeds. Not all chips support all speeds so use available_speeds() to
+ * determine what a given chip supports.
+ */
+static inline const char *xve_speed_to_str(u32 speed)
+{
+        if (!speed || !is_power_of_2(speed) ||
+            !(speed & GPU_XVE_SPEED_MASK))
+                return "Unknown ???";
+
+        return speed & GPU_XVE_SPEED_2P5 ? "Gen1" :
+               speed & GPU_XVE_SPEED_5P0 ? "Gen2" :
+               speed & GPU_XVE_SPEED_8P0 ? "Gen3" :
+               "Unknown ???";
+}
+
+#endif