diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
62 files changed, 30541 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h new file mode 100644 index 00000000..9ef1dc30 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __NVGPU_ENABLED_T19X_H__ | ||
24 | #define __NVGPU_ENABLED_T19X_H__ | ||
25 | |||
26 | /* subcontexts are available */ | ||
27 | #define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63 | ||
28 | |||
29 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h new file mode 100644 index 00000000..eea51fbb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __NVGPU_GMMU_T19X_H__ | ||
24 | #define __NVGPU_GMMU_T19X_H__ | ||
25 | |||
26 | struct nvgpu_gmmu_attrs; | ||
27 | |||
28 | struct nvgpu_gmmu_attrs_t19x { | ||
29 | bool l3_alloc; | ||
30 | }; | ||
31 | |||
32 | void nvgpu_gmmu_add_t19x_attrs(struct nvgpu_gmmu_attrs *attrs, u32 flags); | ||
33 | |||
34 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h new file mode 100644 index 00000000..7771f1ea --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | |||
@@ -0,0 +1,227 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_bus_gv100_h_ | ||
57 | #define _hw_bus_gv100_h_ | ||
58 | |||
59 | static inline u32 bus_sw_scratch_r(u32 i) | ||
60 | { | ||
61 | return 0x00001580U + i*4U; | ||
62 | } | ||
63 | static inline u32 bus_bar0_window_r(void) | ||
64 | { | ||
65 | return 0x00001700U; | ||
66 | } | ||
67 | static inline u32 bus_bar0_window_base_f(u32 v) | ||
68 | { | ||
69 | return (v & 0xffffffU) << 0U; | ||
70 | } | ||
71 | static inline u32 bus_bar0_window_target_vid_mem_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) | ||
76 | { | ||
77 | return 0x2000000U; | ||
78 | } | ||
79 | static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) | ||
80 | { | ||
81 | return 0x3000000U; | ||
82 | } | ||
83 | static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) | ||
84 | { | ||
85 | return 0x00000010U; | ||
86 | } | ||
87 | static inline u32 bus_bar1_block_r(void) | ||
88 | { | ||
89 | return 0x00001704U; | ||
90 | } | ||
91 | static inline u32 bus_bar1_block_ptr_f(u32 v) | ||
92 | { | ||
93 | return (v & 0xfffffffU) << 0U; | ||
94 | } | ||
95 | static inline u32 bus_bar1_block_target_vid_mem_f(void) | ||
96 | { | ||
97 | return 0x0U; | ||
98 | } | ||
99 | static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) | ||
100 | { | ||
101 | return 0x20000000U; | ||
102 | } | ||
103 | static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) | ||
104 | { | ||
105 | return 0x30000000U; | ||
106 | } | ||
107 | static inline u32 bus_bar1_block_mode_virtual_f(void) | ||
108 | { | ||
109 | return 0x80000000U; | ||
110 | } | ||
111 | static inline u32 bus_bar2_block_r(void) | ||
112 | { | ||
113 | return 0x00001714U; | ||
114 | } | ||
115 | static inline u32 bus_bar2_block_ptr_f(u32 v) | ||
116 | { | ||
117 | return (v & 0xfffffffU) << 0U; | ||
118 | } | ||
119 | static inline u32 bus_bar2_block_target_vid_mem_f(void) | ||
120 | { | ||
121 | return 0x0U; | ||
122 | } | ||
123 | static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) | ||
124 | { | ||
125 | return 0x20000000U; | ||
126 | } | ||
127 | static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) | ||
128 | { | ||
129 | return 0x30000000U; | ||
130 | } | ||
131 | static inline u32 bus_bar2_block_mode_virtual_f(void) | ||
132 | { | ||
133 | return 0x80000000U; | ||
134 | } | ||
135 | static inline u32 bus_bar1_block_ptr_shift_v(void) | ||
136 | { | ||
137 | return 0x0000000cU; | ||
138 | } | ||
139 | static inline u32 bus_bar2_block_ptr_shift_v(void) | ||
140 | { | ||
141 | return 0x0000000cU; | ||
142 | } | ||
143 | static inline u32 bus_bind_status_r(void) | ||
144 | { | ||
145 | return 0x00001710U; | ||
146 | } | ||
147 | static inline u32 bus_bind_status_bar1_pending_v(u32 r) | ||
148 | { | ||
149 | return (r >> 0U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 bus_bind_status_bar1_pending_empty_f(void) | ||
152 | { | ||
153 | return 0x0U; | ||
154 | } | ||
155 | static inline u32 bus_bind_status_bar1_pending_busy_f(void) | ||
156 | { | ||
157 | return 0x1U; | ||
158 | } | ||
159 | static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) | ||
160 | { | ||
161 | return (r >> 1U) & 0x1U; | ||
162 | } | ||
163 | static inline u32 bus_bind_status_bar1_outstanding_false_f(void) | ||
164 | { | ||
165 | return 0x0U; | ||
166 | } | ||
167 | static inline u32 bus_bind_status_bar1_outstanding_true_f(void) | ||
168 | { | ||
169 | return 0x2U; | ||
170 | } | ||
171 | static inline u32 bus_bind_status_bar2_pending_v(u32 r) | ||
172 | { | ||
173 | return (r >> 2U) & 0x1U; | ||
174 | } | ||
175 | static inline u32 bus_bind_status_bar2_pending_empty_f(void) | ||
176 | { | ||
177 | return 0x0U; | ||
178 | } | ||
179 | static inline u32 bus_bind_status_bar2_pending_busy_f(void) | ||
180 | { | ||
181 | return 0x4U; | ||
182 | } | ||
183 | static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) | ||
184 | { | ||
185 | return (r >> 3U) & 0x1U; | ||
186 | } | ||
187 | static inline u32 bus_bind_status_bar2_outstanding_false_f(void) | ||
188 | { | ||
189 | return 0x0U; | ||
190 | } | ||
191 | static inline u32 bus_bind_status_bar2_outstanding_true_f(void) | ||
192 | { | ||
193 | return 0x8U; | ||
194 | } | ||
195 | static inline u32 bus_intr_0_r(void) | ||
196 | { | ||
197 | return 0x00001100U; | ||
198 | } | ||
199 | static inline u32 bus_intr_0_pri_squash_m(void) | ||
200 | { | ||
201 | return 0x1U << 1U; | ||
202 | } | ||
203 | static inline u32 bus_intr_0_pri_fecserr_m(void) | ||
204 | { | ||
205 | return 0x1U << 2U; | ||
206 | } | ||
207 | static inline u32 bus_intr_0_pri_timeout_m(void) | ||
208 | { | ||
209 | return 0x1U << 3U; | ||
210 | } | ||
211 | static inline u32 bus_intr_en_0_r(void) | ||
212 | { | ||
213 | return 0x00001140U; | ||
214 | } | ||
215 | static inline u32 bus_intr_en_0_pri_squash_m(void) | ||
216 | { | ||
217 | return 0x1U << 1U; | ||
218 | } | ||
219 | static inline u32 bus_intr_en_0_pri_fecserr_m(void) | ||
220 | { | ||
221 | return 0x1U << 2U; | ||
222 | } | ||
223 | static inline u32 bus_intr_en_0_pri_timeout_m(void) | ||
224 | { | ||
225 | return 0x1U << 3U; | ||
226 | } | ||
227 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h new file mode 100644 index 00000000..b1478037 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | |||
@@ -0,0 +1,187 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ccsr_gv100_h_ | ||
57 | #define _hw_ccsr_gv100_h_ | ||
58 | |||
59 | static inline u32 ccsr_channel_inst_r(u32 i) | ||
60 | { | ||
61 | return 0x00800000U + i*8U; | ||
62 | } | ||
63 | static inline u32 ccsr_channel_inst__size_1_v(void) | ||
64 | { | ||
65 | return 0x00001000U; | ||
66 | } | ||
67 | static inline u32 ccsr_channel_inst_ptr_f(u32 v) | ||
68 | { | ||
69 | return (v & 0xfffffffU) << 0U; | ||
70 | } | ||
71 | static inline u32 ccsr_channel_inst_target_vid_mem_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) | ||
76 | { | ||
77 | return 0x20000000U; | ||
78 | } | ||
79 | static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) | ||
80 | { | ||
81 | return 0x30000000U; | ||
82 | } | ||
83 | static inline u32 ccsr_channel_inst_bind_false_f(void) | ||
84 | { | ||
85 | return 0x0U; | ||
86 | } | ||
87 | static inline u32 ccsr_channel_inst_bind_true_f(void) | ||
88 | { | ||
89 | return 0x80000000U; | ||
90 | } | ||
91 | static inline u32 ccsr_channel_r(u32 i) | ||
92 | { | ||
93 | return 0x00800004U + i*8U; | ||
94 | } | ||
95 | static inline u32 ccsr_channel__size_1_v(void) | ||
96 | { | ||
97 | return 0x00001000U; | ||
98 | } | ||
99 | static inline u32 ccsr_channel_enable_v(u32 r) | ||
100 | { | ||
101 | return (r >> 0U) & 0x1U; | ||
102 | } | ||
103 | static inline u32 ccsr_channel_enable_set_f(u32 v) | ||
104 | { | ||
105 | return (v & 0x1U) << 10U; | ||
106 | } | ||
107 | static inline u32 ccsr_channel_enable_set_true_f(void) | ||
108 | { | ||
109 | return 0x400U; | ||
110 | } | ||
111 | static inline u32 ccsr_channel_enable_clr_true_f(void) | ||
112 | { | ||
113 | return 0x800U; | ||
114 | } | ||
115 | static inline u32 ccsr_channel_status_v(u32 r) | ||
116 | { | ||
117 | return (r >> 24U) & 0xfU; | ||
118 | } | ||
119 | static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | ||
120 | { | ||
121 | return 0x00000002U; | ||
122 | } | ||
123 | static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) | ||
124 | { | ||
125 | return 0x00000004U; | ||
126 | } | ||
127 | static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) | ||
128 | { | ||
129 | return 0x0000000aU; | ||
130 | } | ||
131 | static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) | ||
132 | { | ||
133 | return 0x0000000bU; | ||
134 | } | ||
135 | static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) | ||
136 | { | ||
137 | return 0x0000000cU; | ||
138 | } | ||
139 | static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) | ||
140 | { | ||
141 | return 0x0000000dU; | ||
142 | } | ||
143 | static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) | ||
144 | { | ||
145 | return 0x0000000eU; | ||
146 | } | ||
147 | static inline u32 ccsr_channel_next_v(u32 r) | ||
148 | { | ||
149 | return (r >> 1U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 ccsr_channel_next_true_v(void) | ||
152 | { | ||
153 | return 0x00000001U; | ||
154 | } | ||
155 | static inline u32 ccsr_channel_force_ctx_reload_true_f(void) | ||
156 | { | ||
157 | return 0x100U; | ||
158 | } | ||
159 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x1U) << 22U; | ||
162 | } | ||
163 | static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) | ||
164 | { | ||
165 | return 0x400000U; | ||
166 | } | ||
167 | static inline u32 ccsr_channel_eng_faulted_f(u32 v) | ||
168 | { | ||
169 | return (v & 0x1U) << 23U; | ||
170 | } | ||
171 | static inline u32 ccsr_channel_eng_faulted_v(u32 r) | ||
172 | { | ||
173 | return (r >> 23U) & 0x1U; | ||
174 | } | ||
175 | static inline u32 ccsr_channel_eng_faulted_reset_f(void) | ||
176 | { | ||
177 | return 0x800000U; | ||
178 | } | ||
179 | static inline u32 ccsr_channel_eng_faulted_true_v(void) | ||
180 | { | ||
181 | return 0x00000001U; | ||
182 | } | ||
183 | static inline u32 ccsr_channel_busy_v(u32 r) | ||
184 | { | ||
185 | return (r >> 28U) & 0x1U; | ||
186 | } | ||
187 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h new file mode 100644 index 00000000..18b5fc66 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h | |||
@@ -0,0 +1,107 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ce_gv100_h_ | ||
57 | #define _hw_ce_gv100_h_ | ||
58 | |||
59 | static inline u32 ce_intr_status_r(u32 i) | ||
60 | { | ||
61 | return 0x00104410U + i*128U; | ||
62 | } | ||
63 | static inline u32 ce_intr_status_blockpipe_pending_f(void) | ||
64 | { | ||
65 | return 0x1U; | ||
66 | } | ||
67 | static inline u32 ce_intr_status_blockpipe_reset_f(void) | ||
68 | { | ||
69 | return 0x1U; | ||
70 | } | ||
71 | static inline u32 ce_intr_status_nonblockpipe_pending_f(void) | ||
72 | { | ||
73 | return 0x2U; | ||
74 | } | ||
75 | static inline u32 ce_intr_status_nonblockpipe_reset_f(void) | ||
76 | { | ||
77 | return 0x2U; | ||
78 | } | ||
79 | static inline u32 ce_intr_status_launcherr_pending_f(void) | ||
80 | { | ||
81 | return 0x4U; | ||
82 | } | ||
83 | static inline u32 ce_intr_status_launcherr_reset_f(void) | ||
84 | { | ||
85 | return 0x4U; | ||
86 | } | ||
87 | static inline u32 ce_intr_status_invalid_config_pending_f(void) | ||
88 | { | ||
89 | return 0x8U; | ||
90 | } | ||
91 | static inline u32 ce_intr_status_invalid_config_reset_f(void) | ||
92 | { | ||
93 | return 0x8U; | ||
94 | } | ||
95 | static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) | ||
96 | { | ||
97 | return 0x10U; | ||
98 | } | ||
99 | static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) | ||
100 | { | ||
101 | return 0x10U; | ||
102 | } | ||
103 | static inline u32 ce_pce_map_r(void) | ||
104 | { | ||
105 | return 0x00104028U; | ||
106 | } | ||
107 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h new file mode 100644 index 00000000..cd792835 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | |||
@@ -0,0 +1,455 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ctxsw_prog_gv100_h_ | ||
57 | #define _hw_ctxsw_prog_gv100_h_ | ||
58 | |||
59 | static inline u32 ctxsw_prog_fecs_header_v(void) | ||
60 | { | ||
61 | return 0x00000100U; | ||
62 | } | ||
63 | static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) | ||
64 | { | ||
65 | return 0x00000008U; | ||
66 | } | ||
67 | static inline u32 ctxsw_prog_main_image_ctl_o(void) | ||
68 | { | ||
69 | return 0x0000000cU; | ||
70 | } | ||
71 | static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) | ||
72 | { | ||
73 | return (v & 0x3fU) << 0U; | ||
74 | } | ||
75 | static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) | ||
76 | { | ||
77 | return 0x00000000U; | ||
78 | } | ||
79 | static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) | ||
80 | { | ||
81 | return 0x00000008U; | ||
82 | } | ||
83 | static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) | ||
84 | { | ||
85 | return 0x00000010U; | ||
86 | } | ||
87 | static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) | ||
88 | { | ||
89 | return 0x00000011U; | ||
90 | } | ||
91 | static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) | ||
92 | { | ||
93 | return 0x00000012U; | ||
94 | } | ||
95 | static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) | ||
96 | { | ||
97 | return 0x00000020U; | ||
98 | } | ||
99 | static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) | ||
100 | { | ||
101 | return 0x00000021U; | ||
102 | } | ||
103 | static inline u32 ctxsw_prog_main_image_patch_count_o(void) | ||
104 | { | ||
105 | return 0x00000010U; | ||
106 | } | ||
107 | static inline u32 ctxsw_prog_main_image_context_id_o(void) | ||
108 | { | ||
109 | return 0x000000f0U; | ||
110 | } | ||
111 | static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) | ||
112 | { | ||
113 | return 0x00000014U; | ||
114 | } | ||
115 | static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) | ||
116 | { | ||
117 | return 0x00000018U; | ||
118 | } | ||
119 | static inline u32 ctxsw_prog_main_image_zcull_o(void) | ||
120 | { | ||
121 | return 0x0000001cU; | ||
122 | } | ||
123 | static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) | ||
124 | { | ||
125 | return 0x00000001U; | ||
126 | } | ||
127 | static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) | ||
128 | { | ||
129 | return 0x00000002U; | ||
130 | } | ||
131 | static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) | ||
132 | { | ||
133 | return 0x00000020U; | ||
134 | } | ||
135 | static inline u32 ctxsw_prog_main_image_pm_o(void) | ||
136 | { | ||
137 | return 0x00000028U; | ||
138 | } | ||
139 | static inline u32 ctxsw_prog_main_image_pm_mode_m(void) | ||
140 | { | ||
141 | return 0x7U << 0U; | ||
142 | } | ||
143 | static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) | ||
144 | { | ||
145 | return 0x0U; | ||
146 | } | ||
147 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) | ||
148 | { | ||
149 | return 0x7U << 3U; | ||
150 | } | ||
151 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) | ||
152 | { | ||
153 | return 0x8U; | ||
154 | } | ||
155 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) | ||
156 | { | ||
157 | return 0x0U; | ||
158 | } | ||
159 | static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) | ||
160 | { | ||
161 | return 0x0000002cU; | ||
162 | } | ||
163 | static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) | ||
164 | { | ||
165 | return 0x000000f4U; | ||
166 | } | ||
167 | static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) | ||
168 | { | ||
169 | return 0x000000d0U; | ||
170 | } | ||
171 | static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) | ||
172 | { | ||
173 | return 0x000000d4U; | ||
174 | } | ||
175 | static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) | ||
176 | { | ||
177 | return 0x000000d8U; | ||
178 | } | ||
179 | static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) | ||
180 | { | ||
181 | return 0x000000dcU; | ||
182 | } | ||
183 | static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) | ||
184 | { | ||
185 | return 0x000000f8U; | ||
186 | } | ||
187 | static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) | ||
188 | { | ||
189 | return 0x00000060U; | ||
190 | } | ||
191 | static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1ffffU) << 0U; | ||
194 | } | ||
195 | static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) | ||
196 | { | ||
197 | return 0x00000094U; | ||
198 | } | ||
199 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) | ||
200 | { | ||
201 | return 0x00000064U; | ||
202 | } | ||
203 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1ffffU) << 0U; | ||
206 | } | ||
207 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) | ||
208 | { | ||
209 | return 0x00000068U; | ||
210 | } | ||
211 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) | ||
212 | { | ||
213 | return (v & 0xffffffffU) << 0U; | ||
214 | } | ||
215 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) | ||
216 | { | ||
217 | return 0x00000070U; | ||
218 | } | ||
219 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1ffffU) << 0U; | ||
222 | } | ||
223 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) | ||
224 | { | ||
225 | return 0x00000074U; | ||
226 | } | ||
227 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) | ||
228 | { | ||
229 | return (v & 0xffffffffU) << 0U; | ||
230 | } | ||
231 | static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) | ||
232 | { | ||
233 | return 0x00000078U; | ||
234 | } | ||
235 | static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1ffffU) << 0U; | ||
238 | } | ||
239 | static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) | ||
240 | { | ||
241 | return 0x0000007cU; | ||
242 | } | ||
243 | static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xffffffffU) << 0U; | ||
246 | } | ||
247 | static inline u32 ctxsw_prog_main_image_magic_value_o(void) | ||
248 | { | ||
249 | return 0x000000fcU; | ||
250 | } | ||
251 | static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) | ||
252 | { | ||
253 | return 0x600dc0deU; | ||
254 | } | ||
255 | static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) | ||
256 | { | ||
257 | return 0x0000000cU; | ||
258 | } | ||
259 | static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) | ||
260 | { | ||
261 | return (r >> 0U) & 0xffffU; | ||
262 | } | ||
263 | static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) | ||
264 | { | ||
265 | return 0x000000b8U; | ||
266 | } | ||
267 | static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) | ||
268 | { | ||
269 | return (v & 0xffffffffU) << 0U; | ||
270 | } | ||
271 | static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) | ||
272 | { | ||
273 | return 0x000000bcU; | ||
274 | } | ||
275 | static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) | ||
276 | { | ||
277 | return (v & 0x1ffffU) << 0U; | ||
278 | } | ||
279 | static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) | ||
280 | { | ||
281 | return 0x000000c0U; | ||
282 | } | ||
283 | static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) | ||
284 | { | ||
285 | return (v & 0xffffffffU) << 0U; | ||
286 | } | ||
287 | static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) | ||
288 | { | ||
289 | return 0x000000c4U; | ||
290 | } | ||
291 | static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) | ||
292 | { | ||
293 | return (v & 0x1ffffU) << 0U; | ||
294 | } | ||
295 | static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) | ||
296 | { | ||
297 | return 0x000000c8U; | ||
298 | } | ||
299 | static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) | ||
300 | { | ||
301 | return (v & 0xffffffffU) << 0U; | ||
302 | } | ||
303 | static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) | ||
304 | { | ||
305 | return 0x000000ccU; | ||
306 | } | ||
307 | static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1ffffU) << 0U; | ||
310 | } | ||
311 | static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) | ||
312 | { | ||
313 | return 0x000000e0U; | ||
314 | } | ||
315 | static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) | ||
316 | { | ||
317 | return (v & 0xffffffffU) << 0U; | ||
318 | } | ||
319 | static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) | ||
320 | { | ||
321 | return 0x000000e4U; | ||
322 | } | ||
323 | static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1ffffU) << 0U; | ||
326 | } | ||
327 | static inline u32 ctxsw_prog_local_image_ppc_info_o(void) | ||
328 | { | ||
329 | return 0x000000f4U; | ||
330 | } | ||
331 | static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) | ||
332 | { | ||
333 | return (r >> 0U) & 0xffffU; | ||
334 | } | ||
335 | static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) | ||
336 | { | ||
337 | return (r >> 16U) & 0xffffU; | ||
338 | } | ||
339 | static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) | ||
340 | { | ||
341 | return 0x000000f8U; | ||
342 | } | ||
343 | static inline u32 ctxsw_prog_local_magic_value_o(void) | ||
344 | { | ||
345 | return 0x000000fcU; | ||
346 | } | ||
347 | static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) | ||
348 | { | ||
349 | return 0xad0becabU; | ||
350 | } | ||
351 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) | ||
352 | { | ||
353 | return 0x000000ecU; | ||
354 | } | ||
355 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) | ||
356 | { | ||
357 | return (r >> 0U) & 0xffffU; | ||
358 | } | ||
359 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) | ||
360 | { | ||
361 | return (r >> 16U) & 0xffU; | ||
362 | } | ||
363 | static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) | ||
364 | { | ||
365 | return 0x00000100U; | ||
366 | } | ||
367 | static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) | ||
368 | { | ||
369 | return 0x00000004U; | ||
370 | } | ||
371 | static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) | ||
372 | { | ||
373 | return 0x00000000U; | ||
374 | } | ||
375 | static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) | ||
376 | { | ||
377 | return 0x00000002U; | ||
378 | } | ||
379 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) | ||
380 | { | ||
381 | return 0x000000a0U; | ||
382 | } | ||
383 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) | ||
384 | { | ||
385 | return 2U; | ||
386 | } | ||
387 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) | ||
388 | { | ||
389 | return (v & 0x3U) << 0U; | ||
390 | } | ||
391 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) | ||
392 | { | ||
393 | return 0x3U << 0U; | ||
394 | } | ||
395 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) | ||
396 | { | ||
397 | return (r >> 0U) & 0x3U; | ||
398 | } | ||
399 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) | ||
400 | { | ||
401 | return 0x0U; | ||
402 | } | ||
403 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) | ||
404 | { | ||
405 | return 0x2U; | ||
406 | } | ||
407 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) | ||
408 | { | ||
409 | return 0x000000a4U; | ||
410 | } | ||
411 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) | ||
412 | { | ||
413 | return 0x000000a8U; | ||
414 | } | ||
415 | static inline u32 ctxsw_prog_main_image_misc_options_o(void) | ||
416 | { | ||
417 | return 0x0000003cU; | ||
418 | } | ||
419 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) | ||
420 | { | ||
421 | return 0x1U << 3U; | ||
422 | } | ||
423 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) | ||
424 | { | ||
425 | return 0x0U; | ||
426 | } | ||
427 | static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) | ||
428 | { | ||
429 | return 0x00000080U; | ||
430 | } | ||
431 | static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) | ||
432 | { | ||
433 | return (v & 0x3U) << 0U; | ||
434 | } | ||
435 | static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) | ||
436 | { | ||
437 | return 0x1U; | ||
438 | } | ||
439 | static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) | ||
440 | { | ||
441 | return 0x00000084U; | ||
442 | } | ||
443 | static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) | ||
444 | { | ||
445 | return (v & 0x3U) << 0U; | ||
446 | } | ||
447 | static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) | ||
448 | { | ||
449 | return 0x1U; | ||
450 | } | ||
451 | static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) | ||
452 | { | ||
453 | return 0x2U; | ||
454 | } | ||
455 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h new file mode 100644 index 00000000..122956bb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h | |||
@@ -0,0 +1,599 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_falcon_gv100_h_ | ||
57 | #define _hw_falcon_gv100_h_ | ||
58 | |||
59 | static inline u32 falcon_falcon_irqsset_r(void) | ||
60 | { | ||
61 | return 0x00000000U; | ||
62 | } | ||
63 | static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) | ||
64 | { | ||
65 | return 0x40U; | ||
66 | } | ||
67 | static inline u32 falcon_falcon_irqsclr_r(void) | ||
68 | { | ||
69 | return 0x00000004U; | ||
70 | } | ||
71 | static inline u32 falcon_falcon_irqstat_r(void) | ||
72 | { | ||
73 | return 0x00000008U; | ||
74 | } | ||
75 | static inline u32 falcon_falcon_irqstat_halt_true_f(void) | ||
76 | { | ||
77 | return 0x10U; | ||
78 | } | ||
79 | static inline u32 falcon_falcon_irqstat_exterr_true_f(void) | ||
80 | { | ||
81 | return 0x20U; | ||
82 | } | ||
83 | static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) | ||
84 | { | ||
85 | return 0x40U; | ||
86 | } | ||
87 | static inline u32 falcon_falcon_irqmode_r(void) | ||
88 | { | ||
89 | return 0x0000000cU; | ||
90 | } | ||
91 | static inline u32 falcon_falcon_irqmset_r(void) | ||
92 | { | ||
93 | return 0x00000010U; | ||
94 | } | ||
95 | static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) | ||
96 | { | ||
97 | return (v & 0x1U) << 0U; | ||
98 | } | ||
99 | static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 1U; | ||
102 | } | ||
103 | static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) | ||
104 | { | ||
105 | return (v & 0x1U) << 2U; | ||
106 | } | ||
107 | static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x1U) << 3U; | ||
110 | } | ||
111 | static inline u32 falcon_falcon_irqmset_halt_f(u32 v) | ||
112 | { | ||
113 | return (v & 0x1U) << 4U; | ||
114 | } | ||
115 | static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 5U; | ||
118 | } | ||
119 | static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) | ||
120 | { | ||
121 | return (v & 0x1U) << 6U; | ||
122 | } | ||
123 | static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) | ||
124 | { | ||
125 | return (v & 0x1U) << 7U; | ||
126 | } | ||
127 | static inline u32 falcon_falcon_irqmclr_r(void) | ||
128 | { | ||
129 | return 0x00000014U; | ||
130 | } | ||
131 | static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 0U; | ||
134 | } | ||
135 | static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) | ||
136 | { | ||
137 | return (v & 0x1U) << 1U; | ||
138 | } | ||
139 | static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 2U; | ||
142 | } | ||
143 | static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1U) << 3U; | ||
146 | } | ||
147 | static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) | ||
148 | { | ||
149 | return (v & 0x1U) << 4U; | ||
150 | } | ||
151 | static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x1U) << 5U; | ||
154 | } | ||
155 | static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) | ||
156 | { | ||
157 | return (v & 0x1U) << 6U; | ||
158 | } | ||
159 | static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x1U) << 7U; | ||
162 | } | ||
163 | static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) | ||
164 | { | ||
165 | return (v & 0xffU) << 8U; | ||
166 | } | ||
167 | static inline u32 falcon_falcon_irqmask_r(void) | ||
168 | { | ||
169 | return 0x00000018U; | ||
170 | } | ||
171 | static inline u32 falcon_falcon_irqdest_r(void) | ||
172 | { | ||
173 | return 0x0000001cU; | ||
174 | } | ||
175 | static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x1U) << 0U; | ||
178 | } | ||
179 | static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) | ||
180 | { | ||
181 | return (v & 0x1U) << 1U; | ||
182 | } | ||
183 | static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1U) << 2U; | ||
186 | } | ||
187 | static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 3U; | ||
190 | } | ||
191 | static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1U) << 4U; | ||
194 | } | ||
195 | static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x1U) << 5U; | ||
198 | } | ||
199 | static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) | ||
200 | { | ||
201 | return (v & 0x1U) << 6U; | ||
202 | } | ||
203 | static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1U) << 7U; | ||
206 | } | ||
207 | static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) | ||
208 | { | ||
209 | return (v & 0xffU) << 8U; | ||
210 | } | ||
211 | static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x1U) << 16U; | ||
214 | } | ||
215 | static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) | ||
216 | { | ||
217 | return (v & 0x1U) << 17U; | ||
218 | } | ||
219 | static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1U) << 18U; | ||
222 | } | ||
223 | static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) | ||
224 | { | ||
225 | return (v & 0x1U) << 19U; | ||
226 | } | ||
227 | static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x1U) << 20U; | ||
230 | } | ||
231 | static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) | ||
232 | { | ||
233 | return (v & 0x1U) << 21U; | ||
234 | } | ||
235 | static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1U) << 22U; | ||
238 | } | ||
239 | static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x1U) << 23U; | ||
242 | } | ||
243 | static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xffU) << 24U; | ||
246 | } | ||
247 | static inline u32 falcon_falcon_curctx_r(void) | ||
248 | { | ||
249 | return 0x00000050U; | ||
250 | } | ||
251 | static inline u32 falcon_falcon_nxtctx_r(void) | ||
252 | { | ||
253 | return 0x00000054U; | ||
254 | } | ||
255 | static inline u32 falcon_falcon_mailbox0_r(void) | ||
256 | { | ||
257 | return 0x00000040U; | ||
258 | } | ||
259 | static inline u32 falcon_falcon_mailbox1_r(void) | ||
260 | { | ||
261 | return 0x00000044U; | ||
262 | } | ||
263 | static inline u32 falcon_falcon_itfen_r(void) | ||
264 | { | ||
265 | return 0x00000048U; | ||
266 | } | ||
267 | static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) | ||
268 | { | ||
269 | return 0x1U; | ||
270 | } | ||
271 | static inline u32 falcon_falcon_idlestate_r(void) | ||
272 | { | ||
273 | return 0x0000004cU; | ||
274 | } | ||
275 | static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) | ||
276 | { | ||
277 | return (r >> 0U) & 0x1U; | ||
278 | } | ||
279 | static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) | ||
280 | { | ||
281 | return (r >> 1U) & 0x7fffU; | ||
282 | } | ||
283 | static inline u32 falcon_falcon_os_r(void) | ||
284 | { | ||
285 | return 0x00000080U; | ||
286 | } | ||
287 | static inline u32 falcon_falcon_engctl_r(void) | ||
288 | { | ||
289 | return 0x000000a4U; | ||
290 | } | ||
291 | static inline u32 falcon_falcon_cpuctl_r(void) | ||
292 | { | ||
293 | return 0x00000100U; | ||
294 | } | ||
295 | static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x1U) << 1U; | ||
298 | } | ||
299 | static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) | ||
300 | { | ||
301 | return (v & 0x1U) << 2U; | ||
302 | } | ||
303 | static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) | ||
304 | { | ||
305 | return (v & 0x1U) << 3U; | ||
306 | } | ||
307 | static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1U) << 4U; | ||
310 | } | ||
311 | static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) | ||
312 | { | ||
313 | return 0x1U << 4U; | ||
314 | } | ||
315 | static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) | ||
316 | { | ||
317 | return (r >> 4U) & 0x1U; | ||
318 | } | ||
319 | static inline u32 falcon_falcon_cpuctl_stopped_m(void) | ||
320 | { | ||
321 | return 0x1U << 5U; | ||
322 | } | ||
323 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1U) << 6U; | ||
326 | } | ||
327 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) | ||
328 | { | ||
329 | return 0x1U << 6U; | ||
330 | } | ||
331 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) | ||
332 | { | ||
333 | return (r >> 6U) & 0x1U; | ||
334 | } | ||
335 | static inline u32 falcon_falcon_cpuctl_alias_r(void) | ||
336 | { | ||
337 | return 0x00000130U; | ||
338 | } | ||
339 | static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) | ||
340 | { | ||
341 | return (v & 0x1U) << 1U; | ||
342 | } | ||
343 | static inline u32 falcon_falcon_imemc_r(u32 i) | ||
344 | { | ||
345 | return 0x00000180U + i*16U; | ||
346 | } | ||
347 | static inline u32 falcon_falcon_imemc_offs_f(u32 v) | ||
348 | { | ||
349 | return (v & 0x3fU) << 2U; | ||
350 | } | ||
351 | static inline u32 falcon_falcon_imemc_blk_f(u32 v) | ||
352 | { | ||
353 | return (v & 0xffU) << 8U; | ||
354 | } | ||
355 | static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | ||
356 | { | ||
357 | return (v & 0x1U) << 24U; | ||
358 | } | ||
359 | static inline u32 falcon_falcon_imemd_r(u32 i) | ||
360 | { | ||
361 | return 0x00000184U + i*16U; | ||
362 | } | ||
363 | static inline u32 falcon_falcon_imemt_r(u32 i) | ||
364 | { | ||
365 | return 0x00000188U + i*16U; | ||
366 | } | ||
367 | static inline u32 falcon_falcon_sctl_r(void) | ||
368 | { | ||
369 | return 0x00000240U; | ||
370 | } | ||
371 | static inline u32 falcon_falcon_mmu_phys_sec_r(void) | ||
372 | { | ||
373 | return 0x00100ce4U; | ||
374 | } | ||
375 | static inline u32 falcon_falcon_bootvec_r(void) | ||
376 | { | ||
377 | return 0x00000104U; | ||
378 | } | ||
379 | static inline u32 falcon_falcon_bootvec_vec_f(u32 v) | ||
380 | { | ||
381 | return (v & 0xffffffffU) << 0U; | ||
382 | } | ||
383 | static inline u32 falcon_falcon_dmactl_r(void) | ||
384 | { | ||
385 | return 0x0000010cU; | ||
386 | } | ||
387 | static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) | ||
388 | { | ||
389 | return 0x1U << 1U; | ||
390 | } | ||
391 | static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) | ||
392 | { | ||
393 | return 0x1U << 2U; | ||
394 | } | ||
395 | static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) | ||
396 | { | ||
397 | return (v & 0x1U) << 0U; | ||
398 | } | ||
399 | static inline u32 falcon_falcon_hwcfg_r(void) | ||
400 | { | ||
401 | return 0x00000108U; | ||
402 | } | ||
403 | static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) | ||
404 | { | ||
405 | return (r >> 0U) & 0x1ffU; | ||
406 | } | ||
407 | static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) | ||
408 | { | ||
409 | return (r >> 9U) & 0x1ffU; | ||
410 | } | ||
411 | static inline u32 falcon_falcon_dmatrfbase_r(void) | ||
412 | { | ||
413 | return 0x00000110U; | ||
414 | } | ||
415 | static inline u32 falcon_falcon_dmatrfbase1_r(void) | ||
416 | { | ||
417 | return 0x00000128U; | ||
418 | } | ||
419 | static inline u32 falcon_falcon_dmatrfmoffs_r(void) | ||
420 | { | ||
421 | return 0x00000114U; | ||
422 | } | ||
423 | static inline u32 falcon_falcon_dmatrfcmd_r(void) | ||
424 | { | ||
425 | return 0x00000118U; | ||
426 | } | ||
427 | static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) | ||
428 | { | ||
429 | return (v & 0x1U) << 4U; | ||
430 | } | ||
431 | static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) | ||
432 | { | ||
433 | return (v & 0x1U) << 5U; | ||
434 | } | ||
435 | static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) | ||
436 | { | ||
437 | return (v & 0x7U) << 8U; | ||
438 | } | ||
439 | static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) | ||
440 | { | ||
441 | return (v & 0x7U) << 12U; | ||
442 | } | ||
443 | static inline u32 falcon_falcon_dmatrffboffs_r(void) | ||
444 | { | ||
445 | return 0x0000011cU; | ||
446 | } | ||
447 | static inline u32 falcon_falcon_imctl_debug_r(void) | ||
448 | { | ||
449 | return 0x0000015cU; | ||
450 | } | ||
451 | static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) | ||
452 | { | ||
453 | return (v & 0xffffffU) << 0U; | ||
454 | } | ||
455 | static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) | ||
456 | { | ||
457 | return (v & 0x7U) << 24U; | ||
458 | } | ||
459 | static inline u32 falcon_falcon_imstat_r(void) | ||
460 | { | ||
461 | return 0x00000144U; | ||
462 | } | ||
463 | static inline u32 falcon_falcon_traceidx_r(void) | ||
464 | { | ||
465 | return 0x00000148U; | ||
466 | } | ||
467 | static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) | ||
468 | { | ||
469 | return (r >> 16U) & 0xffU; | ||
470 | } | ||
471 | static inline u32 falcon_falcon_traceidx_idx_f(u32 v) | ||
472 | { | ||
473 | return (v & 0xffU) << 0U; | ||
474 | } | ||
475 | static inline u32 falcon_falcon_tracepc_r(void) | ||
476 | { | ||
477 | return 0x0000014cU; | ||
478 | } | ||
479 | static inline u32 falcon_falcon_tracepc_pc_v(u32 r) | ||
480 | { | ||
481 | return (r >> 0U) & 0xffffffU; | ||
482 | } | ||
483 | static inline u32 falcon_falcon_exterraddr_r(void) | ||
484 | { | ||
485 | return 0x00000168U; | ||
486 | } | ||
487 | static inline u32 falcon_falcon_exterrstat_r(void) | ||
488 | { | ||
489 | return 0x0000016cU; | ||
490 | } | ||
491 | static inline u32 falcon_falcon_exterrstat_valid_m(void) | ||
492 | { | ||
493 | return 0x1U << 31U; | ||
494 | } | ||
495 | static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) | ||
496 | { | ||
497 | return (r >> 31U) & 0x1U; | ||
498 | } | ||
499 | static inline u32 falcon_falcon_exterrstat_valid_true_v(void) | ||
500 | { | ||
501 | return 0x00000001U; | ||
502 | } | ||
503 | static inline u32 falcon_falcon_icd_cmd_r(void) | ||
504 | { | ||
505 | return 0x00000200U; | ||
506 | } | ||
507 | static inline u32 falcon_falcon_icd_cmd_opc_s(void) | ||
508 | { | ||
509 | return 4U; | ||
510 | } | ||
511 | static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) | ||
512 | { | ||
513 | return (v & 0xfU) << 0U; | ||
514 | } | ||
515 | static inline u32 falcon_falcon_icd_cmd_opc_m(void) | ||
516 | { | ||
517 | return 0xfU << 0U; | ||
518 | } | ||
519 | static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) | ||
520 | { | ||
521 | return (r >> 0U) & 0xfU; | ||
522 | } | ||
523 | static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) | ||
524 | { | ||
525 | return 0x8U; | ||
526 | } | ||
527 | static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) | ||
528 | { | ||
529 | return 0xeU; | ||
530 | } | ||
531 | static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) | ||
532 | { | ||
533 | return (v & 0x1fU) << 8U; | ||
534 | } | ||
535 | static inline u32 falcon_falcon_icd_rdata_r(void) | ||
536 | { | ||
537 | return 0x0000020cU; | ||
538 | } | ||
539 | static inline u32 falcon_falcon_dmemc_r(u32 i) | ||
540 | { | ||
541 | return 0x000001c0U + i*8U; | ||
542 | } | ||
543 | static inline u32 falcon_falcon_dmemc_offs_f(u32 v) | ||
544 | { | ||
545 | return (v & 0x3fU) << 2U; | ||
546 | } | ||
547 | static inline u32 falcon_falcon_dmemc_offs_m(void) | ||
548 | { | ||
549 | return 0x3fU << 2U; | ||
550 | } | ||
551 | static inline u32 falcon_falcon_dmemc_blk_f(u32 v) | ||
552 | { | ||
553 | return (v & 0xffU) << 8U; | ||
554 | } | ||
555 | static inline u32 falcon_falcon_dmemc_blk_m(void) | ||
556 | { | ||
557 | return 0xffU << 8U; | ||
558 | } | ||
559 | static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) | ||
560 | { | ||
561 | return (v & 0x1U) << 24U; | ||
562 | } | ||
563 | static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) | ||
564 | { | ||
565 | return (v & 0x1U) << 25U; | ||
566 | } | ||
567 | static inline u32 falcon_falcon_dmemd_r(u32 i) | ||
568 | { | ||
569 | return 0x000001c4U + i*8U; | ||
570 | } | ||
571 | static inline u32 falcon_falcon_debug1_r(void) | ||
572 | { | ||
573 | return 0x00000090U; | ||
574 | } | ||
575 | static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) | ||
576 | { | ||
577 | return 1U; | ||
578 | } | ||
579 | static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) | ||
580 | { | ||
581 | return (v & 0x1U) << 16U; | ||
582 | } | ||
583 | static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) | ||
584 | { | ||
585 | return 0x1U << 16U; | ||
586 | } | ||
587 | static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) | ||
588 | { | ||
589 | return (r >> 16U) & 0x1U; | ||
590 | } | ||
591 | static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) | ||
592 | { | ||
593 | return 0x0U; | ||
594 | } | ||
595 | static inline u32 falcon_falcon_debuginfo_r(void) | ||
596 | { | ||
597 | return 0x00000094U; | ||
598 | } | ||
599 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h new file mode 100644 index 00000000..a4fcd1e6 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | |||
@@ -0,0 +1,1511 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_fb_gv100_h_ | ||
57 | #define _hw_fb_gv100_h_ | ||
58 | |||
59 | static inline u32 fb_fbhub_num_active_ltcs_r(void) | ||
60 | { | ||
61 | return 0x00100800U; | ||
62 | } | ||
63 | static inline u32 fb_mmu_ctrl_r(void) | ||
64 | { | ||
65 | return 0x00100c80U; | ||
66 | } | ||
67 | static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) | ||
68 | { | ||
69 | return (v & 0x1U) << 0U; | ||
70 | } | ||
71 | static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) | ||
76 | { | ||
77 | return 0x1U; | ||
78 | } | ||
79 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) | ||
80 | { | ||
81 | return (r >> 15U) & 0x1U; | ||
82 | } | ||
83 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) | ||
84 | { | ||
85 | return 0x0U; | ||
86 | } | ||
87 | static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) | ||
88 | { | ||
89 | return (r >> 16U) & 0xffU; | ||
90 | } | ||
91 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) | ||
92 | { | ||
93 | return (r >> 11U) & 0x1U; | ||
94 | } | ||
95 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) | ||
96 | { | ||
97 | return 0x800U; | ||
98 | } | ||
99 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) | ||
100 | { | ||
101 | return 0x0U; | ||
102 | } | ||
103 | static inline u32 fb_priv_mmu_phy_secure_r(void) | ||
104 | { | ||
105 | return 0x00100ce4U; | ||
106 | } | ||
107 | static inline u32 fb_mmu_invalidate_pdb_r(void) | ||
108 | { | ||
109 | return 0x00100cb8U; | ||
110 | } | ||
111 | static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) | ||
112 | { | ||
113 | return 0x0U; | ||
114 | } | ||
115 | static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) | ||
116 | { | ||
117 | return 0x2U; | ||
118 | } | ||
119 | static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) | ||
120 | { | ||
121 | return (v & 0xfffffffU) << 4U; | ||
122 | } | ||
123 | static inline u32 fb_mmu_invalidate_r(void) | ||
124 | { | ||
125 | return 0x00100cbcU; | ||
126 | } | ||
127 | static inline u32 fb_mmu_invalidate_all_va_true_f(void) | ||
128 | { | ||
129 | return 0x1U; | ||
130 | } | ||
131 | static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) | ||
132 | { | ||
133 | return 0x2U; | ||
134 | } | ||
135 | static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) | ||
136 | { | ||
137 | return 1U; | ||
138 | } | ||
139 | static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 2U; | ||
142 | } | ||
143 | static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) | ||
144 | { | ||
145 | return 0x1U << 2U; | ||
146 | } | ||
147 | static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) | ||
148 | { | ||
149 | return (r >> 2U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) | ||
152 | { | ||
153 | return 0x4U; | ||
154 | } | ||
155 | static inline u32 fb_mmu_invalidate_replay_s(void) | ||
156 | { | ||
157 | return 3U; | ||
158 | } | ||
159 | static inline u32 fb_mmu_invalidate_replay_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x7U) << 3U; | ||
162 | } | ||
163 | static inline u32 fb_mmu_invalidate_replay_m(void) | ||
164 | { | ||
165 | return 0x7U << 3U; | ||
166 | } | ||
167 | static inline u32 fb_mmu_invalidate_replay_v(u32 r) | ||
168 | { | ||
169 | return (r >> 3U) & 0x7U; | ||
170 | } | ||
171 | static inline u32 fb_mmu_invalidate_replay_none_f(void) | ||
172 | { | ||
173 | return 0x0U; | ||
174 | } | ||
175 | static inline u32 fb_mmu_invalidate_replay_start_f(void) | ||
176 | { | ||
177 | return 0x8U; | ||
178 | } | ||
179 | static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) | ||
180 | { | ||
181 | return 0x10U; | ||
182 | } | ||
183 | static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) | ||
184 | { | ||
185 | return 0x20U; | ||
186 | } | ||
187 | static inline u32 fb_mmu_invalidate_sys_membar_s(void) | ||
188 | { | ||
189 | return 1U; | ||
190 | } | ||
191 | static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1U) << 6U; | ||
194 | } | ||
195 | static inline u32 fb_mmu_invalidate_sys_membar_m(void) | ||
196 | { | ||
197 | return 0x1U << 6U; | ||
198 | } | ||
199 | static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) | ||
200 | { | ||
201 | return (r >> 6U) & 0x1U; | ||
202 | } | ||
203 | static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) | ||
204 | { | ||
205 | return 0x40U; | ||
206 | } | ||
207 | static inline u32 fb_mmu_invalidate_ack_s(void) | ||
208 | { | ||
209 | return 2U; | ||
210 | } | ||
211 | static inline u32 fb_mmu_invalidate_ack_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x3U) << 7U; | ||
214 | } | ||
215 | static inline u32 fb_mmu_invalidate_ack_m(void) | ||
216 | { | ||
217 | return 0x3U << 7U; | ||
218 | } | ||
219 | static inline u32 fb_mmu_invalidate_ack_v(u32 r) | ||
220 | { | ||
221 | return (r >> 7U) & 0x3U; | ||
222 | } | ||
223 | static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) | ||
224 | { | ||
225 | return 0x0U; | ||
226 | } | ||
227 | static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) | ||
228 | { | ||
229 | return 0x100U; | ||
230 | } | ||
231 | static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) | ||
232 | { | ||
233 | return 0x80U; | ||
234 | } | ||
235 | static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) | ||
236 | { | ||
237 | return 6U; | ||
238 | } | ||
239 | static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x3fU) << 9U; | ||
242 | } | ||
243 | static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) | ||
244 | { | ||
245 | return 0x3fU << 9U; | ||
246 | } | ||
247 | static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) | ||
248 | { | ||
249 | return (r >> 9U) & 0x3fU; | ||
250 | } | ||
251 | static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) | ||
252 | { | ||
253 | return 5U; | ||
254 | } | ||
255 | static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) | ||
256 | { | ||
257 | return (v & 0x1fU) << 15U; | ||
258 | } | ||
259 | static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) | ||
260 | { | ||
261 | return 0x1fU << 15U; | ||
262 | } | ||
263 | static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) | ||
264 | { | ||
265 | return (r >> 15U) & 0x1fU; | ||
266 | } | ||
267 | static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) | ||
268 | { | ||
269 | return 1U; | ||
270 | } | ||
271 | static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) | ||
272 | { | ||
273 | return (v & 0x1U) << 20U; | ||
274 | } | ||
275 | static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) | ||
276 | { | ||
277 | return 0x1U << 20U; | ||
278 | } | ||
279 | static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) | ||
280 | { | ||
281 | return (r >> 20U) & 0x1U; | ||
282 | } | ||
283 | static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) | ||
284 | { | ||
285 | return 0x0U; | ||
286 | } | ||
287 | static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) | ||
288 | { | ||
289 | return 0x100000U; | ||
290 | } | ||
291 | static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) | ||
292 | { | ||
293 | return 3U; | ||
294 | } | ||
295 | static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x7U) << 24U; | ||
298 | } | ||
299 | static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) | ||
300 | { | ||
301 | return 0x7U << 24U; | ||
302 | } | ||
303 | static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) | ||
304 | { | ||
305 | return (r >> 24U) & 0x7U; | ||
306 | } | ||
307 | static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) | ||
308 | { | ||
309 | return 0x0U; | ||
310 | } | ||
311 | static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) | ||
312 | { | ||
313 | return 0x1000000U; | ||
314 | } | ||
315 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) | ||
316 | { | ||
317 | return 0x2000000U; | ||
318 | } | ||
319 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) | ||
320 | { | ||
321 | return 0x3000000U; | ||
322 | } | ||
323 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) | ||
324 | { | ||
325 | return 0x4000000U; | ||
326 | } | ||
327 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) | ||
328 | { | ||
329 | return 0x5000000U; | ||
330 | } | ||
331 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) | ||
332 | { | ||
333 | return 0x6000000U; | ||
334 | } | ||
335 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) | ||
336 | { | ||
337 | return 0x7000000U; | ||
338 | } | ||
339 | static inline u32 fb_mmu_invalidate_trigger_s(void) | ||
340 | { | ||
341 | return 1U; | ||
342 | } | ||
343 | static inline u32 fb_mmu_invalidate_trigger_f(u32 v) | ||
344 | { | ||
345 | return (v & 0x1U) << 31U; | ||
346 | } | ||
347 | static inline u32 fb_mmu_invalidate_trigger_m(void) | ||
348 | { | ||
349 | return 0x1U << 31U; | ||
350 | } | ||
351 | static inline u32 fb_mmu_invalidate_trigger_v(u32 r) | ||
352 | { | ||
353 | return (r >> 31U) & 0x1U; | ||
354 | } | ||
355 | static inline u32 fb_mmu_invalidate_trigger_true_f(void) | ||
356 | { | ||
357 | return 0x80000000U; | ||
358 | } | ||
359 | static inline u32 fb_mmu_debug_wr_r(void) | ||
360 | { | ||
361 | return 0x00100cc8U; | ||
362 | } | ||
363 | static inline u32 fb_mmu_debug_wr_aperture_s(void) | ||
364 | { | ||
365 | return 2U; | ||
366 | } | ||
367 | static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) | ||
368 | { | ||
369 | return (v & 0x3U) << 0U; | ||
370 | } | ||
371 | static inline u32 fb_mmu_debug_wr_aperture_m(void) | ||
372 | { | ||
373 | return 0x3U << 0U; | ||
374 | } | ||
375 | static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) | ||
376 | { | ||
377 | return (r >> 0U) & 0x3U; | ||
378 | } | ||
379 | static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) | ||
380 | { | ||
381 | return 0x0U; | ||
382 | } | ||
383 | static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) | ||
384 | { | ||
385 | return 0x2U; | ||
386 | } | ||
387 | static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) | ||
388 | { | ||
389 | return 0x3U; | ||
390 | } | ||
391 | static inline u32 fb_mmu_debug_wr_vol_false_f(void) | ||
392 | { | ||
393 | return 0x0U; | ||
394 | } | ||
395 | static inline u32 fb_mmu_debug_wr_vol_true_v(void) | ||
396 | { | ||
397 | return 0x00000001U; | ||
398 | } | ||
399 | static inline u32 fb_mmu_debug_wr_vol_true_f(void) | ||
400 | { | ||
401 | return 0x4U; | ||
402 | } | ||
403 | static inline u32 fb_mmu_debug_wr_addr_f(u32 v) | ||
404 | { | ||
405 | return (v & 0xfffffffU) << 4U; | ||
406 | } | ||
407 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) | ||
408 | { | ||
409 | return 0x0000000cU; | ||
410 | } | ||
411 | static inline u32 fb_mmu_debug_rd_r(void) | ||
412 | { | ||
413 | return 0x00100cccU; | ||
414 | } | ||
415 | static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) | ||
416 | { | ||
417 | return 0x0U; | ||
418 | } | ||
419 | static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) | ||
420 | { | ||
421 | return 0x2U; | ||
422 | } | ||
423 | static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) | ||
424 | { | ||
425 | return 0x3U; | ||
426 | } | ||
427 | static inline u32 fb_mmu_debug_rd_vol_false_f(void) | ||
428 | { | ||
429 | return 0x0U; | ||
430 | } | ||
431 | static inline u32 fb_mmu_debug_rd_addr_f(u32 v) | ||
432 | { | ||
433 | return (v & 0xfffffffU) << 4U; | ||
434 | } | ||
435 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) | ||
436 | { | ||
437 | return 0x0000000cU; | ||
438 | } | ||
439 | static inline u32 fb_mmu_debug_ctrl_r(void) | ||
440 | { | ||
441 | return 0x00100cc4U; | ||
442 | } | ||
443 | static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) | ||
444 | { | ||
445 | return (r >> 16U) & 0x1U; | ||
446 | } | ||
447 | static inline u32 fb_mmu_debug_ctrl_debug_m(void) | ||
448 | { | ||
449 | return 0x1U << 16U; | ||
450 | } | ||
451 | static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) | ||
452 | { | ||
453 | return 0x00000001U; | ||
454 | } | ||
455 | static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) | ||
456 | { | ||
457 | return 0x00000000U; | ||
458 | } | ||
459 | static inline u32 fb_mmu_vpr_info_r(void) | ||
460 | { | ||
461 | return 0x00100cd0U; | ||
462 | } | ||
463 | static inline u32 fb_mmu_vpr_info_index_f(u32 v) | ||
464 | { | ||
465 | return (v & 0x3U) << 0U; | ||
466 | } | ||
467 | static inline u32 fb_mmu_vpr_info_index_v(u32 r) | ||
468 | { | ||
469 | return (r >> 0U) & 0x3U; | ||
470 | } | ||
471 | static inline u32 fb_mmu_vpr_info_index_m(void) | ||
472 | { | ||
473 | return 0x3U << 0U; | ||
474 | } | ||
475 | static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void) | ||
476 | { | ||
477 | return 0x00000000U; | ||
478 | } | ||
479 | static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void) | ||
480 | { | ||
481 | return 0x00000001U; | ||
482 | } | ||
483 | static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void) | ||
484 | { | ||
485 | return 0x00000002U; | ||
486 | } | ||
487 | static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void) | ||
488 | { | ||
489 | return 0x00000003U; | ||
490 | } | ||
491 | static inline u32 fb_mmu_vpr_info_cya_lo_in_use_m(void) | ||
492 | { | ||
493 | return 0x1U << 4U; | ||
494 | } | ||
495 | static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) | ||
496 | { | ||
497 | return (v & 0x1U) << 2U; | ||
498 | } | ||
499 | static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) | ||
500 | { | ||
501 | return (r >> 2U) & 0x1U; | ||
502 | } | ||
503 | static inline u32 fb_mmu_vpr_info_fetch_false_v(void) | ||
504 | { | ||
505 | return 0x00000000U; | ||
506 | } | ||
507 | static inline u32 fb_mmu_vpr_info_fetch_true_v(void) | ||
508 | { | ||
509 | return 0x00000001U; | ||
510 | } | ||
511 | static inline u32 fb_niso_flush_sysmem_addr_r(void) | ||
512 | { | ||
513 | return 0x00100c10U; | ||
514 | } | ||
515 | static inline u32 fb_niso_intr_r(void) | ||
516 | { | ||
517 | return 0x00100a20U; | ||
518 | } | ||
519 | static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) | ||
520 | { | ||
521 | return 0x1U << 0U; | ||
522 | } | ||
523 | static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) | ||
524 | { | ||
525 | return 0x1U; | ||
526 | } | ||
527 | static inline u32 fb_niso_intr_hub_access_counter_error_m(void) | ||
528 | { | ||
529 | return 0x1U << 1U; | ||
530 | } | ||
531 | static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) | ||
532 | { | ||
533 | return 0x2U; | ||
534 | } | ||
535 | static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) | ||
536 | { | ||
537 | return 0x1U << 27U; | ||
538 | } | ||
539 | static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) | ||
540 | { | ||
541 | return 0x8000000U; | ||
542 | } | ||
543 | static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) | ||
544 | { | ||
545 | return 0x1U << 28U; | ||
546 | } | ||
547 | static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) | ||
548 | { | ||
549 | return 0x10000000U; | ||
550 | } | ||
551 | static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) | ||
552 | { | ||
553 | return 0x1U << 29U; | ||
554 | } | ||
555 | static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) | ||
556 | { | ||
557 | return 0x20000000U; | ||
558 | } | ||
559 | static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) | ||
560 | { | ||
561 | return 0x1U << 30U; | ||
562 | } | ||
563 | static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) | ||
564 | { | ||
565 | return 0x40000000U; | ||
566 | } | ||
567 | static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) | ||
568 | { | ||
569 | return 0x1U << 31U; | ||
570 | } | ||
571 | static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) | ||
572 | { | ||
573 | return 0x80000000U; | ||
574 | } | ||
575 | static inline u32 fb_niso_intr_en_r(u32 i) | ||
576 | { | ||
577 | return 0x00100a24U + i*4U; | ||
578 | } | ||
579 | static inline u32 fb_niso_intr_en__size_1_v(void) | ||
580 | { | ||
581 | return 0x00000002U; | ||
582 | } | ||
583 | static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) | ||
584 | { | ||
585 | return (v & 0x1U) << 0U; | ||
586 | } | ||
587 | static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) | ||
588 | { | ||
589 | return 0x1U; | ||
590 | } | ||
591 | static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) | ||
592 | { | ||
593 | return (v & 0x1U) << 1U; | ||
594 | } | ||
595 | static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) | ||
596 | { | ||
597 | return 0x2U; | ||
598 | } | ||
599 | static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) | ||
600 | { | ||
601 | return (v & 0x1U) << 27U; | ||
602 | } | ||
603 | static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) | ||
604 | { | ||
605 | return 0x8000000U; | ||
606 | } | ||
607 | static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) | ||
608 | { | ||
609 | return (v & 0x1U) << 28U; | ||
610 | } | ||
611 | static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) | ||
612 | { | ||
613 | return 0x10000000U; | ||
614 | } | ||
615 | static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) | ||
616 | { | ||
617 | return (v & 0x1U) << 29U; | ||
618 | } | ||
619 | static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) | ||
620 | { | ||
621 | return 0x20000000U; | ||
622 | } | ||
623 | static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) | ||
624 | { | ||
625 | return (v & 0x1U) << 30U; | ||
626 | } | ||
627 | static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) | ||
628 | { | ||
629 | return 0x40000000U; | ||
630 | } | ||
631 | static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) | ||
632 | { | ||
633 | return (v & 0x1U) << 31U; | ||
634 | } | ||
635 | static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) | ||
636 | { | ||
637 | return 0x80000000U; | ||
638 | } | ||
639 | static inline u32 fb_niso_intr_en_set_r(u32 i) | ||
640 | { | ||
641 | return 0x00100a2cU + i*4U; | ||
642 | } | ||
643 | static inline u32 fb_niso_intr_en_set__size_1_v(void) | ||
644 | { | ||
645 | return 0x00000002U; | ||
646 | } | ||
647 | static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) | ||
648 | { | ||
649 | return 0x1U << 0U; | ||
650 | } | ||
651 | static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) | ||
652 | { | ||
653 | return 0x1U; | ||
654 | } | ||
655 | static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) | ||
656 | { | ||
657 | return 0x1U << 1U; | ||
658 | } | ||
659 | static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) | ||
660 | { | ||
661 | return 0x2U; | ||
662 | } | ||
663 | static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) | ||
664 | { | ||
665 | return 0x1U << 27U; | ||
666 | } | ||
667 | static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) | ||
668 | { | ||
669 | return 0x8000000U; | ||
670 | } | ||
671 | static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) | ||
672 | { | ||
673 | return 0x1U << 28U; | ||
674 | } | ||
675 | static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) | ||
676 | { | ||
677 | return 0x10000000U; | ||
678 | } | ||
679 | static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) | ||
680 | { | ||
681 | return 0x1U << 29U; | ||
682 | } | ||
683 | static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) | ||
684 | { | ||
685 | return 0x20000000U; | ||
686 | } | ||
687 | static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) | ||
688 | { | ||
689 | return 0x1U << 30U; | ||
690 | } | ||
691 | static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) | ||
692 | { | ||
693 | return 0x40000000U; | ||
694 | } | ||
695 | static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) | ||
696 | { | ||
697 | return 0x1U << 31U; | ||
698 | } | ||
699 | static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) | ||
700 | { | ||
701 | return 0x80000000U; | ||
702 | } | ||
703 | static inline u32 fb_niso_intr_en_clr_r(u32 i) | ||
704 | { | ||
705 | return 0x00100a34U + i*4U; | ||
706 | } | ||
707 | static inline u32 fb_niso_intr_en_clr__size_1_v(void) | ||
708 | { | ||
709 | return 0x00000002U; | ||
710 | } | ||
711 | static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) | ||
712 | { | ||
713 | return 0x1U << 0U; | ||
714 | } | ||
715 | static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) | ||
716 | { | ||
717 | return 0x1U; | ||
718 | } | ||
719 | static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) | ||
720 | { | ||
721 | return 0x1U << 1U; | ||
722 | } | ||
723 | static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) | ||
724 | { | ||
725 | return 0x2U; | ||
726 | } | ||
727 | static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) | ||
728 | { | ||
729 | return 0x1U << 27U; | ||
730 | } | ||
731 | static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) | ||
732 | { | ||
733 | return 0x8000000U; | ||
734 | } | ||
735 | static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) | ||
736 | { | ||
737 | return 0x1U << 28U; | ||
738 | } | ||
739 | static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) | ||
740 | { | ||
741 | return 0x10000000U; | ||
742 | } | ||
743 | static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) | ||
744 | { | ||
745 | return 0x1U << 29U; | ||
746 | } | ||
747 | static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) | ||
748 | { | ||
749 | return 0x20000000U; | ||
750 | } | ||
751 | static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) | ||
752 | { | ||
753 | return 0x1U << 30U; | ||
754 | } | ||
755 | static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) | ||
756 | { | ||
757 | return 0x40000000U; | ||
758 | } | ||
759 | static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) | ||
760 | { | ||
761 | return 0x1U << 31U; | ||
762 | } | ||
763 | static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) | ||
764 | { | ||
765 | return 0x80000000U; | ||
766 | } | ||
767 | static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) | ||
768 | { | ||
769 | return 0x00000000U; | ||
770 | } | ||
771 | static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) | ||
772 | { | ||
773 | return 0x00000001U; | ||
774 | } | ||
775 | static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) | ||
776 | { | ||
777 | return 0x00100e24U + i*20U; | ||
778 | } | ||
779 | static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) | ||
780 | { | ||
781 | return 0x00000002U; | ||
782 | } | ||
783 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) | ||
784 | { | ||
785 | return (v & 0x1U) << 0U; | ||
786 | } | ||
787 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) | ||
788 | { | ||
789 | return (r >> 0U) & 0x1U; | ||
790 | } | ||
791 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) | ||
792 | { | ||
793 | return 0x00000000U; | ||
794 | } | ||
795 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) | ||
796 | { | ||
797 | return 0x0U; | ||
798 | } | ||
799 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) | ||
800 | { | ||
801 | return 0x00000001U; | ||
802 | } | ||
803 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) | ||
804 | { | ||
805 | return 0x1U; | ||
806 | } | ||
807 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) | ||
808 | { | ||
809 | return (v & 0x3U) << 1U; | ||
810 | } | ||
811 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) | ||
812 | { | ||
813 | return (r >> 1U) & 0x3U; | ||
814 | } | ||
815 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) | ||
816 | { | ||
817 | return 0x00000002U; | ||
818 | } | ||
819 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) | ||
820 | { | ||
821 | return 0x4U; | ||
822 | } | ||
823 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) | ||
824 | { | ||
825 | return 0x00000003U; | ||
826 | } | ||
827 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) | ||
828 | { | ||
829 | return 0x6U; | ||
830 | } | ||
831 | static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) | ||
832 | { | ||
833 | return (v & 0x1U) << 3U; | ||
834 | } | ||
835 | static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) | ||
836 | { | ||
837 | return (r >> 3U) & 0x1U; | ||
838 | } | ||
839 | static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) | ||
840 | { | ||
841 | return (v & 0xfffffU) << 12U; | ||
842 | } | ||
843 | static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) | ||
844 | { | ||
845 | return (r >> 12U) & 0xfffffU; | ||
846 | } | ||
847 | static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) | ||
848 | { | ||
849 | return 0x00100e28U + i*20U; | ||
850 | } | ||
851 | static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) | ||
852 | { | ||
853 | return 0x00000002U; | ||
854 | } | ||
855 | static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) | ||
856 | { | ||
857 | return (v & 0xffffffffU) << 0U; | ||
858 | } | ||
859 | static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) | ||
860 | { | ||
861 | return (r >> 0U) & 0xffffffffU; | ||
862 | } | ||
863 | static inline u32 fb_mmu_fault_buffer_get_r(u32 i) | ||
864 | { | ||
865 | return 0x00100e2cU + i*20U; | ||
866 | } | ||
867 | static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) | ||
868 | { | ||
869 | return 0x00000002U; | ||
870 | } | ||
871 | static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) | ||
872 | { | ||
873 | return (v & 0xfffffU) << 0U; | ||
874 | } | ||
875 | static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) | ||
876 | { | ||
877 | return 0xfffffU << 0U; | ||
878 | } | ||
879 | static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) | ||
880 | { | ||
881 | return (r >> 0U) & 0xfffffU; | ||
882 | } | ||
883 | static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) | ||
884 | { | ||
885 | return (v & 0x1U) << 30U; | ||
886 | } | ||
887 | static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) | ||
888 | { | ||
889 | return 0x1U << 30U; | ||
890 | } | ||
891 | static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) | ||
892 | { | ||
893 | return 0x00000001U; | ||
894 | } | ||
895 | static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) | ||
896 | { | ||
897 | return 0x40000000U; | ||
898 | } | ||
899 | static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) | ||
900 | { | ||
901 | return (v & 0x1U) << 31U; | ||
902 | } | ||
903 | static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) | ||
904 | { | ||
905 | return 0x1U << 31U; | ||
906 | } | ||
907 | static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) | ||
908 | { | ||
909 | return 0x00000001U; | ||
910 | } | ||
911 | static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) | ||
912 | { | ||
913 | return 0x80000000U; | ||
914 | } | ||
915 | static inline u32 fb_mmu_fault_buffer_put_r(u32 i) | ||
916 | { | ||
917 | return 0x00100e30U + i*20U; | ||
918 | } | ||
919 | static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) | ||
920 | { | ||
921 | return 0x00000002U; | ||
922 | } | ||
923 | static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) | ||
924 | { | ||
925 | return (v & 0xfffffU) << 0U; | ||
926 | } | ||
927 | static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) | ||
928 | { | ||
929 | return (r >> 0U) & 0xfffffU; | ||
930 | } | ||
931 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) | ||
932 | { | ||
933 | return (v & 0x1U) << 30U; | ||
934 | } | ||
935 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) | ||
936 | { | ||
937 | return (r >> 30U) & 0x1U; | ||
938 | } | ||
939 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) | ||
940 | { | ||
941 | return 0x00000001U; | ||
942 | } | ||
943 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) | ||
944 | { | ||
945 | return 0x40000000U; | ||
946 | } | ||
947 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) | ||
948 | { | ||
949 | return 0x00000000U; | ||
950 | } | ||
951 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) | ||
952 | { | ||
953 | return 0x0U; | ||
954 | } | ||
955 | static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) | ||
956 | { | ||
957 | return (v & 0x1U) << 31U; | ||
958 | } | ||
959 | static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) | ||
960 | { | ||
961 | return (r >> 31U) & 0x1U; | ||
962 | } | ||
963 | static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) | ||
964 | { | ||
965 | return 0x00000001U; | ||
966 | } | ||
967 | static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) | ||
968 | { | ||
969 | return 0x80000000U; | ||
970 | } | ||
971 | static inline u32 fb_mmu_fault_buffer_size_r(u32 i) | ||
972 | { | ||
973 | return 0x00100e34U + i*20U; | ||
974 | } | ||
975 | static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) | ||
976 | { | ||
977 | return 0x00000002U; | ||
978 | } | ||
979 | static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) | ||
980 | { | ||
981 | return (v & 0xfffffU) << 0U; | ||
982 | } | ||
983 | static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) | ||
984 | { | ||
985 | return (r >> 0U) & 0xfffffU; | ||
986 | } | ||
987 | static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) | ||
988 | { | ||
989 | return (v & 0x1U) << 29U; | ||
990 | } | ||
991 | static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) | ||
992 | { | ||
993 | return (r >> 29U) & 0x1U; | ||
994 | } | ||
995 | static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) | ||
996 | { | ||
997 | return 0x00000001U; | ||
998 | } | ||
999 | static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) | ||
1000 | { | ||
1001 | return 0x20000000U; | ||
1002 | } | ||
1003 | static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) | ||
1004 | { | ||
1005 | return (v & 0x1U) << 30U; | ||
1006 | } | ||
1007 | static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) | ||
1008 | { | ||
1009 | return (r >> 30U) & 0x1U; | ||
1010 | } | ||
1011 | static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) | ||
1012 | { | ||
1013 | return 0x00000001U; | ||
1014 | } | ||
1015 | static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) | ||
1016 | { | ||
1017 | return 0x40000000U; | ||
1018 | } | ||
1019 | static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) | ||
1020 | { | ||
1021 | return (v & 0x1U) << 31U; | ||
1022 | } | ||
1023 | static inline u32 fb_mmu_fault_buffer_size_enable_m(void) | ||
1024 | { | ||
1025 | return 0x1U << 31U; | ||
1026 | } | ||
1027 | static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) | ||
1028 | { | ||
1029 | return (r >> 31U) & 0x1U; | ||
1030 | } | ||
1031 | static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) | ||
1032 | { | ||
1033 | return 0x00000001U; | ||
1034 | } | ||
1035 | static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) | ||
1036 | { | ||
1037 | return 0x80000000U; | ||
1038 | } | ||
1039 | static inline u32 fb_mmu_fault_addr_lo_r(void) | ||
1040 | { | ||
1041 | return 0x00100e4cU; | ||
1042 | } | ||
1043 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) | ||
1044 | { | ||
1045 | return (v & 0x3U) << 0U; | ||
1046 | } | ||
1047 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) | ||
1048 | { | ||
1049 | return (r >> 0U) & 0x3U; | ||
1050 | } | ||
1051 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) | ||
1052 | { | ||
1053 | return 0x00000002U; | ||
1054 | } | ||
1055 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) | ||
1056 | { | ||
1057 | return 0x2U; | ||
1058 | } | ||
1059 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) | ||
1060 | { | ||
1061 | return 0x00000003U; | ||
1062 | } | ||
1063 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) | ||
1064 | { | ||
1065 | return 0x3U; | ||
1066 | } | ||
1067 | static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) | ||
1068 | { | ||
1069 | return (v & 0xfffffU) << 12U; | ||
1070 | } | ||
1071 | static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) | ||
1072 | { | ||
1073 | return (r >> 12U) & 0xfffffU; | ||
1074 | } | ||
1075 | static inline u32 fb_mmu_fault_addr_hi_r(void) | ||
1076 | { | ||
1077 | return 0x00100e50U; | ||
1078 | } | ||
1079 | static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) | ||
1080 | { | ||
1081 | return (v & 0xffffffffU) << 0U; | ||
1082 | } | ||
1083 | static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) | ||
1084 | { | ||
1085 | return (r >> 0U) & 0xffffffffU; | ||
1086 | } | ||
1087 | static inline u32 fb_mmu_fault_inst_lo_r(void) | ||
1088 | { | ||
1089 | return 0x00100e54U; | ||
1090 | } | ||
1091 | static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) | ||
1092 | { | ||
1093 | return (r >> 0U) & 0x1ffU; | ||
1094 | } | ||
1095 | static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) | ||
1096 | { | ||
1097 | return (r >> 10U) & 0x3U; | ||
1098 | } | ||
1099 | static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) | ||
1100 | { | ||
1101 | return 0x00000002U; | ||
1102 | } | ||
1103 | static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) | ||
1104 | { | ||
1105 | return 0x00000003U; | ||
1106 | } | ||
1107 | static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) | ||
1108 | { | ||
1109 | return (v & 0xfffffU) << 12U; | ||
1110 | } | ||
1111 | static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) | ||
1112 | { | ||
1113 | return (r >> 12U) & 0xfffffU; | ||
1114 | } | ||
1115 | static inline u32 fb_mmu_fault_inst_hi_r(void) | ||
1116 | { | ||
1117 | return 0x00100e58U; | ||
1118 | } | ||
1119 | static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) | ||
1120 | { | ||
1121 | return (r >> 0U) & 0xffffffffU; | ||
1122 | } | ||
1123 | static inline u32 fb_mmu_fault_info_r(void) | ||
1124 | { | ||
1125 | return 0x00100e5cU; | ||
1126 | } | ||
1127 | static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) | ||
1128 | { | ||
1129 | return (r >> 0U) & 0x1fU; | ||
1130 | } | ||
1131 | static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) | ||
1132 | { | ||
1133 | return (r >> 7U) & 0x1U; | ||
1134 | } | ||
1135 | static inline u32 fb_mmu_fault_info_client_v(u32 r) | ||
1136 | { | ||
1137 | return (r >> 8U) & 0x7fU; | ||
1138 | } | ||
1139 | static inline u32 fb_mmu_fault_info_access_type_v(u32 r) | ||
1140 | { | ||
1141 | return (r >> 16U) & 0xfU; | ||
1142 | } | ||
1143 | static inline u32 fb_mmu_fault_info_client_type_v(u32 r) | ||
1144 | { | ||
1145 | return (r >> 20U) & 0x1U; | ||
1146 | } | ||
1147 | static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) | ||
1148 | { | ||
1149 | return (r >> 24U) & 0x1fU; | ||
1150 | } | ||
1151 | static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) | ||
1152 | { | ||
1153 | return (r >> 29U) & 0x1U; | ||
1154 | } | ||
1155 | static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) | ||
1156 | { | ||
1157 | return (r >> 30U) & 0x1U; | ||
1158 | } | ||
1159 | static inline u32 fb_mmu_fault_info_valid_v(u32 r) | ||
1160 | { | ||
1161 | return (r >> 31U) & 0x1U; | ||
1162 | } | ||
1163 | static inline u32 fb_mmu_fault_status_r(void) | ||
1164 | { | ||
1165 | return 0x00100e60U; | ||
1166 | } | ||
1167 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) | ||
1168 | { | ||
1169 | return 0x1U << 0U; | ||
1170 | } | ||
1171 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) | ||
1172 | { | ||
1173 | return 0x00000001U; | ||
1174 | } | ||
1175 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) | ||
1176 | { | ||
1177 | return 0x1U; | ||
1178 | } | ||
1179 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) | ||
1180 | { | ||
1181 | return 0x00000001U; | ||
1182 | } | ||
1183 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) | ||
1184 | { | ||
1185 | return 0x1U; | ||
1186 | } | ||
1187 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) | ||
1188 | { | ||
1189 | return 0x1U << 1U; | ||
1190 | } | ||
1191 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) | ||
1192 | { | ||
1193 | return 0x00000001U; | ||
1194 | } | ||
1195 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) | ||
1196 | { | ||
1197 | return 0x2U; | ||
1198 | } | ||
1199 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) | ||
1200 | { | ||
1201 | return 0x00000001U; | ||
1202 | } | ||
1203 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) | ||
1204 | { | ||
1205 | return 0x2U; | ||
1206 | } | ||
1207 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) | ||
1208 | { | ||
1209 | return 0x1U << 2U; | ||
1210 | } | ||
1211 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) | ||
1212 | { | ||
1213 | return 0x00000001U; | ||
1214 | } | ||
1215 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) | ||
1216 | { | ||
1217 | return 0x4U; | ||
1218 | } | ||
1219 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) | ||
1220 | { | ||
1221 | return 0x00000001U; | ||
1222 | } | ||
1223 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) | ||
1224 | { | ||
1225 | return 0x4U; | ||
1226 | } | ||
1227 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) | ||
1228 | { | ||
1229 | return 0x1U << 3U; | ||
1230 | } | ||
1231 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) | ||
1232 | { | ||
1233 | return 0x00000001U; | ||
1234 | } | ||
1235 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) | ||
1236 | { | ||
1237 | return 0x8U; | ||
1238 | } | ||
1239 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) | ||
1240 | { | ||
1241 | return 0x00000001U; | ||
1242 | } | ||
1243 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) | ||
1244 | { | ||
1245 | return 0x8U; | ||
1246 | } | ||
1247 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) | ||
1248 | { | ||
1249 | return 0x1U << 4U; | ||
1250 | } | ||
1251 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) | ||
1252 | { | ||
1253 | return 0x00000001U; | ||
1254 | } | ||
1255 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) | ||
1256 | { | ||
1257 | return 0x10U; | ||
1258 | } | ||
1259 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) | ||
1260 | { | ||
1261 | return 0x00000001U; | ||
1262 | } | ||
1263 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) | ||
1264 | { | ||
1265 | return 0x10U; | ||
1266 | } | ||
1267 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) | ||
1268 | { | ||
1269 | return 0x1U << 5U; | ||
1270 | } | ||
1271 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) | ||
1272 | { | ||
1273 | return 0x00000001U; | ||
1274 | } | ||
1275 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) | ||
1276 | { | ||
1277 | return 0x20U; | ||
1278 | } | ||
1279 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) | ||
1280 | { | ||
1281 | return 0x00000001U; | ||
1282 | } | ||
1283 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) | ||
1284 | { | ||
1285 | return 0x20U; | ||
1286 | } | ||
1287 | static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) | ||
1288 | { | ||
1289 | return 0x1U << 6U; | ||
1290 | } | ||
1291 | static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) | ||
1292 | { | ||
1293 | return 0x00000001U; | ||
1294 | } | ||
1295 | static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) | ||
1296 | { | ||
1297 | return 0x40U; | ||
1298 | } | ||
1299 | static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) | ||
1300 | { | ||
1301 | return 0x00000001U; | ||
1302 | } | ||
1303 | static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) | ||
1304 | { | ||
1305 | return 0x40U; | ||
1306 | } | ||
1307 | static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) | ||
1308 | { | ||
1309 | return 0x1U << 7U; | ||
1310 | } | ||
1311 | static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) | ||
1312 | { | ||
1313 | return 0x00000001U; | ||
1314 | } | ||
1315 | static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) | ||
1316 | { | ||
1317 | return 0x80U; | ||
1318 | } | ||
1319 | static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) | ||
1320 | { | ||
1321 | return 0x00000001U; | ||
1322 | } | ||
1323 | static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) | ||
1324 | { | ||
1325 | return 0x80U; | ||
1326 | } | ||
1327 | static inline u32 fb_mmu_fault_status_replayable_m(void) | ||
1328 | { | ||
1329 | return 0x1U << 8U; | ||
1330 | } | ||
1331 | static inline u32 fb_mmu_fault_status_replayable_set_v(void) | ||
1332 | { | ||
1333 | return 0x00000001U; | ||
1334 | } | ||
1335 | static inline u32 fb_mmu_fault_status_replayable_set_f(void) | ||
1336 | { | ||
1337 | return 0x100U; | ||
1338 | } | ||
1339 | static inline u32 fb_mmu_fault_status_replayable_reset_f(void) | ||
1340 | { | ||
1341 | return 0x0U; | ||
1342 | } | ||
1343 | static inline u32 fb_mmu_fault_status_non_replayable_m(void) | ||
1344 | { | ||
1345 | return 0x1U << 9U; | ||
1346 | } | ||
1347 | static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) | ||
1348 | { | ||
1349 | return 0x00000001U; | ||
1350 | } | ||
1351 | static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) | ||
1352 | { | ||
1353 | return 0x200U; | ||
1354 | } | ||
1355 | static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) | ||
1356 | { | ||
1357 | return 0x0U; | ||
1358 | } | ||
1359 | static inline u32 fb_mmu_fault_status_replayable_error_m(void) | ||
1360 | { | ||
1361 | return 0x1U << 10U; | ||
1362 | } | ||
1363 | static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) | ||
1364 | { | ||
1365 | return 0x00000001U; | ||
1366 | } | ||
1367 | static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) | ||
1368 | { | ||
1369 | return 0x400U; | ||
1370 | } | ||
1371 | static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) | ||
1372 | { | ||
1373 | return 0x0U; | ||
1374 | } | ||
1375 | static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) | ||
1376 | { | ||
1377 | return 0x1U << 11U; | ||
1378 | } | ||
1379 | static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) | ||
1380 | { | ||
1381 | return 0x00000001U; | ||
1382 | } | ||
1383 | static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) | ||
1384 | { | ||
1385 | return 0x800U; | ||
1386 | } | ||
1387 | static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) | ||
1388 | { | ||
1389 | return 0x0U; | ||
1390 | } | ||
1391 | static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) | ||
1392 | { | ||
1393 | return 0x1U << 12U; | ||
1394 | } | ||
1395 | static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) | ||
1396 | { | ||
1397 | return 0x00000001U; | ||
1398 | } | ||
1399 | static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) | ||
1400 | { | ||
1401 | return 0x1000U; | ||
1402 | } | ||
1403 | static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) | ||
1404 | { | ||
1405 | return 0x0U; | ||
1406 | } | ||
1407 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) | ||
1408 | { | ||
1409 | return 0x1U << 13U; | ||
1410 | } | ||
1411 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) | ||
1412 | { | ||
1413 | return 0x00000001U; | ||
1414 | } | ||
1415 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) | ||
1416 | { | ||
1417 | return 0x2000U; | ||
1418 | } | ||
1419 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) | ||
1420 | { | ||
1421 | return 0x0U; | ||
1422 | } | ||
1423 | static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) | ||
1424 | { | ||
1425 | return 0x1U << 14U; | ||
1426 | } | ||
1427 | static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) | ||
1428 | { | ||
1429 | return 0x00000001U; | ||
1430 | } | ||
1431 | static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) | ||
1432 | { | ||
1433 | return 0x4000U; | ||
1434 | } | ||
1435 | static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) | ||
1436 | { | ||
1437 | return 0x1U << 15U; | ||
1438 | } | ||
1439 | static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) | ||
1440 | { | ||
1441 | return 0x00000001U; | ||
1442 | } | ||
1443 | static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) | ||
1444 | { | ||
1445 | return 0x8000U; | ||
1446 | } | ||
1447 | static inline u32 fb_mmu_fault_status_busy_m(void) | ||
1448 | { | ||
1449 | return 0x1U << 30U; | ||
1450 | } | ||
1451 | static inline u32 fb_mmu_fault_status_busy_true_v(void) | ||
1452 | { | ||
1453 | return 0x00000001U; | ||
1454 | } | ||
1455 | static inline u32 fb_mmu_fault_status_busy_true_f(void) | ||
1456 | { | ||
1457 | return 0x40000000U; | ||
1458 | } | ||
1459 | static inline u32 fb_mmu_fault_status_valid_m(void) | ||
1460 | { | ||
1461 | return 0x1U << 31U; | ||
1462 | } | ||
1463 | static inline u32 fb_mmu_fault_status_valid_set_v(void) | ||
1464 | { | ||
1465 | return 0x00000001U; | ||
1466 | } | ||
1467 | static inline u32 fb_mmu_fault_status_valid_set_f(void) | ||
1468 | { | ||
1469 | return 0x80000000U; | ||
1470 | } | ||
1471 | static inline u32 fb_mmu_fault_status_valid_clear_v(void) | ||
1472 | { | ||
1473 | return 0x00000001U; | ||
1474 | } | ||
1475 | static inline u32 fb_mmu_fault_status_valid_clear_f(void) | ||
1476 | { | ||
1477 | return 0x80000000U; | ||
1478 | } | ||
1479 | static inline u32 fb_mmu_local_memory_range_r(void) | ||
1480 | { | ||
1481 | return 0x00100ce0U; | ||
1482 | } | ||
1483 | static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) | ||
1484 | { | ||
1485 | return (r >> 0U) & 0xfU; | ||
1486 | } | ||
1487 | static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) | ||
1488 | { | ||
1489 | return (r >> 4U) & 0x3fU; | ||
1490 | } | ||
1491 | static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) | ||
1492 | { | ||
1493 | return (r >> 30U) & 0x1U; | ||
1494 | } | ||
1495 | static inline u32 fb_niso_scrub_status_r(void) | ||
1496 | { | ||
1497 | return 0x00100b20U; | ||
1498 | } | ||
1499 | static inline u32 fb_niso_scrub_status_flag_v(u32 r) | ||
1500 | { | ||
1501 | return (r >> 0U) & 0x1U; | ||
1502 | } | ||
1503 | static inline u32 fb_mmu_priv_level_mask_r(void) | ||
1504 | { | ||
1505 | return 0x00100cdcU; | ||
1506 | } | ||
1507 | static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) | ||
1508 | { | ||
1509 | return 0x1U << 7U; | ||
1510 | } | ||
1511 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h new file mode 100644 index 00000000..743afb1e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h | |||
@@ -0,0 +1,551 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_fifo_gv100_h_ | ||
57 | #define _hw_fifo_gv100_h_ | ||
58 | |||
59 | static inline u32 fifo_bar1_base_r(void) | ||
60 | { | ||
61 | return 0x00002254U; | ||
62 | } | ||
63 | static inline u32 fifo_bar1_base_ptr_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xfffffffU) << 0U; | ||
66 | } | ||
67 | static inline u32 fifo_bar1_base_ptr_align_shift_v(void) | ||
68 | { | ||
69 | return 0x0000000cU; | ||
70 | } | ||
71 | static inline u32 fifo_bar1_base_valid_false_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 fifo_bar1_base_valid_true_f(void) | ||
76 | { | ||
77 | return 0x10000000U; | ||
78 | } | ||
79 | static inline u32 fifo_userd_writeback_r(void) | ||
80 | { | ||
81 | return 0x0000225cU; | ||
82 | } | ||
83 | static inline u32 fifo_userd_writeback_timer_f(u32 v) | ||
84 | { | ||
85 | return (v & 0xffU) << 0U; | ||
86 | } | ||
87 | static inline u32 fifo_userd_writeback_timer_disabled_v(void) | ||
88 | { | ||
89 | return 0x00000000U; | ||
90 | } | ||
91 | static inline u32 fifo_userd_writeback_timer_shorter_v(void) | ||
92 | { | ||
93 | return 0x00000003U; | ||
94 | } | ||
95 | static inline u32 fifo_userd_writeback_timer_100us_v(void) | ||
96 | { | ||
97 | return 0x00000064U; | ||
98 | } | ||
99 | static inline u32 fifo_userd_writeback_timescale_f(u32 v) | ||
100 | { | ||
101 | return (v & 0xfU) << 12U; | ||
102 | } | ||
103 | static inline u32 fifo_userd_writeback_timescale_0_v(void) | ||
104 | { | ||
105 | return 0x00000000U; | ||
106 | } | ||
107 | static inline u32 fifo_runlist_base_r(void) | ||
108 | { | ||
109 | return 0x00002270U; | ||
110 | } | ||
111 | static inline u32 fifo_runlist_base_ptr_f(u32 v) | ||
112 | { | ||
113 | return (v & 0xfffffffU) << 0U; | ||
114 | } | ||
115 | static inline u32 fifo_runlist_base_target_vid_mem_f(void) | ||
116 | { | ||
117 | return 0x0U; | ||
118 | } | ||
119 | static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) | ||
120 | { | ||
121 | return 0x20000000U; | ||
122 | } | ||
123 | static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) | ||
124 | { | ||
125 | return 0x30000000U; | ||
126 | } | ||
127 | static inline u32 fifo_runlist_r(void) | ||
128 | { | ||
129 | return 0x00002274U; | ||
130 | } | ||
131 | static inline u32 fifo_runlist_engine_f(u32 v) | ||
132 | { | ||
133 | return (v & 0xfU) << 20U; | ||
134 | } | ||
135 | static inline u32 fifo_eng_runlist_base_r(u32 i) | ||
136 | { | ||
137 | return 0x00002280U + i*8U; | ||
138 | } | ||
139 | static inline u32 fifo_eng_runlist_base__size_1_v(void) | ||
140 | { | ||
141 | return 0x0000000dU; | ||
142 | } | ||
143 | static inline u32 fifo_eng_runlist_r(u32 i) | ||
144 | { | ||
145 | return 0x00002284U + i*8U; | ||
146 | } | ||
147 | static inline u32 fifo_eng_runlist__size_1_v(void) | ||
148 | { | ||
149 | return 0x0000000dU; | ||
150 | } | ||
151 | static inline u32 fifo_eng_runlist_length_f(u32 v) | ||
152 | { | ||
153 | return (v & 0xffffU) << 0U; | ||
154 | } | ||
155 | static inline u32 fifo_eng_runlist_length_max_v(void) | ||
156 | { | ||
157 | return 0x0000ffffU; | ||
158 | } | ||
159 | static inline u32 fifo_eng_runlist_pending_true_f(void) | ||
160 | { | ||
161 | return 0x100000U; | ||
162 | } | ||
163 | static inline u32 fifo_pb_timeslice_r(u32 i) | ||
164 | { | ||
165 | return 0x00002350U + i*4U; | ||
166 | } | ||
167 | static inline u32 fifo_pb_timeslice_timeout_16_f(void) | ||
168 | { | ||
169 | return 0x10U; | ||
170 | } | ||
171 | static inline u32 fifo_pb_timeslice_timescale_0_f(void) | ||
172 | { | ||
173 | return 0x0U; | ||
174 | } | ||
175 | static inline u32 fifo_pb_timeslice_enable_true_f(void) | ||
176 | { | ||
177 | return 0x10000000U; | ||
178 | } | ||
179 | static inline u32 fifo_pbdma_map_r(u32 i) | ||
180 | { | ||
181 | return 0x00002390U + i*4U; | ||
182 | } | ||
183 | static inline u32 fifo_intr_0_r(void) | ||
184 | { | ||
185 | return 0x00002100U; | ||
186 | } | ||
187 | static inline u32 fifo_intr_0_bind_error_pending_f(void) | ||
188 | { | ||
189 | return 0x1U; | ||
190 | } | ||
191 | static inline u32 fifo_intr_0_bind_error_reset_f(void) | ||
192 | { | ||
193 | return 0x1U; | ||
194 | } | ||
195 | static inline u32 fifo_intr_0_sched_error_pending_f(void) | ||
196 | { | ||
197 | return 0x100U; | ||
198 | } | ||
199 | static inline u32 fifo_intr_0_sched_error_reset_f(void) | ||
200 | { | ||
201 | return 0x100U; | ||
202 | } | ||
203 | static inline u32 fifo_intr_0_chsw_error_pending_f(void) | ||
204 | { | ||
205 | return 0x10000U; | ||
206 | } | ||
207 | static inline u32 fifo_intr_0_chsw_error_reset_f(void) | ||
208 | { | ||
209 | return 0x10000U; | ||
210 | } | ||
211 | static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) | ||
212 | { | ||
213 | return 0x800000U; | ||
214 | } | ||
215 | static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) | ||
216 | { | ||
217 | return 0x800000U; | ||
218 | } | ||
219 | static inline u32 fifo_intr_0_lb_error_pending_f(void) | ||
220 | { | ||
221 | return 0x1000000U; | ||
222 | } | ||
223 | static inline u32 fifo_intr_0_lb_error_reset_f(void) | ||
224 | { | ||
225 | return 0x1000000U; | ||
226 | } | ||
227 | static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) | ||
228 | { | ||
229 | return 0x20000000U; | ||
230 | } | ||
231 | static inline u32 fifo_intr_0_runlist_event_pending_f(void) | ||
232 | { | ||
233 | return 0x40000000U; | ||
234 | } | ||
235 | static inline u32 fifo_intr_0_channel_intr_pending_f(void) | ||
236 | { | ||
237 | return 0x80000000U; | ||
238 | } | ||
239 | static inline u32 fifo_intr_en_0_r(void) | ||
240 | { | ||
241 | return 0x00002140U; | ||
242 | } | ||
243 | static inline u32 fifo_intr_en_0_sched_error_f(u32 v) | ||
244 | { | ||
245 | return (v & 0x1U) << 8U; | ||
246 | } | ||
247 | static inline u32 fifo_intr_en_0_sched_error_m(void) | ||
248 | { | ||
249 | return 0x1U << 8U; | ||
250 | } | ||
251 | static inline u32 fifo_intr_en_1_r(void) | ||
252 | { | ||
253 | return 0x00002528U; | ||
254 | } | ||
255 | static inline u32 fifo_intr_bind_error_r(void) | ||
256 | { | ||
257 | return 0x0000252cU; | ||
258 | } | ||
259 | static inline u32 fifo_intr_sched_error_r(void) | ||
260 | { | ||
261 | return 0x0000254cU; | ||
262 | } | ||
263 | static inline u32 fifo_intr_sched_error_code_f(u32 v) | ||
264 | { | ||
265 | return (v & 0xffU) << 0U; | ||
266 | } | ||
267 | static inline u32 fifo_intr_chsw_error_r(void) | ||
268 | { | ||
269 | return 0x0000256cU; | ||
270 | } | ||
271 | static inline u32 fifo_intr_pbdma_id_r(void) | ||
272 | { | ||
273 | return 0x000025a0U; | ||
274 | } | ||
275 | static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) | ||
276 | { | ||
277 | return (v & 0x1U) << (0U + i*1U); | ||
278 | } | ||
279 | static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) | ||
280 | { | ||
281 | return (r >> (0U + i*1U)) & 0x1U; | ||
282 | } | ||
283 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) | ||
284 | { | ||
285 | return 0x0000000eU; | ||
286 | } | ||
287 | static inline u32 fifo_intr_runlist_r(void) | ||
288 | { | ||
289 | return 0x00002a00U; | ||
290 | } | ||
291 | static inline u32 fifo_fb_timeout_r(void) | ||
292 | { | ||
293 | return 0x00002a04U; | ||
294 | } | ||
295 | static inline u32 fifo_fb_timeout_period_m(void) | ||
296 | { | ||
297 | return 0x3fffffffU << 0U; | ||
298 | } | ||
299 | static inline u32 fifo_fb_timeout_period_max_f(void) | ||
300 | { | ||
301 | return 0x3fffffffU; | ||
302 | } | ||
303 | static inline u32 fifo_fb_timeout_period_init_f(void) | ||
304 | { | ||
305 | return 0x3c00U; | ||
306 | } | ||
307 | static inline u32 fifo_sched_disable_r(void) | ||
308 | { | ||
309 | return 0x00002630U; | ||
310 | } | ||
311 | static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) | ||
312 | { | ||
313 | return (v & 0x1U) << (0U + i*1U); | ||
314 | } | ||
315 | static inline u32 fifo_sched_disable_runlist_m(u32 i) | ||
316 | { | ||
317 | return 0x1U << (0U + i*1U); | ||
318 | } | ||
319 | static inline u32 fifo_sched_disable_true_v(void) | ||
320 | { | ||
321 | return 0x00000001U; | ||
322 | } | ||
323 | static inline u32 fifo_runlist_preempt_r(void) | ||
324 | { | ||
325 | return 0x00002638U; | ||
326 | } | ||
327 | static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) | ||
328 | { | ||
329 | return (v & 0x1U) << (0U + i*1U); | ||
330 | } | ||
331 | static inline u32 fifo_runlist_preempt_runlist_m(u32 i) | ||
332 | { | ||
333 | return 0x1U << (0U + i*1U); | ||
334 | } | ||
335 | static inline u32 fifo_runlist_preempt_runlist_pending_v(void) | ||
336 | { | ||
337 | return 0x00000001U; | ||
338 | } | ||
339 | static inline u32 fifo_preempt_r(void) | ||
340 | { | ||
341 | return 0x00002634U; | ||
342 | } | ||
343 | static inline u32 fifo_preempt_pending_true_f(void) | ||
344 | { | ||
345 | return 0x100000U; | ||
346 | } | ||
347 | static inline u32 fifo_preempt_type_channel_f(void) | ||
348 | { | ||
349 | return 0x0U; | ||
350 | } | ||
351 | static inline u32 fifo_preempt_type_tsg_f(void) | ||
352 | { | ||
353 | return 0x1000000U; | ||
354 | } | ||
355 | static inline u32 fifo_preempt_chid_f(u32 v) | ||
356 | { | ||
357 | return (v & 0xfffU) << 0U; | ||
358 | } | ||
359 | static inline u32 fifo_preempt_id_f(u32 v) | ||
360 | { | ||
361 | return (v & 0xfffU) << 0U; | ||
362 | } | ||
363 | static inline u32 fifo_engine_status_r(u32 i) | ||
364 | { | ||
365 | return 0x00002640U + i*8U; | ||
366 | } | ||
367 | static inline u32 fifo_engine_status__size_1_v(void) | ||
368 | { | ||
369 | return 0x0000000fU; | ||
370 | } | ||
371 | static inline u32 fifo_engine_status_id_v(u32 r) | ||
372 | { | ||
373 | return (r >> 0U) & 0xfffU; | ||
374 | } | ||
375 | static inline u32 fifo_engine_status_id_type_v(u32 r) | ||
376 | { | ||
377 | return (r >> 12U) & 0x1U; | ||
378 | } | ||
379 | static inline u32 fifo_engine_status_id_type_chid_v(void) | ||
380 | { | ||
381 | return 0x00000000U; | ||
382 | } | ||
383 | static inline u32 fifo_engine_status_id_type_tsgid_v(void) | ||
384 | { | ||
385 | return 0x00000001U; | ||
386 | } | ||
387 | static inline u32 fifo_engine_status_ctx_status_v(u32 r) | ||
388 | { | ||
389 | return (r >> 13U) & 0x7U; | ||
390 | } | ||
391 | static inline u32 fifo_engine_status_ctx_status_valid_v(void) | ||
392 | { | ||
393 | return 0x00000001U; | ||
394 | } | ||
395 | static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) | ||
396 | { | ||
397 | return 0x00000005U; | ||
398 | } | ||
399 | static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) | ||
400 | { | ||
401 | return 0x00000006U; | ||
402 | } | ||
403 | static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) | ||
404 | { | ||
405 | return 0x00000007U; | ||
406 | } | ||
407 | static inline u32 fifo_engine_status_next_id_v(u32 r) | ||
408 | { | ||
409 | return (r >> 16U) & 0xfffU; | ||
410 | } | ||
411 | static inline u32 fifo_engine_status_next_id_type_v(u32 r) | ||
412 | { | ||
413 | return (r >> 28U) & 0x1U; | ||
414 | } | ||
415 | static inline u32 fifo_engine_status_next_id_type_chid_v(void) | ||
416 | { | ||
417 | return 0x00000000U; | ||
418 | } | ||
419 | static inline u32 fifo_engine_status_eng_reload_v(u32 r) | ||
420 | { | ||
421 | return (r >> 29U) & 0x1U; | ||
422 | } | ||
423 | static inline u32 fifo_engine_status_faulted_v(u32 r) | ||
424 | { | ||
425 | return (r >> 30U) & 0x1U; | ||
426 | } | ||
427 | static inline u32 fifo_engine_status_faulted_true_v(void) | ||
428 | { | ||
429 | return 0x00000001U; | ||
430 | } | ||
431 | static inline u32 fifo_engine_status_engine_v(u32 r) | ||
432 | { | ||
433 | return (r >> 31U) & 0x1U; | ||
434 | } | ||
435 | static inline u32 fifo_engine_status_engine_idle_v(void) | ||
436 | { | ||
437 | return 0x00000000U; | ||
438 | } | ||
439 | static inline u32 fifo_engine_status_engine_busy_v(void) | ||
440 | { | ||
441 | return 0x00000001U; | ||
442 | } | ||
443 | static inline u32 fifo_engine_status_ctxsw_v(u32 r) | ||
444 | { | ||
445 | return (r >> 15U) & 0x1U; | ||
446 | } | ||
447 | static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) | ||
448 | { | ||
449 | return 0x00000001U; | ||
450 | } | ||
451 | static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) | ||
452 | { | ||
453 | return 0x8000U; | ||
454 | } | ||
455 | static inline u32 fifo_pbdma_status_r(u32 i) | ||
456 | { | ||
457 | return 0x00003080U + i*4U; | ||
458 | } | ||
459 | static inline u32 fifo_pbdma_status__size_1_v(void) | ||
460 | { | ||
461 | return 0x0000000eU; | ||
462 | } | ||
463 | static inline u32 fifo_pbdma_status_id_v(u32 r) | ||
464 | { | ||
465 | return (r >> 0U) & 0xfffU; | ||
466 | } | ||
467 | static inline u32 fifo_pbdma_status_id_type_v(u32 r) | ||
468 | { | ||
469 | return (r >> 12U) & 0x1U; | ||
470 | } | ||
471 | static inline u32 fifo_pbdma_status_id_type_chid_v(void) | ||
472 | { | ||
473 | return 0x00000000U; | ||
474 | } | ||
475 | static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) | ||
476 | { | ||
477 | return 0x00000001U; | ||
478 | } | ||
479 | static inline u32 fifo_pbdma_status_chan_status_v(u32 r) | ||
480 | { | ||
481 | return (r >> 13U) & 0x7U; | ||
482 | } | ||
483 | static inline u32 fifo_pbdma_status_chan_status_valid_v(void) | ||
484 | { | ||
485 | return 0x00000001U; | ||
486 | } | ||
487 | static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) | ||
488 | { | ||
489 | return 0x00000005U; | ||
490 | } | ||
491 | static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) | ||
492 | { | ||
493 | return 0x00000006U; | ||
494 | } | ||
495 | static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) | ||
496 | { | ||
497 | return 0x00000007U; | ||
498 | } | ||
499 | static inline u32 fifo_pbdma_status_next_id_v(u32 r) | ||
500 | { | ||
501 | return (r >> 16U) & 0xfffU; | ||
502 | } | ||
503 | static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) | ||
504 | { | ||
505 | return (r >> 28U) & 0x1U; | ||
506 | } | ||
507 | static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) | ||
508 | { | ||
509 | return 0x00000000U; | ||
510 | } | ||
511 | static inline u32 fifo_pbdma_status_chsw_v(u32 r) | ||
512 | { | ||
513 | return (r >> 15U) & 0x1U; | ||
514 | } | ||
515 | static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) | ||
516 | { | ||
517 | return 0x00000001U; | ||
518 | } | ||
519 | static inline u32 fifo_cfg0_r(void) | ||
520 | { | ||
521 | return 0x00002004U; | ||
522 | } | ||
523 | static inline u32 fifo_cfg0_num_pbdma_v(u32 r) | ||
524 | { | ||
525 | return (r >> 0U) & 0xffU; | ||
526 | } | ||
527 | static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) | ||
528 | { | ||
529 | return (r >> 16U) & 0xffU; | ||
530 | } | ||
531 | static inline u32 fifo_fb_iface_r(void) | ||
532 | { | ||
533 | return 0x000026f0U; | ||
534 | } | ||
535 | static inline u32 fifo_fb_iface_control_v(u32 r) | ||
536 | { | ||
537 | return (r >> 0U) & 0x1U; | ||
538 | } | ||
539 | static inline u32 fifo_fb_iface_control_enable_f(void) | ||
540 | { | ||
541 | return 0x1U; | ||
542 | } | ||
543 | static inline u32 fifo_fb_iface_status_v(u32 r) | ||
544 | { | ||
545 | return (r >> 4U) & 0x1U; | ||
546 | } | ||
547 | static inline u32 fifo_fb_iface_status_enabled_f(void) | ||
548 | { | ||
549 | return 0x10U; | ||
550 | } | ||
551 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h new file mode 100644 index 00000000..b6045626 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h | |||
@@ -0,0 +1,187 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_flush_gv100_h_ | ||
57 | #define _hw_flush_gv100_h_ | ||
58 | |||
59 | static inline u32 flush_l2_system_invalidate_r(void) | ||
60 | { | ||
61 | return 0x00070004U; | ||
62 | } | ||
63 | static inline u32 flush_l2_system_invalidate_pending_v(u32 r) | ||
64 | { | ||
65 | return (r >> 0U) & 0x1U; | ||
66 | } | ||
67 | static inline u32 flush_l2_system_invalidate_pending_busy_v(void) | ||
68 | { | ||
69 | return 0x00000001U; | ||
70 | } | ||
71 | static inline u32 flush_l2_system_invalidate_pending_busy_f(void) | ||
72 | { | ||
73 | return 0x1U; | ||
74 | } | ||
75 | static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) | ||
76 | { | ||
77 | return (r >> 1U) & 0x1U; | ||
78 | } | ||
79 | static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) | ||
80 | { | ||
81 | return 0x00000001U; | ||
82 | } | ||
83 | static inline u32 flush_l2_flush_dirty_r(void) | ||
84 | { | ||
85 | return 0x00070010U; | ||
86 | } | ||
87 | static inline u32 flush_l2_flush_dirty_pending_v(u32 r) | ||
88 | { | ||
89 | return (r >> 0U) & 0x1U; | ||
90 | } | ||
91 | static inline u32 flush_l2_flush_dirty_pending_empty_v(void) | ||
92 | { | ||
93 | return 0x00000000U; | ||
94 | } | ||
95 | static inline u32 flush_l2_flush_dirty_pending_empty_f(void) | ||
96 | { | ||
97 | return 0x0U; | ||
98 | } | ||
99 | static inline u32 flush_l2_flush_dirty_pending_busy_v(void) | ||
100 | { | ||
101 | return 0x00000001U; | ||
102 | } | ||
103 | static inline u32 flush_l2_flush_dirty_pending_busy_f(void) | ||
104 | { | ||
105 | return 0x1U; | ||
106 | } | ||
107 | static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) | ||
108 | { | ||
109 | return (r >> 1U) & 0x1U; | ||
110 | } | ||
111 | static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) | ||
112 | { | ||
113 | return 0x00000000U; | ||
114 | } | ||
115 | static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) | ||
116 | { | ||
117 | return 0x0U; | ||
118 | } | ||
119 | static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) | ||
120 | { | ||
121 | return 0x00000001U; | ||
122 | } | ||
123 | static inline u32 flush_l2_clean_comptags_r(void) | ||
124 | { | ||
125 | return 0x0007000cU; | ||
126 | } | ||
127 | static inline u32 flush_l2_clean_comptags_pending_v(u32 r) | ||
128 | { | ||
129 | return (r >> 0U) & 0x1U; | ||
130 | } | ||
131 | static inline u32 flush_l2_clean_comptags_pending_empty_v(void) | ||
132 | { | ||
133 | return 0x00000000U; | ||
134 | } | ||
135 | static inline u32 flush_l2_clean_comptags_pending_empty_f(void) | ||
136 | { | ||
137 | return 0x0U; | ||
138 | } | ||
139 | static inline u32 flush_l2_clean_comptags_pending_busy_v(void) | ||
140 | { | ||
141 | return 0x00000001U; | ||
142 | } | ||
143 | static inline u32 flush_l2_clean_comptags_pending_busy_f(void) | ||
144 | { | ||
145 | return 0x1U; | ||
146 | } | ||
147 | static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) | ||
148 | { | ||
149 | return (r >> 1U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) | ||
152 | { | ||
153 | return 0x00000000U; | ||
154 | } | ||
155 | static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) | ||
156 | { | ||
157 | return 0x0U; | ||
158 | } | ||
159 | static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) | ||
160 | { | ||
161 | return 0x00000001U; | ||
162 | } | ||
163 | static inline u32 flush_fb_flush_r(void) | ||
164 | { | ||
165 | return 0x00070000U; | ||
166 | } | ||
167 | static inline u32 flush_fb_flush_pending_v(u32 r) | ||
168 | { | ||
169 | return (r >> 0U) & 0x1U; | ||
170 | } | ||
171 | static inline u32 flush_fb_flush_pending_busy_v(void) | ||
172 | { | ||
173 | return 0x00000001U; | ||
174 | } | ||
175 | static inline u32 flush_fb_flush_pending_busy_f(void) | ||
176 | { | ||
177 | return 0x1U; | ||
178 | } | ||
179 | static inline u32 flush_fb_flush_outstanding_v(u32 r) | ||
180 | { | ||
181 | return (r >> 1U) & 0x1U; | ||
182 | } | ||
183 | static inline u32 flush_fb_flush_outstanding_true_v(void) | ||
184 | { | ||
185 | return 0x00000001U; | ||
186 | } | ||
187 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h new file mode 100644 index 00000000..f7eacd29 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | |||
@@ -0,0 +1,143 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_fuse_gv100_h_ | ||
57 | #define _hw_fuse_gv100_h_ | ||
58 | |||
59 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) | ||
60 | { | ||
61 | return 0x00021c38U + i*4U; | ||
62 | } | ||
63 | static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) | ||
64 | { | ||
65 | return 0x00021838U + i*4U; | ||
66 | } | ||
67 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) | ||
68 | { | ||
69 | return 0x00021944U; | ||
70 | } | ||
71 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) | ||
72 | { | ||
73 | return (v & 0xffU) << 0U; | ||
74 | } | ||
75 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) | ||
76 | { | ||
77 | return 0xffU << 0U; | ||
78 | } | ||
79 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) | ||
80 | { | ||
81 | return (r >> 0U) & 0xffU; | ||
82 | } | ||
83 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) | ||
84 | { | ||
85 | return 0x00021948U; | ||
86 | } | ||
87 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) | ||
88 | { | ||
89 | return (v & 0x1U) << 0U; | ||
90 | } | ||
91 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) | ||
92 | { | ||
93 | return 0x1U << 0U; | ||
94 | } | ||
95 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) | ||
96 | { | ||
97 | return (r >> 0U) & 0x1U; | ||
98 | } | ||
99 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) | ||
100 | { | ||
101 | return 0x1U; | ||
102 | } | ||
103 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) | ||
104 | { | ||
105 | return 0x0U; | ||
106 | } | ||
107 | static inline u32 fuse_status_opt_fbio_r(void) | ||
108 | { | ||
109 | return 0x00021c14U; | ||
110 | } | ||
111 | static inline u32 fuse_status_opt_fbio_data_f(u32 v) | ||
112 | { | ||
113 | return (v & 0xffffU) << 0U; | ||
114 | } | ||
115 | static inline u32 fuse_status_opt_fbio_data_m(void) | ||
116 | { | ||
117 | return 0xffffU << 0U; | ||
118 | } | ||
119 | static inline u32 fuse_status_opt_fbio_data_v(u32 r) | ||
120 | { | ||
121 | return (r >> 0U) & 0xffffU; | ||
122 | } | ||
123 | static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) | ||
124 | { | ||
125 | return 0x00021d70U + i*4U; | ||
126 | } | ||
127 | static inline u32 fuse_status_opt_fbp_r(void) | ||
128 | { | ||
129 | return 0x00021d38U; | ||
130 | } | ||
131 | static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) | ||
132 | { | ||
133 | return (r >> (0U + i*1U)) & 0x1U; | ||
134 | } | ||
135 | static inline u32 fuse_opt_ecc_en_r(void) | ||
136 | { | ||
137 | return 0x00021228U; | ||
138 | } | ||
139 | static inline u32 fuse_opt_feature_fuses_override_disable_r(void) | ||
140 | { | ||
141 | return 0x000213f0U; | ||
142 | } | ||
143 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h new file mode 100644 index 00000000..cf89f5f8 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h | |||
@@ -0,0 +1,1287 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_gmmu_gv100_h_ | ||
57 | #define _hw_gmmu_gv100_h_ | ||
58 | |||
59 | static inline u32 gmmu_new_pde_is_pte_w(void) | ||
60 | { | ||
61 | return 0U; | ||
62 | } | ||
63 | static inline u32 gmmu_new_pde_is_pte_false_f(void) | ||
64 | { | ||
65 | return 0x0U; | ||
66 | } | ||
67 | static inline u32 gmmu_new_pde_aperture_w(void) | ||
68 | { | ||
69 | return 0U; | ||
70 | } | ||
71 | static inline u32 gmmu_new_pde_aperture_invalid_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 gmmu_new_pde_aperture_video_memory_f(void) | ||
76 | { | ||
77 | return 0x2U; | ||
78 | } | ||
79 | static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) | ||
80 | { | ||
81 | return 0x4U; | ||
82 | } | ||
83 | static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) | ||
84 | { | ||
85 | return 0x6U; | ||
86 | } | ||
87 | static inline u32 gmmu_new_pde_address_sys_f(u32 v) | ||
88 | { | ||
89 | return (v & 0xffffffU) << 8U; | ||
90 | } | ||
91 | static inline u32 gmmu_new_pde_address_sys_w(void) | ||
92 | { | ||
93 | return 0U; | ||
94 | } | ||
95 | static inline u32 gmmu_new_pde_vol_w(void) | ||
96 | { | ||
97 | return 0U; | ||
98 | } | ||
99 | static inline u32 gmmu_new_pde_vol_true_f(void) | ||
100 | { | ||
101 | return 0x8U; | ||
102 | } | ||
103 | static inline u32 gmmu_new_pde_vol_false_f(void) | ||
104 | { | ||
105 | return 0x0U; | ||
106 | } | ||
107 | static inline u32 gmmu_new_pde_address_shift_v(void) | ||
108 | { | ||
109 | return 0x0000000cU; | ||
110 | } | ||
111 | static inline u32 gmmu_new_pde__size_v(void) | ||
112 | { | ||
113 | return 0x00000008U; | ||
114 | } | ||
115 | static inline u32 gmmu_new_dual_pde_is_pte_w(void) | ||
116 | { | ||
117 | return 0U; | ||
118 | } | ||
119 | static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) | ||
120 | { | ||
121 | return 0x0U; | ||
122 | } | ||
123 | static inline u32 gmmu_new_dual_pde_aperture_big_w(void) | ||
124 | { | ||
125 | return 0U; | ||
126 | } | ||
127 | static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) | ||
128 | { | ||
129 | return 0x0U; | ||
130 | } | ||
131 | static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) | ||
132 | { | ||
133 | return 0x2U; | ||
134 | } | ||
135 | static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) | ||
136 | { | ||
137 | return 0x4U; | ||
138 | } | ||
139 | static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) | ||
140 | { | ||
141 | return 0x6U; | ||
142 | } | ||
143 | static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) | ||
144 | { | ||
145 | return (v & 0xfffffffU) << 4U; | ||
146 | } | ||
147 | static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) | ||
148 | { | ||
149 | return 0U; | ||
150 | } | ||
151 | static inline u32 gmmu_new_dual_pde_aperture_small_w(void) | ||
152 | { | ||
153 | return 2U; | ||
154 | } | ||
155 | static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) | ||
156 | { | ||
157 | return 0x0U; | ||
158 | } | ||
159 | static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) | ||
160 | { | ||
161 | return 0x2U; | ||
162 | } | ||
163 | static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) | ||
164 | { | ||
165 | return 0x4U; | ||
166 | } | ||
167 | static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) | ||
168 | { | ||
169 | return 0x6U; | ||
170 | } | ||
171 | static inline u32 gmmu_new_dual_pde_vol_small_w(void) | ||
172 | { | ||
173 | return 2U; | ||
174 | } | ||
175 | static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) | ||
176 | { | ||
177 | return 0x8U; | ||
178 | } | ||
179 | static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) | ||
180 | { | ||
181 | return 0x0U; | ||
182 | } | ||
183 | static inline u32 gmmu_new_dual_pde_vol_big_w(void) | ||
184 | { | ||
185 | return 0U; | ||
186 | } | ||
187 | static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) | ||
188 | { | ||
189 | return 0x8U; | ||
190 | } | ||
191 | static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) | ||
192 | { | ||
193 | return 0x0U; | ||
194 | } | ||
195 | static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) | ||
196 | { | ||
197 | return (v & 0xffffffU) << 8U; | ||
198 | } | ||
199 | static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) | ||
200 | { | ||
201 | return 2U; | ||
202 | } | ||
203 | static inline u32 gmmu_new_dual_pde_address_shift_v(void) | ||
204 | { | ||
205 | return 0x0000000cU; | ||
206 | } | ||
207 | static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) | ||
208 | { | ||
209 | return 0x00000008U; | ||
210 | } | ||
211 | static inline u32 gmmu_new_dual_pde__size_v(void) | ||
212 | { | ||
213 | return 0x00000010U; | ||
214 | } | ||
215 | static inline u32 gmmu_new_pte__size_v(void) | ||
216 | { | ||
217 | return 0x00000008U; | ||
218 | } | ||
219 | static inline u32 gmmu_new_pte_valid_w(void) | ||
220 | { | ||
221 | return 0U; | ||
222 | } | ||
223 | static inline u32 gmmu_new_pte_valid_true_f(void) | ||
224 | { | ||
225 | return 0x1U; | ||
226 | } | ||
227 | static inline u32 gmmu_new_pte_valid_false_f(void) | ||
228 | { | ||
229 | return 0x0U; | ||
230 | } | ||
231 | static inline u32 gmmu_new_pte_privilege_w(void) | ||
232 | { | ||
233 | return 0U; | ||
234 | } | ||
235 | static inline u32 gmmu_new_pte_privilege_true_f(void) | ||
236 | { | ||
237 | return 0x20U; | ||
238 | } | ||
239 | static inline u32 gmmu_new_pte_privilege_false_f(void) | ||
240 | { | ||
241 | return 0x0U; | ||
242 | } | ||
243 | static inline u32 gmmu_new_pte_address_sys_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xffffffU) << 8U; | ||
246 | } | ||
247 | static inline u32 gmmu_new_pte_address_sys_w(void) | ||
248 | { | ||
249 | return 0U; | ||
250 | } | ||
251 | static inline u32 gmmu_new_pte_address_vid_f(u32 v) | ||
252 | { | ||
253 | return (v & 0xffffffU) << 8U; | ||
254 | } | ||
255 | static inline u32 gmmu_new_pte_address_vid_w(void) | ||
256 | { | ||
257 | return 0U; | ||
258 | } | ||
259 | static inline u32 gmmu_new_pte_vol_w(void) | ||
260 | { | ||
261 | return 0U; | ||
262 | } | ||
263 | static inline u32 gmmu_new_pte_vol_true_f(void) | ||
264 | { | ||
265 | return 0x8U; | ||
266 | } | ||
267 | static inline u32 gmmu_new_pte_vol_false_f(void) | ||
268 | { | ||
269 | return 0x0U; | ||
270 | } | ||
271 | static inline u32 gmmu_new_pte_aperture_w(void) | ||
272 | { | ||
273 | return 0U; | ||
274 | } | ||
275 | static inline u32 gmmu_new_pte_aperture_video_memory_f(void) | ||
276 | { | ||
277 | return 0x0U; | ||
278 | } | ||
279 | static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) | ||
280 | { | ||
281 | return 0x4U; | ||
282 | } | ||
283 | static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) | ||
284 | { | ||
285 | return 0x6U; | ||
286 | } | ||
287 | static inline u32 gmmu_new_pte_read_only_w(void) | ||
288 | { | ||
289 | return 0U; | ||
290 | } | ||
291 | static inline u32 gmmu_new_pte_read_only_true_f(void) | ||
292 | { | ||
293 | return 0x40U; | ||
294 | } | ||
295 | static inline u32 gmmu_new_pte_comptagline_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x3ffffU) << 4U; | ||
298 | } | ||
299 | static inline u32 gmmu_new_pte_comptagline_w(void) | ||
300 | { | ||
301 | return 1U; | ||
302 | } | ||
303 | static inline u32 gmmu_new_pte_kind_f(u32 v) | ||
304 | { | ||
305 | return (v & 0xffU) << 24U; | ||
306 | } | ||
307 | static inline u32 gmmu_new_pte_kind_w(void) | ||
308 | { | ||
309 | return 1U; | ||
310 | } | ||
311 | static inline u32 gmmu_new_pte_address_shift_v(void) | ||
312 | { | ||
313 | return 0x0000000cU; | ||
314 | } | ||
315 | static inline u32 gmmu_pte_kind_f(u32 v) | ||
316 | { | ||
317 | return (v & 0xffU) << 4U; | ||
318 | } | ||
319 | static inline u32 gmmu_pte_kind_w(void) | ||
320 | { | ||
321 | return 1U; | ||
322 | } | ||
323 | static inline u32 gmmu_pte_kind_invalid_v(void) | ||
324 | { | ||
325 | return 0x000000ffU; | ||
326 | } | ||
327 | static inline u32 gmmu_pte_kind_pitch_v(void) | ||
328 | { | ||
329 | return 0x00000000U; | ||
330 | } | ||
331 | static inline u32 gmmu_pte_kind_z16_v(void) | ||
332 | { | ||
333 | return 0x00000001U; | ||
334 | } | ||
335 | static inline u32 gmmu_pte_kind_z16_2c_v(void) | ||
336 | { | ||
337 | return 0x00000002U; | ||
338 | } | ||
339 | static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) | ||
340 | { | ||
341 | return 0x00000003U; | ||
342 | } | ||
343 | static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) | ||
344 | { | ||
345 | return 0x00000004U; | ||
346 | } | ||
347 | static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) | ||
348 | { | ||
349 | return 0x00000005U; | ||
350 | } | ||
351 | static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) | ||
352 | { | ||
353 | return 0x00000006U; | ||
354 | } | ||
355 | static inline u32 gmmu_pte_kind_z16_2z_v(void) | ||
356 | { | ||
357 | return 0x00000007U; | ||
358 | } | ||
359 | static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) | ||
360 | { | ||
361 | return 0x00000008U; | ||
362 | } | ||
363 | static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) | ||
364 | { | ||
365 | return 0x00000009U; | ||
366 | } | ||
367 | static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) | ||
368 | { | ||
369 | return 0x0000000aU; | ||
370 | } | ||
371 | static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) | ||
372 | { | ||
373 | return 0x0000000bU; | ||
374 | } | ||
375 | static inline u32 gmmu_pte_kind_z16_2cz_v(void) | ||
376 | { | ||
377 | return 0x00000036U; | ||
378 | } | ||
379 | static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) | ||
380 | { | ||
381 | return 0x00000037U; | ||
382 | } | ||
383 | static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) | ||
384 | { | ||
385 | return 0x00000038U; | ||
386 | } | ||
387 | static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) | ||
388 | { | ||
389 | return 0x00000039U; | ||
390 | } | ||
391 | static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) | ||
392 | { | ||
393 | return 0x0000005fU; | ||
394 | } | ||
395 | static inline u32 gmmu_pte_kind_s8z24_v(void) | ||
396 | { | ||
397 | return 0x00000011U; | ||
398 | } | ||
399 | static inline u32 gmmu_pte_kind_s8z24_1z_v(void) | ||
400 | { | ||
401 | return 0x00000012U; | ||
402 | } | ||
403 | static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) | ||
404 | { | ||
405 | return 0x00000013U; | ||
406 | } | ||
407 | static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) | ||
408 | { | ||
409 | return 0x00000014U; | ||
410 | } | ||
411 | static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) | ||
412 | { | ||
413 | return 0x00000015U; | ||
414 | } | ||
415 | static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) | ||
416 | { | ||
417 | return 0x00000016U; | ||
418 | } | ||
419 | static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) | ||
420 | { | ||
421 | return 0x00000017U; | ||
422 | } | ||
423 | static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) | ||
424 | { | ||
425 | return 0x00000018U; | ||
426 | } | ||
427 | static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) | ||
428 | { | ||
429 | return 0x00000019U; | ||
430 | } | ||
431 | static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) | ||
432 | { | ||
433 | return 0x0000001aU; | ||
434 | } | ||
435 | static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) | ||
436 | { | ||
437 | return 0x0000001bU; | ||
438 | } | ||
439 | static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) | ||
440 | { | ||
441 | return 0x0000001cU; | ||
442 | } | ||
443 | static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) | ||
444 | { | ||
445 | return 0x0000001dU; | ||
446 | } | ||
447 | static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) | ||
448 | { | ||
449 | return 0x0000001eU; | ||
450 | } | ||
451 | static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) | ||
452 | { | ||
453 | return 0x0000001fU; | ||
454 | } | ||
455 | static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) | ||
456 | { | ||
457 | return 0x00000020U; | ||
458 | } | ||
459 | static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) | ||
460 | { | ||
461 | return 0x00000021U; | ||
462 | } | ||
463 | static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) | ||
464 | { | ||
465 | return 0x00000022U; | ||
466 | } | ||
467 | static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) | ||
468 | { | ||
469 | return 0x00000023U; | ||
470 | } | ||
471 | static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) | ||
472 | { | ||
473 | return 0x00000024U; | ||
474 | } | ||
475 | static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) | ||
476 | { | ||
477 | return 0x00000025U; | ||
478 | } | ||
479 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) | ||
480 | { | ||
481 | return 0x00000026U; | ||
482 | } | ||
483 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) | ||
484 | { | ||
485 | return 0x00000027U; | ||
486 | } | ||
487 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) | ||
488 | { | ||
489 | return 0x00000028U; | ||
490 | } | ||
491 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) | ||
492 | { | ||
493 | return 0x00000029U; | ||
494 | } | ||
495 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) | ||
496 | { | ||
497 | return 0x0000002eU; | ||
498 | } | ||
499 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) | ||
500 | { | ||
501 | return 0x0000002fU; | ||
502 | } | ||
503 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) | ||
504 | { | ||
505 | return 0x00000030U; | ||
506 | } | ||
507 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) | ||
508 | { | ||
509 | return 0x00000031U; | ||
510 | } | ||
511 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) | ||
512 | { | ||
513 | return 0x00000032U; | ||
514 | } | ||
515 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) | ||
516 | { | ||
517 | return 0x00000033U; | ||
518 | } | ||
519 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) | ||
520 | { | ||
521 | return 0x00000034U; | ||
522 | } | ||
523 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) | ||
524 | { | ||
525 | return 0x00000035U; | ||
526 | } | ||
527 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) | ||
528 | { | ||
529 | return 0x0000003aU; | ||
530 | } | ||
531 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) | ||
532 | { | ||
533 | return 0x0000003bU; | ||
534 | } | ||
535 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) | ||
536 | { | ||
537 | return 0x0000003cU; | ||
538 | } | ||
539 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) | ||
540 | { | ||
541 | return 0x0000003dU; | ||
542 | } | ||
543 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) | ||
544 | { | ||
545 | return 0x0000003eU; | ||
546 | } | ||
547 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) | ||
548 | { | ||
549 | return 0x0000003fU; | ||
550 | } | ||
551 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) | ||
552 | { | ||
553 | return 0x00000040U; | ||
554 | } | ||
555 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) | ||
556 | { | ||
557 | return 0x00000041U; | ||
558 | } | ||
559 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) | ||
560 | { | ||
561 | return 0x00000042U; | ||
562 | } | ||
563 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) | ||
564 | { | ||
565 | return 0x00000043U; | ||
566 | } | ||
567 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) | ||
568 | { | ||
569 | return 0x00000044U; | ||
570 | } | ||
571 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) | ||
572 | { | ||
573 | return 0x00000045U; | ||
574 | } | ||
575 | static inline u32 gmmu_pte_kind_z24s8_v(void) | ||
576 | { | ||
577 | return 0x00000046U; | ||
578 | } | ||
579 | static inline u32 gmmu_pte_kind_z24s8_1z_v(void) | ||
580 | { | ||
581 | return 0x00000047U; | ||
582 | } | ||
583 | static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) | ||
584 | { | ||
585 | return 0x00000048U; | ||
586 | } | ||
587 | static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) | ||
588 | { | ||
589 | return 0x00000049U; | ||
590 | } | ||
591 | static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) | ||
592 | { | ||
593 | return 0x0000004aU; | ||
594 | } | ||
595 | static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) | ||
596 | { | ||
597 | return 0x0000004bU; | ||
598 | } | ||
599 | static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) | ||
600 | { | ||
601 | return 0x0000004cU; | ||
602 | } | ||
603 | static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) | ||
604 | { | ||
605 | return 0x0000004dU; | ||
606 | } | ||
607 | static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) | ||
608 | { | ||
609 | return 0x0000004eU; | ||
610 | } | ||
611 | static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) | ||
612 | { | ||
613 | return 0x0000004fU; | ||
614 | } | ||
615 | static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) | ||
616 | { | ||
617 | return 0x00000050U; | ||
618 | } | ||
619 | static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) | ||
620 | { | ||
621 | return 0x00000051U; | ||
622 | } | ||
623 | static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) | ||
624 | { | ||
625 | return 0x00000052U; | ||
626 | } | ||
627 | static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) | ||
628 | { | ||
629 | return 0x00000053U; | ||
630 | } | ||
631 | static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) | ||
632 | { | ||
633 | return 0x00000054U; | ||
634 | } | ||
635 | static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) | ||
636 | { | ||
637 | return 0x00000055U; | ||
638 | } | ||
639 | static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) | ||
640 | { | ||
641 | return 0x00000056U; | ||
642 | } | ||
643 | static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) | ||
644 | { | ||
645 | return 0x00000057U; | ||
646 | } | ||
647 | static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) | ||
648 | { | ||
649 | return 0x00000058U; | ||
650 | } | ||
651 | static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) | ||
652 | { | ||
653 | return 0x00000059U; | ||
654 | } | ||
655 | static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) | ||
656 | { | ||
657 | return 0x0000005aU; | ||
658 | } | ||
659 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) | ||
660 | { | ||
661 | return 0x0000005bU; | ||
662 | } | ||
663 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) | ||
664 | { | ||
665 | return 0x0000005cU; | ||
666 | } | ||
667 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) | ||
668 | { | ||
669 | return 0x0000005dU; | ||
670 | } | ||
671 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) | ||
672 | { | ||
673 | return 0x0000005eU; | ||
674 | } | ||
675 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) | ||
676 | { | ||
677 | return 0x00000063U; | ||
678 | } | ||
679 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) | ||
680 | { | ||
681 | return 0x00000064U; | ||
682 | } | ||
683 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) | ||
684 | { | ||
685 | return 0x00000065U; | ||
686 | } | ||
687 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) | ||
688 | { | ||
689 | return 0x00000066U; | ||
690 | } | ||
691 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) | ||
692 | { | ||
693 | return 0x00000067U; | ||
694 | } | ||
695 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) | ||
696 | { | ||
697 | return 0x00000068U; | ||
698 | } | ||
699 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) | ||
700 | { | ||
701 | return 0x00000069U; | ||
702 | } | ||
703 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) | ||
704 | { | ||
705 | return 0x0000006aU; | ||
706 | } | ||
707 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) | ||
708 | { | ||
709 | return 0x0000006fU; | ||
710 | } | ||
711 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) | ||
712 | { | ||
713 | return 0x00000070U; | ||
714 | } | ||
715 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) | ||
716 | { | ||
717 | return 0x00000071U; | ||
718 | } | ||
719 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) | ||
720 | { | ||
721 | return 0x00000072U; | ||
722 | } | ||
723 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) | ||
724 | { | ||
725 | return 0x00000073U; | ||
726 | } | ||
727 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) | ||
728 | { | ||
729 | return 0x00000074U; | ||
730 | } | ||
731 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) | ||
732 | { | ||
733 | return 0x00000075U; | ||
734 | } | ||
735 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) | ||
736 | { | ||
737 | return 0x00000076U; | ||
738 | } | ||
739 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) | ||
740 | { | ||
741 | return 0x00000077U; | ||
742 | } | ||
743 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) | ||
744 | { | ||
745 | return 0x00000078U; | ||
746 | } | ||
747 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) | ||
748 | { | ||
749 | return 0x00000079U; | ||
750 | } | ||
751 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) | ||
752 | { | ||
753 | return 0x0000007aU; | ||
754 | } | ||
755 | static inline u32 gmmu_pte_kind_zf32_v(void) | ||
756 | { | ||
757 | return 0x0000007bU; | ||
758 | } | ||
759 | static inline u32 gmmu_pte_kind_zf32_1z_v(void) | ||
760 | { | ||
761 | return 0x0000007cU; | ||
762 | } | ||
763 | static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) | ||
764 | { | ||
765 | return 0x0000007dU; | ||
766 | } | ||
767 | static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) | ||
768 | { | ||
769 | return 0x0000007eU; | ||
770 | } | ||
771 | static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) | ||
772 | { | ||
773 | return 0x0000007fU; | ||
774 | } | ||
775 | static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) | ||
776 | { | ||
777 | return 0x00000080U; | ||
778 | } | ||
779 | static inline u32 gmmu_pte_kind_zf32_2cs_v(void) | ||
780 | { | ||
781 | return 0x00000081U; | ||
782 | } | ||
783 | static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) | ||
784 | { | ||
785 | return 0x00000082U; | ||
786 | } | ||
787 | static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) | ||
788 | { | ||
789 | return 0x00000083U; | ||
790 | } | ||
791 | static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) | ||
792 | { | ||
793 | return 0x00000084U; | ||
794 | } | ||
795 | static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) | ||
796 | { | ||
797 | return 0x00000085U; | ||
798 | } | ||
799 | static inline u32 gmmu_pte_kind_zf32_2cz_v(void) | ||
800 | { | ||
801 | return 0x00000086U; | ||
802 | } | ||
803 | static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) | ||
804 | { | ||
805 | return 0x00000087U; | ||
806 | } | ||
807 | static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) | ||
808 | { | ||
809 | return 0x00000088U; | ||
810 | } | ||
811 | static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) | ||
812 | { | ||
813 | return 0x00000089U; | ||
814 | } | ||
815 | static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) | ||
816 | { | ||
817 | return 0x0000008aU; | ||
818 | } | ||
819 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) | ||
820 | { | ||
821 | return 0x0000008bU; | ||
822 | } | ||
823 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) | ||
824 | { | ||
825 | return 0x0000008cU; | ||
826 | } | ||
827 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) | ||
828 | { | ||
829 | return 0x0000008dU; | ||
830 | } | ||
831 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) | ||
832 | { | ||
833 | return 0x0000008eU; | ||
834 | } | ||
835 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) | ||
836 | { | ||
837 | return 0x0000008fU; | ||
838 | } | ||
839 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) | ||
840 | { | ||
841 | return 0x00000090U; | ||
842 | } | ||
843 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) | ||
844 | { | ||
845 | return 0x00000091U; | ||
846 | } | ||
847 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) | ||
848 | { | ||
849 | return 0x00000092U; | ||
850 | } | ||
851 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) | ||
852 | { | ||
853 | return 0x00000097U; | ||
854 | } | ||
855 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) | ||
856 | { | ||
857 | return 0x00000098U; | ||
858 | } | ||
859 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) | ||
860 | { | ||
861 | return 0x00000099U; | ||
862 | } | ||
863 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) | ||
864 | { | ||
865 | return 0x0000009aU; | ||
866 | } | ||
867 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) | ||
868 | { | ||
869 | return 0x0000009bU; | ||
870 | } | ||
871 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) | ||
872 | { | ||
873 | return 0x0000009cU; | ||
874 | } | ||
875 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) | ||
876 | { | ||
877 | return 0x0000009dU; | ||
878 | } | ||
879 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) | ||
880 | { | ||
881 | return 0x0000009eU; | ||
882 | } | ||
883 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) | ||
884 | { | ||
885 | return 0x0000009fU; | ||
886 | } | ||
887 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) | ||
888 | { | ||
889 | return 0x000000a0U; | ||
890 | } | ||
891 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) | ||
892 | { | ||
893 | return 0x000000a1U; | ||
894 | } | ||
895 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) | ||
896 | { | ||
897 | return 0x000000a2U; | ||
898 | } | ||
899 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) | ||
900 | { | ||
901 | return 0x000000a3U; | ||
902 | } | ||
903 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) | ||
904 | { | ||
905 | return 0x000000a4U; | ||
906 | } | ||
907 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) | ||
908 | { | ||
909 | return 0x000000a5U; | ||
910 | } | ||
911 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) | ||
912 | { | ||
913 | return 0x000000a6U; | ||
914 | } | ||
915 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) | ||
916 | { | ||
917 | return 0x000000a7U; | ||
918 | } | ||
919 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) | ||
920 | { | ||
921 | return 0x000000a8U; | ||
922 | } | ||
923 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) | ||
924 | { | ||
925 | return 0x000000a9U; | ||
926 | } | ||
927 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) | ||
928 | { | ||
929 | return 0x000000aaU; | ||
930 | } | ||
931 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) | ||
932 | { | ||
933 | return 0x000000abU; | ||
934 | } | ||
935 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) | ||
936 | { | ||
937 | return 0x000000acU; | ||
938 | } | ||
939 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) | ||
940 | { | ||
941 | return 0x000000adU; | ||
942 | } | ||
943 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) | ||
944 | { | ||
945 | return 0x000000aeU; | ||
946 | } | ||
947 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) | ||
948 | { | ||
949 | return 0x000000b3U; | ||
950 | } | ||
951 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) | ||
952 | { | ||
953 | return 0x000000b4U; | ||
954 | } | ||
955 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) | ||
956 | { | ||
957 | return 0x000000b5U; | ||
958 | } | ||
959 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) | ||
960 | { | ||
961 | return 0x000000b6U; | ||
962 | } | ||
963 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) | ||
964 | { | ||
965 | return 0x000000b7U; | ||
966 | } | ||
967 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) | ||
968 | { | ||
969 | return 0x000000b8U; | ||
970 | } | ||
971 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) | ||
972 | { | ||
973 | return 0x000000b9U; | ||
974 | } | ||
975 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) | ||
976 | { | ||
977 | return 0x000000baU; | ||
978 | } | ||
979 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) | ||
980 | { | ||
981 | return 0x000000bbU; | ||
982 | } | ||
983 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) | ||
984 | { | ||
985 | return 0x000000bcU; | ||
986 | } | ||
987 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) | ||
988 | { | ||
989 | return 0x000000bdU; | ||
990 | } | ||
991 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) | ||
992 | { | ||
993 | return 0x000000beU; | ||
994 | } | ||
995 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) | ||
996 | { | ||
997 | return 0x000000bfU; | ||
998 | } | ||
999 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) | ||
1000 | { | ||
1001 | return 0x000000c0U; | ||
1002 | } | ||
1003 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) | ||
1004 | { | ||
1005 | return 0x000000c1U; | ||
1006 | } | ||
1007 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) | ||
1008 | { | ||
1009 | return 0x000000c2U; | ||
1010 | } | ||
1011 | static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) | ||
1012 | { | ||
1013 | return 0x000000c3U; | ||
1014 | } | ||
1015 | static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) | ||
1016 | { | ||
1017 | return 0x000000c4U; | ||
1018 | } | ||
1019 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) | ||
1020 | { | ||
1021 | return 0x000000c5U; | ||
1022 | } | ||
1023 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) | ||
1024 | { | ||
1025 | return 0x000000c6U; | ||
1026 | } | ||
1027 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) | ||
1028 | { | ||
1029 | return 0x000000c7U; | ||
1030 | } | ||
1031 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) | ||
1032 | { | ||
1033 | return 0x000000c8U; | ||
1034 | } | ||
1035 | static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) | ||
1036 | { | ||
1037 | return 0x000000ceU; | ||
1038 | } | ||
1039 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) | ||
1040 | { | ||
1041 | return 0x000000cfU; | ||
1042 | } | ||
1043 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) | ||
1044 | { | ||
1045 | return 0x000000d0U; | ||
1046 | } | ||
1047 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) | ||
1048 | { | ||
1049 | return 0x000000d1U; | ||
1050 | } | ||
1051 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) | ||
1052 | { | ||
1053 | return 0x000000d2U; | ||
1054 | } | ||
1055 | static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) | ||
1056 | { | ||
1057 | return 0x000000d3U; | ||
1058 | } | ||
1059 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) | ||
1060 | { | ||
1061 | return 0x000000d4U; | ||
1062 | } | ||
1063 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) | ||
1064 | { | ||
1065 | return 0x000000d5U; | ||
1066 | } | ||
1067 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) | ||
1068 | { | ||
1069 | return 0x000000d6U; | ||
1070 | } | ||
1071 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) | ||
1072 | { | ||
1073 | return 0x000000d7U; | ||
1074 | } | ||
1075 | static inline u32 gmmu_pte_kind_generic_16bx2_v(void) | ||
1076 | { | ||
1077 | return 0x000000feU; | ||
1078 | } | ||
1079 | static inline u32 gmmu_pte_kind_c32_2c_v(void) | ||
1080 | { | ||
1081 | return 0x000000d8U; | ||
1082 | } | ||
1083 | static inline u32 gmmu_pte_kind_c32_2cbr_v(void) | ||
1084 | { | ||
1085 | return 0x000000d9U; | ||
1086 | } | ||
1087 | static inline u32 gmmu_pte_kind_c32_2cba_v(void) | ||
1088 | { | ||
1089 | return 0x000000daU; | ||
1090 | } | ||
1091 | static inline u32 gmmu_pte_kind_c32_2cra_v(void) | ||
1092 | { | ||
1093 | return 0x000000dbU; | ||
1094 | } | ||
1095 | static inline u32 gmmu_pte_kind_c32_2bra_v(void) | ||
1096 | { | ||
1097 | return 0x000000dcU; | ||
1098 | } | ||
1099 | static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) | ||
1100 | { | ||
1101 | return 0x000000ddU; | ||
1102 | } | ||
1103 | static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) | ||
1104 | { | ||
1105 | return 0x000000deU; | ||
1106 | } | ||
1107 | static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) | ||
1108 | { | ||
1109 | return 0x000000ccU; | ||
1110 | } | ||
1111 | static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) | ||
1112 | { | ||
1113 | return 0x000000dfU; | ||
1114 | } | ||
1115 | static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) | ||
1116 | { | ||
1117 | return 0x000000e0U; | ||
1118 | } | ||
1119 | static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) | ||
1120 | { | ||
1121 | return 0x000000e1U; | ||
1122 | } | ||
1123 | static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) | ||
1124 | { | ||
1125 | return 0x000000e2U; | ||
1126 | } | ||
1127 | static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) | ||
1128 | { | ||
1129 | return 0x000000e3U; | ||
1130 | } | ||
1131 | static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) | ||
1132 | { | ||
1133 | return 0x0000002cU; | ||
1134 | } | ||
1135 | static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) | ||
1136 | { | ||
1137 | return 0x000000e4U; | ||
1138 | } | ||
1139 | static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) | ||
1140 | { | ||
1141 | return 0x000000e5U; | ||
1142 | } | ||
1143 | static inline u32 gmmu_pte_kind_c64_2c_v(void) | ||
1144 | { | ||
1145 | return 0x000000e6U; | ||
1146 | } | ||
1147 | static inline u32 gmmu_pte_kind_c64_2cbr_v(void) | ||
1148 | { | ||
1149 | return 0x000000e7U; | ||
1150 | } | ||
1151 | static inline u32 gmmu_pte_kind_c64_2cba_v(void) | ||
1152 | { | ||
1153 | return 0x000000e8U; | ||
1154 | } | ||
1155 | static inline u32 gmmu_pte_kind_c64_2cra_v(void) | ||
1156 | { | ||
1157 | return 0x000000e9U; | ||
1158 | } | ||
1159 | static inline u32 gmmu_pte_kind_c64_2bra_v(void) | ||
1160 | { | ||
1161 | return 0x000000eaU; | ||
1162 | } | ||
1163 | static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) | ||
1164 | { | ||
1165 | return 0x000000ebU; | ||
1166 | } | ||
1167 | static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) | ||
1168 | { | ||
1169 | return 0x000000ecU; | ||
1170 | } | ||
1171 | static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) | ||
1172 | { | ||
1173 | return 0x000000cdU; | ||
1174 | } | ||
1175 | static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) | ||
1176 | { | ||
1177 | return 0x000000edU; | ||
1178 | } | ||
1179 | static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) | ||
1180 | { | ||
1181 | return 0x000000eeU; | ||
1182 | } | ||
1183 | static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) | ||
1184 | { | ||
1185 | return 0x000000efU; | ||
1186 | } | ||
1187 | static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) | ||
1188 | { | ||
1189 | return 0x000000f0U; | ||
1190 | } | ||
1191 | static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) | ||
1192 | { | ||
1193 | return 0x000000f1U; | ||
1194 | } | ||
1195 | static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) | ||
1196 | { | ||
1197 | return 0x0000002dU; | ||
1198 | } | ||
1199 | static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) | ||
1200 | { | ||
1201 | return 0x000000f2U; | ||
1202 | } | ||
1203 | static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) | ||
1204 | { | ||
1205 | return 0x000000f3U; | ||
1206 | } | ||
1207 | static inline u32 gmmu_pte_kind_c128_2c_v(void) | ||
1208 | { | ||
1209 | return 0x000000f4U; | ||
1210 | } | ||
1211 | static inline u32 gmmu_pte_kind_c128_2cr_v(void) | ||
1212 | { | ||
1213 | return 0x000000f5U; | ||
1214 | } | ||
1215 | static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) | ||
1216 | { | ||
1217 | return 0x000000f6U; | ||
1218 | } | ||
1219 | static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) | ||
1220 | { | ||
1221 | return 0x000000f7U; | ||
1222 | } | ||
1223 | static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) | ||
1224 | { | ||
1225 | return 0x000000f8U; | ||
1226 | } | ||
1227 | static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) | ||
1228 | { | ||
1229 | return 0x000000f9U; | ||
1230 | } | ||
1231 | static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) | ||
1232 | { | ||
1233 | return 0x000000faU; | ||
1234 | } | ||
1235 | static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) | ||
1236 | { | ||
1237 | return 0x000000fbU; | ||
1238 | } | ||
1239 | static inline u32 gmmu_pte_kind_x8c24_v(void) | ||
1240 | { | ||
1241 | return 0x000000fcU; | ||
1242 | } | ||
1243 | static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) | ||
1244 | { | ||
1245 | return 0x000000fdU; | ||
1246 | } | ||
1247 | static inline u32 gmmu_pte_kind_smsked_message_v(void) | ||
1248 | { | ||
1249 | return 0x000000caU; | ||
1250 | } | ||
1251 | static inline u32 gmmu_pte_kind_smhost_message_v(void) | ||
1252 | { | ||
1253 | return 0x000000cbU; | ||
1254 | } | ||
1255 | static inline u32 gmmu_pte_kind_s8_v(void) | ||
1256 | { | ||
1257 | return 0x0000002aU; | ||
1258 | } | ||
1259 | static inline u32 gmmu_pte_kind_s8_2s_v(void) | ||
1260 | { | ||
1261 | return 0x0000002bU; | ||
1262 | } | ||
1263 | static inline u32 gmmu_fault_client_type_gpc_v(void) | ||
1264 | { | ||
1265 | return 0x00000000U; | ||
1266 | } | ||
1267 | static inline u32 gmmu_fault_client_type_hub_v(void) | ||
1268 | { | ||
1269 | return 0x00000001U; | ||
1270 | } | ||
1271 | static inline u32 gmmu_fault_type_unbound_inst_block_v(void) | ||
1272 | { | ||
1273 | return 0x00000004U; | ||
1274 | } | ||
1275 | static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) | ||
1276 | { | ||
1277 | return 0x00000005U; | ||
1278 | } | ||
1279 | static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) | ||
1280 | { | ||
1281 | return 0x0000001fU; | ||
1282 | } | ||
1283 | static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) | ||
1284 | { | ||
1285 | return 0x0000000fU; | ||
1286 | } | ||
1287 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h new file mode 100644 index 00000000..09cbc793 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | |||
@@ -0,0 +1,3935 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_gr_gv100_h_ | ||
57 | #define _hw_gr_gv100_h_ | ||
58 | |||
59 | static inline u32 gr_intr_r(void) | ||
60 | { | ||
61 | return 0x00400100U; | ||
62 | } | ||
63 | static inline u32 gr_intr_notify_pending_f(void) | ||
64 | { | ||
65 | return 0x1U; | ||
66 | } | ||
67 | static inline u32 gr_intr_notify_reset_f(void) | ||
68 | { | ||
69 | return 0x1U; | ||
70 | } | ||
71 | static inline u32 gr_intr_semaphore_pending_f(void) | ||
72 | { | ||
73 | return 0x2U; | ||
74 | } | ||
75 | static inline u32 gr_intr_semaphore_reset_f(void) | ||
76 | { | ||
77 | return 0x2U; | ||
78 | } | ||
79 | static inline u32 gr_intr_illegal_method_pending_f(void) | ||
80 | { | ||
81 | return 0x10U; | ||
82 | } | ||
83 | static inline u32 gr_intr_illegal_method_reset_f(void) | ||
84 | { | ||
85 | return 0x10U; | ||
86 | } | ||
87 | static inline u32 gr_intr_illegal_notify_pending_f(void) | ||
88 | { | ||
89 | return 0x40U; | ||
90 | } | ||
91 | static inline u32 gr_intr_illegal_notify_reset_f(void) | ||
92 | { | ||
93 | return 0x40U; | ||
94 | } | ||
95 | static inline u32 gr_intr_firmware_method_f(u32 v) | ||
96 | { | ||
97 | return (v & 0x1U) << 8U; | ||
98 | } | ||
99 | static inline u32 gr_intr_firmware_method_pending_f(void) | ||
100 | { | ||
101 | return 0x100U; | ||
102 | } | ||
103 | static inline u32 gr_intr_firmware_method_reset_f(void) | ||
104 | { | ||
105 | return 0x100U; | ||
106 | } | ||
107 | static inline u32 gr_intr_illegal_class_pending_f(void) | ||
108 | { | ||
109 | return 0x20U; | ||
110 | } | ||
111 | static inline u32 gr_intr_illegal_class_reset_f(void) | ||
112 | { | ||
113 | return 0x20U; | ||
114 | } | ||
115 | static inline u32 gr_intr_fecs_error_pending_f(void) | ||
116 | { | ||
117 | return 0x80000U; | ||
118 | } | ||
119 | static inline u32 gr_intr_fecs_error_reset_f(void) | ||
120 | { | ||
121 | return 0x80000U; | ||
122 | } | ||
123 | static inline u32 gr_intr_class_error_pending_f(void) | ||
124 | { | ||
125 | return 0x100000U; | ||
126 | } | ||
127 | static inline u32 gr_intr_class_error_reset_f(void) | ||
128 | { | ||
129 | return 0x100000U; | ||
130 | } | ||
131 | static inline u32 gr_intr_exception_pending_f(void) | ||
132 | { | ||
133 | return 0x200000U; | ||
134 | } | ||
135 | static inline u32 gr_intr_exception_reset_f(void) | ||
136 | { | ||
137 | return 0x200000U; | ||
138 | } | ||
139 | static inline u32 gr_fecs_intr_r(void) | ||
140 | { | ||
141 | return 0x00400144U; | ||
142 | } | ||
143 | static inline u32 gr_class_error_r(void) | ||
144 | { | ||
145 | return 0x00400110U; | ||
146 | } | ||
147 | static inline u32 gr_class_error_code_v(u32 r) | ||
148 | { | ||
149 | return (r >> 0U) & 0xffffU; | ||
150 | } | ||
151 | static inline u32 gr_intr_nonstall_r(void) | ||
152 | { | ||
153 | return 0x00400120U; | ||
154 | } | ||
155 | static inline u32 gr_intr_nonstall_trap_pending_f(void) | ||
156 | { | ||
157 | return 0x2U; | ||
158 | } | ||
159 | static inline u32 gr_intr_en_r(void) | ||
160 | { | ||
161 | return 0x0040013cU; | ||
162 | } | ||
163 | static inline u32 gr_exception_r(void) | ||
164 | { | ||
165 | return 0x00400108U; | ||
166 | } | ||
167 | static inline u32 gr_exception_fe_m(void) | ||
168 | { | ||
169 | return 0x1U << 0U; | ||
170 | } | ||
171 | static inline u32 gr_exception_gpc_m(void) | ||
172 | { | ||
173 | return 0x1U << 24U; | ||
174 | } | ||
175 | static inline u32 gr_exception_memfmt_m(void) | ||
176 | { | ||
177 | return 0x1U << 1U; | ||
178 | } | ||
179 | static inline u32 gr_exception_ds_m(void) | ||
180 | { | ||
181 | return 0x1U << 4U; | ||
182 | } | ||
183 | static inline u32 gr_exception_sked_m(void) | ||
184 | { | ||
185 | return 0x1U << 8U; | ||
186 | } | ||
187 | static inline u32 gr_exception1_r(void) | ||
188 | { | ||
189 | return 0x00400118U; | ||
190 | } | ||
191 | static inline u32 gr_exception1_gpc_0_pending_f(void) | ||
192 | { | ||
193 | return 0x1U; | ||
194 | } | ||
195 | static inline u32 gr_exception2_r(void) | ||
196 | { | ||
197 | return 0x0040011cU; | ||
198 | } | ||
199 | static inline u32 gr_exception_en_r(void) | ||
200 | { | ||
201 | return 0x00400138U; | ||
202 | } | ||
203 | static inline u32 gr_exception_en_fe_m(void) | ||
204 | { | ||
205 | return 0x1U << 0U; | ||
206 | } | ||
207 | static inline u32 gr_exception_en_fe_enabled_f(void) | ||
208 | { | ||
209 | return 0x1U; | ||
210 | } | ||
211 | static inline u32 gr_exception_en_gpc_m(void) | ||
212 | { | ||
213 | return 0x1U << 24U; | ||
214 | } | ||
215 | static inline u32 gr_exception_en_gpc_enabled_f(void) | ||
216 | { | ||
217 | return 0x1000000U; | ||
218 | } | ||
219 | static inline u32 gr_exception_en_memfmt_m(void) | ||
220 | { | ||
221 | return 0x1U << 1U; | ||
222 | } | ||
223 | static inline u32 gr_exception_en_memfmt_enabled_f(void) | ||
224 | { | ||
225 | return 0x2U; | ||
226 | } | ||
227 | static inline u32 gr_exception_en_ds_m(void) | ||
228 | { | ||
229 | return 0x1U << 4U; | ||
230 | } | ||
231 | static inline u32 gr_exception_en_ds_enabled_f(void) | ||
232 | { | ||
233 | return 0x10U; | ||
234 | } | ||
235 | static inline u32 gr_exception1_en_r(void) | ||
236 | { | ||
237 | return 0x00400130U; | ||
238 | } | ||
239 | static inline u32 gr_exception2_en_r(void) | ||
240 | { | ||
241 | return 0x00400134U; | ||
242 | } | ||
243 | static inline u32 gr_gpfifo_ctl_r(void) | ||
244 | { | ||
245 | return 0x00400500U; | ||
246 | } | ||
247 | static inline u32 gr_gpfifo_ctl_access_f(u32 v) | ||
248 | { | ||
249 | return (v & 0x1U) << 0U; | ||
250 | } | ||
251 | static inline u32 gr_gpfifo_ctl_access_disabled_f(void) | ||
252 | { | ||
253 | return 0x0U; | ||
254 | } | ||
255 | static inline u32 gr_gpfifo_ctl_access_enabled_f(void) | ||
256 | { | ||
257 | return 0x1U; | ||
258 | } | ||
259 | static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) | ||
260 | { | ||
261 | return (v & 0x1U) << 16U; | ||
262 | } | ||
263 | static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) | ||
264 | { | ||
265 | return 0x00000001U; | ||
266 | } | ||
267 | static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) | ||
268 | { | ||
269 | return 0x10000U; | ||
270 | } | ||
271 | static inline u32 gr_gpfifo_status_r(void) | ||
272 | { | ||
273 | return 0x00400504U; | ||
274 | } | ||
275 | static inline u32 gr_trapped_addr_r(void) | ||
276 | { | ||
277 | return 0x00400704U; | ||
278 | } | ||
279 | static inline u32 gr_trapped_addr_mthd_v(u32 r) | ||
280 | { | ||
281 | return (r >> 2U) & 0xfffU; | ||
282 | } | ||
283 | static inline u32 gr_trapped_addr_subch_v(u32 r) | ||
284 | { | ||
285 | return (r >> 16U) & 0x7U; | ||
286 | } | ||
287 | static inline u32 gr_trapped_addr_mme_generated_v(u32 r) | ||
288 | { | ||
289 | return (r >> 20U) & 0x1U; | ||
290 | } | ||
291 | static inline u32 gr_trapped_addr_datahigh_v(u32 r) | ||
292 | { | ||
293 | return (r >> 24U) & 0x1U; | ||
294 | } | ||
295 | static inline u32 gr_trapped_addr_priv_v(u32 r) | ||
296 | { | ||
297 | return (r >> 28U) & 0x1U; | ||
298 | } | ||
299 | static inline u32 gr_trapped_addr_status_v(u32 r) | ||
300 | { | ||
301 | return (r >> 31U) & 0x1U; | ||
302 | } | ||
303 | static inline u32 gr_trapped_data_lo_r(void) | ||
304 | { | ||
305 | return 0x00400708U; | ||
306 | } | ||
307 | static inline u32 gr_trapped_data_hi_r(void) | ||
308 | { | ||
309 | return 0x0040070cU; | ||
310 | } | ||
311 | static inline u32 gr_trapped_data_mme_r(void) | ||
312 | { | ||
313 | return 0x00400710U; | ||
314 | } | ||
315 | static inline u32 gr_trapped_data_mme_pc_v(u32 r) | ||
316 | { | ||
317 | return (r >> 0U) & 0xfffU; | ||
318 | } | ||
319 | static inline u32 gr_status_r(void) | ||
320 | { | ||
321 | return 0x00400700U; | ||
322 | } | ||
323 | static inline u32 gr_status_fe_method_upper_v(u32 r) | ||
324 | { | ||
325 | return (r >> 1U) & 0x1U; | ||
326 | } | ||
327 | static inline u32 gr_status_fe_method_lower_v(u32 r) | ||
328 | { | ||
329 | return (r >> 2U) & 0x1U; | ||
330 | } | ||
331 | static inline u32 gr_status_fe_method_lower_idle_v(void) | ||
332 | { | ||
333 | return 0x00000000U; | ||
334 | } | ||
335 | static inline u32 gr_status_fe_gi_v(u32 r) | ||
336 | { | ||
337 | return (r >> 21U) & 0x1U; | ||
338 | } | ||
339 | static inline u32 gr_status_mask_r(void) | ||
340 | { | ||
341 | return 0x00400610U; | ||
342 | } | ||
343 | static inline u32 gr_status_1_r(void) | ||
344 | { | ||
345 | return 0x00400604U; | ||
346 | } | ||
347 | static inline u32 gr_status_2_r(void) | ||
348 | { | ||
349 | return 0x00400608U; | ||
350 | } | ||
351 | static inline u32 gr_engine_status_r(void) | ||
352 | { | ||
353 | return 0x0040060cU; | ||
354 | } | ||
355 | static inline u32 gr_engine_status_value_busy_f(void) | ||
356 | { | ||
357 | return 0x1U; | ||
358 | } | ||
359 | static inline u32 gr_pri_be0_becs_be_exception_r(void) | ||
360 | { | ||
361 | return 0x00410204U; | ||
362 | } | ||
363 | static inline u32 gr_pri_be0_becs_be_exception_en_r(void) | ||
364 | { | ||
365 | return 0x00410208U; | ||
366 | } | ||
367 | static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) | ||
368 | { | ||
369 | return 0x00502c90U; | ||
370 | } | ||
371 | static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) | ||
372 | { | ||
373 | return 0x00502c94U; | ||
374 | } | ||
375 | static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) | ||
376 | { | ||
377 | return 0x00504508U; | ||
378 | } | ||
379 | static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | ||
380 | { | ||
381 | return 0x0050450cU; | ||
382 | } | ||
383 | static inline u32 gr_activity_0_r(void) | ||
384 | { | ||
385 | return 0x00400380U; | ||
386 | } | ||
387 | static inline u32 gr_activity_1_r(void) | ||
388 | { | ||
389 | return 0x00400384U; | ||
390 | } | ||
391 | static inline u32 gr_activity_2_r(void) | ||
392 | { | ||
393 | return 0x00400388U; | ||
394 | } | ||
395 | static inline u32 gr_activity_4_r(void) | ||
396 | { | ||
397 | return 0x00400390U; | ||
398 | } | ||
399 | static inline u32 gr_activity_4_gpc0_s(void) | ||
400 | { | ||
401 | return 3U; | ||
402 | } | ||
403 | static inline u32 gr_activity_4_gpc0_f(u32 v) | ||
404 | { | ||
405 | return (v & 0x7U) << 0U; | ||
406 | } | ||
407 | static inline u32 gr_activity_4_gpc0_m(void) | ||
408 | { | ||
409 | return 0x7U << 0U; | ||
410 | } | ||
411 | static inline u32 gr_activity_4_gpc0_v(u32 r) | ||
412 | { | ||
413 | return (r >> 0U) & 0x7U; | ||
414 | } | ||
415 | static inline u32 gr_activity_4_gpc0_empty_v(void) | ||
416 | { | ||
417 | return 0x00000000U; | ||
418 | } | ||
419 | static inline u32 gr_activity_4_gpc0_preempted_v(void) | ||
420 | { | ||
421 | return 0x00000004U; | ||
422 | } | ||
423 | static inline u32 gr_pri_gpc0_gcc_dbg_r(void) | ||
424 | { | ||
425 | return 0x00501000U; | ||
426 | } | ||
427 | static inline u32 gr_pri_gpcs_gcc_dbg_r(void) | ||
428 | { | ||
429 | return 0x00419000U; | ||
430 | } | ||
431 | static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) | ||
432 | { | ||
433 | return 0x1U << 1U; | ||
434 | } | ||
435 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) | ||
436 | { | ||
437 | return 0x0050433cU; | ||
438 | } | ||
439 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) | ||
440 | { | ||
441 | return 0x00419b3cU; | ||
442 | } | ||
443 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) | ||
444 | { | ||
445 | return 0x1U << 0U; | ||
446 | } | ||
447 | static inline u32 gr_pri_sked_activity_r(void) | ||
448 | { | ||
449 | return 0x00407054U; | ||
450 | } | ||
451 | static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) | ||
452 | { | ||
453 | return 0x00502c80U; | ||
454 | } | ||
455 | static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) | ||
456 | { | ||
457 | return 0x00502c84U; | ||
458 | } | ||
459 | static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) | ||
460 | { | ||
461 | return 0x00502c88U; | ||
462 | } | ||
463 | static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) | ||
464 | { | ||
465 | return 0x00502c8cU; | ||
466 | } | ||
467 | static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) | ||
468 | { | ||
469 | return 0x00504500U; | ||
470 | } | ||
471 | static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) | ||
472 | { | ||
473 | return 0x00504d00U; | ||
474 | } | ||
475 | static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) | ||
476 | { | ||
477 | return 0x00501d00U; | ||
478 | } | ||
479 | static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) | ||
480 | { | ||
481 | return 0x0041ac80U; | ||
482 | } | ||
483 | static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) | ||
484 | { | ||
485 | return 0x0041ac84U; | ||
486 | } | ||
487 | static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) | ||
488 | { | ||
489 | return 0x0041ac88U; | ||
490 | } | ||
491 | static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) | ||
492 | { | ||
493 | return 0x0041ac8cU; | ||
494 | } | ||
495 | static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) | ||
496 | { | ||
497 | return 0x0041c500U; | ||
498 | } | ||
499 | static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) | ||
500 | { | ||
501 | return 0x0041cd00U; | ||
502 | } | ||
503 | static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) | ||
504 | { | ||
505 | return 0x00419d00U; | ||
506 | } | ||
507 | static inline u32 gr_pri_be0_becs_be_activity0_r(void) | ||
508 | { | ||
509 | return 0x00410200U; | ||
510 | } | ||
511 | static inline u32 gr_pri_be1_becs_be_activity0_r(void) | ||
512 | { | ||
513 | return 0x00410600U; | ||
514 | } | ||
515 | static inline u32 gr_pri_bes_becs_be_activity0_r(void) | ||
516 | { | ||
517 | return 0x00408a00U; | ||
518 | } | ||
519 | static inline u32 gr_pri_ds_mpipe_status_r(void) | ||
520 | { | ||
521 | return 0x00405858U; | ||
522 | } | ||
523 | static inline u32 gr_pri_fe_go_idle_info_r(void) | ||
524 | { | ||
525 | return 0x00404194U; | ||
526 | } | ||
527 | static inline u32 gr_pri_fe_chip_def_info_r(void) | ||
528 | { | ||
529 | return 0x00404030U; | ||
530 | } | ||
531 | static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) | ||
532 | { | ||
533 | return (r >> 0U) & 0xfffU; | ||
534 | } | ||
535 | static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) | ||
536 | { | ||
537 | return 0x00000040U; | ||
538 | } | ||
539 | static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) | ||
540 | { | ||
541 | return 0x00504238U; | ||
542 | } | ||
543 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) | ||
544 | { | ||
545 | return 0x00504358U; | ||
546 | } | ||
547 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) | ||
548 | { | ||
549 | return 0x1U << 0U; | ||
550 | } | ||
551 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) | ||
552 | { | ||
553 | return 0x1U << 1U; | ||
554 | } | ||
555 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) | ||
556 | { | ||
557 | return 0x1U << 2U; | ||
558 | } | ||
559 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) | ||
560 | { | ||
561 | return 0x1U << 3U; | ||
562 | } | ||
563 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) | ||
564 | { | ||
565 | return 0x1U << 4U; | ||
566 | } | ||
567 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) | ||
568 | { | ||
569 | return 0x1U << 5U; | ||
570 | } | ||
571 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) | ||
572 | { | ||
573 | return 0x1U << 6U; | ||
574 | } | ||
575 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) | ||
576 | { | ||
577 | return 0x1U << 7U; | ||
578 | } | ||
579 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) | ||
580 | { | ||
581 | return 0x1U << 8U; | ||
582 | } | ||
583 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) | ||
584 | { | ||
585 | return 0x1U << 9U; | ||
586 | } | ||
587 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) | ||
588 | { | ||
589 | return 0x1U << 10U; | ||
590 | } | ||
591 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) | ||
592 | { | ||
593 | return 0x1U << 11U; | ||
594 | } | ||
595 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) | ||
596 | { | ||
597 | return 0x1U << 12U; | ||
598 | } | ||
599 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) | ||
600 | { | ||
601 | return 0x1U << 13U; | ||
602 | } | ||
603 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) | ||
604 | { | ||
605 | return 0x1U << 14U; | ||
606 | } | ||
607 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) | ||
608 | { | ||
609 | return 0x1U << 15U; | ||
610 | } | ||
611 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
612 | { | ||
613 | return (r >> 24U) & 0x1U; | ||
614 | } | ||
615 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
616 | { | ||
617 | return (r >> 26U) & 0x1U; | ||
618 | } | ||
619 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) | ||
620 | { | ||
621 | return 0x40000000U; | ||
622 | } | ||
623 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) | ||
624 | { | ||
625 | return 0x0050435cU; | ||
626 | } | ||
627 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) | ||
628 | { | ||
629 | return 16U; | ||
630 | } | ||
631 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) | ||
632 | { | ||
633 | return (r >> 0U) & 0xffffU; | ||
634 | } | ||
635 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) | ||
636 | { | ||
637 | return 0x00504360U; | ||
638 | } | ||
639 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) | ||
640 | { | ||
641 | return 16U; | ||
642 | } | ||
643 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) | ||
644 | { | ||
645 | return (r >> 0U) & 0xffffU; | ||
646 | } | ||
647 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) | ||
648 | { | ||
649 | return 0x0050436cU; | ||
650 | } | ||
651 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) | ||
652 | { | ||
653 | return 0x1U << 0U; | ||
654 | } | ||
655 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) | ||
656 | { | ||
657 | return 0x1U << 1U; | ||
658 | } | ||
659 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) | ||
660 | { | ||
661 | return 0x1U << 2U; | ||
662 | } | ||
663 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) | ||
664 | { | ||
665 | return 0x1U << 3U; | ||
666 | } | ||
667 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
668 | { | ||
669 | return (r >> 8U) & 0x1U; | ||
670 | } | ||
671 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
672 | { | ||
673 | return (r >> 10U) & 0x1U; | ||
674 | } | ||
675 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) | ||
676 | { | ||
677 | return 0x40000000U; | ||
678 | } | ||
679 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) | ||
680 | { | ||
681 | return 0x00504370U; | ||
682 | } | ||
683 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) | ||
684 | { | ||
685 | return 16U; | ||
686 | } | ||
687 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) | ||
688 | { | ||
689 | return (r >> 0U) & 0xffffU; | ||
690 | } | ||
691 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) | ||
692 | { | ||
693 | return 0x00504374U; | ||
694 | } | ||
695 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) | ||
696 | { | ||
697 | return 16U; | ||
698 | } | ||
699 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) | ||
700 | { | ||
701 | return (r >> 0U) & 0xffffU; | ||
702 | } | ||
703 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) | ||
704 | { | ||
705 | return 0x00504638U; | ||
706 | } | ||
707 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) | ||
708 | { | ||
709 | return 0x1U << 0U; | ||
710 | } | ||
711 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) | ||
712 | { | ||
713 | return 0x1U << 1U; | ||
714 | } | ||
715 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) | ||
716 | { | ||
717 | return 0x1U << 2U; | ||
718 | } | ||
719 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) | ||
720 | { | ||
721 | return 0x1U << 3U; | ||
722 | } | ||
723 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) | ||
724 | { | ||
725 | return 0x1U << 4U; | ||
726 | } | ||
727 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) | ||
728 | { | ||
729 | return 0x1U << 5U; | ||
730 | } | ||
731 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) | ||
732 | { | ||
733 | return 0x1U << 6U; | ||
734 | } | ||
735 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) | ||
736 | { | ||
737 | return 0x1U << 7U; | ||
738 | } | ||
739 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
740 | { | ||
741 | return (r >> 16U) & 0x1U; | ||
742 | } | ||
743 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
744 | { | ||
745 | return (r >> 18U) & 0x1U; | ||
746 | } | ||
747 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) | ||
748 | { | ||
749 | return 0x40000000U; | ||
750 | } | ||
751 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) | ||
752 | { | ||
753 | return 0x0050463cU; | ||
754 | } | ||
755 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) | ||
756 | { | ||
757 | return 16U; | ||
758 | } | ||
759 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) | ||
760 | { | ||
761 | return (r >> 0U) & 0xffffU; | ||
762 | } | ||
763 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) | ||
764 | { | ||
765 | return 0x00504640U; | ||
766 | } | ||
767 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) | ||
768 | { | ||
769 | return 16U; | ||
770 | } | ||
771 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) | ||
772 | { | ||
773 | return (r >> 0U) & 0xffffU; | ||
774 | } | ||
775 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) | ||
776 | { | ||
777 | return 0x005042c4U; | ||
778 | } | ||
779 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) | ||
780 | { | ||
781 | return 0x0U; | ||
782 | } | ||
783 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) | ||
784 | { | ||
785 | return 0x1U; | ||
786 | } | ||
787 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) | ||
788 | { | ||
789 | return 0x2U; | ||
790 | } | ||
791 | static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) | ||
792 | { | ||
793 | return 0x00504430U; | ||
794 | } | ||
795 | static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) | ||
796 | { | ||
797 | return 0x40000000U; | ||
798 | } | ||
799 | static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) | ||
800 | { | ||
801 | return 0x00504434U; | ||
802 | } | ||
803 | static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) | ||
804 | { | ||
805 | return (r >> 0U) & 0x3fU; | ||
806 | } | ||
807 | static inline u32 gr_pri_be0_crop_status1_r(void) | ||
808 | { | ||
809 | return 0x00410134U; | ||
810 | } | ||
811 | static inline u32 gr_pri_bes_crop_status1_r(void) | ||
812 | { | ||
813 | return 0x00408934U; | ||
814 | } | ||
815 | static inline u32 gr_pri_be0_zrop_status_r(void) | ||
816 | { | ||
817 | return 0x00410048U; | ||
818 | } | ||
819 | static inline u32 gr_pri_be0_zrop_status2_r(void) | ||
820 | { | ||
821 | return 0x0041004cU; | ||
822 | } | ||
823 | static inline u32 gr_pri_bes_zrop_status_r(void) | ||
824 | { | ||
825 | return 0x00408848U; | ||
826 | } | ||
827 | static inline u32 gr_pri_bes_zrop_status2_r(void) | ||
828 | { | ||
829 | return 0x0040884cU; | ||
830 | } | ||
831 | static inline u32 gr_pipe_bundle_address_r(void) | ||
832 | { | ||
833 | return 0x00400200U; | ||
834 | } | ||
835 | static inline u32 gr_pipe_bundle_address_value_v(u32 r) | ||
836 | { | ||
837 | return (r >> 0U) & 0xffffU; | ||
838 | } | ||
839 | static inline u32 gr_pipe_bundle_address_veid_f(u32 v) | ||
840 | { | ||
841 | return (v & 0x3fU) << 20U; | ||
842 | } | ||
843 | static inline u32 gr_pipe_bundle_address_veid_w(void) | ||
844 | { | ||
845 | return 0U; | ||
846 | } | ||
847 | static inline u32 gr_pipe_bundle_data_r(void) | ||
848 | { | ||
849 | return 0x00400204U; | ||
850 | } | ||
851 | static inline u32 gr_pipe_bundle_config_r(void) | ||
852 | { | ||
853 | return 0x00400208U; | ||
854 | } | ||
855 | static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) | ||
856 | { | ||
857 | return 0x0U; | ||
858 | } | ||
859 | static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) | ||
860 | { | ||
861 | return 0x80000000U; | ||
862 | } | ||
863 | static inline u32 gr_fe_hww_esr_r(void) | ||
864 | { | ||
865 | return 0x00404000U; | ||
866 | } | ||
867 | static inline u32 gr_fe_hww_esr_reset_active_f(void) | ||
868 | { | ||
869 | return 0x40000000U; | ||
870 | } | ||
871 | static inline u32 gr_fe_hww_esr_en_enable_f(void) | ||
872 | { | ||
873 | return 0x80000000U; | ||
874 | } | ||
875 | static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) | ||
876 | { | ||
877 | return 0x00419eacU; | ||
878 | } | ||
879 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) | ||
880 | { | ||
881 | return 0x0050472cU; | ||
882 | } | ||
883 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) | ||
884 | { | ||
885 | return 0x4U; | ||
886 | } | ||
887 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) | ||
888 | { | ||
889 | return 0x10U; | ||
890 | } | ||
891 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) | ||
892 | { | ||
893 | return 0x20U; | ||
894 | } | ||
895 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) | ||
896 | { | ||
897 | return 0x40U; | ||
898 | } | ||
899 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) | ||
900 | { | ||
901 | return 0x100U; | ||
902 | } | ||
903 | static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) | ||
904 | { | ||
905 | return 0x00419eb4U; | ||
906 | } | ||
907 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) | ||
908 | { | ||
909 | return 0x00504734U; | ||
910 | } | ||
911 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) | ||
912 | { | ||
913 | return 0x1U << 4U; | ||
914 | } | ||
915 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) | ||
916 | { | ||
917 | return 0x10U; | ||
918 | } | ||
919 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) | ||
920 | { | ||
921 | return 0x1U << 5U; | ||
922 | } | ||
923 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) | ||
924 | { | ||
925 | return 0x20U; | ||
926 | } | ||
927 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) | ||
928 | { | ||
929 | return 0x1U << 6U; | ||
930 | } | ||
931 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) | ||
932 | { | ||
933 | return 0x40U; | ||
934 | } | ||
935 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) | ||
936 | { | ||
937 | return 0x1U << 2U; | ||
938 | } | ||
939 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
940 | { | ||
941 | return 0x4U; | ||
942 | } | ||
943 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) | ||
944 | { | ||
945 | return 0x1U << 8U; | ||
946 | } | ||
947 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) | ||
948 | { | ||
949 | return 0x100U; | ||
950 | } | ||
951 | static inline u32 gr_fe_go_idle_timeout_r(void) | ||
952 | { | ||
953 | return 0x00404154U; | ||
954 | } | ||
955 | static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) | ||
956 | { | ||
957 | return (v & 0xffffffffU) << 0U; | ||
958 | } | ||
959 | static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) | ||
960 | { | ||
961 | return 0x0U; | ||
962 | } | ||
963 | static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) | ||
964 | { | ||
965 | return 0x1800U; | ||
966 | } | ||
967 | static inline u32 gr_fe_object_table_r(u32 i) | ||
968 | { | ||
969 | return 0x00404200U + i*4U; | ||
970 | } | ||
971 | static inline u32 gr_fe_object_table_nvclass_v(u32 r) | ||
972 | { | ||
973 | return (r >> 0U) & 0xffffU; | ||
974 | } | ||
975 | static inline u32 gr_fe_tpc_fs_r(u32 i) | ||
976 | { | ||
977 | return 0x0040a200U + i*4U; | ||
978 | } | ||
979 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) | ||
980 | { | ||
981 | return 0x00404488U; | ||
982 | } | ||
983 | static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) | ||
984 | { | ||
985 | return 0x80000000U; | ||
986 | } | ||
987 | static inline u32 gr_pri_mme_shadow_raw_data_r(void) | ||
988 | { | ||
989 | return 0x0040448cU; | ||
990 | } | ||
991 | static inline u32 gr_mme_hww_esr_r(void) | ||
992 | { | ||
993 | return 0x00404490U; | ||
994 | } | ||
995 | static inline u32 gr_mme_hww_esr_reset_active_f(void) | ||
996 | { | ||
997 | return 0x40000000U; | ||
998 | } | ||
999 | static inline u32 gr_mme_hww_esr_en_enable_f(void) | ||
1000 | { | ||
1001 | return 0x80000000U; | ||
1002 | } | ||
1003 | static inline u32 gr_memfmt_hww_esr_r(void) | ||
1004 | { | ||
1005 | return 0x00404600U; | ||
1006 | } | ||
1007 | static inline u32 gr_memfmt_hww_esr_reset_active_f(void) | ||
1008 | { | ||
1009 | return 0x40000000U; | ||
1010 | } | ||
1011 | static inline u32 gr_memfmt_hww_esr_en_enable_f(void) | ||
1012 | { | ||
1013 | return 0x80000000U; | ||
1014 | } | ||
1015 | static inline u32 gr_fecs_cpuctl_r(void) | ||
1016 | { | ||
1017 | return 0x00409100U; | ||
1018 | } | ||
1019 | static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) | ||
1020 | { | ||
1021 | return (v & 0x1U) << 1U; | ||
1022 | } | ||
1023 | static inline u32 gr_fecs_cpuctl_alias_r(void) | ||
1024 | { | ||
1025 | return 0x00409130U; | ||
1026 | } | ||
1027 | static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) | ||
1028 | { | ||
1029 | return (v & 0x1U) << 1U; | ||
1030 | } | ||
1031 | static inline u32 gr_fecs_dmactl_r(void) | ||
1032 | { | ||
1033 | return 0x0040910cU; | ||
1034 | } | ||
1035 | static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) | ||
1036 | { | ||
1037 | return (v & 0x1U) << 0U; | ||
1038 | } | ||
1039 | static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) | ||
1040 | { | ||
1041 | return 0x1U << 1U; | ||
1042 | } | ||
1043 | static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) | ||
1044 | { | ||
1045 | return 0x1U << 2U; | ||
1046 | } | ||
1047 | static inline u32 gr_fecs_os_r(void) | ||
1048 | { | ||
1049 | return 0x00409080U; | ||
1050 | } | ||
1051 | static inline u32 gr_fecs_idlestate_r(void) | ||
1052 | { | ||
1053 | return 0x0040904cU; | ||
1054 | } | ||
1055 | static inline u32 gr_fecs_mailbox0_r(void) | ||
1056 | { | ||
1057 | return 0x00409040U; | ||
1058 | } | ||
1059 | static inline u32 gr_fecs_mailbox1_r(void) | ||
1060 | { | ||
1061 | return 0x00409044U; | ||
1062 | } | ||
1063 | static inline u32 gr_fecs_irqstat_r(void) | ||
1064 | { | ||
1065 | return 0x00409008U; | ||
1066 | } | ||
1067 | static inline u32 gr_fecs_irqmode_r(void) | ||
1068 | { | ||
1069 | return 0x0040900cU; | ||
1070 | } | ||
1071 | static inline u32 gr_fecs_irqmask_r(void) | ||
1072 | { | ||
1073 | return 0x00409018U; | ||
1074 | } | ||
1075 | static inline u32 gr_fecs_irqdest_r(void) | ||
1076 | { | ||
1077 | return 0x0040901cU; | ||
1078 | } | ||
1079 | static inline u32 gr_fecs_curctx_r(void) | ||
1080 | { | ||
1081 | return 0x00409050U; | ||
1082 | } | ||
1083 | static inline u32 gr_fecs_nxtctx_r(void) | ||
1084 | { | ||
1085 | return 0x00409054U; | ||
1086 | } | ||
1087 | static inline u32 gr_fecs_engctl_r(void) | ||
1088 | { | ||
1089 | return 0x004090a4U; | ||
1090 | } | ||
1091 | static inline u32 gr_fecs_debug1_r(void) | ||
1092 | { | ||
1093 | return 0x00409090U; | ||
1094 | } | ||
1095 | static inline u32 gr_fecs_debuginfo_r(void) | ||
1096 | { | ||
1097 | return 0x00409094U; | ||
1098 | } | ||
1099 | static inline u32 gr_fecs_icd_cmd_r(void) | ||
1100 | { | ||
1101 | return 0x00409200U; | ||
1102 | } | ||
1103 | static inline u32 gr_fecs_icd_cmd_opc_s(void) | ||
1104 | { | ||
1105 | return 4U; | ||
1106 | } | ||
1107 | static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) | ||
1108 | { | ||
1109 | return (v & 0xfU) << 0U; | ||
1110 | } | ||
1111 | static inline u32 gr_fecs_icd_cmd_opc_m(void) | ||
1112 | { | ||
1113 | return 0xfU << 0U; | ||
1114 | } | ||
1115 | static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) | ||
1116 | { | ||
1117 | return (r >> 0U) & 0xfU; | ||
1118 | } | ||
1119 | static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) | ||
1120 | { | ||
1121 | return 0x8U; | ||
1122 | } | ||
1123 | static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) | ||
1124 | { | ||
1125 | return 0xeU; | ||
1126 | } | ||
1127 | static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) | ||
1128 | { | ||
1129 | return (v & 0x1fU) << 8U; | ||
1130 | } | ||
1131 | static inline u32 gr_fecs_icd_rdata_r(void) | ||
1132 | { | ||
1133 | return 0x0040920cU; | ||
1134 | } | ||
1135 | static inline u32 gr_fecs_imemc_r(u32 i) | ||
1136 | { | ||
1137 | return 0x00409180U + i*16U; | ||
1138 | } | ||
1139 | static inline u32 gr_fecs_imemc_offs_f(u32 v) | ||
1140 | { | ||
1141 | return (v & 0x3fU) << 2U; | ||
1142 | } | ||
1143 | static inline u32 gr_fecs_imemc_blk_f(u32 v) | ||
1144 | { | ||
1145 | return (v & 0xffU) << 8U; | ||
1146 | } | ||
1147 | static inline u32 gr_fecs_imemc_aincw_f(u32 v) | ||
1148 | { | ||
1149 | return (v & 0x1U) << 24U; | ||
1150 | } | ||
1151 | static inline u32 gr_fecs_imemd_r(u32 i) | ||
1152 | { | ||
1153 | return 0x00409184U + i*16U; | ||
1154 | } | ||
1155 | static inline u32 gr_fecs_imemt_r(u32 i) | ||
1156 | { | ||
1157 | return 0x00409188U + i*16U; | ||
1158 | } | ||
1159 | static inline u32 gr_fecs_imemt_tag_f(u32 v) | ||
1160 | { | ||
1161 | return (v & 0xffffU) << 0U; | ||
1162 | } | ||
1163 | static inline u32 gr_fecs_dmemc_r(u32 i) | ||
1164 | { | ||
1165 | return 0x004091c0U + i*8U; | ||
1166 | } | ||
1167 | static inline u32 gr_fecs_dmemc_offs_s(void) | ||
1168 | { | ||
1169 | return 6U; | ||
1170 | } | ||
1171 | static inline u32 gr_fecs_dmemc_offs_f(u32 v) | ||
1172 | { | ||
1173 | return (v & 0x3fU) << 2U; | ||
1174 | } | ||
1175 | static inline u32 gr_fecs_dmemc_offs_m(void) | ||
1176 | { | ||
1177 | return 0x3fU << 2U; | ||
1178 | } | ||
1179 | static inline u32 gr_fecs_dmemc_offs_v(u32 r) | ||
1180 | { | ||
1181 | return (r >> 2U) & 0x3fU; | ||
1182 | } | ||
1183 | static inline u32 gr_fecs_dmemc_blk_f(u32 v) | ||
1184 | { | ||
1185 | return (v & 0xffU) << 8U; | ||
1186 | } | ||
1187 | static inline u32 gr_fecs_dmemc_aincw_f(u32 v) | ||
1188 | { | ||
1189 | return (v & 0x1U) << 24U; | ||
1190 | } | ||
1191 | static inline u32 gr_fecs_dmemd_r(u32 i) | ||
1192 | { | ||
1193 | return 0x004091c4U + i*8U; | ||
1194 | } | ||
1195 | static inline u32 gr_fecs_dmatrfbase_r(void) | ||
1196 | { | ||
1197 | return 0x00409110U; | ||
1198 | } | ||
1199 | static inline u32 gr_fecs_dmatrfmoffs_r(void) | ||
1200 | { | ||
1201 | return 0x00409114U; | ||
1202 | } | ||
1203 | static inline u32 gr_fecs_dmatrffboffs_r(void) | ||
1204 | { | ||
1205 | return 0x0040911cU; | ||
1206 | } | ||
1207 | static inline u32 gr_fecs_dmatrfcmd_r(void) | ||
1208 | { | ||
1209 | return 0x00409118U; | ||
1210 | } | ||
1211 | static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) | ||
1212 | { | ||
1213 | return (v & 0x1U) << 4U; | ||
1214 | } | ||
1215 | static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) | ||
1216 | { | ||
1217 | return (v & 0x1U) << 5U; | ||
1218 | } | ||
1219 | static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) | ||
1220 | { | ||
1221 | return (v & 0x7U) << 8U; | ||
1222 | } | ||
1223 | static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) | ||
1224 | { | ||
1225 | return (v & 0x7U) << 12U; | ||
1226 | } | ||
1227 | static inline u32 gr_fecs_bootvec_r(void) | ||
1228 | { | ||
1229 | return 0x00409104U; | ||
1230 | } | ||
1231 | static inline u32 gr_fecs_bootvec_vec_f(u32 v) | ||
1232 | { | ||
1233 | return (v & 0xffffffffU) << 0U; | ||
1234 | } | ||
1235 | static inline u32 gr_fecs_falcon_hwcfg_r(void) | ||
1236 | { | ||
1237 | return 0x00409108U; | ||
1238 | } | ||
1239 | static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) | ||
1240 | { | ||
1241 | return 0x0041a108U; | ||
1242 | } | ||
1243 | static inline u32 gr_fecs_falcon_rm_r(void) | ||
1244 | { | ||
1245 | return 0x00409084U; | ||
1246 | } | ||
1247 | static inline u32 gr_fecs_current_ctx_r(void) | ||
1248 | { | ||
1249 | return 0x00409b00U; | ||
1250 | } | ||
1251 | static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) | ||
1252 | { | ||
1253 | return (v & 0xfffffffU) << 0U; | ||
1254 | } | ||
1255 | static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) | ||
1256 | { | ||
1257 | return (r >> 0U) & 0xfffffffU; | ||
1258 | } | ||
1259 | static inline u32 gr_fecs_current_ctx_target_s(void) | ||
1260 | { | ||
1261 | return 2U; | ||
1262 | } | ||
1263 | static inline u32 gr_fecs_current_ctx_target_f(u32 v) | ||
1264 | { | ||
1265 | return (v & 0x3U) << 28U; | ||
1266 | } | ||
1267 | static inline u32 gr_fecs_current_ctx_target_m(void) | ||
1268 | { | ||
1269 | return 0x3U << 28U; | ||
1270 | } | ||
1271 | static inline u32 gr_fecs_current_ctx_target_v(u32 r) | ||
1272 | { | ||
1273 | return (r >> 28U) & 0x3U; | ||
1274 | } | ||
1275 | static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) | ||
1276 | { | ||
1277 | return 0x0U; | ||
1278 | } | ||
1279 | static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) | ||
1280 | { | ||
1281 | return 0x20000000U; | ||
1282 | } | ||
1283 | static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) | ||
1284 | { | ||
1285 | return 0x30000000U; | ||
1286 | } | ||
1287 | static inline u32 gr_fecs_current_ctx_valid_s(void) | ||
1288 | { | ||
1289 | return 1U; | ||
1290 | } | ||
1291 | static inline u32 gr_fecs_current_ctx_valid_f(u32 v) | ||
1292 | { | ||
1293 | return (v & 0x1U) << 31U; | ||
1294 | } | ||
1295 | static inline u32 gr_fecs_current_ctx_valid_m(void) | ||
1296 | { | ||
1297 | return 0x1U << 31U; | ||
1298 | } | ||
1299 | static inline u32 gr_fecs_current_ctx_valid_v(u32 r) | ||
1300 | { | ||
1301 | return (r >> 31U) & 0x1U; | ||
1302 | } | ||
1303 | static inline u32 gr_fecs_current_ctx_valid_false_f(void) | ||
1304 | { | ||
1305 | return 0x0U; | ||
1306 | } | ||
1307 | static inline u32 gr_fecs_method_data_r(void) | ||
1308 | { | ||
1309 | return 0x00409500U; | ||
1310 | } | ||
1311 | static inline u32 gr_fecs_method_push_r(void) | ||
1312 | { | ||
1313 | return 0x00409504U; | ||
1314 | } | ||
1315 | static inline u32 gr_fecs_method_push_adr_f(u32 v) | ||
1316 | { | ||
1317 | return (v & 0xfffU) << 0U; | ||
1318 | } | ||
1319 | static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) | ||
1320 | { | ||
1321 | return 0x00000003U; | ||
1322 | } | ||
1323 | static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) | ||
1324 | { | ||
1325 | return 0x3U; | ||
1326 | } | ||
1327 | static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) | ||
1328 | { | ||
1329 | return 0x00000010U; | ||
1330 | } | ||
1331 | static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) | ||
1332 | { | ||
1333 | return 0x00000009U; | ||
1334 | } | ||
1335 | static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) | ||
1336 | { | ||
1337 | return 0x00000015U; | ||
1338 | } | ||
1339 | static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) | ||
1340 | { | ||
1341 | return 0x00000016U; | ||
1342 | } | ||
1343 | static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) | ||
1344 | { | ||
1345 | return 0x00000025U; | ||
1346 | } | ||
1347 | static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) | ||
1348 | { | ||
1349 | return 0x00000030U; | ||
1350 | } | ||
1351 | static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) | ||
1352 | { | ||
1353 | return 0x00000031U; | ||
1354 | } | ||
1355 | static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) | ||
1356 | { | ||
1357 | return 0x00000032U; | ||
1358 | } | ||
1359 | static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) | ||
1360 | { | ||
1361 | return 0x00000038U; | ||
1362 | } | ||
1363 | static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) | ||
1364 | { | ||
1365 | return 0x00000039U; | ||
1366 | } | ||
1367 | static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | ||
1368 | { | ||
1369 | return 0x21U; | ||
1370 | } | ||
1371 | static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) | ||
1372 | { | ||
1373 | return 0x0000001aU; | ||
1374 | } | ||
1375 | static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) | ||
1376 | { | ||
1377 | return 0x00000004U; | ||
1378 | } | ||
1379 | static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) | ||
1380 | { | ||
1381 | return 0x0000003aU; | ||
1382 | } | ||
1383 | static inline u32 gr_fecs_host_int_status_r(void) | ||
1384 | { | ||
1385 | return 0x00409c18U; | ||
1386 | } | ||
1387 | static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) | ||
1388 | { | ||
1389 | return (v & 0x1U) << 16U; | ||
1390 | } | ||
1391 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | ||
1392 | { | ||
1393 | return (v & 0x1U) << 17U; | ||
1394 | } | ||
1395 | static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | ||
1396 | { | ||
1397 | return (v & 0x1U) << 18U; | ||
1398 | } | ||
1399 | static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) | ||
1400 | { | ||
1401 | return (v & 0xffffU) << 0U; | ||
1402 | } | ||
1403 | static inline u32 gr_fecs_host_int_clear_r(void) | ||
1404 | { | ||
1405 | return 0x00409c20U; | ||
1406 | } | ||
1407 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) | ||
1408 | { | ||
1409 | return (v & 0x1U) << 1U; | ||
1410 | } | ||
1411 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) | ||
1412 | { | ||
1413 | return 0x2U; | ||
1414 | } | ||
1415 | static inline u32 gr_fecs_host_int_enable_r(void) | ||
1416 | { | ||
1417 | return 0x00409c24U; | ||
1418 | } | ||
1419 | static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) | ||
1420 | { | ||
1421 | return 0x2U; | ||
1422 | } | ||
1423 | static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) | ||
1424 | { | ||
1425 | return 0x10000U; | ||
1426 | } | ||
1427 | static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) | ||
1428 | { | ||
1429 | return 0x20000U; | ||
1430 | } | ||
1431 | static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) | ||
1432 | { | ||
1433 | return 0x40000U; | ||
1434 | } | ||
1435 | static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) | ||
1436 | { | ||
1437 | return 0x80000U; | ||
1438 | } | ||
1439 | static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) | ||
1440 | { | ||
1441 | return 0x00409614U; | ||
1442 | } | ||
1443 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) | ||
1444 | { | ||
1445 | return 0x0U; | ||
1446 | } | ||
1447 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) | ||
1448 | { | ||
1449 | return 0x0U; | ||
1450 | } | ||
1451 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) | ||
1452 | { | ||
1453 | return 0x0U; | ||
1454 | } | ||
1455 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) | ||
1456 | { | ||
1457 | return 0x10U; | ||
1458 | } | ||
1459 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) | ||
1460 | { | ||
1461 | return 0x20U; | ||
1462 | } | ||
1463 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) | ||
1464 | { | ||
1465 | return 0x40U; | ||
1466 | } | ||
1467 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) | ||
1468 | { | ||
1469 | return 0x0U; | ||
1470 | } | ||
1471 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) | ||
1472 | { | ||
1473 | return 0x100U; | ||
1474 | } | ||
1475 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) | ||
1476 | { | ||
1477 | return 0x0U; | ||
1478 | } | ||
1479 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) | ||
1480 | { | ||
1481 | return 0x200U; | ||
1482 | } | ||
1483 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) | ||
1484 | { | ||
1485 | return 1U; | ||
1486 | } | ||
1487 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) | ||
1488 | { | ||
1489 | return (v & 0x1U) << 10U; | ||
1490 | } | ||
1491 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) | ||
1492 | { | ||
1493 | return 0x1U << 10U; | ||
1494 | } | ||
1495 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) | ||
1496 | { | ||
1497 | return (r >> 10U) & 0x1U; | ||
1498 | } | ||
1499 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) | ||
1500 | { | ||
1501 | return 0x0U; | ||
1502 | } | ||
1503 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) | ||
1504 | { | ||
1505 | return 0x400U; | ||
1506 | } | ||
1507 | static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) | ||
1508 | { | ||
1509 | return 0x0040960cU; | ||
1510 | } | ||
1511 | static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) | ||
1512 | { | ||
1513 | return 0x00409800U + i*4U; | ||
1514 | } | ||
1515 | static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) | ||
1516 | { | ||
1517 | return 0x00000010U; | ||
1518 | } | ||
1519 | static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) | ||
1520 | { | ||
1521 | return (v & 0xffffffffU) << 0U; | ||
1522 | } | ||
1523 | static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) | ||
1524 | { | ||
1525 | return 0x00000001U; | ||
1526 | } | ||
1527 | static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) | ||
1528 | { | ||
1529 | return 0x00000002U; | ||
1530 | } | ||
1531 | static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) | ||
1532 | { | ||
1533 | return 0x004098c0U + i*4U; | ||
1534 | } | ||
1535 | static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) | ||
1536 | { | ||
1537 | return (v & 0xffffffffU) << 0U; | ||
1538 | } | ||
1539 | static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) | ||
1540 | { | ||
1541 | return 0x00409840U + i*4U; | ||
1542 | } | ||
1543 | static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) | ||
1544 | { | ||
1545 | return (v & 0xffffffffU) << 0U; | ||
1546 | } | ||
1547 | static inline u32 gr_fecs_fs_r(void) | ||
1548 | { | ||
1549 | return 0x00409604U; | ||
1550 | } | ||
1551 | static inline u32 gr_fecs_fs_num_available_gpcs_s(void) | ||
1552 | { | ||
1553 | return 5U; | ||
1554 | } | ||
1555 | static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) | ||
1556 | { | ||
1557 | return (v & 0x1fU) << 0U; | ||
1558 | } | ||
1559 | static inline u32 gr_fecs_fs_num_available_gpcs_m(void) | ||
1560 | { | ||
1561 | return 0x1fU << 0U; | ||
1562 | } | ||
1563 | static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) | ||
1564 | { | ||
1565 | return (r >> 0U) & 0x1fU; | ||
1566 | } | ||
1567 | static inline u32 gr_fecs_fs_num_available_fbps_s(void) | ||
1568 | { | ||
1569 | return 5U; | ||
1570 | } | ||
1571 | static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) | ||
1572 | { | ||
1573 | return (v & 0x1fU) << 16U; | ||
1574 | } | ||
1575 | static inline u32 gr_fecs_fs_num_available_fbps_m(void) | ||
1576 | { | ||
1577 | return 0x1fU << 16U; | ||
1578 | } | ||
1579 | static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) | ||
1580 | { | ||
1581 | return (r >> 16U) & 0x1fU; | ||
1582 | } | ||
1583 | static inline u32 gr_fecs_cfg_r(void) | ||
1584 | { | ||
1585 | return 0x00409620U; | ||
1586 | } | ||
1587 | static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) | ||
1588 | { | ||
1589 | return (r >> 0U) & 0xffU; | ||
1590 | } | ||
1591 | static inline u32 gr_fecs_rc_lanes_r(void) | ||
1592 | { | ||
1593 | return 0x00409880U; | ||
1594 | } | ||
1595 | static inline u32 gr_fecs_rc_lanes_num_chains_s(void) | ||
1596 | { | ||
1597 | return 6U; | ||
1598 | } | ||
1599 | static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) | ||
1600 | { | ||
1601 | return (v & 0x3fU) << 0U; | ||
1602 | } | ||
1603 | static inline u32 gr_fecs_rc_lanes_num_chains_m(void) | ||
1604 | { | ||
1605 | return 0x3fU << 0U; | ||
1606 | } | ||
1607 | static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) | ||
1608 | { | ||
1609 | return (r >> 0U) & 0x3fU; | ||
1610 | } | ||
1611 | static inline u32 gr_fecs_ctxsw_status_1_r(void) | ||
1612 | { | ||
1613 | return 0x00409400U; | ||
1614 | } | ||
1615 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) | ||
1616 | { | ||
1617 | return 1U; | ||
1618 | } | ||
1619 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) | ||
1620 | { | ||
1621 | return (v & 0x1U) << 12U; | ||
1622 | } | ||
1623 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) | ||
1624 | { | ||
1625 | return 0x1U << 12U; | ||
1626 | } | ||
1627 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) | ||
1628 | { | ||
1629 | return (r >> 12U) & 0x1U; | ||
1630 | } | ||
1631 | static inline u32 gr_fecs_arb_ctx_adr_r(void) | ||
1632 | { | ||
1633 | return 0x00409a24U; | ||
1634 | } | ||
1635 | static inline u32 gr_fecs_new_ctx_r(void) | ||
1636 | { | ||
1637 | return 0x00409b04U; | ||
1638 | } | ||
1639 | static inline u32 gr_fecs_new_ctx_ptr_s(void) | ||
1640 | { | ||
1641 | return 28U; | ||
1642 | } | ||
1643 | static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) | ||
1644 | { | ||
1645 | return (v & 0xfffffffU) << 0U; | ||
1646 | } | ||
1647 | static inline u32 gr_fecs_new_ctx_ptr_m(void) | ||
1648 | { | ||
1649 | return 0xfffffffU << 0U; | ||
1650 | } | ||
1651 | static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) | ||
1652 | { | ||
1653 | return (r >> 0U) & 0xfffffffU; | ||
1654 | } | ||
1655 | static inline u32 gr_fecs_new_ctx_target_s(void) | ||
1656 | { | ||
1657 | return 2U; | ||
1658 | } | ||
1659 | static inline u32 gr_fecs_new_ctx_target_f(u32 v) | ||
1660 | { | ||
1661 | return (v & 0x3U) << 28U; | ||
1662 | } | ||
1663 | static inline u32 gr_fecs_new_ctx_target_m(void) | ||
1664 | { | ||
1665 | return 0x3U << 28U; | ||
1666 | } | ||
1667 | static inline u32 gr_fecs_new_ctx_target_v(u32 r) | ||
1668 | { | ||
1669 | return (r >> 28U) & 0x3U; | ||
1670 | } | ||
1671 | static inline u32 gr_fecs_new_ctx_valid_s(void) | ||
1672 | { | ||
1673 | return 1U; | ||
1674 | } | ||
1675 | static inline u32 gr_fecs_new_ctx_valid_f(u32 v) | ||
1676 | { | ||
1677 | return (v & 0x1U) << 31U; | ||
1678 | } | ||
1679 | static inline u32 gr_fecs_new_ctx_valid_m(void) | ||
1680 | { | ||
1681 | return 0x1U << 31U; | ||
1682 | } | ||
1683 | static inline u32 gr_fecs_new_ctx_valid_v(u32 r) | ||
1684 | { | ||
1685 | return (r >> 31U) & 0x1U; | ||
1686 | } | ||
1687 | static inline u32 gr_fecs_arb_ctx_ptr_r(void) | ||
1688 | { | ||
1689 | return 0x00409a0cU; | ||
1690 | } | ||
1691 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) | ||
1692 | { | ||
1693 | return 28U; | ||
1694 | } | ||
1695 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) | ||
1696 | { | ||
1697 | return (v & 0xfffffffU) << 0U; | ||
1698 | } | ||
1699 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) | ||
1700 | { | ||
1701 | return 0xfffffffU << 0U; | ||
1702 | } | ||
1703 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) | ||
1704 | { | ||
1705 | return (r >> 0U) & 0xfffffffU; | ||
1706 | } | ||
1707 | static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) | ||
1708 | { | ||
1709 | return 2U; | ||
1710 | } | ||
1711 | static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) | ||
1712 | { | ||
1713 | return (v & 0x3U) << 28U; | ||
1714 | } | ||
1715 | static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) | ||
1716 | { | ||
1717 | return 0x3U << 28U; | ||
1718 | } | ||
1719 | static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) | ||
1720 | { | ||
1721 | return (r >> 28U) & 0x3U; | ||
1722 | } | ||
1723 | static inline u32 gr_fecs_arb_ctx_cmd_r(void) | ||
1724 | { | ||
1725 | return 0x00409a10U; | ||
1726 | } | ||
1727 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) | ||
1728 | { | ||
1729 | return 5U; | ||
1730 | } | ||
1731 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) | ||
1732 | { | ||
1733 | return (v & 0x1fU) << 0U; | ||
1734 | } | ||
1735 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) | ||
1736 | { | ||
1737 | return 0x1fU << 0U; | ||
1738 | } | ||
1739 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) | ||
1740 | { | ||
1741 | return (r >> 0U) & 0x1fU; | ||
1742 | } | ||
1743 | static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) | ||
1744 | { | ||
1745 | return 0x00409c00U; | ||
1746 | } | ||
1747 | static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) | ||
1748 | { | ||
1749 | return 0x00502c04U; | ||
1750 | } | ||
1751 | static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) | ||
1752 | { | ||
1753 | return 0x00502400U; | ||
1754 | } | ||
1755 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) | ||
1756 | { | ||
1757 | return 0x00409420U; | ||
1758 | } | ||
1759 | static inline u32 gr_fecs_feature_override_ecc_r(void) | ||
1760 | { | ||
1761 | return 0x00409658U; | ||
1762 | } | ||
1763 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) | ||
1764 | { | ||
1765 | return (r >> 3U) & 0x1U; | ||
1766 | } | ||
1767 | static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) | ||
1768 | { | ||
1769 | return (r >> 15U) & 0x1U; | ||
1770 | } | ||
1771 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) | ||
1772 | { | ||
1773 | return (r >> 0U) & 0x1U; | ||
1774 | } | ||
1775 | static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) | ||
1776 | { | ||
1777 | return (r >> 12U) & 0x1U; | ||
1778 | } | ||
1779 | static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) | ||
1780 | { | ||
1781 | return 0x00502420U; | ||
1782 | } | ||
1783 | static inline u32 gr_rstr2d_gpc_map_r(u32 i) | ||
1784 | { | ||
1785 | return 0x0040780cU + i*4U; | ||
1786 | } | ||
1787 | static inline u32 gr_rstr2d_map_table_cfg_r(void) | ||
1788 | { | ||
1789 | return 0x004078bcU; | ||
1790 | } | ||
1791 | static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) | ||
1792 | { | ||
1793 | return (v & 0xffU) << 0U; | ||
1794 | } | ||
1795 | static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) | ||
1796 | { | ||
1797 | return (v & 0xffU) << 8U; | ||
1798 | } | ||
1799 | static inline u32 gr_pd_hww_esr_r(void) | ||
1800 | { | ||
1801 | return 0x00406018U; | ||
1802 | } | ||
1803 | static inline u32 gr_pd_hww_esr_reset_active_f(void) | ||
1804 | { | ||
1805 | return 0x40000000U; | ||
1806 | } | ||
1807 | static inline u32 gr_pd_hww_esr_en_enable_f(void) | ||
1808 | { | ||
1809 | return 0x80000000U; | ||
1810 | } | ||
1811 | static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) | ||
1812 | { | ||
1813 | return 0x00406028U + i*4U; | ||
1814 | } | ||
1815 | static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) | ||
1816 | { | ||
1817 | return 0x00000004U; | ||
1818 | } | ||
1819 | static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) | ||
1820 | { | ||
1821 | return (v & 0xfU) << 0U; | ||
1822 | } | ||
1823 | static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) | ||
1824 | { | ||
1825 | return (v & 0xfU) << 4U; | ||
1826 | } | ||
1827 | static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) | ||
1828 | { | ||
1829 | return (v & 0xfU) << 8U; | ||
1830 | } | ||
1831 | static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) | ||
1832 | { | ||
1833 | return (v & 0xfU) << 12U; | ||
1834 | } | ||
1835 | static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) | ||
1836 | { | ||
1837 | return (v & 0xfU) << 16U; | ||
1838 | } | ||
1839 | static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) | ||
1840 | { | ||
1841 | return (v & 0xfU) << 20U; | ||
1842 | } | ||
1843 | static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) | ||
1844 | { | ||
1845 | return (v & 0xfU) << 24U; | ||
1846 | } | ||
1847 | static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) | ||
1848 | { | ||
1849 | return (v & 0xfU) << 28U; | ||
1850 | } | ||
1851 | static inline u32 gr_pd_ab_dist_cfg0_r(void) | ||
1852 | { | ||
1853 | return 0x004064c0U; | ||
1854 | } | ||
1855 | static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) | ||
1856 | { | ||
1857 | return 0x80000000U; | ||
1858 | } | ||
1859 | static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) | ||
1860 | { | ||
1861 | return 0x0U; | ||
1862 | } | ||
1863 | static inline u32 gr_pd_ab_dist_cfg1_r(void) | ||
1864 | { | ||
1865 | return 0x004064c4U; | ||
1866 | } | ||
1867 | static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) | ||
1868 | { | ||
1869 | return 0xffffU; | ||
1870 | } | ||
1871 | static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) | ||
1872 | { | ||
1873 | return (v & 0xffffU) << 16U; | ||
1874 | } | ||
1875 | static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) | ||
1876 | { | ||
1877 | return 0x00000080U; | ||
1878 | } | ||
1879 | static inline u32 gr_pd_ab_dist_cfg2_r(void) | ||
1880 | { | ||
1881 | return 0x004064c8U; | ||
1882 | } | ||
1883 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) | ||
1884 | { | ||
1885 | return (v & 0x1fffU) << 0U; | ||
1886 | } | ||
1887 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) | ||
1888 | { | ||
1889 | return 0x00001680U; | ||
1890 | } | ||
1891 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) | ||
1892 | { | ||
1893 | return (v & 0x1fffU) << 16U; | ||
1894 | } | ||
1895 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) | ||
1896 | { | ||
1897 | return 0x00000020U; | ||
1898 | } | ||
1899 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) | ||
1900 | { | ||
1901 | return 0x00001680U; | ||
1902 | } | ||
1903 | static inline u32 gr_pd_dist_skip_table_r(u32 i) | ||
1904 | { | ||
1905 | return 0x004064d0U + i*4U; | ||
1906 | } | ||
1907 | static inline u32 gr_pd_dist_skip_table__size_1_v(void) | ||
1908 | { | ||
1909 | return 0x00000008U; | ||
1910 | } | ||
1911 | static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) | ||
1912 | { | ||
1913 | return (v & 0xffU) << 0U; | ||
1914 | } | ||
1915 | static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) | ||
1916 | { | ||
1917 | return (v & 0xffU) << 8U; | ||
1918 | } | ||
1919 | static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) | ||
1920 | { | ||
1921 | return (v & 0xffU) << 16U; | ||
1922 | } | ||
1923 | static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) | ||
1924 | { | ||
1925 | return (v & 0xffU) << 24U; | ||
1926 | } | ||
1927 | static inline u32 gr_ds_debug_r(void) | ||
1928 | { | ||
1929 | return 0x00405800U; | ||
1930 | } | ||
1931 | static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) | ||
1932 | { | ||
1933 | return 0x0U; | ||
1934 | } | ||
1935 | static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) | ||
1936 | { | ||
1937 | return 0x8000000U; | ||
1938 | } | ||
1939 | static inline u32 gr_ds_zbc_color_r_r(void) | ||
1940 | { | ||
1941 | return 0x00405804U; | ||
1942 | } | ||
1943 | static inline u32 gr_ds_zbc_color_r_val_f(u32 v) | ||
1944 | { | ||
1945 | return (v & 0xffffffffU) << 0U; | ||
1946 | } | ||
1947 | static inline u32 gr_ds_zbc_color_g_r(void) | ||
1948 | { | ||
1949 | return 0x00405808U; | ||
1950 | } | ||
1951 | static inline u32 gr_ds_zbc_color_g_val_f(u32 v) | ||
1952 | { | ||
1953 | return (v & 0xffffffffU) << 0U; | ||
1954 | } | ||
1955 | static inline u32 gr_ds_zbc_color_b_r(void) | ||
1956 | { | ||
1957 | return 0x0040580cU; | ||
1958 | } | ||
1959 | static inline u32 gr_ds_zbc_color_b_val_f(u32 v) | ||
1960 | { | ||
1961 | return (v & 0xffffffffU) << 0U; | ||
1962 | } | ||
1963 | static inline u32 gr_ds_zbc_color_a_r(void) | ||
1964 | { | ||
1965 | return 0x00405810U; | ||
1966 | } | ||
1967 | static inline u32 gr_ds_zbc_color_a_val_f(u32 v) | ||
1968 | { | ||
1969 | return (v & 0xffffffffU) << 0U; | ||
1970 | } | ||
1971 | static inline u32 gr_ds_zbc_color_fmt_r(void) | ||
1972 | { | ||
1973 | return 0x00405814U; | ||
1974 | } | ||
1975 | static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) | ||
1976 | { | ||
1977 | return (v & 0x7fU) << 0U; | ||
1978 | } | ||
1979 | static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) | ||
1980 | { | ||
1981 | return 0x0U; | ||
1982 | } | ||
1983 | static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) | ||
1984 | { | ||
1985 | return 0x00000001U; | ||
1986 | } | ||
1987 | static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) | ||
1988 | { | ||
1989 | return 0x00000002U; | ||
1990 | } | ||
1991 | static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | ||
1992 | { | ||
1993 | return 0x00000004U; | ||
1994 | } | ||
1995 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
1996 | { | ||
1997 | return 0x00000028U; | ||
1998 | } | ||
1999 | static inline u32 gr_ds_zbc_z_r(void) | ||
2000 | { | ||
2001 | return 0x00405818U; | ||
2002 | } | ||
2003 | static inline u32 gr_ds_zbc_z_val_s(void) | ||
2004 | { | ||
2005 | return 32U; | ||
2006 | } | ||
2007 | static inline u32 gr_ds_zbc_z_val_f(u32 v) | ||
2008 | { | ||
2009 | return (v & 0xffffffffU) << 0U; | ||
2010 | } | ||
2011 | static inline u32 gr_ds_zbc_z_val_m(void) | ||
2012 | { | ||
2013 | return 0xffffffffU << 0U; | ||
2014 | } | ||
2015 | static inline u32 gr_ds_zbc_z_val_v(u32 r) | ||
2016 | { | ||
2017 | return (r >> 0U) & 0xffffffffU; | ||
2018 | } | ||
2019 | static inline u32 gr_ds_zbc_z_val__init_v(void) | ||
2020 | { | ||
2021 | return 0x00000000U; | ||
2022 | } | ||
2023 | static inline u32 gr_ds_zbc_z_val__init_f(void) | ||
2024 | { | ||
2025 | return 0x0U; | ||
2026 | } | ||
2027 | static inline u32 gr_ds_zbc_z_fmt_r(void) | ||
2028 | { | ||
2029 | return 0x0040581cU; | ||
2030 | } | ||
2031 | static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) | ||
2032 | { | ||
2033 | return (v & 0x1U) << 0U; | ||
2034 | } | ||
2035 | static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) | ||
2036 | { | ||
2037 | return 0x0U; | ||
2038 | } | ||
2039 | static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) | ||
2040 | { | ||
2041 | return 0x00000001U; | ||
2042 | } | ||
2043 | static inline u32 gr_ds_zbc_tbl_index_r(void) | ||
2044 | { | ||
2045 | return 0x00405820U; | ||
2046 | } | ||
2047 | static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) | ||
2048 | { | ||
2049 | return (v & 0xfU) << 0U; | ||
2050 | } | ||
2051 | static inline u32 gr_ds_zbc_tbl_ld_r(void) | ||
2052 | { | ||
2053 | return 0x00405824U; | ||
2054 | } | ||
2055 | static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) | ||
2056 | { | ||
2057 | return 0x0U; | ||
2058 | } | ||
2059 | static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) | ||
2060 | { | ||
2061 | return 0x1U; | ||
2062 | } | ||
2063 | static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) | ||
2064 | { | ||
2065 | return 0x0U; | ||
2066 | } | ||
2067 | static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) | ||
2068 | { | ||
2069 | return 0x4U; | ||
2070 | } | ||
2071 | static inline u32 gr_ds_tga_constraintlogic_beta_r(void) | ||
2072 | { | ||
2073 | return 0x00405830U; | ||
2074 | } | ||
2075 | static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) | ||
2076 | { | ||
2077 | return (v & 0x3fffffU) << 0U; | ||
2078 | } | ||
2079 | static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) | ||
2080 | { | ||
2081 | return 0x0040585cU; | ||
2082 | } | ||
2083 | static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) | ||
2084 | { | ||
2085 | return (v & 0xffffU) << 0U; | ||
2086 | } | ||
2087 | static inline u32 gr_ds_hww_esr_r(void) | ||
2088 | { | ||
2089 | return 0x00405840U; | ||
2090 | } | ||
2091 | static inline u32 gr_ds_hww_esr_reset_s(void) | ||
2092 | { | ||
2093 | return 1U; | ||
2094 | } | ||
2095 | static inline u32 gr_ds_hww_esr_reset_f(u32 v) | ||
2096 | { | ||
2097 | return (v & 0x1U) << 30U; | ||
2098 | } | ||
2099 | static inline u32 gr_ds_hww_esr_reset_m(void) | ||
2100 | { | ||
2101 | return 0x1U << 30U; | ||
2102 | } | ||
2103 | static inline u32 gr_ds_hww_esr_reset_v(u32 r) | ||
2104 | { | ||
2105 | return (r >> 30U) & 0x1U; | ||
2106 | } | ||
2107 | static inline u32 gr_ds_hww_esr_reset_task_v(void) | ||
2108 | { | ||
2109 | return 0x00000001U; | ||
2110 | } | ||
2111 | static inline u32 gr_ds_hww_esr_reset_task_f(void) | ||
2112 | { | ||
2113 | return 0x40000000U; | ||
2114 | } | ||
2115 | static inline u32 gr_ds_hww_esr_en_enabled_f(void) | ||
2116 | { | ||
2117 | return 0x80000000U; | ||
2118 | } | ||
2119 | static inline u32 gr_ds_hww_esr_2_r(void) | ||
2120 | { | ||
2121 | return 0x00405848U; | ||
2122 | } | ||
2123 | static inline u32 gr_ds_hww_esr_2_reset_s(void) | ||
2124 | { | ||
2125 | return 1U; | ||
2126 | } | ||
2127 | static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) | ||
2128 | { | ||
2129 | return (v & 0x1U) << 30U; | ||
2130 | } | ||
2131 | static inline u32 gr_ds_hww_esr_2_reset_m(void) | ||
2132 | { | ||
2133 | return 0x1U << 30U; | ||
2134 | } | ||
2135 | static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) | ||
2136 | { | ||
2137 | return (r >> 30U) & 0x1U; | ||
2138 | } | ||
2139 | static inline u32 gr_ds_hww_esr_2_reset_task_v(void) | ||
2140 | { | ||
2141 | return 0x00000001U; | ||
2142 | } | ||
2143 | static inline u32 gr_ds_hww_esr_2_reset_task_f(void) | ||
2144 | { | ||
2145 | return 0x40000000U; | ||
2146 | } | ||
2147 | static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) | ||
2148 | { | ||
2149 | return 0x80000000U; | ||
2150 | } | ||
2151 | static inline u32 gr_ds_hww_report_mask_r(void) | ||
2152 | { | ||
2153 | return 0x00405844U; | ||
2154 | } | ||
2155 | static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) | ||
2156 | { | ||
2157 | return 0x1U; | ||
2158 | } | ||
2159 | static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) | ||
2160 | { | ||
2161 | return 0x2U; | ||
2162 | } | ||
2163 | static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) | ||
2164 | { | ||
2165 | return 0x4U; | ||
2166 | } | ||
2167 | static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) | ||
2168 | { | ||
2169 | return 0x8U; | ||
2170 | } | ||
2171 | static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) | ||
2172 | { | ||
2173 | return 0x10U; | ||
2174 | } | ||
2175 | static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) | ||
2176 | { | ||
2177 | return 0x20U; | ||
2178 | } | ||
2179 | static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) | ||
2180 | { | ||
2181 | return 0x40U; | ||
2182 | } | ||
2183 | static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) | ||
2184 | { | ||
2185 | return 0x80U; | ||
2186 | } | ||
2187 | static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) | ||
2188 | { | ||
2189 | return 0x100U; | ||
2190 | } | ||
2191 | static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) | ||
2192 | { | ||
2193 | return 0x200U; | ||
2194 | } | ||
2195 | static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) | ||
2196 | { | ||
2197 | return 0x400U; | ||
2198 | } | ||
2199 | static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) | ||
2200 | { | ||
2201 | return 0x800U; | ||
2202 | } | ||
2203 | static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) | ||
2204 | { | ||
2205 | return 0x1000U; | ||
2206 | } | ||
2207 | static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) | ||
2208 | { | ||
2209 | return 0x2000U; | ||
2210 | } | ||
2211 | static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) | ||
2212 | { | ||
2213 | return 0x4000U; | ||
2214 | } | ||
2215 | static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) | ||
2216 | { | ||
2217 | return 0x8000U; | ||
2218 | } | ||
2219 | static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) | ||
2220 | { | ||
2221 | return 0x10000U; | ||
2222 | } | ||
2223 | static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) | ||
2224 | { | ||
2225 | return 0x20000U; | ||
2226 | } | ||
2227 | static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) | ||
2228 | { | ||
2229 | return 0x40000U; | ||
2230 | } | ||
2231 | static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) | ||
2232 | { | ||
2233 | return 0x80000U; | ||
2234 | } | ||
2235 | static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) | ||
2236 | { | ||
2237 | return 0x100000U; | ||
2238 | } | ||
2239 | static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) | ||
2240 | { | ||
2241 | return 0x200000U; | ||
2242 | } | ||
2243 | static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) | ||
2244 | { | ||
2245 | return 0x400000U; | ||
2246 | } | ||
2247 | static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) | ||
2248 | { | ||
2249 | return 0x800000U; | ||
2250 | } | ||
2251 | static inline u32 gr_ds_hww_report_mask_2_r(void) | ||
2252 | { | ||
2253 | return 0x0040584cU; | ||
2254 | } | ||
2255 | static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) | ||
2256 | { | ||
2257 | return 0x1U; | ||
2258 | } | ||
2259 | static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) | ||
2260 | { | ||
2261 | return 0x00405870U + i*4U; | ||
2262 | } | ||
2263 | static inline u32 gr_scc_bundle_cb_base_r(void) | ||
2264 | { | ||
2265 | return 0x00408004U; | ||
2266 | } | ||
2267 | static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) | ||
2268 | { | ||
2269 | return (v & 0xffffffffU) << 0U; | ||
2270 | } | ||
2271 | static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) | ||
2272 | { | ||
2273 | return 0x00000008U; | ||
2274 | } | ||
2275 | static inline u32 gr_scc_bundle_cb_size_r(void) | ||
2276 | { | ||
2277 | return 0x00408008U; | ||
2278 | } | ||
2279 | static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) | ||
2280 | { | ||
2281 | return (v & 0x7ffU) << 0U; | ||
2282 | } | ||
2283 | static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) | ||
2284 | { | ||
2285 | return 0x00000030U; | ||
2286 | } | ||
2287 | static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) | ||
2288 | { | ||
2289 | return 0x00000100U; | ||
2290 | } | ||
2291 | static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) | ||
2292 | { | ||
2293 | return 0x00000000U; | ||
2294 | } | ||
2295 | static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) | ||
2296 | { | ||
2297 | return 0x0U; | ||
2298 | } | ||
2299 | static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) | ||
2300 | { | ||
2301 | return 0x80000000U; | ||
2302 | } | ||
2303 | static inline u32 gr_scc_pagepool_base_r(void) | ||
2304 | { | ||
2305 | return 0x0040800cU; | ||
2306 | } | ||
2307 | static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) | ||
2308 | { | ||
2309 | return (v & 0xffffffffU) << 0U; | ||
2310 | } | ||
2311 | static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) | ||
2312 | { | ||
2313 | return 0x00000008U; | ||
2314 | } | ||
2315 | static inline u32 gr_scc_pagepool_r(void) | ||
2316 | { | ||
2317 | return 0x00408010U; | ||
2318 | } | ||
2319 | static inline u32 gr_scc_pagepool_total_pages_f(u32 v) | ||
2320 | { | ||
2321 | return (v & 0x3ffU) << 0U; | ||
2322 | } | ||
2323 | static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) | ||
2324 | { | ||
2325 | return 0x00000000U; | ||
2326 | } | ||
2327 | static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) | ||
2328 | { | ||
2329 | return 0x00000200U; | ||
2330 | } | ||
2331 | static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) | ||
2332 | { | ||
2333 | return 0x00000100U; | ||
2334 | } | ||
2335 | static inline u32 gr_scc_pagepool_max_valid_pages_s(void) | ||
2336 | { | ||
2337 | return 10U; | ||
2338 | } | ||
2339 | static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) | ||
2340 | { | ||
2341 | return (v & 0x3ffU) << 10U; | ||
2342 | } | ||
2343 | static inline u32 gr_scc_pagepool_max_valid_pages_m(void) | ||
2344 | { | ||
2345 | return 0x3ffU << 10U; | ||
2346 | } | ||
2347 | static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) | ||
2348 | { | ||
2349 | return (r >> 10U) & 0x3ffU; | ||
2350 | } | ||
2351 | static inline u32 gr_scc_pagepool_valid_true_f(void) | ||
2352 | { | ||
2353 | return 0x80000000U; | ||
2354 | } | ||
2355 | static inline u32 gr_scc_init_r(void) | ||
2356 | { | ||
2357 | return 0x0040802cU; | ||
2358 | } | ||
2359 | static inline u32 gr_scc_init_ram_trigger_f(void) | ||
2360 | { | ||
2361 | return 0x1U; | ||
2362 | } | ||
2363 | static inline u32 gr_scc_hww_esr_r(void) | ||
2364 | { | ||
2365 | return 0x00408030U; | ||
2366 | } | ||
2367 | static inline u32 gr_scc_hww_esr_reset_active_f(void) | ||
2368 | { | ||
2369 | return 0x40000000U; | ||
2370 | } | ||
2371 | static inline u32 gr_scc_hww_esr_en_enable_f(void) | ||
2372 | { | ||
2373 | return 0x80000000U; | ||
2374 | } | ||
2375 | static inline u32 gr_sked_hww_esr_r(void) | ||
2376 | { | ||
2377 | return 0x00407020U; | ||
2378 | } | ||
2379 | static inline u32 gr_sked_hww_esr_reset_active_f(void) | ||
2380 | { | ||
2381 | return 0x40000000U; | ||
2382 | } | ||
2383 | static inline u32 gr_sked_hww_esr_en_r(void) | ||
2384 | { | ||
2385 | return 0x00407024U; | ||
2386 | } | ||
2387 | static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) | ||
2388 | { | ||
2389 | return 0x1U << 25U; | ||
2390 | } | ||
2391 | static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) | ||
2392 | { | ||
2393 | return 0x0U; | ||
2394 | } | ||
2395 | static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) | ||
2396 | { | ||
2397 | return 0x2000000U; | ||
2398 | } | ||
2399 | static inline u32 gr_cwd_fs_r(void) | ||
2400 | { | ||
2401 | return 0x00405b00U; | ||
2402 | } | ||
2403 | static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) | ||
2404 | { | ||
2405 | return (v & 0xffU) << 0U; | ||
2406 | } | ||
2407 | static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) | ||
2408 | { | ||
2409 | return (v & 0xffU) << 8U; | ||
2410 | } | ||
2411 | static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) | ||
2412 | { | ||
2413 | return 0x00405b60U + i*4U; | ||
2414 | } | ||
2415 | static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) | ||
2416 | { | ||
2417 | return 4U; | ||
2418 | } | ||
2419 | static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) | ||
2420 | { | ||
2421 | return (v & 0xfU) << 0U; | ||
2422 | } | ||
2423 | static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) | ||
2424 | { | ||
2425 | return 4U; | ||
2426 | } | ||
2427 | static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) | ||
2428 | { | ||
2429 | return (v & 0xfU) << 4U; | ||
2430 | } | ||
2431 | static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) | ||
2432 | { | ||
2433 | return (v & 0xfU) << 8U; | ||
2434 | } | ||
2435 | static inline u32 gr_cwd_sm_id_r(u32 i) | ||
2436 | { | ||
2437 | return 0x00405ba0U + i*4U; | ||
2438 | } | ||
2439 | static inline u32 gr_cwd_sm_id__size_1_v(void) | ||
2440 | { | ||
2441 | return 0x00000010U; | ||
2442 | } | ||
2443 | static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) | ||
2444 | { | ||
2445 | return (v & 0xffU) << 0U; | ||
2446 | } | ||
2447 | static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) | ||
2448 | { | ||
2449 | return (v & 0xffU) << 8U; | ||
2450 | } | ||
2451 | static inline u32 gr_gpc0_fs_gpc_r(void) | ||
2452 | { | ||
2453 | return 0x00502608U; | ||
2454 | } | ||
2455 | static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) | ||
2456 | { | ||
2457 | return (r >> 0U) & 0x1fU; | ||
2458 | } | ||
2459 | static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) | ||
2460 | { | ||
2461 | return (r >> 16U) & 0x1fU; | ||
2462 | } | ||
2463 | static inline u32 gr_gpc0_cfg_r(void) | ||
2464 | { | ||
2465 | return 0x00502620U; | ||
2466 | } | ||
2467 | static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) | ||
2468 | { | ||
2469 | return (r >> 0U) & 0xffU; | ||
2470 | } | ||
2471 | static inline u32 gr_gpccs_rc_lanes_r(void) | ||
2472 | { | ||
2473 | return 0x00502880U; | ||
2474 | } | ||
2475 | static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) | ||
2476 | { | ||
2477 | return 6U; | ||
2478 | } | ||
2479 | static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) | ||
2480 | { | ||
2481 | return (v & 0x3fU) << 0U; | ||
2482 | } | ||
2483 | static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) | ||
2484 | { | ||
2485 | return 0x3fU << 0U; | ||
2486 | } | ||
2487 | static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) | ||
2488 | { | ||
2489 | return (r >> 0U) & 0x3fU; | ||
2490 | } | ||
2491 | static inline u32 gr_gpccs_rc_lane_size_r(void) | ||
2492 | { | ||
2493 | return 0x00502910U; | ||
2494 | } | ||
2495 | static inline u32 gr_gpccs_rc_lane_size_v_s(void) | ||
2496 | { | ||
2497 | return 24U; | ||
2498 | } | ||
2499 | static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) | ||
2500 | { | ||
2501 | return (v & 0xffffffU) << 0U; | ||
2502 | } | ||
2503 | static inline u32 gr_gpccs_rc_lane_size_v_m(void) | ||
2504 | { | ||
2505 | return 0xffffffU << 0U; | ||
2506 | } | ||
2507 | static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) | ||
2508 | { | ||
2509 | return (r >> 0U) & 0xffffffU; | ||
2510 | } | ||
2511 | static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) | ||
2512 | { | ||
2513 | return 0x00000000U; | ||
2514 | } | ||
2515 | static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) | ||
2516 | { | ||
2517 | return 0x0U; | ||
2518 | } | ||
2519 | static inline u32 gr_gpc0_zcull_fs_r(void) | ||
2520 | { | ||
2521 | return 0x00500910U; | ||
2522 | } | ||
2523 | static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) | ||
2524 | { | ||
2525 | return (v & 0x1ffU) << 0U; | ||
2526 | } | ||
2527 | static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) | ||
2528 | { | ||
2529 | return (v & 0xfU) << 16U; | ||
2530 | } | ||
2531 | static inline u32 gr_gpc0_zcull_ram_addr_r(void) | ||
2532 | { | ||
2533 | return 0x00500914U; | ||
2534 | } | ||
2535 | static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) | ||
2536 | { | ||
2537 | return (v & 0xfU) << 0U; | ||
2538 | } | ||
2539 | static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) | ||
2540 | { | ||
2541 | return (v & 0xfU) << 8U; | ||
2542 | } | ||
2543 | static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) | ||
2544 | { | ||
2545 | return 0x00500918U; | ||
2546 | } | ||
2547 | static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) | ||
2548 | { | ||
2549 | return (v & 0xffffffU) << 0U; | ||
2550 | } | ||
2551 | static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) | ||
2552 | { | ||
2553 | return 0x00800000U; | ||
2554 | } | ||
2555 | static inline u32 gr_gpc0_zcull_total_ram_size_r(void) | ||
2556 | { | ||
2557 | return 0x00500920U; | ||
2558 | } | ||
2559 | static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) | ||
2560 | { | ||
2561 | return (v & 0xffffU) << 0U; | ||
2562 | } | ||
2563 | static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) | ||
2564 | { | ||
2565 | return 0x00500a04U + i*32U; | ||
2566 | } | ||
2567 | static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) | ||
2568 | { | ||
2569 | return 0x00000040U; | ||
2570 | } | ||
2571 | static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) | ||
2572 | { | ||
2573 | return 0x00000010U; | ||
2574 | } | ||
2575 | static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) | ||
2576 | { | ||
2577 | return 0x00500c10U + i*4U; | ||
2578 | } | ||
2579 | static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) | ||
2580 | { | ||
2581 | return (v & 0xffU) << 0U; | ||
2582 | } | ||
2583 | static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) | ||
2584 | { | ||
2585 | return 0x00500c30U + i*4U; | ||
2586 | } | ||
2587 | static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) | ||
2588 | { | ||
2589 | return (r >> 0U) & 0xffU; | ||
2590 | } | ||
2591 | static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) | ||
2592 | { | ||
2593 | return 0x00504088U; | ||
2594 | } | ||
2595 | static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) | ||
2596 | { | ||
2597 | return (v & 0xffffU) << 0U; | ||
2598 | } | ||
2599 | static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) | ||
2600 | { | ||
2601 | return 0x00504608U; | ||
2602 | } | ||
2603 | static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) | ||
2604 | { | ||
2605 | return (v & 0xffffU) << 0U; | ||
2606 | } | ||
2607 | static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) | ||
2608 | { | ||
2609 | return (r >> 0U) & 0xffffU; | ||
2610 | } | ||
2611 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) | ||
2612 | { | ||
2613 | return 0x00504330U; | ||
2614 | } | ||
2615 | static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) | ||
2616 | { | ||
2617 | return (r >> 0U) & 0xffU; | ||
2618 | } | ||
2619 | static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) | ||
2620 | { | ||
2621 | return (r >> 8U) & 0xfffU; | ||
2622 | } | ||
2623 | static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) | ||
2624 | { | ||
2625 | return (r >> 20U) & 0xfffU; | ||
2626 | } | ||
2627 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) | ||
2628 | { | ||
2629 | return 0x00503018U; | ||
2630 | } | ||
2631 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) | ||
2632 | { | ||
2633 | return 0x1U << 0U; | ||
2634 | } | ||
2635 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) | ||
2636 | { | ||
2637 | return 0x1U; | ||
2638 | } | ||
2639 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) | ||
2640 | { | ||
2641 | return 0x005030c0U; | ||
2642 | } | ||
2643 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) | ||
2644 | { | ||
2645 | return (v & 0x3fffffU) << 0U; | ||
2646 | } | ||
2647 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) | ||
2648 | { | ||
2649 | return 0x3fffffU << 0U; | ||
2650 | } | ||
2651 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) | ||
2652 | { | ||
2653 | return 0x00000480U; | ||
2654 | } | ||
2655 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) | ||
2656 | { | ||
2657 | return 0x00000d10U; | ||
2658 | } | ||
2659 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) | ||
2660 | { | ||
2661 | return 0x00000020U; | ||
2662 | } | ||
2663 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) | ||
2664 | { | ||
2665 | return 0x005030f4U; | ||
2666 | } | ||
2667 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) | ||
2668 | { | ||
2669 | return 0x005030e4U; | ||
2670 | } | ||
2671 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) | ||
2672 | { | ||
2673 | return (v & 0xffffU) << 0U; | ||
2674 | } | ||
2675 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) | ||
2676 | { | ||
2677 | return 0xffffU << 0U; | ||
2678 | } | ||
2679 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) | ||
2680 | { | ||
2681 | return 0x00000800U; | ||
2682 | } | ||
2683 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) | ||
2684 | { | ||
2685 | return 0x00000020U; | ||
2686 | } | ||
2687 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) | ||
2688 | { | ||
2689 | return 0x005030f8U; | ||
2690 | } | ||
2691 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) | ||
2692 | { | ||
2693 | return 0x005030f0U; | ||
2694 | } | ||
2695 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) | ||
2696 | { | ||
2697 | return (v & 0x3fffffU) << 0U; | ||
2698 | } | ||
2699 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) | ||
2700 | { | ||
2701 | return 0x00000480U; | ||
2702 | } | ||
2703 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) | ||
2704 | { | ||
2705 | return 0x00419e00U; | ||
2706 | } | ||
2707 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) | ||
2708 | { | ||
2709 | return (v & 0xffffffffU) << 0U; | ||
2710 | } | ||
2711 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) | ||
2712 | { | ||
2713 | return 0x00419e04U; | ||
2714 | } | ||
2715 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) | ||
2716 | { | ||
2717 | return 21U; | ||
2718 | } | ||
2719 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) | ||
2720 | { | ||
2721 | return (v & 0x1fffffU) << 0U; | ||
2722 | } | ||
2723 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) | ||
2724 | { | ||
2725 | return 0x1fffffU << 0U; | ||
2726 | } | ||
2727 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) | ||
2728 | { | ||
2729 | return (r >> 0U) & 0x1fffffU; | ||
2730 | } | ||
2731 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) | ||
2732 | { | ||
2733 | return 0x80U; | ||
2734 | } | ||
2735 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) | ||
2736 | { | ||
2737 | return 1U; | ||
2738 | } | ||
2739 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) | ||
2740 | { | ||
2741 | return (v & 0x1U) << 31U; | ||
2742 | } | ||
2743 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) | ||
2744 | { | ||
2745 | return 0x1U << 31U; | ||
2746 | } | ||
2747 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) | ||
2748 | { | ||
2749 | return (r >> 31U) & 0x1U; | ||
2750 | } | ||
2751 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) | ||
2752 | { | ||
2753 | return 0x80000000U; | ||
2754 | } | ||
2755 | static inline u32 gr_gpccs_falcon_addr_r(void) | ||
2756 | { | ||
2757 | return 0x0041a0acU; | ||
2758 | } | ||
2759 | static inline u32 gr_gpccs_falcon_addr_lsb_s(void) | ||
2760 | { | ||
2761 | return 6U; | ||
2762 | } | ||
2763 | static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) | ||
2764 | { | ||
2765 | return (v & 0x3fU) << 0U; | ||
2766 | } | ||
2767 | static inline u32 gr_gpccs_falcon_addr_lsb_m(void) | ||
2768 | { | ||
2769 | return 0x3fU << 0U; | ||
2770 | } | ||
2771 | static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) | ||
2772 | { | ||
2773 | return (r >> 0U) & 0x3fU; | ||
2774 | } | ||
2775 | static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) | ||
2776 | { | ||
2777 | return 0x00000000U; | ||
2778 | } | ||
2779 | static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) | ||
2780 | { | ||
2781 | return 0x0U; | ||
2782 | } | ||
2783 | static inline u32 gr_gpccs_falcon_addr_msb_s(void) | ||
2784 | { | ||
2785 | return 6U; | ||
2786 | } | ||
2787 | static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) | ||
2788 | { | ||
2789 | return (v & 0x3fU) << 6U; | ||
2790 | } | ||
2791 | static inline u32 gr_gpccs_falcon_addr_msb_m(void) | ||
2792 | { | ||
2793 | return 0x3fU << 6U; | ||
2794 | } | ||
2795 | static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) | ||
2796 | { | ||
2797 | return (r >> 6U) & 0x3fU; | ||
2798 | } | ||
2799 | static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) | ||
2800 | { | ||
2801 | return 0x00000000U; | ||
2802 | } | ||
2803 | static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) | ||
2804 | { | ||
2805 | return 0x0U; | ||
2806 | } | ||
2807 | static inline u32 gr_gpccs_falcon_addr_ext_s(void) | ||
2808 | { | ||
2809 | return 12U; | ||
2810 | } | ||
2811 | static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) | ||
2812 | { | ||
2813 | return (v & 0xfffU) << 0U; | ||
2814 | } | ||
2815 | static inline u32 gr_gpccs_falcon_addr_ext_m(void) | ||
2816 | { | ||
2817 | return 0xfffU << 0U; | ||
2818 | } | ||
2819 | static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) | ||
2820 | { | ||
2821 | return (r >> 0U) & 0xfffU; | ||
2822 | } | ||
2823 | static inline u32 gr_gpccs_cpuctl_r(void) | ||
2824 | { | ||
2825 | return 0x0041a100U; | ||
2826 | } | ||
2827 | static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) | ||
2828 | { | ||
2829 | return (v & 0x1U) << 1U; | ||
2830 | } | ||
2831 | static inline u32 gr_gpccs_dmactl_r(void) | ||
2832 | { | ||
2833 | return 0x0041a10cU; | ||
2834 | } | ||
2835 | static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) | ||
2836 | { | ||
2837 | return (v & 0x1U) << 0U; | ||
2838 | } | ||
2839 | static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) | ||
2840 | { | ||
2841 | return 0x1U << 1U; | ||
2842 | } | ||
2843 | static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) | ||
2844 | { | ||
2845 | return 0x1U << 2U; | ||
2846 | } | ||
2847 | static inline u32 gr_gpccs_imemc_r(u32 i) | ||
2848 | { | ||
2849 | return 0x0041a180U + i*16U; | ||
2850 | } | ||
2851 | static inline u32 gr_gpccs_imemc_offs_f(u32 v) | ||
2852 | { | ||
2853 | return (v & 0x3fU) << 2U; | ||
2854 | } | ||
2855 | static inline u32 gr_gpccs_imemc_blk_f(u32 v) | ||
2856 | { | ||
2857 | return (v & 0xffU) << 8U; | ||
2858 | } | ||
2859 | static inline u32 gr_gpccs_imemc_aincw_f(u32 v) | ||
2860 | { | ||
2861 | return (v & 0x1U) << 24U; | ||
2862 | } | ||
2863 | static inline u32 gr_gpccs_imemd_r(u32 i) | ||
2864 | { | ||
2865 | return 0x0041a184U + i*16U; | ||
2866 | } | ||
2867 | static inline u32 gr_gpccs_imemt_r(u32 i) | ||
2868 | { | ||
2869 | return 0x0041a188U + i*16U; | ||
2870 | } | ||
2871 | static inline u32 gr_gpccs_imemt__size_1_v(void) | ||
2872 | { | ||
2873 | return 0x00000004U; | ||
2874 | } | ||
2875 | static inline u32 gr_gpccs_imemt_tag_f(u32 v) | ||
2876 | { | ||
2877 | return (v & 0xffffU) << 0U; | ||
2878 | } | ||
2879 | static inline u32 gr_gpccs_dmemc_r(u32 i) | ||
2880 | { | ||
2881 | return 0x0041a1c0U + i*8U; | ||
2882 | } | ||
2883 | static inline u32 gr_gpccs_dmemc_offs_f(u32 v) | ||
2884 | { | ||
2885 | return (v & 0x3fU) << 2U; | ||
2886 | } | ||
2887 | static inline u32 gr_gpccs_dmemc_blk_f(u32 v) | ||
2888 | { | ||
2889 | return (v & 0xffU) << 8U; | ||
2890 | } | ||
2891 | static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) | ||
2892 | { | ||
2893 | return (v & 0x1U) << 24U; | ||
2894 | } | ||
2895 | static inline u32 gr_gpccs_dmemd_r(u32 i) | ||
2896 | { | ||
2897 | return 0x0041a1c4U + i*8U; | ||
2898 | } | ||
2899 | static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) | ||
2900 | { | ||
2901 | return 0x0041a800U + i*4U; | ||
2902 | } | ||
2903 | static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) | ||
2904 | { | ||
2905 | return (v & 0xffffffffU) << 0U; | ||
2906 | } | ||
2907 | static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) | ||
2908 | { | ||
2909 | return 0x00418e24U; | ||
2910 | } | ||
2911 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) | ||
2912 | { | ||
2913 | return 32U; | ||
2914 | } | ||
2915 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) | ||
2916 | { | ||
2917 | return (v & 0xffffffffU) << 0U; | ||
2918 | } | ||
2919 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) | ||
2920 | { | ||
2921 | return 0xffffffffU << 0U; | ||
2922 | } | ||
2923 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) | ||
2924 | { | ||
2925 | return (r >> 0U) & 0xffffffffU; | ||
2926 | } | ||
2927 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) | ||
2928 | { | ||
2929 | return 0x00000000U; | ||
2930 | } | ||
2931 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) | ||
2932 | { | ||
2933 | return 0x0U; | ||
2934 | } | ||
2935 | static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) | ||
2936 | { | ||
2937 | return 0x00418e28U; | ||
2938 | } | ||
2939 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) | ||
2940 | { | ||
2941 | return 11U; | ||
2942 | } | ||
2943 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) | ||
2944 | { | ||
2945 | return (v & 0x7ffU) << 0U; | ||
2946 | } | ||
2947 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) | ||
2948 | { | ||
2949 | return 0x7ffU << 0U; | ||
2950 | } | ||
2951 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) | ||
2952 | { | ||
2953 | return (r >> 0U) & 0x7ffU; | ||
2954 | } | ||
2955 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) | ||
2956 | { | ||
2957 | return 0x00000030U; | ||
2958 | } | ||
2959 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) | ||
2960 | { | ||
2961 | return 0x30U; | ||
2962 | } | ||
2963 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) | ||
2964 | { | ||
2965 | return 1U; | ||
2966 | } | ||
2967 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) | ||
2968 | { | ||
2969 | return (v & 0x1U) << 31U; | ||
2970 | } | ||
2971 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) | ||
2972 | { | ||
2973 | return 0x1U << 31U; | ||
2974 | } | ||
2975 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) | ||
2976 | { | ||
2977 | return (r >> 31U) & 0x1U; | ||
2978 | } | ||
2979 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) | ||
2980 | { | ||
2981 | return 0x00000000U; | ||
2982 | } | ||
2983 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) | ||
2984 | { | ||
2985 | return 0x0U; | ||
2986 | } | ||
2987 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) | ||
2988 | { | ||
2989 | return 0x00000001U; | ||
2990 | } | ||
2991 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) | ||
2992 | { | ||
2993 | return 0x80000000U; | ||
2994 | } | ||
2995 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) | ||
2996 | { | ||
2997 | return 0x005001dcU; | ||
2998 | } | ||
2999 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) | ||
3000 | { | ||
3001 | return (v & 0xffffU) << 0U; | ||
3002 | } | ||
3003 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) | ||
3004 | { | ||
3005 | return 0x000004b0U; | ||
3006 | } | ||
3007 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) | ||
3008 | { | ||
3009 | return 0x00000100U; | ||
3010 | } | ||
3011 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) | ||
3012 | { | ||
3013 | return 0x005001d8U; | ||
3014 | } | ||
3015 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) | ||
3016 | { | ||
3017 | return (v & 0xffffffffU) << 0U; | ||
3018 | } | ||
3019 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) | ||
3020 | { | ||
3021 | return 0x00000008U; | ||
3022 | } | ||
3023 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) | ||
3024 | { | ||
3025 | return 0x004181e4U; | ||
3026 | } | ||
3027 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) | ||
3028 | { | ||
3029 | return (v & 0xfffU) << 0U; | ||
3030 | } | ||
3031 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) | ||
3032 | { | ||
3033 | return 0x00000100U; | ||
3034 | } | ||
3035 | static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) | ||
3036 | { | ||
3037 | return 0x0041befcU; | ||
3038 | } | ||
3039 | static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) | ||
3040 | { | ||
3041 | return (v & 0xfffU) << 0U; | ||
3042 | } | ||
3043 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) | ||
3044 | { | ||
3045 | return 0x00418ea0U + i*4U; | ||
3046 | } | ||
3047 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) | ||
3048 | { | ||
3049 | return (v & 0x3fffffU) << 0U; | ||
3050 | } | ||
3051 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) | ||
3052 | { | ||
3053 | return 0x3fffffU << 0U; | ||
3054 | } | ||
3055 | static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) | ||
3056 | { | ||
3057 | return 0x00418010U + i*4U; | ||
3058 | } | ||
3059 | static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) | ||
3060 | { | ||
3061 | return (v & 0xffffffffU) << 0U; | ||
3062 | } | ||
3063 | static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) | ||
3064 | { | ||
3065 | return 0x0041804cU + i*4U; | ||
3066 | } | ||
3067 | static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) | ||
3068 | { | ||
3069 | return (v & 0xffffffffU) << 0U; | ||
3070 | } | ||
3071 | static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) | ||
3072 | { | ||
3073 | return 0x00418088U + i*4U; | ||
3074 | } | ||
3075 | static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) | ||
3076 | { | ||
3077 | return (v & 0xffffffffU) << 0U; | ||
3078 | } | ||
3079 | static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) | ||
3080 | { | ||
3081 | return 0x004180c4U + i*4U; | ||
3082 | } | ||
3083 | static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) | ||
3084 | { | ||
3085 | return (v & 0xffffffffU) << 0U; | ||
3086 | } | ||
3087 | static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) | ||
3088 | { | ||
3089 | return 0x00418100U; | ||
3090 | } | ||
3091 | static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) | ||
3092 | { | ||
3093 | return 0x00418110U + i*4U; | ||
3094 | } | ||
3095 | static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) | ||
3096 | { | ||
3097 | return (v & 0xffffffffU) << 0U; | ||
3098 | } | ||
3099 | static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) | ||
3100 | { | ||
3101 | return 0x0041814cU; | ||
3102 | } | ||
3103 | static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) | ||
3104 | { | ||
3105 | return 0x0041815cU + i*4U; | ||
3106 | } | ||
3107 | static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) | ||
3108 | { | ||
3109 | return (v & 0xffU) << 0U; | ||
3110 | } | ||
3111 | static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) | ||
3112 | { | ||
3113 | return 0x00418198U; | ||
3114 | } | ||
3115 | static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) | ||
3116 | { | ||
3117 | return 0x00418810U; | ||
3118 | } | ||
3119 | static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) | ||
3120 | { | ||
3121 | return (v & 0xfffffffU) << 0U; | ||
3122 | } | ||
3123 | static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) | ||
3124 | { | ||
3125 | return 0x0000000cU; | ||
3126 | } | ||
3127 | static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) | ||
3128 | { | ||
3129 | return 0x80000000U; | ||
3130 | } | ||
3131 | static inline u32 gr_crstr_gpc_map_r(u32 i) | ||
3132 | { | ||
3133 | return 0x00418b08U + i*4U; | ||
3134 | } | ||
3135 | static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) | ||
3136 | { | ||
3137 | return (v & 0x1fU) << 0U; | ||
3138 | } | ||
3139 | static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) | ||
3140 | { | ||
3141 | return (v & 0x1fU) << 5U; | ||
3142 | } | ||
3143 | static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) | ||
3144 | { | ||
3145 | return (v & 0x1fU) << 10U; | ||
3146 | } | ||
3147 | static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) | ||
3148 | { | ||
3149 | return (v & 0x1fU) << 15U; | ||
3150 | } | ||
3151 | static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) | ||
3152 | { | ||
3153 | return (v & 0x1fU) << 20U; | ||
3154 | } | ||
3155 | static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) | ||
3156 | { | ||
3157 | return (v & 0x1fU) << 25U; | ||
3158 | } | ||
3159 | static inline u32 gr_crstr_map_table_cfg_r(void) | ||
3160 | { | ||
3161 | return 0x00418bb8U; | ||
3162 | } | ||
3163 | static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) | ||
3164 | { | ||
3165 | return (v & 0xffU) << 0U; | ||
3166 | } | ||
3167 | static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) | ||
3168 | { | ||
3169 | return (v & 0xffU) << 8U; | ||
3170 | } | ||
3171 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) | ||
3172 | { | ||
3173 | return 0x00418980U + i*4U; | ||
3174 | } | ||
3175 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) | ||
3176 | { | ||
3177 | return (v & 0x7U) << 0U; | ||
3178 | } | ||
3179 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) | ||
3180 | { | ||
3181 | return (v & 0x7U) << 4U; | ||
3182 | } | ||
3183 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) | ||
3184 | { | ||
3185 | return (v & 0x7U) << 8U; | ||
3186 | } | ||
3187 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) | ||
3188 | { | ||
3189 | return (v & 0x7U) << 12U; | ||
3190 | } | ||
3191 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) | ||
3192 | { | ||
3193 | return (v & 0x7U) << 16U; | ||
3194 | } | ||
3195 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) | ||
3196 | { | ||
3197 | return (v & 0x7U) << 20U; | ||
3198 | } | ||
3199 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) | ||
3200 | { | ||
3201 | return (v & 0x7U) << 24U; | ||
3202 | } | ||
3203 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) | ||
3204 | { | ||
3205 | return (v & 0x7U) << 28U; | ||
3206 | } | ||
3207 | static inline u32 gr_gpcs_gpm_pd_cfg_r(void) | ||
3208 | { | ||
3209 | return 0x00418c6cU; | ||
3210 | } | ||
3211 | static inline u32 gr_gpcs_gcc_pagepool_base_r(void) | ||
3212 | { | ||
3213 | return 0x00419004U; | ||
3214 | } | ||
3215 | static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) | ||
3216 | { | ||
3217 | return (v & 0xffffffffU) << 0U; | ||
3218 | } | ||
3219 | static inline u32 gr_gpcs_gcc_pagepool_r(void) | ||
3220 | { | ||
3221 | return 0x00419008U; | ||
3222 | } | ||
3223 | static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) | ||
3224 | { | ||
3225 | return (v & 0x3ffU) << 0U; | ||
3226 | } | ||
3227 | static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) | ||
3228 | { | ||
3229 | return 0x0041980cU; | ||
3230 | } | ||
3231 | static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) | ||
3232 | { | ||
3233 | return 0x10U; | ||
3234 | } | ||
3235 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) | ||
3236 | { | ||
3237 | return 0x00419848U; | ||
3238 | } | ||
3239 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) | ||
3240 | { | ||
3241 | return (v & 0xfffffffU) << 0U; | ||
3242 | } | ||
3243 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) | ||
3244 | { | ||
3245 | return (v & 0x1U) << 28U; | ||
3246 | } | ||
3247 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) | ||
3248 | { | ||
3249 | return 0x10000000U; | ||
3250 | } | ||
3251 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) | ||
3252 | { | ||
3253 | return 0x00419c00U; | ||
3254 | } | ||
3255 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) | ||
3256 | { | ||
3257 | return 0x0U; | ||
3258 | } | ||
3259 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) | ||
3260 | { | ||
3261 | return 0x8U; | ||
3262 | } | ||
3263 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) | ||
3264 | { | ||
3265 | return 0x00419c2cU; | ||
3266 | } | ||
3267 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) | ||
3268 | { | ||
3269 | return (v & 0xfffffffU) << 0U; | ||
3270 | } | ||
3271 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) | ||
3272 | { | ||
3273 | return (v & 0x1U) << 28U; | ||
3274 | } | ||
3275 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | ||
3276 | { | ||
3277 | return 0x10000000U; | ||
3278 | } | ||
3279 | static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) | ||
3280 | { | ||
3281 | return 0x00419ea8U; | ||
3282 | } | ||
3283 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) | ||
3284 | { | ||
3285 | return 0x00504728U; | ||
3286 | } | ||
3287 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) | ||
3288 | { | ||
3289 | return 0x2U; | ||
3290 | } | ||
3291 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) | ||
3292 | { | ||
3293 | return 0x4U; | ||
3294 | } | ||
3295 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) | ||
3296 | { | ||
3297 | return 0x10U; | ||
3298 | } | ||
3299 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) | ||
3300 | { | ||
3301 | return 0x20U; | ||
3302 | } | ||
3303 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) | ||
3304 | { | ||
3305 | return 0x40U; | ||
3306 | } | ||
3307 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) | ||
3308 | { | ||
3309 | return 0x100U; | ||
3310 | } | ||
3311 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) | ||
3312 | { | ||
3313 | return 0x200U; | ||
3314 | } | ||
3315 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) | ||
3316 | { | ||
3317 | return 0x800U; | ||
3318 | } | ||
3319 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) | ||
3320 | { | ||
3321 | return 0x2000U; | ||
3322 | } | ||
3323 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) | ||
3324 | { | ||
3325 | return 0x4000U; | ||
3326 | } | ||
3327 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) | ||
3328 | { | ||
3329 | return 0x8000U; | ||
3330 | } | ||
3331 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) | ||
3332 | { | ||
3333 | return 0x10000U; | ||
3334 | } | ||
3335 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) | ||
3336 | { | ||
3337 | return 0x40000U; | ||
3338 | } | ||
3339 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) | ||
3340 | { | ||
3341 | return 0x800000U; | ||
3342 | } | ||
3343 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) | ||
3344 | { | ||
3345 | return 0x400000U; | ||
3346 | } | ||
3347 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) | ||
3348 | { | ||
3349 | return 0x00419d0cU; | ||
3350 | } | ||
3351 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) | ||
3352 | { | ||
3353 | return 0x2U; | ||
3354 | } | ||
3355 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) | ||
3356 | { | ||
3357 | return 0x1U; | ||
3358 | } | ||
3359 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) | ||
3360 | { | ||
3361 | return 0x10U; | ||
3362 | } | ||
3363 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | ||
3364 | { | ||
3365 | return 0x0050450cU; | ||
3366 | } | ||
3367 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) | ||
3368 | { | ||
3369 | return (r >> 1U) & 0x1U; | ||
3370 | } | ||
3371 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | ||
3372 | { | ||
3373 | return 0x2U; | ||
3374 | } | ||
3375 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) | ||
3376 | { | ||
3377 | return 0x10U; | ||
3378 | } | ||
3379 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) | ||
3380 | { | ||
3381 | return 0x0041ac94U; | ||
3382 | } | ||
3383 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) | ||
3384 | { | ||
3385 | return (v & 0x1U) << 2U; | ||
3386 | } | ||
3387 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) | ||
3388 | { | ||
3389 | return (v & 0xffU) << 16U; | ||
3390 | } | ||
3391 | static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) | ||
3392 | { | ||
3393 | return 0x00502c90U; | ||
3394 | } | ||
3395 | static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) | ||
3396 | { | ||
3397 | return (r >> 2U) & 0x1U; | ||
3398 | } | ||
3399 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) | ||
3400 | { | ||
3401 | return (r >> 16U) & 0xffU; | ||
3402 | } | ||
3403 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) | ||
3404 | { | ||
3405 | return 0x00000001U; | ||
3406 | } | ||
3407 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) | ||
3408 | { | ||
3409 | return 0x00504508U; | ||
3410 | } | ||
3411 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) | ||
3412 | { | ||
3413 | return (r >> 0U) & 0x1U; | ||
3414 | } | ||
3415 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) | ||
3416 | { | ||
3417 | return 0x00000001U; | ||
3418 | } | ||
3419 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) | ||
3420 | { | ||
3421 | return (r >> 1U) & 0x1U; | ||
3422 | } | ||
3423 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) | ||
3424 | { | ||
3425 | return 0x00000001U; | ||
3426 | } | ||
3427 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) | ||
3428 | { | ||
3429 | return 0x1U << 4U; | ||
3430 | } | ||
3431 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) | ||
3432 | { | ||
3433 | return 0x10U; | ||
3434 | } | ||
3435 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) | ||
3436 | { | ||
3437 | return 0x00504704U; | ||
3438 | } | ||
3439 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) | ||
3440 | { | ||
3441 | return 0x1U << 0U; | ||
3442 | } | ||
3443 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) | ||
3444 | { | ||
3445 | return (r >> 0U) & 0x1U; | ||
3446 | } | ||
3447 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) | ||
3448 | { | ||
3449 | return 0x00000001U; | ||
3450 | } | ||
3451 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) | ||
3452 | { | ||
3453 | return 0x1U; | ||
3454 | } | ||
3455 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) | ||
3456 | { | ||
3457 | return 0x00000000U; | ||
3458 | } | ||
3459 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) | ||
3460 | { | ||
3461 | return 0x0U; | ||
3462 | } | ||
3463 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) | ||
3464 | { | ||
3465 | return 0x1U << 31U; | ||
3466 | } | ||
3467 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) | ||
3468 | { | ||
3469 | return 0x80000000U; | ||
3470 | } | ||
3471 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) | ||
3472 | { | ||
3473 | return 0x0U; | ||
3474 | } | ||
3475 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) | ||
3476 | { | ||
3477 | return 0x1U << 3U; | ||
3478 | } | ||
3479 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) | ||
3480 | { | ||
3481 | return 0x8U; | ||
3482 | } | ||
3483 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) | ||
3484 | { | ||
3485 | return 0x0U; | ||
3486 | } | ||
3487 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) | ||
3488 | { | ||
3489 | return 0x40000000U; | ||
3490 | } | ||
3491 | static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) | ||
3492 | { | ||
3493 | return 0x00504708U; | ||
3494 | } | ||
3495 | static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) | ||
3496 | { | ||
3497 | return 0x0050470cU; | ||
3498 | } | ||
3499 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) | ||
3500 | { | ||
3501 | return 0x00504710U; | ||
3502 | } | ||
3503 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) | ||
3504 | { | ||
3505 | return 0x00504714U; | ||
3506 | } | ||
3507 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) | ||
3508 | { | ||
3509 | return 0x00504718U; | ||
3510 | } | ||
3511 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) | ||
3512 | { | ||
3513 | return 0x0050471cU; | ||
3514 | } | ||
3515 | static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) | ||
3516 | { | ||
3517 | return 0x00419e90U; | ||
3518 | } | ||
3519 | static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) | ||
3520 | { | ||
3521 | return 0x00419e94U; | ||
3522 | } | ||
3523 | static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) | ||
3524 | { | ||
3525 | return 0x00419e80U; | ||
3526 | } | ||
3527 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) | ||
3528 | { | ||
3529 | return 0x00504700U; | ||
3530 | } | ||
3531 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) | ||
3532 | { | ||
3533 | return (r >> 0U) & 0x1U; | ||
3534 | } | ||
3535 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) | ||
3536 | { | ||
3537 | return (r >> 4U) & 0x1U; | ||
3538 | } | ||
3539 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) | ||
3540 | { | ||
3541 | return 0x00000001U; | ||
3542 | } | ||
3543 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) | ||
3544 | { | ||
3545 | return 0x00504730U; | ||
3546 | } | ||
3547 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) | ||
3548 | { | ||
3549 | return (r >> 0U) & 0xffffU; | ||
3550 | } | ||
3551 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) | ||
3552 | { | ||
3553 | return 0x00000000U; | ||
3554 | } | ||
3555 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) | ||
3556 | { | ||
3557 | return 0x0U; | ||
3558 | } | ||
3559 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) | ||
3560 | { | ||
3561 | return 0xffU << 16U; | ||
3562 | } | ||
3563 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) | ||
3564 | { | ||
3565 | return 0xfU << 24U; | ||
3566 | } | ||
3567 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) | ||
3568 | { | ||
3569 | return 0x0U; | ||
3570 | } | ||
3571 | static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) | ||
3572 | { | ||
3573 | return 0x0050460cU; | ||
3574 | } | ||
3575 | static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) | ||
3576 | { | ||
3577 | return (r >> 0U) & 0x1U; | ||
3578 | } | ||
3579 | static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) | ||
3580 | { | ||
3581 | return (r >> 1U) & 0x1U; | ||
3582 | } | ||
3583 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) | ||
3584 | { | ||
3585 | return 0x00504738U; | ||
3586 | } | ||
3587 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) | ||
3588 | { | ||
3589 | return 0x005043a0U; | ||
3590 | } | ||
3591 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) | ||
3592 | { | ||
3593 | return 0x00419ba0U; | ||
3594 | } | ||
3595 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) | ||
3596 | { | ||
3597 | return 0x1U << 4U; | ||
3598 | } | ||
3599 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) | ||
3600 | { | ||
3601 | return (v & 0x1U) << 4U; | ||
3602 | } | ||
3603 | static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) | ||
3604 | { | ||
3605 | return 0x005043b0U; | ||
3606 | } | ||
3607 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) | ||
3608 | { | ||
3609 | return 0x00419bb0U; | ||
3610 | } | ||
3611 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) | ||
3612 | { | ||
3613 | return 0x1U << 0U; | ||
3614 | } | ||
3615 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) | ||
3616 | { | ||
3617 | return (v & 0x1U) << 0U; | ||
3618 | } | ||
3619 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) | ||
3620 | { | ||
3621 | return 0x0041be08U; | ||
3622 | } | ||
3623 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) | ||
3624 | { | ||
3625 | return 0x4U; | ||
3626 | } | ||
3627 | static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) | ||
3628 | { | ||
3629 | return 0x0041bf00U + i*4U; | ||
3630 | } | ||
3631 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) | ||
3632 | { | ||
3633 | return 0x0041bfd0U; | ||
3634 | } | ||
3635 | static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) | ||
3636 | { | ||
3637 | return (v & 0xffU) << 0U; | ||
3638 | } | ||
3639 | static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) | ||
3640 | { | ||
3641 | return (v & 0xffU) << 8U; | ||
3642 | } | ||
3643 | static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) | ||
3644 | { | ||
3645 | return (v & 0x1fU) << 16U; | ||
3646 | } | ||
3647 | static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) | ||
3648 | { | ||
3649 | return (v & 0x7U) << 21U; | ||
3650 | } | ||
3651 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) | ||
3652 | { | ||
3653 | return 0x0041bfd4U; | ||
3654 | } | ||
3655 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) | ||
3656 | { | ||
3657 | return (v & 0xffffffU) << 0U; | ||
3658 | } | ||
3659 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) | ||
3660 | { | ||
3661 | return 0x0041bfb0U + i*4U; | ||
3662 | } | ||
3663 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) | ||
3664 | { | ||
3665 | return 0x00000005U; | ||
3666 | } | ||
3667 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) | ||
3668 | { | ||
3669 | return (v & 0xffU) << 0U; | ||
3670 | } | ||
3671 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) | ||
3672 | { | ||
3673 | return (v & 0xffU) << 8U; | ||
3674 | } | ||
3675 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) | ||
3676 | { | ||
3677 | return (v & 0xffU) << 16U; | ||
3678 | } | ||
3679 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) | ||
3680 | { | ||
3681 | return (v & 0xffU) << 24U; | ||
3682 | } | ||
3683 | static inline u32 gr_bes_zrop_settings_r(void) | ||
3684 | { | ||
3685 | return 0x00408850U; | ||
3686 | } | ||
3687 | static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) | ||
3688 | { | ||
3689 | return (v & 0xfU) << 0U; | ||
3690 | } | ||
3691 | static inline u32 gr_be0_crop_debug3_r(void) | ||
3692 | { | ||
3693 | return 0x00410108U; | ||
3694 | } | ||
3695 | static inline u32 gr_bes_crop_debug3_r(void) | ||
3696 | { | ||
3697 | return 0x00408908U; | ||
3698 | } | ||
3699 | static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) | ||
3700 | { | ||
3701 | return 0x1U << 31U; | ||
3702 | } | ||
3703 | static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) | ||
3704 | { | ||
3705 | return 0x1U << 1U; | ||
3706 | } | ||
3707 | static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) | ||
3708 | { | ||
3709 | return 0x0U; | ||
3710 | } | ||
3711 | static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) | ||
3712 | { | ||
3713 | return 0x2U; | ||
3714 | } | ||
3715 | static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) | ||
3716 | { | ||
3717 | return 0x1U << 2U; | ||
3718 | } | ||
3719 | static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) | ||
3720 | { | ||
3721 | return 0x0U; | ||
3722 | } | ||
3723 | static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) | ||
3724 | { | ||
3725 | return 0x4U; | ||
3726 | } | ||
3727 | static inline u32 gr_bes_crop_settings_r(void) | ||
3728 | { | ||
3729 | return 0x00408958U; | ||
3730 | } | ||
3731 | static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) | ||
3732 | { | ||
3733 | return (v & 0xfU) << 0U; | ||
3734 | } | ||
3735 | static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) | ||
3736 | { | ||
3737 | return 0x00000020U; | ||
3738 | } | ||
3739 | static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) | ||
3740 | { | ||
3741 | return 0x00000020U; | ||
3742 | } | ||
3743 | static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) | ||
3744 | { | ||
3745 | return 0x000000c0U; | ||
3746 | } | ||
3747 | static inline u32 gr_zcull_subregion_qty_v(void) | ||
3748 | { | ||
3749 | return 0x00000010U; | ||
3750 | } | ||
3751 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) | ||
3752 | { | ||
3753 | return 0x00419a00U; | ||
3754 | } | ||
3755 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) | ||
3756 | { | ||
3757 | return (v & 0x1U) << 19U; | ||
3758 | } | ||
3759 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) | ||
3760 | { | ||
3761 | return 0x1U << 19U; | ||
3762 | } | ||
3763 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) | ||
3764 | { | ||
3765 | return 0x00419bf0U; | ||
3766 | } | ||
3767 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) | ||
3768 | { | ||
3769 | return (v & 0x1U) << 5U; | ||
3770 | } | ||
3771 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) | ||
3772 | { | ||
3773 | return 0x1U << 5U; | ||
3774 | } | ||
3775 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) | ||
3776 | { | ||
3777 | return (v & 0x1U) << 10U; | ||
3778 | } | ||
3779 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) | ||
3780 | { | ||
3781 | return 0x1U << 10U; | ||
3782 | } | ||
3783 | static inline u32 gr_fe_pwr_mode_r(void) | ||
3784 | { | ||
3785 | return 0x00404170U; | ||
3786 | } | ||
3787 | static inline u32 gr_fe_pwr_mode_mode_auto_f(void) | ||
3788 | { | ||
3789 | return 0x0U; | ||
3790 | } | ||
3791 | static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) | ||
3792 | { | ||
3793 | return 0x2U; | ||
3794 | } | ||
3795 | static inline u32 gr_fe_pwr_mode_req_v(u32 r) | ||
3796 | { | ||
3797 | return (r >> 4U) & 0x1U; | ||
3798 | } | ||
3799 | static inline u32 gr_fe_pwr_mode_req_send_f(void) | ||
3800 | { | ||
3801 | return 0x10U; | ||
3802 | } | ||
3803 | static inline u32 gr_fe_pwr_mode_req_done_v(void) | ||
3804 | { | ||
3805 | return 0x00000000U; | ||
3806 | } | ||
3807 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) | ||
3808 | { | ||
3809 | return 0x00418880U; | ||
3810 | } | ||
3811 | static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) | ||
3812 | { | ||
3813 | return 0x1U << 0U; | ||
3814 | } | ||
3815 | static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) | ||
3816 | { | ||
3817 | return 0x1U << 11U; | ||
3818 | } | ||
3819 | static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) | ||
3820 | { | ||
3821 | return 0x1U << 1U; | ||
3822 | } | ||
3823 | static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) | ||
3824 | { | ||
3825 | return 0x1U << 2U; | ||
3826 | } | ||
3827 | static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) | ||
3828 | { | ||
3829 | return 0x3U << 3U; | ||
3830 | } | ||
3831 | static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) | ||
3832 | { | ||
3833 | return 0x3U << 5U; | ||
3834 | } | ||
3835 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) | ||
3836 | { | ||
3837 | return 0x3U << 28U; | ||
3838 | } | ||
3839 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) | ||
3840 | { | ||
3841 | return 0x1U << 30U; | ||
3842 | } | ||
3843 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) | ||
3844 | { | ||
3845 | return 0x1U << 31U; | ||
3846 | } | ||
3847 | static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) | ||
3848 | { | ||
3849 | return 0x00418890U; | ||
3850 | } | ||
3851 | static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) | ||
3852 | { | ||
3853 | return 0x00418894U; | ||
3854 | } | ||
3855 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) | ||
3856 | { | ||
3857 | return 0x004188b0U; | ||
3858 | } | ||
3859 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) | ||
3860 | { | ||
3861 | return (r >> 16U) & 0x1U; | ||
3862 | } | ||
3863 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) | ||
3864 | { | ||
3865 | return 0x00000001U; | ||
3866 | } | ||
3867 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) | ||
3868 | { | ||
3869 | return 0x004188b4U; | ||
3870 | } | ||
3871 | static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) | ||
3872 | { | ||
3873 | return 0x004188b8U; | ||
3874 | } | ||
3875 | static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) | ||
3876 | { | ||
3877 | return 0x004188acU; | ||
3878 | } | ||
3879 | static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) | ||
3880 | { | ||
3881 | return 0x00419e84U; | ||
3882 | } | ||
3883 | static inline u32 gr_fe_gfxp_wfi_timeout_r(void) | ||
3884 | { | ||
3885 | return 0x004041c0U; | ||
3886 | } | ||
3887 | static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) | ||
3888 | { | ||
3889 | return (v & 0xffffffffU) << 0U; | ||
3890 | } | ||
3891 | static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) | ||
3892 | { | ||
3893 | return 0x0U; | ||
3894 | } | ||
3895 | static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) | ||
3896 | { | ||
3897 | return 0x00419bd8U; | ||
3898 | } | ||
3899 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) | ||
3900 | { | ||
3901 | return (v & 0x7U) << 8U; | ||
3902 | } | ||
3903 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) | ||
3904 | { | ||
3905 | return 0x7U << 8U; | ||
3906 | } | ||
3907 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) | ||
3908 | { | ||
3909 | return 0x100U; | ||
3910 | } | ||
3911 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) | ||
3912 | { | ||
3913 | return 0x00419ba4U; | ||
3914 | } | ||
3915 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) | ||
3916 | { | ||
3917 | return 0x3U << 11U; | ||
3918 | } | ||
3919 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) | ||
3920 | { | ||
3921 | return 0x1000U; | ||
3922 | } | ||
3923 | static inline u32 gr_gpcs_tc_debug0_r(void) | ||
3924 | { | ||
3925 | return 0x00418708U; | ||
3926 | } | ||
3927 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) | ||
3928 | { | ||
3929 | return (v & 0x1ffU) << 0U; | ||
3930 | } | ||
3931 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) | ||
3932 | { | ||
3933 | return 0x1ffU << 0U; | ||
3934 | } | ||
3935 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h new file mode 100644 index 00000000..3543f0b7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h | |||
@@ -0,0 +1,619 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ltc_gv100_h_ | ||
57 | #define _hw_ltc_gv100_h_ | ||
58 | |||
59 | static inline u32 ltc_pltcg_base_v(void) | ||
60 | { | ||
61 | return 0x00140000U; | ||
62 | } | ||
63 | static inline u32 ltc_pltcg_extent_v(void) | ||
64 | { | ||
65 | return 0x0017ffffU; | ||
66 | } | ||
67 | static inline u32 ltc_ltc0_ltss_v(void) | ||
68 | { | ||
69 | return 0x00140200U; | ||
70 | } | ||
71 | static inline u32 ltc_ltc0_lts0_v(void) | ||
72 | { | ||
73 | return 0x00140400U; | ||
74 | } | ||
75 | static inline u32 ltc_ltcs_ltss_v(void) | ||
76 | { | ||
77 | return 0x0017e200U; | ||
78 | } | ||
79 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | ||
80 | { | ||
81 | return 0x0014046cU; | ||
82 | } | ||
83 | static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) | ||
84 | { | ||
85 | return 0x00140518U; | ||
86 | } | ||
87 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) | ||
88 | { | ||
89 | return 0x0017e318U; | ||
90 | } | ||
91 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) | ||
92 | { | ||
93 | return 0x1U << 15U; | ||
94 | } | ||
95 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) | ||
96 | { | ||
97 | return 0x00140494U; | ||
98 | } | ||
99 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) | ||
100 | { | ||
101 | return (r >> 0U) & 0xffffU; | ||
102 | } | ||
103 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) | ||
104 | { | ||
105 | return (r >> 16U) & 0x3U; | ||
106 | } | ||
107 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) | ||
108 | { | ||
109 | return 0x00000000U; | ||
110 | } | ||
111 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) | ||
112 | { | ||
113 | return 0x00000001U; | ||
114 | } | ||
115 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) | ||
116 | { | ||
117 | return 0x00000002U; | ||
118 | } | ||
119 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) | ||
120 | { | ||
121 | return 0x0017e26cU; | ||
122 | } | ||
123 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) | ||
124 | { | ||
125 | return 0x1U; | ||
126 | } | ||
127 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) | ||
128 | { | ||
129 | return 0x2U; | ||
130 | } | ||
131 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) | ||
132 | { | ||
133 | return (r >> 2U) & 0x1U; | ||
134 | } | ||
135 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) | ||
136 | { | ||
137 | return 0x00000001U; | ||
138 | } | ||
139 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) | ||
140 | { | ||
141 | return 0x4U; | ||
142 | } | ||
143 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) | ||
144 | { | ||
145 | return 0x0014046cU; | ||
146 | } | ||
147 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | ||
148 | { | ||
149 | return 0x0017e270U; | ||
150 | } | ||
151 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x3ffffU) << 0U; | ||
154 | } | ||
155 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | ||
156 | { | ||
157 | return 0x0017e274U; | ||
158 | } | ||
159 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x3ffffU) << 0U; | ||
162 | } | ||
163 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) | ||
164 | { | ||
165 | return 0x0003ffffU; | ||
166 | } | ||
167 | static inline u32 ltc_ltcs_ltss_cbc_base_r(void) | ||
168 | { | ||
169 | return 0x0017e278U; | ||
170 | } | ||
171 | static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) | ||
172 | { | ||
173 | return 0x0000000bU; | ||
174 | } | ||
175 | static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) | ||
176 | { | ||
177 | return (r >> 0U) & 0x3ffffffU; | ||
178 | } | ||
179 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) | ||
180 | { | ||
181 | return 0x0017e27cU; | ||
182 | } | ||
183 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) | ||
184 | { | ||
185 | return (r >> 0U) & 0x1fU; | ||
186 | } | ||
187 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 24U; | ||
190 | } | ||
191 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) | ||
192 | { | ||
193 | return (r >> 24U) & 0x1U; | ||
194 | } | ||
195 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x1U) << 25U; | ||
198 | } | ||
199 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) | ||
200 | { | ||
201 | return (r >> 25U) & 0x1U; | ||
202 | } | ||
203 | static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) | ||
204 | { | ||
205 | return 0x0017e000U; | ||
206 | } | ||
207 | static inline u32 ltc_ltcs_ltss_cbc_param_r(void) | ||
208 | { | ||
209 | return 0x0017e280U; | ||
210 | } | ||
211 | static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) | ||
212 | { | ||
213 | return (r >> 0U) & 0xffffU; | ||
214 | } | ||
215 | static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) | ||
216 | { | ||
217 | return (r >> 24U) & 0xfU; | ||
218 | } | ||
219 | static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) | ||
220 | { | ||
221 | return (r >> 28U) & 0xfU; | ||
222 | } | ||
223 | static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) | ||
224 | { | ||
225 | return 0x0017e3f4U; | ||
226 | } | ||
227 | static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) | ||
228 | { | ||
229 | return (r >> 0U) & 0xffffU; | ||
230 | } | ||
231 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) | ||
232 | { | ||
233 | return 0x0017e2acU; | ||
234 | } | ||
235 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1fU) << 16U; | ||
238 | } | ||
239 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) | ||
240 | { | ||
241 | return 0x0017e338U; | ||
242 | } | ||
243 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xfU) << 0U; | ||
246 | } | ||
247 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) | ||
248 | { | ||
249 | return 0x0017e33cU + i*4U; | ||
250 | } | ||
251 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) | ||
252 | { | ||
253 | return 0x00000004U; | ||
254 | } | ||
255 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) | ||
256 | { | ||
257 | return 0x0017e34cU; | ||
258 | } | ||
259 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) | ||
260 | { | ||
261 | return 32U; | ||
262 | } | ||
263 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) | ||
264 | { | ||
265 | return (v & 0xffffffffU) << 0U; | ||
266 | } | ||
267 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) | ||
268 | { | ||
269 | return 0xffffffffU << 0U; | ||
270 | } | ||
271 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) | ||
272 | { | ||
273 | return (r >> 0U) & 0xffffffffU; | ||
274 | } | ||
275 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) | ||
276 | { | ||
277 | return 0x0017e204U; | ||
278 | } | ||
279 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) | ||
280 | { | ||
281 | return 8U; | ||
282 | } | ||
283 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) | ||
284 | { | ||
285 | return (v & 0xffU) << 0U; | ||
286 | } | ||
287 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) | ||
288 | { | ||
289 | return 0xffU << 0U; | ||
290 | } | ||
291 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) | ||
292 | { | ||
293 | return (r >> 0U) & 0xffU; | ||
294 | } | ||
295 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) | ||
296 | { | ||
297 | return 0x0017e2b0U; | ||
298 | } | ||
299 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) | ||
300 | { | ||
301 | return 0x10000000U; | ||
302 | } | ||
303 | static inline u32 ltc_ltcs_ltss_g_elpg_r(void) | ||
304 | { | ||
305 | return 0x0017e214U; | ||
306 | } | ||
307 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) | ||
308 | { | ||
309 | return (r >> 0U) & 0x1U; | ||
310 | } | ||
311 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) | ||
312 | { | ||
313 | return 0x00000001U; | ||
314 | } | ||
315 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) | ||
316 | { | ||
317 | return 0x1U; | ||
318 | } | ||
319 | static inline u32 ltc_ltc0_ltss_g_elpg_r(void) | ||
320 | { | ||
321 | return 0x00140214U; | ||
322 | } | ||
323 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) | ||
324 | { | ||
325 | return (r >> 0U) & 0x1U; | ||
326 | } | ||
327 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) | ||
328 | { | ||
329 | return 0x00000001U; | ||
330 | } | ||
331 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) | ||
332 | { | ||
333 | return 0x1U; | ||
334 | } | ||
335 | static inline u32 ltc_ltc1_ltss_g_elpg_r(void) | ||
336 | { | ||
337 | return 0x00142214U; | ||
338 | } | ||
339 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) | ||
340 | { | ||
341 | return (r >> 0U) & 0x1U; | ||
342 | } | ||
343 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) | ||
344 | { | ||
345 | return 0x00000001U; | ||
346 | } | ||
347 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) | ||
348 | { | ||
349 | return 0x1U; | ||
350 | } | ||
351 | static inline u32 ltc_ltcs_ltss_intr_r(void) | ||
352 | { | ||
353 | return 0x0017e20cU; | ||
354 | } | ||
355 | static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) | ||
356 | { | ||
357 | return 0x100U; | ||
358 | } | ||
359 | static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) | ||
360 | { | ||
361 | return 0x200U; | ||
362 | } | ||
363 | static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) | ||
364 | { | ||
365 | return 0x1U << 20U; | ||
366 | } | ||
367 | static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) | ||
368 | { | ||
369 | return 0x1U << 30U; | ||
370 | } | ||
371 | static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) | ||
372 | { | ||
373 | return 0x1000000U; | ||
374 | } | ||
375 | static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) | ||
376 | { | ||
377 | return 0x2000000U; | ||
378 | } | ||
379 | static inline u32 ltc_ltc0_lts0_intr_r(void) | ||
380 | { | ||
381 | return 0x0014040cU; | ||
382 | } | ||
383 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) | ||
384 | { | ||
385 | return 0x0014051cU; | ||
386 | } | ||
387 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) | ||
388 | { | ||
389 | return 0xffU << 0U; | ||
390 | } | ||
391 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) | ||
392 | { | ||
393 | return (r >> 0U) & 0xffU; | ||
394 | } | ||
395 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) | ||
396 | { | ||
397 | return 0xffU << 16U; | ||
398 | } | ||
399 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) | ||
400 | { | ||
401 | return (r >> 16U) & 0xffU; | ||
402 | } | ||
403 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) | ||
404 | { | ||
405 | return 0x0017e2a0U; | ||
406 | } | ||
407 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
408 | { | ||
409 | return (r >> 0U) & 0x1U; | ||
410 | } | ||
411 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
412 | { | ||
413 | return 0x00000001U; | ||
414 | } | ||
415 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
416 | { | ||
417 | return 0x1U; | ||
418 | } | ||
419 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) | ||
420 | { | ||
421 | return (r >> 8U) & 0xfU; | ||
422 | } | ||
423 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) | ||
424 | { | ||
425 | return 0x00000003U; | ||
426 | } | ||
427 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) | ||
428 | { | ||
429 | return 0x300U; | ||
430 | } | ||
431 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) | ||
432 | { | ||
433 | return (r >> 28U) & 0x1U; | ||
434 | } | ||
435 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) | ||
436 | { | ||
437 | return 0x00000001U; | ||
438 | } | ||
439 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) | ||
440 | { | ||
441 | return 0x10000000U; | ||
442 | } | ||
443 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) | ||
444 | { | ||
445 | return (r >> 29U) & 0x1U; | ||
446 | } | ||
447 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) | ||
448 | { | ||
449 | return 0x00000001U; | ||
450 | } | ||
451 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) | ||
452 | { | ||
453 | return 0x20000000U; | ||
454 | } | ||
455 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) | ||
456 | { | ||
457 | return (r >> 30U) & 0x1U; | ||
458 | } | ||
459 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) | ||
460 | { | ||
461 | return 0x00000001U; | ||
462 | } | ||
463 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) | ||
464 | { | ||
465 | return 0x40000000U; | ||
466 | } | ||
467 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) | ||
468 | { | ||
469 | return 0x0017e2a4U; | ||
470 | } | ||
471 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
472 | { | ||
473 | return (r >> 0U) & 0x1U; | ||
474 | } | ||
475 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
476 | { | ||
477 | return 0x00000001U; | ||
478 | } | ||
479 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
480 | { | ||
481 | return 0x1U; | ||
482 | } | ||
483 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) | ||
484 | { | ||
485 | return (r >> 8U) & 0xfU; | ||
486 | } | ||
487 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) | ||
488 | { | ||
489 | return 0x00000003U; | ||
490 | } | ||
491 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) | ||
492 | { | ||
493 | return 0x300U; | ||
494 | } | ||
495 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) | ||
496 | { | ||
497 | return (r >> 16U) & 0x1U; | ||
498 | } | ||
499 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) | ||
500 | { | ||
501 | return 0x00000001U; | ||
502 | } | ||
503 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) | ||
504 | { | ||
505 | return 0x10000U; | ||
506 | } | ||
507 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) | ||
508 | { | ||
509 | return (r >> 28U) & 0x1U; | ||
510 | } | ||
511 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) | ||
512 | { | ||
513 | return 0x00000001U; | ||
514 | } | ||
515 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) | ||
516 | { | ||
517 | return 0x10000000U; | ||
518 | } | ||
519 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) | ||
520 | { | ||
521 | return (r >> 29U) & 0x1U; | ||
522 | } | ||
523 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) | ||
524 | { | ||
525 | return 0x00000001U; | ||
526 | } | ||
527 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) | ||
528 | { | ||
529 | return 0x20000000U; | ||
530 | } | ||
531 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) | ||
532 | { | ||
533 | return (r >> 30U) & 0x1U; | ||
534 | } | ||
535 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) | ||
536 | { | ||
537 | return 0x00000001U; | ||
538 | } | ||
539 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) | ||
540 | { | ||
541 | return 0x40000000U; | ||
542 | } | ||
543 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) | ||
544 | { | ||
545 | return 0x001402a0U; | ||
546 | } | ||
547 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
548 | { | ||
549 | return (r >> 0U) & 0x1U; | ||
550 | } | ||
551 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
552 | { | ||
553 | return 0x00000001U; | ||
554 | } | ||
555 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
556 | { | ||
557 | return 0x1U; | ||
558 | } | ||
559 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) | ||
560 | { | ||
561 | return 0x001402a4U; | ||
562 | } | ||
563 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
564 | { | ||
565 | return (r >> 0U) & 0x1U; | ||
566 | } | ||
567 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
568 | { | ||
569 | return 0x00000001U; | ||
570 | } | ||
571 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
572 | { | ||
573 | return 0x1U; | ||
574 | } | ||
575 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) | ||
576 | { | ||
577 | return 0x001422a0U; | ||
578 | } | ||
579 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
580 | { | ||
581 | return (r >> 0U) & 0x1U; | ||
582 | } | ||
583 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
584 | { | ||
585 | return 0x00000001U; | ||
586 | } | ||
587 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
588 | { | ||
589 | return 0x1U; | ||
590 | } | ||
591 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) | ||
592 | { | ||
593 | return 0x001422a4U; | ||
594 | } | ||
595 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
596 | { | ||
597 | return (r >> 0U) & 0x1U; | ||
598 | } | ||
599 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
600 | { | ||
601 | return 0x00000001U; | ||
602 | } | ||
603 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
604 | { | ||
605 | return 0x1U; | ||
606 | } | ||
607 | static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) | ||
608 | { | ||
609 | return 0x0014058cU; | ||
610 | } | ||
611 | static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) | ||
612 | { | ||
613 | return (r >> 0U) & 0xffffU; | ||
614 | } | ||
615 | static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) | ||
616 | { | ||
617 | return (r >> 16U) & 0x1fU; | ||
618 | } | ||
619 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h new file mode 100644 index 00000000..f367991e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | |||
@@ -0,0 +1,259 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_mc_gv100_h_ | ||
57 | #define _hw_mc_gv100_h_ | ||
58 | |||
59 | static inline u32 mc_boot_0_r(void) | ||
60 | { | ||
61 | return 0x00000000U; | ||
62 | } | ||
63 | static inline u32 mc_boot_0_architecture_v(u32 r) | ||
64 | { | ||
65 | return (r >> 24U) & 0x1fU; | ||
66 | } | ||
67 | static inline u32 mc_boot_0_implementation_v(u32 r) | ||
68 | { | ||
69 | return (r >> 20U) & 0xfU; | ||
70 | } | ||
71 | static inline u32 mc_boot_0_major_revision_v(u32 r) | ||
72 | { | ||
73 | return (r >> 4U) & 0xfU; | ||
74 | } | ||
75 | static inline u32 mc_boot_0_minor_revision_v(u32 r) | ||
76 | { | ||
77 | return (r >> 0U) & 0xfU; | ||
78 | } | ||
79 | static inline u32 mc_intr_r(u32 i) | ||
80 | { | ||
81 | return 0x00000100U + i*4U; | ||
82 | } | ||
83 | static inline u32 mc_intr_pfifo_pending_f(void) | ||
84 | { | ||
85 | return 0x100U; | ||
86 | } | ||
87 | static inline u32 mc_intr_hub_pending_f(void) | ||
88 | { | ||
89 | return 0x200U; | ||
90 | } | ||
91 | static inline u32 mc_intr_pgraph_pending_f(void) | ||
92 | { | ||
93 | return 0x1000U; | ||
94 | } | ||
95 | static inline u32 mc_intr_pmu_pending_f(void) | ||
96 | { | ||
97 | return 0x1000000U; | ||
98 | } | ||
99 | static inline u32 mc_intr_ltc_pending_f(void) | ||
100 | { | ||
101 | return 0x2000000U; | ||
102 | } | ||
103 | static inline u32 mc_intr_priv_ring_pending_f(void) | ||
104 | { | ||
105 | return 0x40000000U; | ||
106 | } | ||
107 | static inline u32 mc_intr_pbus_pending_f(void) | ||
108 | { | ||
109 | return 0x10000000U; | ||
110 | } | ||
111 | static inline u32 mc_intr_en_r(u32 i) | ||
112 | { | ||
113 | return 0x00000140U + i*4U; | ||
114 | } | ||
115 | static inline u32 mc_intr_en_set_r(u32 i) | ||
116 | { | ||
117 | return 0x00000160U + i*4U; | ||
118 | } | ||
119 | static inline u32 mc_intr_en_clear_r(u32 i) | ||
120 | { | ||
121 | return 0x00000180U + i*4U; | ||
122 | } | ||
123 | static inline u32 mc_enable_r(void) | ||
124 | { | ||
125 | return 0x00000200U; | ||
126 | } | ||
127 | static inline u32 mc_enable_xbar_enabled_f(void) | ||
128 | { | ||
129 | return 0x4U; | ||
130 | } | ||
131 | static inline u32 mc_enable_l2_enabled_f(void) | ||
132 | { | ||
133 | return 0x8U; | ||
134 | } | ||
135 | static inline u32 mc_enable_pmedia_s(void) | ||
136 | { | ||
137 | return 1U; | ||
138 | } | ||
139 | static inline u32 mc_enable_pmedia_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 4U; | ||
142 | } | ||
143 | static inline u32 mc_enable_pmedia_m(void) | ||
144 | { | ||
145 | return 0x1U << 4U; | ||
146 | } | ||
147 | static inline u32 mc_enable_pmedia_v(u32 r) | ||
148 | { | ||
149 | return (r >> 4U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 mc_enable_ce0_m(void) | ||
152 | { | ||
153 | return 0x1U << 6U; | ||
154 | } | ||
155 | static inline u32 mc_enable_pfifo_enabled_f(void) | ||
156 | { | ||
157 | return 0x100U; | ||
158 | } | ||
159 | static inline u32 mc_enable_pgraph_enabled_f(void) | ||
160 | { | ||
161 | return 0x1000U; | ||
162 | } | ||
163 | static inline u32 mc_enable_pwr_v(u32 r) | ||
164 | { | ||
165 | return (r >> 13U) & 0x1U; | ||
166 | } | ||
167 | static inline u32 mc_enable_pwr_disabled_v(void) | ||
168 | { | ||
169 | return 0x00000000U; | ||
170 | } | ||
171 | static inline u32 mc_enable_pwr_enabled_f(void) | ||
172 | { | ||
173 | return 0x2000U; | ||
174 | } | ||
175 | static inline u32 mc_enable_pfb_enabled_f(void) | ||
176 | { | ||
177 | return 0x100000U; | ||
178 | } | ||
179 | static inline u32 mc_enable_ce2_m(void) | ||
180 | { | ||
181 | return 0x1U << 21U; | ||
182 | } | ||
183 | static inline u32 mc_enable_ce2_enabled_f(void) | ||
184 | { | ||
185 | return 0x200000U; | ||
186 | } | ||
187 | static inline u32 mc_enable_blg_enabled_f(void) | ||
188 | { | ||
189 | return 0x8000000U; | ||
190 | } | ||
191 | static inline u32 mc_enable_perfmon_enabled_f(void) | ||
192 | { | ||
193 | return 0x10000000U; | ||
194 | } | ||
195 | static inline u32 mc_enable_hub_enabled_f(void) | ||
196 | { | ||
197 | return 0x20000000U; | ||
198 | } | ||
199 | static inline u32 mc_enable_nvdec_disabled_v(void) | ||
200 | { | ||
201 | return 0x00000000U; | ||
202 | } | ||
203 | static inline u32 mc_enable_nvdec_enabled_f(void) | ||
204 | { | ||
205 | return 0x8000U; | ||
206 | } | ||
207 | static inline u32 mc_intr_ltc_r(void) | ||
208 | { | ||
209 | return 0x000001c0U; | ||
210 | } | ||
211 | static inline u32 mc_enable_pb_r(void) | ||
212 | { | ||
213 | return 0x00000204U; | ||
214 | } | ||
215 | static inline u32 mc_enable_pb_0_s(void) | ||
216 | { | ||
217 | return 1U; | ||
218 | } | ||
219 | static inline u32 mc_enable_pb_0_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1U) << 0U; | ||
222 | } | ||
223 | static inline u32 mc_enable_pb_0_m(void) | ||
224 | { | ||
225 | return 0x1U << 0U; | ||
226 | } | ||
227 | static inline u32 mc_enable_pb_0_v(u32 r) | ||
228 | { | ||
229 | return (r >> 0U) & 0x1U; | ||
230 | } | ||
231 | static inline u32 mc_enable_pb_0_enabled_v(void) | ||
232 | { | ||
233 | return 0x00000001U; | ||
234 | } | ||
235 | static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) | ||
236 | { | ||
237 | return (v & 0x1U) << (0U + i*1U); | ||
238 | } | ||
239 | static inline u32 mc_elpg_enable_r(void) | ||
240 | { | ||
241 | return 0x0000020cU; | ||
242 | } | ||
243 | static inline u32 mc_elpg_enable_xbar_enabled_f(void) | ||
244 | { | ||
245 | return 0x4U; | ||
246 | } | ||
247 | static inline u32 mc_elpg_enable_pfb_enabled_f(void) | ||
248 | { | ||
249 | return 0x100000U; | ||
250 | } | ||
251 | static inline u32 mc_elpg_enable_hub_enabled_f(void) | ||
252 | { | ||
253 | return 0x20000000U; | ||
254 | } | ||
255 | static inline u32 mc_elpg_enable_l2_enabled_f(void) | ||
256 | { | ||
257 | return 0x8U; | ||
258 | } | ||
259 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h new file mode 100644 index 00000000..66a0737c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | |||
@@ -0,0 +1,659 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pbdma_gv100_h_ | ||
57 | #define _hw_pbdma_gv100_h_ | ||
58 | |||
59 | static inline u32 pbdma_gp_entry1_r(void) | ||
60 | { | ||
61 | return 0x10000004U; | ||
62 | } | ||
63 | static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) | ||
64 | { | ||
65 | return (r >> 0U) & 0xffU; | ||
66 | } | ||
67 | static inline u32 pbdma_gp_entry1_length_f(u32 v) | ||
68 | { | ||
69 | return (v & 0x1fffffU) << 10U; | ||
70 | } | ||
71 | static inline u32 pbdma_gp_entry1_length_v(u32 r) | ||
72 | { | ||
73 | return (r >> 10U) & 0x1fffffU; | ||
74 | } | ||
75 | static inline u32 pbdma_gp_base_r(u32 i) | ||
76 | { | ||
77 | return 0x00040048U + i*8192U; | ||
78 | } | ||
79 | static inline u32 pbdma_gp_base__size_1_v(void) | ||
80 | { | ||
81 | return 0x0000000eU; | ||
82 | } | ||
83 | static inline u32 pbdma_gp_base_offset_f(u32 v) | ||
84 | { | ||
85 | return (v & 0x1fffffffU) << 3U; | ||
86 | } | ||
87 | static inline u32 pbdma_gp_base_rsvd_s(void) | ||
88 | { | ||
89 | return 3U; | ||
90 | } | ||
91 | static inline u32 pbdma_gp_base_hi_r(u32 i) | ||
92 | { | ||
93 | return 0x0004004cU + i*8192U; | ||
94 | } | ||
95 | static inline u32 pbdma_gp_base_hi_offset_f(u32 v) | ||
96 | { | ||
97 | return (v & 0xffU) << 0U; | ||
98 | } | ||
99 | static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1fU) << 16U; | ||
102 | } | ||
103 | static inline u32 pbdma_gp_fetch_r(u32 i) | ||
104 | { | ||
105 | return 0x00040050U + i*8192U; | ||
106 | } | ||
107 | static inline u32 pbdma_gp_get_r(u32 i) | ||
108 | { | ||
109 | return 0x00040014U + i*8192U; | ||
110 | } | ||
111 | static inline u32 pbdma_gp_put_r(u32 i) | ||
112 | { | ||
113 | return 0x00040000U + i*8192U; | ||
114 | } | ||
115 | static inline u32 pbdma_pb_fetch_r(u32 i) | ||
116 | { | ||
117 | return 0x00040054U + i*8192U; | ||
118 | } | ||
119 | static inline u32 pbdma_pb_fetch_hi_r(u32 i) | ||
120 | { | ||
121 | return 0x00040058U + i*8192U; | ||
122 | } | ||
123 | static inline u32 pbdma_get_r(u32 i) | ||
124 | { | ||
125 | return 0x00040018U + i*8192U; | ||
126 | } | ||
127 | static inline u32 pbdma_get_hi_r(u32 i) | ||
128 | { | ||
129 | return 0x0004001cU + i*8192U; | ||
130 | } | ||
131 | static inline u32 pbdma_put_r(u32 i) | ||
132 | { | ||
133 | return 0x0004005cU + i*8192U; | ||
134 | } | ||
135 | static inline u32 pbdma_put_hi_r(u32 i) | ||
136 | { | ||
137 | return 0x00040060U + i*8192U; | ||
138 | } | ||
139 | static inline u32 pbdma_pb_header_r(u32 i) | ||
140 | { | ||
141 | return 0x00040084U + i*8192U; | ||
142 | } | ||
143 | static inline u32 pbdma_pb_header_priv_user_f(void) | ||
144 | { | ||
145 | return 0x0U; | ||
146 | } | ||
147 | static inline u32 pbdma_pb_header_method_zero_f(void) | ||
148 | { | ||
149 | return 0x0U; | ||
150 | } | ||
151 | static inline u32 pbdma_pb_header_subchannel_zero_f(void) | ||
152 | { | ||
153 | return 0x0U; | ||
154 | } | ||
155 | static inline u32 pbdma_pb_header_level_main_f(void) | ||
156 | { | ||
157 | return 0x0U; | ||
158 | } | ||
159 | static inline u32 pbdma_pb_header_first_true_f(void) | ||
160 | { | ||
161 | return 0x400000U; | ||
162 | } | ||
163 | static inline u32 pbdma_pb_header_type_inc_f(void) | ||
164 | { | ||
165 | return 0x20000000U; | ||
166 | } | ||
167 | static inline u32 pbdma_pb_header_type_non_inc_f(void) | ||
168 | { | ||
169 | return 0x60000000U; | ||
170 | } | ||
171 | static inline u32 pbdma_hdr_shadow_r(u32 i) | ||
172 | { | ||
173 | return 0x00040118U + i*8192U; | ||
174 | } | ||
175 | static inline u32 pbdma_gp_shadow_0_r(u32 i) | ||
176 | { | ||
177 | return 0x00040110U + i*8192U; | ||
178 | } | ||
179 | static inline u32 pbdma_gp_shadow_1_r(u32 i) | ||
180 | { | ||
181 | return 0x00040114U + i*8192U; | ||
182 | } | ||
183 | static inline u32 pbdma_subdevice_r(u32 i) | ||
184 | { | ||
185 | return 0x00040094U + i*8192U; | ||
186 | } | ||
187 | static inline u32 pbdma_subdevice_id_f(u32 v) | ||
188 | { | ||
189 | return (v & 0xfffU) << 0U; | ||
190 | } | ||
191 | static inline u32 pbdma_subdevice_status_active_f(void) | ||
192 | { | ||
193 | return 0x10000000U; | ||
194 | } | ||
195 | static inline u32 pbdma_subdevice_channel_dma_enable_f(void) | ||
196 | { | ||
197 | return 0x20000000U; | ||
198 | } | ||
199 | static inline u32 pbdma_method0_r(u32 i) | ||
200 | { | ||
201 | return 0x000400c0U + i*8192U; | ||
202 | } | ||
203 | static inline u32 pbdma_method0_fifo_size_v(void) | ||
204 | { | ||
205 | return 0x00000004U; | ||
206 | } | ||
207 | static inline u32 pbdma_method0_addr_f(u32 v) | ||
208 | { | ||
209 | return (v & 0xfffU) << 2U; | ||
210 | } | ||
211 | static inline u32 pbdma_method0_addr_v(u32 r) | ||
212 | { | ||
213 | return (r >> 2U) & 0xfffU; | ||
214 | } | ||
215 | static inline u32 pbdma_method0_subch_v(u32 r) | ||
216 | { | ||
217 | return (r >> 16U) & 0x7U; | ||
218 | } | ||
219 | static inline u32 pbdma_method0_first_true_f(void) | ||
220 | { | ||
221 | return 0x400000U; | ||
222 | } | ||
223 | static inline u32 pbdma_method0_valid_true_f(void) | ||
224 | { | ||
225 | return 0x80000000U; | ||
226 | } | ||
227 | static inline u32 pbdma_method1_r(u32 i) | ||
228 | { | ||
229 | return 0x000400c8U + i*8192U; | ||
230 | } | ||
231 | static inline u32 pbdma_method2_r(u32 i) | ||
232 | { | ||
233 | return 0x000400d0U + i*8192U; | ||
234 | } | ||
235 | static inline u32 pbdma_method3_r(u32 i) | ||
236 | { | ||
237 | return 0x000400d8U + i*8192U; | ||
238 | } | ||
239 | static inline u32 pbdma_data0_r(u32 i) | ||
240 | { | ||
241 | return 0x000400c4U + i*8192U; | ||
242 | } | ||
243 | static inline u32 pbdma_acquire_r(u32 i) | ||
244 | { | ||
245 | return 0x00040030U + i*8192U; | ||
246 | } | ||
247 | static inline u32 pbdma_acquire_retry_man_2_f(void) | ||
248 | { | ||
249 | return 0x2U; | ||
250 | } | ||
251 | static inline u32 pbdma_acquire_retry_exp_2_f(void) | ||
252 | { | ||
253 | return 0x100U; | ||
254 | } | ||
255 | static inline u32 pbdma_acquire_timeout_exp_f(u32 v) | ||
256 | { | ||
257 | return (v & 0xfU) << 11U; | ||
258 | } | ||
259 | static inline u32 pbdma_acquire_timeout_exp_max_v(void) | ||
260 | { | ||
261 | return 0x0000000fU; | ||
262 | } | ||
263 | static inline u32 pbdma_acquire_timeout_exp_max_f(void) | ||
264 | { | ||
265 | return 0x7800U; | ||
266 | } | ||
267 | static inline u32 pbdma_acquire_timeout_man_f(u32 v) | ||
268 | { | ||
269 | return (v & 0xffffU) << 15U; | ||
270 | } | ||
271 | static inline u32 pbdma_acquire_timeout_man_max_v(void) | ||
272 | { | ||
273 | return 0x0000ffffU; | ||
274 | } | ||
275 | static inline u32 pbdma_acquire_timeout_man_max_f(void) | ||
276 | { | ||
277 | return 0x7fff8000U; | ||
278 | } | ||
279 | static inline u32 pbdma_acquire_timeout_en_enable_f(void) | ||
280 | { | ||
281 | return 0x80000000U; | ||
282 | } | ||
283 | static inline u32 pbdma_acquire_timeout_en_disable_f(void) | ||
284 | { | ||
285 | return 0x0U; | ||
286 | } | ||
287 | static inline u32 pbdma_status_r(u32 i) | ||
288 | { | ||
289 | return 0x00040100U + i*8192U; | ||
290 | } | ||
291 | static inline u32 pbdma_channel_r(u32 i) | ||
292 | { | ||
293 | return 0x00040120U + i*8192U; | ||
294 | } | ||
295 | static inline u32 pbdma_signature_r(u32 i) | ||
296 | { | ||
297 | return 0x00040010U + i*8192U; | ||
298 | } | ||
299 | static inline u32 pbdma_signature_hw_valid_f(void) | ||
300 | { | ||
301 | return 0xfaceU; | ||
302 | } | ||
303 | static inline u32 pbdma_signature_sw_zero_f(void) | ||
304 | { | ||
305 | return 0x0U; | ||
306 | } | ||
307 | static inline u32 pbdma_userd_r(u32 i) | ||
308 | { | ||
309 | return 0x00040008U + i*8192U; | ||
310 | } | ||
311 | static inline u32 pbdma_userd_target_vid_mem_f(void) | ||
312 | { | ||
313 | return 0x0U; | ||
314 | } | ||
315 | static inline u32 pbdma_userd_target_sys_mem_coh_f(void) | ||
316 | { | ||
317 | return 0x2U; | ||
318 | } | ||
319 | static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) | ||
320 | { | ||
321 | return 0x3U; | ||
322 | } | ||
323 | static inline u32 pbdma_userd_addr_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x7fffffU) << 9U; | ||
326 | } | ||
327 | static inline u32 pbdma_config_r(u32 i) | ||
328 | { | ||
329 | return 0x000400f4U + i*8192U; | ||
330 | } | ||
331 | static inline u32 pbdma_config_l2_evict_first_f(void) | ||
332 | { | ||
333 | return 0x0U; | ||
334 | } | ||
335 | static inline u32 pbdma_config_l2_evict_normal_f(void) | ||
336 | { | ||
337 | return 0x1U; | ||
338 | } | ||
339 | static inline u32 pbdma_config_l2_evict_last_f(void) | ||
340 | { | ||
341 | return 0x2U; | ||
342 | } | ||
343 | static inline u32 pbdma_config_ce_split_enable_f(void) | ||
344 | { | ||
345 | return 0x0U; | ||
346 | } | ||
347 | static inline u32 pbdma_config_ce_split_disable_f(void) | ||
348 | { | ||
349 | return 0x10U; | ||
350 | } | ||
351 | static inline u32 pbdma_config_auth_level_non_privileged_f(void) | ||
352 | { | ||
353 | return 0x0U; | ||
354 | } | ||
355 | static inline u32 pbdma_config_auth_level_privileged_f(void) | ||
356 | { | ||
357 | return 0x100U; | ||
358 | } | ||
359 | static inline u32 pbdma_config_userd_writeback_disable_f(void) | ||
360 | { | ||
361 | return 0x0U; | ||
362 | } | ||
363 | static inline u32 pbdma_config_userd_writeback_enable_f(void) | ||
364 | { | ||
365 | return 0x1000U; | ||
366 | } | ||
367 | static inline u32 pbdma_userd_hi_r(u32 i) | ||
368 | { | ||
369 | return 0x0004000cU + i*8192U; | ||
370 | } | ||
371 | static inline u32 pbdma_userd_hi_addr_f(u32 v) | ||
372 | { | ||
373 | return (v & 0xffU) << 0U; | ||
374 | } | ||
375 | static inline u32 pbdma_hce_ctrl_r(u32 i) | ||
376 | { | ||
377 | return 0x000400e4U + i*8192U; | ||
378 | } | ||
379 | static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) | ||
380 | { | ||
381 | return 0x20U; | ||
382 | } | ||
383 | static inline u32 pbdma_intr_0_r(u32 i) | ||
384 | { | ||
385 | return 0x00040108U + i*8192U; | ||
386 | } | ||
387 | static inline u32 pbdma_intr_0_memreq_v(u32 r) | ||
388 | { | ||
389 | return (r >> 0U) & 0x1U; | ||
390 | } | ||
391 | static inline u32 pbdma_intr_0_memreq_pending_f(void) | ||
392 | { | ||
393 | return 0x1U; | ||
394 | } | ||
395 | static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) | ||
396 | { | ||
397 | return 0x2U; | ||
398 | } | ||
399 | static inline u32 pbdma_intr_0_memack_extra_pending_f(void) | ||
400 | { | ||
401 | return 0x4U; | ||
402 | } | ||
403 | static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) | ||
404 | { | ||
405 | return 0x8U; | ||
406 | } | ||
407 | static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) | ||
408 | { | ||
409 | return 0x10U; | ||
410 | } | ||
411 | static inline u32 pbdma_intr_0_memflush_pending_f(void) | ||
412 | { | ||
413 | return 0x20U; | ||
414 | } | ||
415 | static inline u32 pbdma_intr_0_memop_pending_f(void) | ||
416 | { | ||
417 | return 0x40U; | ||
418 | } | ||
419 | static inline u32 pbdma_intr_0_lbconnect_pending_f(void) | ||
420 | { | ||
421 | return 0x80U; | ||
422 | } | ||
423 | static inline u32 pbdma_intr_0_lbreq_pending_f(void) | ||
424 | { | ||
425 | return 0x100U; | ||
426 | } | ||
427 | static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) | ||
428 | { | ||
429 | return 0x200U; | ||
430 | } | ||
431 | static inline u32 pbdma_intr_0_lback_extra_pending_f(void) | ||
432 | { | ||
433 | return 0x400U; | ||
434 | } | ||
435 | static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) | ||
436 | { | ||
437 | return 0x800U; | ||
438 | } | ||
439 | static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) | ||
440 | { | ||
441 | return 0x1000U; | ||
442 | } | ||
443 | static inline u32 pbdma_intr_0_gpfifo_pending_f(void) | ||
444 | { | ||
445 | return 0x2000U; | ||
446 | } | ||
447 | static inline u32 pbdma_intr_0_gpptr_pending_f(void) | ||
448 | { | ||
449 | return 0x4000U; | ||
450 | } | ||
451 | static inline u32 pbdma_intr_0_gpentry_pending_f(void) | ||
452 | { | ||
453 | return 0x8000U; | ||
454 | } | ||
455 | static inline u32 pbdma_intr_0_gpcrc_pending_f(void) | ||
456 | { | ||
457 | return 0x10000U; | ||
458 | } | ||
459 | static inline u32 pbdma_intr_0_pbptr_pending_f(void) | ||
460 | { | ||
461 | return 0x20000U; | ||
462 | } | ||
463 | static inline u32 pbdma_intr_0_pbentry_pending_f(void) | ||
464 | { | ||
465 | return 0x40000U; | ||
466 | } | ||
467 | static inline u32 pbdma_intr_0_pbcrc_pending_f(void) | ||
468 | { | ||
469 | return 0x80000U; | ||
470 | } | ||
471 | static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) | ||
472 | { | ||
473 | return 0x100000U; | ||
474 | } | ||
475 | static inline u32 pbdma_intr_0_method_pending_f(void) | ||
476 | { | ||
477 | return 0x200000U; | ||
478 | } | ||
479 | static inline u32 pbdma_intr_0_methodcrc_pending_f(void) | ||
480 | { | ||
481 | return 0x400000U; | ||
482 | } | ||
483 | static inline u32 pbdma_intr_0_device_pending_f(void) | ||
484 | { | ||
485 | return 0x800000U; | ||
486 | } | ||
487 | static inline u32 pbdma_intr_0_eng_reset_pending_f(void) | ||
488 | { | ||
489 | return 0x1000000U; | ||
490 | } | ||
491 | static inline u32 pbdma_intr_0_semaphore_pending_f(void) | ||
492 | { | ||
493 | return 0x2000000U; | ||
494 | } | ||
495 | static inline u32 pbdma_intr_0_acquire_pending_f(void) | ||
496 | { | ||
497 | return 0x4000000U; | ||
498 | } | ||
499 | static inline u32 pbdma_intr_0_pri_pending_f(void) | ||
500 | { | ||
501 | return 0x8000000U; | ||
502 | } | ||
503 | static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) | ||
504 | { | ||
505 | return 0x20000000U; | ||
506 | } | ||
507 | static inline u32 pbdma_intr_0_pbseg_pending_f(void) | ||
508 | { | ||
509 | return 0x40000000U; | ||
510 | } | ||
511 | static inline u32 pbdma_intr_0_signature_pending_f(void) | ||
512 | { | ||
513 | return 0x80000000U; | ||
514 | } | ||
515 | static inline u32 pbdma_intr_1_r(u32 i) | ||
516 | { | ||
517 | return 0x00040148U + i*8192U; | ||
518 | } | ||
519 | static inline u32 pbdma_intr_1_ctxnotvalid_m(void) | ||
520 | { | ||
521 | return 0x1U << 31U; | ||
522 | } | ||
523 | static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) | ||
524 | { | ||
525 | return 0x80000000U; | ||
526 | } | ||
527 | static inline u32 pbdma_intr_en_0_r(u32 i) | ||
528 | { | ||
529 | return 0x0004010cU + i*8192U; | ||
530 | } | ||
531 | static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) | ||
532 | { | ||
533 | return 0x100U; | ||
534 | } | ||
535 | static inline u32 pbdma_intr_en_1_r(u32 i) | ||
536 | { | ||
537 | return 0x0004014cU + i*8192U; | ||
538 | } | ||
539 | static inline u32 pbdma_intr_stall_r(u32 i) | ||
540 | { | ||
541 | return 0x0004013cU + i*8192U; | ||
542 | } | ||
543 | static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) | ||
544 | { | ||
545 | return 0x100U; | ||
546 | } | ||
547 | static inline u32 pbdma_intr_stall_1_r(u32 i) | ||
548 | { | ||
549 | return 0x00040140U + i*8192U; | ||
550 | } | ||
551 | static inline u32 pbdma_udma_nop_r(void) | ||
552 | { | ||
553 | return 0x00000008U; | ||
554 | } | ||
555 | static inline u32 pbdma_runlist_timeslice_r(u32 i) | ||
556 | { | ||
557 | return 0x000400f8U + i*8192U; | ||
558 | } | ||
559 | static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) | ||
560 | { | ||
561 | return 0x80U; | ||
562 | } | ||
563 | static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) | ||
564 | { | ||
565 | return 0x3000U; | ||
566 | } | ||
567 | static inline u32 pbdma_runlist_timeslice_enable_true_f(void) | ||
568 | { | ||
569 | return 0x10000000U; | ||
570 | } | ||
571 | static inline u32 pbdma_target_r(u32 i) | ||
572 | { | ||
573 | return 0x000400acU + i*8192U; | ||
574 | } | ||
575 | static inline u32 pbdma_target_engine_sw_f(void) | ||
576 | { | ||
577 | return 0x1fU; | ||
578 | } | ||
579 | static inline u32 pbdma_target_eng_ctx_valid_true_f(void) | ||
580 | { | ||
581 | return 0x10000U; | ||
582 | } | ||
583 | static inline u32 pbdma_target_eng_ctx_valid_false_f(void) | ||
584 | { | ||
585 | return 0x0U; | ||
586 | } | ||
587 | static inline u32 pbdma_target_ce_ctx_valid_true_f(void) | ||
588 | { | ||
589 | return 0x20000U; | ||
590 | } | ||
591 | static inline u32 pbdma_target_ce_ctx_valid_false_f(void) | ||
592 | { | ||
593 | return 0x0U; | ||
594 | } | ||
595 | static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) | ||
596 | { | ||
597 | return 0x0U; | ||
598 | } | ||
599 | static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) | ||
600 | { | ||
601 | return 0x1000000U; | ||
602 | } | ||
603 | static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) | ||
604 | { | ||
605 | return 0x2000000U; | ||
606 | } | ||
607 | static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) | ||
608 | { | ||
609 | return 0x3000000U; | ||
610 | } | ||
611 | static inline u32 pbdma_target_should_send_tsg_event_true_f(void) | ||
612 | { | ||
613 | return 0x20000000U; | ||
614 | } | ||
615 | static inline u32 pbdma_target_should_send_tsg_event_false_f(void) | ||
616 | { | ||
617 | return 0x0U; | ||
618 | } | ||
619 | static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) | ||
620 | { | ||
621 | return 0x80000000U; | ||
622 | } | ||
623 | static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) | ||
624 | { | ||
625 | return 0x0U; | ||
626 | } | ||
627 | static inline u32 pbdma_set_channel_info_r(u32 i) | ||
628 | { | ||
629 | return 0x000400fcU + i*8192U; | ||
630 | } | ||
631 | static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) | ||
632 | { | ||
633 | return 0x0U; | ||
634 | } | ||
635 | static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) | ||
636 | { | ||
637 | return 0x1U; | ||
638 | } | ||
639 | static inline u32 pbdma_set_channel_info_veid_f(u32 v) | ||
640 | { | ||
641 | return (v & 0x3fU) << 8U; | ||
642 | } | ||
643 | static inline u32 pbdma_timeout_r(u32 i) | ||
644 | { | ||
645 | return 0x0004012cU + i*8192U; | ||
646 | } | ||
647 | static inline u32 pbdma_timeout_period_m(void) | ||
648 | { | ||
649 | return 0xffffffffU << 0U; | ||
650 | } | ||
651 | static inline u32 pbdma_timeout_period_max_f(void) | ||
652 | { | ||
653 | return 0xffffffffU; | ||
654 | } | ||
655 | static inline u32 pbdma_timeout_period_init_f(void) | ||
656 | { | ||
657 | return 0x10000U; | ||
658 | } | ||
659 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h new file mode 100644 index 00000000..4fbe37cb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | |||
@@ -0,0 +1,211 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_perf_gv100_h_ | ||
57 | #define _hw_perf_gv100_h_ | ||
58 | |||
59 | static inline u32 perf_pmasys_control_r(void) | ||
60 | { | ||
61 | return 0x0024a000U; | ||
62 | } | ||
63 | static inline u32 perf_pmasys_control_membuf_status_v(u32 r) | ||
64 | { | ||
65 | return (r >> 4U) & 0x1U; | ||
66 | } | ||
67 | static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) | ||
68 | { | ||
69 | return 0x00000001U; | ||
70 | } | ||
71 | static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) | ||
72 | { | ||
73 | return 0x10U; | ||
74 | } | ||
75 | static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x1U) << 5U; | ||
78 | } | ||
79 | static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) | ||
80 | { | ||
81 | return (r >> 5U) & 0x1U; | ||
82 | } | ||
83 | static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) | ||
84 | { | ||
85 | return 0x00000001U; | ||
86 | } | ||
87 | static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) | ||
88 | { | ||
89 | return 0x20U; | ||
90 | } | ||
91 | static inline u32 perf_pmasys_mem_block_r(void) | ||
92 | { | ||
93 | return 0x0024a070U; | ||
94 | } | ||
95 | static inline u32 perf_pmasys_mem_block_base_f(u32 v) | ||
96 | { | ||
97 | return (v & 0xfffffffU) << 0U; | ||
98 | } | ||
99 | static inline u32 perf_pmasys_mem_block_target_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x3U) << 28U; | ||
102 | } | ||
103 | static inline u32 perf_pmasys_mem_block_target_v(u32 r) | ||
104 | { | ||
105 | return (r >> 28U) & 0x3U; | ||
106 | } | ||
107 | static inline u32 perf_pmasys_mem_block_target_lfb_v(void) | ||
108 | { | ||
109 | return 0x00000000U; | ||
110 | } | ||
111 | static inline u32 perf_pmasys_mem_block_target_lfb_f(void) | ||
112 | { | ||
113 | return 0x0U; | ||
114 | } | ||
115 | static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) | ||
116 | { | ||
117 | return 0x00000002U; | ||
118 | } | ||
119 | static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) | ||
120 | { | ||
121 | return 0x20000000U; | ||
122 | } | ||
123 | static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) | ||
124 | { | ||
125 | return 0x00000003U; | ||
126 | } | ||
127 | static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) | ||
128 | { | ||
129 | return 0x30000000U; | ||
130 | } | ||
131 | static inline u32 perf_pmasys_mem_block_valid_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 31U; | ||
134 | } | ||
135 | static inline u32 perf_pmasys_mem_block_valid_v(u32 r) | ||
136 | { | ||
137 | return (r >> 31U) & 0x1U; | ||
138 | } | ||
139 | static inline u32 perf_pmasys_mem_block_valid_true_v(void) | ||
140 | { | ||
141 | return 0x00000001U; | ||
142 | } | ||
143 | static inline u32 perf_pmasys_mem_block_valid_true_f(void) | ||
144 | { | ||
145 | return 0x80000000U; | ||
146 | } | ||
147 | static inline u32 perf_pmasys_mem_block_valid_false_v(void) | ||
148 | { | ||
149 | return 0x00000000U; | ||
150 | } | ||
151 | static inline u32 perf_pmasys_mem_block_valid_false_f(void) | ||
152 | { | ||
153 | return 0x0U; | ||
154 | } | ||
155 | static inline u32 perf_pmasys_outbase_r(void) | ||
156 | { | ||
157 | return 0x0024a074U; | ||
158 | } | ||
159 | static inline u32 perf_pmasys_outbase_ptr_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x7ffffffU) << 5U; | ||
162 | } | ||
163 | static inline u32 perf_pmasys_outbaseupper_r(void) | ||
164 | { | ||
165 | return 0x0024a078U; | ||
166 | } | ||
167 | static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) | ||
168 | { | ||
169 | return (v & 0xffU) << 0U; | ||
170 | } | ||
171 | static inline u32 perf_pmasys_outsize_r(void) | ||
172 | { | ||
173 | return 0x0024a07cU; | ||
174 | } | ||
175 | static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x7ffffffU) << 5U; | ||
178 | } | ||
179 | static inline u32 perf_pmasys_mem_bytes_r(void) | ||
180 | { | ||
181 | return 0x0024a084U; | ||
182 | } | ||
183 | static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) | ||
184 | { | ||
185 | return (v & 0xfffffffU) << 4U; | ||
186 | } | ||
187 | static inline u32 perf_pmasys_mem_bump_r(void) | ||
188 | { | ||
189 | return 0x0024a088U; | ||
190 | } | ||
191 | static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) | ||
192 | { | ||
193 | return (v & 0xfffffffU) << 4U; | ||
194 | } | ||
195 | static inline u32 perf_pmasys_enginestatus_r(void) | ||
196 | { | ||
197 | return 0x0024a0a4U; | ||
198 | } | ||
199 | static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) | ||
200 | { | ||
201 | return (v & 0x1U) << 4U; | ||
202 | } | ||
203 | static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) | ||
204 | { | ||
205 | return 0x00000001U; | ||
206 | } | ||
207 | static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) | ||
208 | { | ||
209 | return 0x10U; | ||
210 | } | ||
211 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h new file mode 100644 index 00000000..8f005a22 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h | |||
@@ -0,0 +1,63 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pram_gv100_h_ | ||
57 | #define _hw_pram_gv100_h_ | ||
58 | |||
59 | static inline u32 pram_data032_r(u32 i) | ||
60 | { | ||
61 | return 0x00700000U + i*4U; | ||
62 | } | ||
63 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h new file mode 100644 index 00000000..5eca93cc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | |||
@@ -0,0 +1,167 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pri_ringmaster_gv100_h_ | ||
57 | #define _hw_pri_ringmaster_gv100_h_ | ||
58 | |||
59 | static inline u32 pri_ringmaster_command_r(void) | ||
60 | { | ||
61 | return 0x0012004cU; | ||
62 | } | ||
63 | static inline u32 pri_ringmaster_command_cmd_m(void) | ||
64 | { | ||
65 | return 0x3fU << 0U; | ||
66 | } | ||
67 | static inline u32 pri_ringmaster_command_cmd_v(u32 r) | ||
68 | { | ||
69 | return (r >> 0U) & 0x3fU; | ||
70 | } | ||
71 | static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) | ||
72 | { | ||
73 | return 0x00000000U; | ||
74 | } | ||
75 | static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) | ||
76 | { | ||
77 | return 0x1U; | ||
78 | } | ||
79 | static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) | ||
80 | { | ||
81 | return 0x2U; | ||
82 | } | ||
83 | static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) | ||
84 | { | ||
85 | return 0x3U; | ||
86 | } | ||
87 | static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) | ||
88 | { | ||
89 | return 0x0U; | ||
90 | } | ||
91 | static inline u32 pri_ringmaster_command_data_r(void) | ||
92 | { | ||
93 | return 0x00120048U; | ||
94 | } | ||
95 | static inline u32 pri_ringmaster_start_results_r(void) | ||
96 | { | ||
97 | return 0x00120050U; | ||
98 | } | ||
99 | static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) | ||
100 | { | ||
101 | return (r >> 0U) & 0x1U; | ||
102 | } | ||
103 | static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) | ||
104 | { | ||
105 | return 0x00000001U; | ||
106 | } | ||
107 | static inline u32 pri_ringmaster_intr_status0_r(void) | ||
108 | { | ||
109 | return 0x00120058U; | ||
110 | } | ||
111 | static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) | ||
112 | { | ||
113 | return (r >> 0U) & 0x1U; | ||
114 | } | ||
115 | static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) | ||
116 | { | ||
117 | return (r >> 1U) & 0x1U; | ||
118 | } | ||
119 | static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) | ||
120 | { | ||
121 | return (r >> 2U) & 0x1U; | ||
122 | } | ||
123 | static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) | ||
124 | { | ||
125 | return (r >> 8U) & 0x1U; | ||
126 | } | ||
127 | static inline u32 pri_ringmaster_intr_status1_r(void) | ||
128 | { | ||
129 | return 0x0012005cU; | ||
130 | } | ||
131 | static inline u32 pri_ringmaster_global_ctl_r(void) | ||
132 | { | ||
133 | return 0x00120060U; | ||
134 | } | ||
135 | static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) | ||
136 | { | ||
137 | return 0x1U; | ||
138 | } | ||
139 | static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) | ||
140 | { | ||
141 | return 0x0U; | ||
142 | } | ||
143 | static inline u32 pri_ringmaster_enum_fbp_r(void) | ||
144 | { | ||
145 | return 0x00120074U; | ||
146 | } | ||
147 | static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) | ||
148 | { | ||
149 | return (r >> 0U) & 0x1fU; | ||
150 | } | ||
151 | static inline u32 pri_ringmaster_enum_gpc_r(void) | ||
152 | { | ||
153 | return 0x00120078U; | ||
154 | } | ||
155 | static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) | ||
156 | { | ||
157 | return (r >> 0U) & 0x1fU; | ||
158 | } | ||
159 | static inline u32 pri_ringmaster_enum_ltc_r(void) | ||
160 | { | ||
161 | return 0x0012006cU; | ||
162 | } | ||
163 | static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) | ||
164 | { | ||
165 | return (r >> 0U) & 0x1fU; | ||
166 | } | ||
167 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h new file mode 100644 index 00000000..fc522d51 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | |||
@@ -0,0 +1,79 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pri_ringstation_gpc_gv100_h_ | ||
57 | #define _hw_pri_ringstation_gpc_gv100_h_ | ||
58 | |||
59 | static inline u32 pri_ringstation_gpc_master_config_r(u32 i) | ||
60 | { | ||
61 | return 0x00128300U + i*4U; | ||
62 | } | ||
63 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) | ||
64 | { | ||
65 | return 0x00128120U; | ||
66 | } | ||
67 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) | ||
68 | { | ||
69 | return 0x00128124U; | ||
70 | } | ||
71 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) | ||
72 | { | ||
73 | return 0x00128128U; | ||
74 | } | ||
75 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) | ||
76 | { | ||
77 | return 0x0012812cU; | ||
78 | } | ||
79 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h new file mode 100644 index 00000000..885ea30a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | |||
@@ -0,0 +1,91 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pri_ringstation_sys_gv100_h_ | ||
57 | #define _hw_pri_ringstation_sys_gv100_h_ | ||
58 | |||
59 | static inline u32 pri_ringstation_sys_master_config_r(u32 i) | ||
60 | { | ||
61 | return 0x00122300U + i*4U; | ||
62 | } | ||
63 | static inline u32 pri_ringstation_sys_decode_config_r(void) | ||
64 | { | ||
65 | return 0x00122204U; | ||
66 | } | ||
67 | static inline u32 pri_ringstation_sys_decode_config_ring_m(void) | ||
68 | { | ||
69 | return 0x7U << 0U; | ||
70 | } | ||
71 | static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) | ||
72 | { | ||
73 | return 0x1U; | ||
74 | } | ||
75 | static inline u32 pri_ringstation_sys_priv_error_adr_r(void) | ||
76 | { | ||
77 | return 0x00122120U; | ||
78 | } | ||
79 | static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) | ||
80 | { | ||
81 | return 0x00122124U; | ||
82 | } | ||
83 | static inline u32 pri_ringstation_sys_priv_error_info_r(void) | ||
84 | { | ||
85 | return 0x00122128U; | ||
86 | } | ||
87 | static inline u32 pri_ringstation_sys_priv_error_code_r(void) | ||
88 | { | ||
89 | return 0x0012212cU; | ||
90 | } | ||
91 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h new file mode 100644 index 00000000..dc4c377d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | |||
@@ -0,0 +1,195 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_proj_gv100_h_ | ||
57 | #define _hw_proj_gv100_h_ | ||
58 | |||
59 | static inline u32 proj_gpc_base_v(void) | ||
60 | { | ||
61 | return 0x00500000U; | ||
62 | } | ||
63 | static inline u32 proj_gpc_shared_base_v(void) | ||
64 | { | ||
65 | return 0x00418000U; | ||
66 | } | ||
67 | static inline u32 proj_gpc_stride_v(void) | ||
68 | { | ||
69 | return 0x00008000U; | ||
70 | } | ||
71 | static inline u32 proj_ltc_stride_v(void) | ||
72 | { | ||
73 | return 0x00002000U; | ||
74 | } | ||
75 | static inline u32 proj_lts_stride_v(void) | ||
76 | { | ||
77 | return 0x00000200U; | ||
78 | } | ||
79 | static inline u32 proj_fbpa_base_v(void) | ||
80 | { | ||
81 | return 0x00900000U; | ||
82 | } | ||
83 | static inline u32 proj_fbpa_shared_base_v(void) | ||
84 | { | ||
85 | return 0x009a0000U; | ||
86 | } | ||
87 | static inline u32 proj_fbpa_stride_v(void) | ||
88 | { | ||
89 | return 0x00004000U; | ||
90 | } | ||
91 | static inline u32 proj_ppc_in_gpc_base_v(void) | ||
92 | { | ||
93 | return 0x00003000U; | ||
94 | } | ||
95 | static inline u32 proj_ppc_in_gpc_shared_base_v(void) | ||
96 | { | ||
97 | return 0x00003e00U; | ||
98 | } | ||
99 | static inline u32 proj_ppc_in_gpc_stride_v(void) | ||
100 | { | ||
101 | return 0x00000200U; | ||
102 | } | ||
103 | static inline u32 proj_rop_base_v(void) | ||
104 | { | ||
105 | return 0x00410000U; | ||
106 | } | ||
107 | static inline u32 proj_rop_shared_base_v(void) | ||
108 | { | ||
109 | return 0x00408800U; | ||
110 | } | ||
111 | static inline u32 proj_rop_stride_v(void) | ||
112 | { | ||
113 | return 0x00000400U; | ||
114 | } | ||
115 | static inline u32 proj_tpc_in_gpc_base_v(void) | ||
116 | { | ||
117 | return 0x00004000U; | ||
118 | } | ||
119 | static inline u32 proj_tpc_in_gpc_stride_v(void) | ||
120 | { | ||
121 | return 0x00000800U; | ||
122 | } | ||
123 | static inline u32 proj_tpc_in_gpc_shared_base_v(void) | ||
124 | { | ||
125 | return 0x00001800U; | ||
126 | } | ||
127 | static inline u32 proj_smpc_base_v(void) | ||
128 | { | ||
129 | return 0x00000200U; | ||
130 | } | ||
131 | static inline u32 proj_smpc_shared_base_v(void) | ||
132 | { | ||
133 | return 0x00000300U; | ||
134 | } | ||
135 | static inline u32 proj_smpc_unique_base_v(void) | ||
136 | { | ||
137 | return 0x00000600U; | ||
138 | } | ||
139 | static inline u32 proj_smpc_stride_v(void) | ||
140 | { | ||
141 | return 0x00000100U; | ||
142 | } | ||
143 | static inline u32 proj_host_num_engines_v(void) | ||
144 | { | ||
145 | return 0x0000000fU; | ||
146 | } | ||
147 | static inline u32 proj_host_num_pbdma_v(void) | ||
148 | { | ||
149 | return 0x0000000eU; | ||
150 | } | ||
151 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) | ||
152 | { | ||
153 | return 0x00000007U; | ||
154 | } | ||
155 | static inline u32 proj_scal_litter_num_fbps_v(void) | ||
156 | { | ||
157 | return 0x00000008U; | ||
158 | } | ||
159 | static inline u32 proj_scal_litter_num_fbpas_v(void) | ||
160 | { | ||
161 | return 0x00000010U; | ||
162 | } | ||
163 | static inline u32 proj_scal_litter_num_gpcs_v(void) | ||
164 | { | ||
165 | return 0x00000006U; | ||
166 | } | ||
167 | static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) | ||
168 | { | ||
169 | return 0x00000003U; | ||
170 | } | ||
171 | static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) | ||
172 | { | ||
173 | return 0x00000003U; | ||
174 | } | ||
175 | static inline u32 proj_scal_litter_num_zcull_banks_v(void) | ||
176 | { | ||
177 | return 0x00000004U; | ||
178 | } | ||
179 | static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) | ||
180 | { | ||
181 | return 0x00000002U; | ||
182 | } | ||
183 | static inline u32 proj_scal_max_gpcs_v(void) | ||
184 | { | ||
185 | return 0x00000020U; | ||
186 | } | ||
187 | static inline u32 proj_scal_max_tpc_per_gpc_v(void) | ||
188 | { | ||
189 | return 0x00000008U; | ||
190 | } | ||
191 | static inline u32 proj_sm_stride_v(void) | ||
192 | { | ||
193 | return 0x00000080U; | ||
194 | } | ||
195 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h new file mode 100644 index 00000000..4b0b0326 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h | |||
@@ -0,0 +1,935 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pwr_gv100_h_ | ||
57 | #define _hw_pwr_gv100_h_ | ||
58 | |||
59 | static inline u32 pwr_falcon_irqsset_r(void) | ||
60 | { | ||
61 | return 0x0010a000U; | ||
62 | } | ||
63 | static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) | ||
64 | { | ||
65 | return 0x40U; | ||
66 | } | ||
67 | static inline u32 pwr_falcon_irqsclr_r(void) | ||
68 | { | ||
69 | return 0x0010a004U; | ||
70 | } | ||
71 | static inline u32 pwr_falcon_irqstat_r(void) | ||
72 | { | ||
73 | return 0x0010a008U; | ||
74 | } | ||
75 | static inline u32 pwr_falcon_irqstat_halt_true_f(void) | ||
76 | { | ||
77 | return 0x10U; | ||
78 | } | ||
79 | static inline u32 pwr_falcon_irqstat_exterr_true_f(void) | ||
80 | { | ||
81 | return 0x20U; | ||
82 | } | ||
83 | static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) | ||
84 | { | ||
85 | return 0x40U; | ||
86 | } | ||
87 | static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) | ||
88 | { | ||
89 | return 0x800U; | ||
90 | } | ||
91 | static inline u32 pwr_falcon_irqmode_r(void) | ||
92 | { | ||
93 | return 0x0010a00cU; | ||
94 | } | ||
95 | static inline u32 pwr_falcon_irqmset_r(void) | ||
96 | { | ||
97 | return 0x0010a010U; | ||
98 | } | ||
99 | static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 0U; | ||
102 | } | ||
103 | static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) | ||
104 | { | ||
105 | return (v & 0x1U) << 1U; | ||
106 | } | ||
107 | static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x1U) << 2U; | ||
110 | } | ||
111 | static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) | ||
112 | { | ||
113 | return (v & 0x1U) << 3U; | ||
114 | } | ||
115 | static inline u32 pwr_falcon_irqmset_halt_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 4U; | ||
118 | } | ||
119 | static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) | ||
120 | { | ||
121 | return (v & 0x1U) << 5U; | ||
122 | } | ||
123 | static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) | ||
124 | { | ||
125 | return (v & 0x1U) << 6U; | ||
126 | } | ||
127 | static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) | ||
128 | { | ||
129 | return (v & 0x1U) << 7U; | ||
130 | } | ||
131 | static inline u32 pwr_falcon_irqmset_ext_f(u32 v) | ||
132 | { | ||
133 | return (v & 0xffU) << 8U; | ||
134 | } | ||
135 | static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) | ||
136 | { | ||
137 | return (v & 0x1U) << 8U; | ||
138 | } | ||
139 | static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 9U; | ||
142 | } | ||
143 | static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1U) << 11U; | ||
146 | } | ||
147 | static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) | ||
148 | { | ||
149 | return (v & 0x1U) << 12U; | ||
150 | } | ||
151 | static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x1U) << 13U; | ||
154 | } | ||
155 | static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) | ||
156 | { | ||
157 | return (v & 0x1U) << 14U; | ||
158 | } | ||
159 | static inline u32 pwr_falcon_irqmclr_r(void) | ||
160 | { | ||
161 | return 0x0010a014U; | ||
162 | } | ||
163 | static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) | ||
164 | { | ||
165 | return (v & 0x1U) << 0U; | ||
166 | } | ||
167 | static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) | ||
168 | { | ||
169 | return (v & 0x1U) << 1U; | ||
170 | } | ||
171 | static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) | ||
172 | { | ||
173 | return (v & 0x1U) << 2U; | ||
174 | } | ||
175 | static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x1U) << 3U; | ||
178 | } | ||
179 | static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) | ||
180 | { | ||
181 | return (v & 0x1U) << 4U; | ||
182 | } | ||
183 | static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1U) << 5U; | ||
186 | } | ||
187 | static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 6U; | ||
190 | } | ||
191 | static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1U) << 7U; | ||
194 | } | ||
195 | static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) | ||
196 | { | ||
197 | return (v & 0xffU) << 8U; | ||
198 | } | ||
199 | static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) | ||
200 | { | ||
201 | return (v & 0x1U) << 8U; | ||
202 | } | ||
203 | static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1U) << 9U; | ||
206 | } | ||
207 | static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) | ||
208 | { | ||
209 | return (v & 0x1U) << 11U; | ||
210 | } | ||
211 | static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x1U) << 12U; | ||
214 | } | ||
215 | static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) | ||
216 | { | ||
217 | return (v & 0x1U) << 13U; | ||
218 | } | ||
219 | static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1U) << 14U; | ||
222 | } | ||
223 | static inline u32 pwr_falcon_irqmask_r(void) | ||
224 | { | ||
225 | return 0x0010a018U; | ||
226 | } | ||
227 | static inline u32 pwr_falcon_irqdest_r(void) | ||
228 | { | ||
229 | return 0x0010a01cU; | ||
230 | } | ||
231 | static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) | ||
232 | { | ||
233 | return (v & 0x1U) << 0U; | ||
234 | } | ||
235 | static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1U) << 1U; | ||
238 | } | ||
239 | static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x1U) << 2U; | ||
242 | } | ||
243 | static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) | ||
244 | { | ||
245 | return (v & 0x1U) << 3U; | ||
246 | } | ||
247 | static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) | ||
248 | { | ||
249 | return (v & 0x1U) << 4U; | ||
250 | } | ||
251 | static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) | ||
252 | { | ||
253 | return (v & 0x1U) << 5U; | ||
254 | } | ||
255 | static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) | ||
256 | { | ||
257 | return (v & 0x1U) << 6U; | ||
258 | } | ||
259 | static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) | ||
260 | { | ||
261 | return (v & 0x1U) << 7U; | ||
262 | } | ||
263 | static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) | ||
264 | { | ||
265 | return (v & 0xffU) << 8U; | ||
266 | } | ||
267 | static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) | ||
268 | { | ||
269 | return (v & 0x1U) << 8U; | ||
270 | } | ||
271 | static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) | ||
272 | { | ||
273 | return (v & 0x1U) << 9U; | ||
274 | } | ||
275 | static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) | ||
276 | { | ||
277 | return (v & 0x1U) << 11U; | ||
278 | } | ||
279 | static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) | ||
280 | { | ||
281 | return (v & 0x1U) << 12U; | ||
282 | } | ||
283 | static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) | ||
284 | { | ||
285 | return (v & 0x1U) << 13U; | ||
286 | } | ||
287 | static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) | ||
288 | { | ||
289 | return (v & 0x1U) << 14U; | ||
290 | } | ||
291 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) | ||
292 | { | ||
293 | return (v & 0x1U) << 16U; | ||
294 | } | ||
295 | static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x1U) << 17U; | ||
298 | } | ||
299 | static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) | ||
300 | { | ||
301 | return (v & 0x1U) << 18U; | ||
302 | } | ||
303 | static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) | ||
304 | { | ||
305 | return (v & 0x1U) << 19U; | ||
306 | } | ||
307 | static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1U) << 20U; | ||
310 | } | ||
311 | static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) | ||
312 | { | ||
313 | return (v & 0x1U) << 21U; | ||
314 | } | ||
315 | static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) | ||
316 | { | ||
317 | return (v & 0x1U) << 22U; | ||
318 | } | ||
319 | static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) | ||
320 | { | ||
321 | return (v & 0x1U) << 23U; | ||
322 | } | ||
323 | static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) | ||
324 | { | ||
325 | return (v & 0xffU) << 24U; | ||
326 | } | ||
327 | static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) | ||
328 | { | ||
329 | return (v & 0x1U) << 24U; | ||
330 | } | ||
331 | static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) | ||
332 | { | ||
333 | return (v & 0x1U) << 25U; | ||
334 | } | ||
335 | static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) | ||
336 | { | ||
337 | return (v & 0x1U) << 27U; | ||
338 | } | ||
339 | static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) | ||
340 | { | ||
341 | return (v & 0x1U) << 28U; | ||
342 | } | ||
343 | static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) | ||
344 | { | ||
345 | return (v & 0x1U) << 29U; | ||
346 | } | ||
347 | static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) | ||
348 | { | ||
349 | return (v & 0x1U) << 30U; | ||
350 | } | ||
351 | static inline u32 pwr_falcon_curctx_r(void) | ||
352 | { | ||
353 | return 0x0010a050U; | ||
354 | } | ||
355 | static inline u32 pwr_falcon_nxtctx_r(void) | ||
356 | { | ||
357 | return 0x0010a054U; | ||
358 | } | ||
359 | static inline u32 pwr_falcon_mailbox0_r(void) | ||
360 | { | ||
361 | return 0x0010a040U; | ||
362 | } | ||
363 | static inline u32 pwr_falcon_mailbox1_r(void) | ||
364 | { | ||
365 | return 0x0010a044U; | ||
366 | } | ||
367 | static inline u32 pwr_falcon_itfen_r(void) | ||
368 | { | ||
369 | return 0x0010a048U; | ||
370 | } | ||
371 | static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) | ||
372 | { | ||
373 | return 0x1U; | ||
374 | } | ||
375 | static inline u32 pwr_falcon_idlestate_r(void) | ||
376 | { | ||
377 | return 0x0010a04cU; | ||
378 | } | ||
379 | static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) | ||
380 | { | ||
381 | return (r >> 0U) & 0x1U; | ||
382 | } | ||
383 | static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) | ||
384 | { | ||
385 | return (r >> 1U) & 0x7fffU; | ||
386 | } | ||
387 | static inline u32 pwr_falcon_os_r(void) | ||
388 | { | ||
389 | return 0x0010a080U; | ||
390 | } | ||
391 | static inline u32 pwr_falcon_engctl_r(void) | ||
392 | { | ||
393 | return 0x0010a0a4U; | ||
394 | } | ||
395 | static inline u32 pwr_falcon_cpuctl_r(void) | ||
396 | { | ||
397 | return 0x0010a100U; | ||
398 | } | ||
399 | static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) | ||
400 | { | ||
401 | return (v & 0x1U) << 1U; | ||
402 | } | ||
403 | static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) | ||
404 | { | ||
405 | return (v & 0x1U) << 4U; | ||
406 | } | ||
407 | static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) | ||
408 | { | ||
409 | return 0x1U << 4U; | ||
410 | } | ||
411 | static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) | ||
412 | { | ||
413 | return (r >> 4U) & 0x1U; | ||
414 | } | ||
415 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) | ||
416 | { | ||
417 | return (v & 0x1U) << 6U; | ||
418 | } | ||
419 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) | ||
420 | { | ||
421 | return 0x1U << 6U; | ||
422 | } | ||
423 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) | ||
424 | { | ||
425 | return (r >> 6U) & 0x1U; | ||
426 | } | ||
427 | static inline u32 pwr_falcon_cpuctl_alias_r(void) | ||
428 | { | ||
429 | return 0x0010a130U; | ||
430 | } | ||
431 | static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) | ||
432 | { | ||
433 | return (v & 0x1U) << 1U; | ||
434 | } | ||
435 | static inline u32 pwr_pmu_scpctl_stat_r(void) | ||
436 | { | ||
437 | return 0x0010ac08U; | ||
438 | } | ||
439 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) | ||
440 | { | ||
441 | return (v & 0x1U) << 20U; | ||
442 | } | ||
443 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) | ||
444 | { | ||
445 | return 0x1U << 20U; | ||
446 | } | ||
447 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) | ||
448 | { | ||
449 | return (r >> 20U) & 0x1U; | ||
450 | } | ||
451 | static inline u32 pwr_falcon_imemc_r(u32 i) | ||
452 | { | ||
453 | return 0x0010a180U + i*16U; | ||
454 | } | ||
455 | static inline u32 pwr_falcon_imemc_offs_f(u32 v) | ||
456 | { | ||
457 | return (v & 0x3fU) << 2U; | ||
458 | } | ||
459 | static inline u32 pwr_falcon_imemc_blk_f(u32 v) | ||
460 | { | ||
461 | return (v & 0xffU) << 8U; | ||
462 | } | ||
463 | static inline u32 pwr_falcon_imemc_aincw_f(u32 v) | ||
464 | { | ||
465 | return (v & 0x1U) << 24U; | ||
466 | } | ||
467 | static inline u32 pwr_falcon_imemd_r(u32 i) | ||
468 | { | ||
469 | return 0x0010a184U + i*16U; | ||
470 | } | ||
471 | static inline u32 pwr_falcon_imemt_r(u32 i) | ||
472 | { | ||
473 | return 0x0010a188U + i*16U; | ||
474 | } | ||
475 | static inline u32 pwr_falcon_sctl_r(void) | ||
476 | { | ||
477 | return 0x0010a240U; | ||
478 | } | ||
479 | static inline u32 pwr_falcon_mmu_phys_sec_r(void) | ||
480 | { | ||
481 | return 0x00100ce4U; | ||
482 | } | ||
483 | static inline u32 pwr_falcon_bootvec_r(void) | ||
484 | { | ||
485 | return 0x0010a104U; | ||
486 | } | ||
487 | static inline u32 pwr_falcon_bootvec_vec_f(u32 v) | ||
488 | { | ||
489 | return (v & 0xffffffffU) << 0U; | ||
490 | } | ||
491 | static inline u32 pwr_falcon_dmactl_r(void) | ||
492 | { | ||
493 | return 0x0010a10cU; | ||
494 | } | ||
495 | static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) | ||
496 | { | ||
497 | return 0x1U << 1U; | ||
498 | } | ||
499 | static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) | ||
500 | { | ||
501 | return 0x1U << 2U; | ||
502 | } | ||
503 | static inline u32 pwr_falcon_hwcfg_r(void) | ||
504 | { | ||
505 | return 0x0010a108U; | ||
506 | } | ||
507 | static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) | ||
508 | { | ||
509 | return (r >> 0U) & 0x1ffU; | ||
510 | } | ||
511 | static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) | ||
512 | { | ||
513 | return (r >> 9U) & 0x1ffU; | ||
514 | } | ||
515 | static inline u32 pwr_falcon_dmatrfbase_r(void) | ||
516 | { | ||
517 | return 0x0010a110U; | ||
518 | } | ||
519 | static inline u32 pwr_falcon_dmatrfbase1_r(void) | ||
520 | { | ||
521 | return 0x0010a128U; | ||
522 | } | ||
523 | static inline u32 pwr_falcon_dmatrfmoffs_r(void) | ||
524 | { | ||
525 | return 0x0010a114U; | ||
526 | } | ||
527 | static inline u32 pwr_falcon_dmatrfcmd_r(void) | ||
528 | { | ||
529 | return 0x0010a118U; | ||
530 | } | ||
531 | static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) | ||
532 | { | ||
533 | return (v & 0x1U) << 4U; | ||
534 | } | ||
535 | static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) | ||
536 | { | ||
537 | return (v & 0x1U) << 5U; | ||
538 | } | ||
539 | static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) | ||
540 | { | ||
541 | return (v & 0x7U) << 8U; | ||
542 | } | ||
543 | static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) | ||
544 | { | ||
545 | return (v & 0x7U) << 12U; | ||
546 | } | ||
547 | static inline u32 pwr_falcon_dmatrffboffs_r(void) | ||
548 | { | ||
549 | return 0x0010a11cU; | ||
550 | } | ||
551 | static inline u32 pwr_falcon_exterraddr_r(void) | ||
552 | { | ||
553 | return 0x0010a168U; | ||
554 | } | ||
555 | static inline u32 pwr_falcon_exterrstat_r(void) | ||
556 | { | ||
557 | return 0x0010a16cU; | ||
558 | } | ||
559 | static inline u32 pwr_falcon_exterrstat_valid_m(void) | ||
560 | { | ||
561 | return 0x1U << 31U; | ||
562 | } | ||
563 | static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) | ||
564 | { | ||
565 | return (r >> 31U) & 0x1U; | ||
566 | } | ||
567 | static inline u32 pwr_falcon_exterrstat_valid_true_v(void) | ||
568 | { | ||
569 | return 0x00000001U; | ||
570 | } | ||
571 | static inline u32 pwr_pmu_falcon_icd_cmd_r(void) | ||
572 | { | ||
573 | return 0x0010a200U; | ||
574 | } | ||
575 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) | ||
576 | { | ||
577 | return 4U; | ||
578 | } | ||
579 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) | ||
580 | { | ||
581 | return (v & 0xfU) << 0U; | ||
582 | } | ||
583 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) | ||
584 | { | ||
585 | return 0xfU << 0U; | ||
586 | } | ||
587 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) | ||
588 | { | ||
589 | return (r >> 0U) & 0xfU; | ||
590 | } | ||
591 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) | ||
592 | { | ||
593 | return 0x8U; | ||
594 | } | ||
595 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) | ||
596 | { | ||
597 | return 0xeU; | ||
598 | } | ||
599 | static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) | ||
600 | { | ||
601 | return (v & 0x1fU) << 8U; | ||
602 | } | ||
603 | static inline u32 pwr_pmu_falcon_icd_rdata_r(void) | ||
604 | { | ||
605 | return 0x0010a20cU; | ||
606 | } | ||
607 | static inline u32 pwr_falcon_dmemc_r(u32 i) | ||
608 | { | ||
609 | return 0x0010a1c0U + i*8U; | ||
610 | } | ||
611 | static inline u32 pwr_falcon_dmemc_offs_f(u32 v) | ||
612 | { | ||
613 | return (v & 0x3fU) << 2U; | ||
614 | } | ||
615 | static inline u32 pwr_falcon_dmemc_offs_m(void) | ||
616 | { | ||
617 | return 0x3fU << 2U; | ||
618 | } | ||
619 | static inline u32 pwr_falcon_dmemc_blk_f(u32 v) | ||
620 | { | ||
621 | return (v & 0xffU) << 8U; | ||
622 | } | ||
623 | static inline u32 pwr_falcon_dmemc_blk_m(void) | ||
624 | { | ||
625 | return 0xffU << 8U; | ||
626 | } | ||
627 | static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) | ||
628 | { | ||
629 | return (v & 0x1U) << 24U; | ||
630 | } | ||
631 | static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) | ||
632 | { | ||
633 | return (v & 0x1U) << 25U; | ||
634 | } | ||
635 | static inline u32 pwr_falcon_dmemd_r(u32 i) | ||
636 | { | ||
637 | return 0x0010a1c4U + i*8U; | ||
638 | } | ||
639 | static inline u32 pwr_pmu_new_instblk_r(void) | ||
640 | { | ||
641 | return 0x0010a480U; | ||
642 | } | ||
643 | static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) | ||
644 | { | ||
645 | return (v & 0xfffffffU) << 0U; | ||
646 | } | ||
647 | static inline u32 pwr_pmu_new_instblk_target_fb_f(void) | ||
648 | { | ||
649 | return 0x0U; | ||
650 | } | ||
651 | static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) | ||
652 | { | ||
653 | return 0x20000000U; | ||
654 | } | ||
655 | static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) | ||
656 | { | ||
657 | return 0x30000000U; | ||
658 | } | ||
659 | static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) | ||
660 | { | ||
661 | return (v & 0x1U) << 30U; | ||
662 | } | ||
663 | static inline u32 pwr_pmu_mutex_id_r(void) | ||
664 | { | ||
665 | return 0x0010a488U; | ||
666 | } | ||
667 | static inline u32 pwr_pmu_mutex_id_value_v(u32 r) | ||
668 | { | ||
669 | return (r >> 0U) & 0xffU; | ||
670 | } | ||
671 | static inline u32 pwr_pmu_mutex_id_value_init_v(void) | ||
672 | { | ||
673 | return 0x00000000U; | ||
674 | } | ||
675 | static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) | ||
676 | { | ||
677 | return 0x000000ffU; | ||
678 | } | ||
679 | static inline u32 pwr_pmu_mutex_id_release_r(void) | ||
680 | { | ||
681 | return 0x0010a48cU; | ||
682 | } | ||
683 | static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) | ||
684 | { | ||
685 | return (v & 0xffU) << 0U; | ||
686 | } | ||
687 | static inline u32 pwr_pmu_mutex_id_release_value_m(void) | ||
688 | { | ||
689 | return 0xffU << 0U; | ||
690 | } | ||
691 | static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) | ||
692 | { | ||
693 | return 0x00000000U; | ||
694 | } | ||
695 | static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) | ||
696 | { | ||
697 | return 0x0U; | ||
698 | } | ||
699 | static inline u32 pwr_pmu_mutex_r(u32 i) | ||
700 | { | ||
701 | return 0x0010a580U + i*4U; | ||
702 | } | ||
703 | static inline u32 pwr_pmu_mutex__size_1_v(void) | ||
704 | { | ||
705 | return 0x00000010U; | ||
706 | } | ||
707 | static inline u32 pwr_pmu_mutex_value_f(u32 v) | ||
708 | { | ||
709 | return (v & 0xffU) << 0U; | ||
710 | } | ||
711 | static inline u32 pwr_pmu_mutex_value_v(u32 r) | ||
712 | { | ||
713 | return (r >> 0U) & 0xffU; | ||
714 | } | ||
715 | static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) | ||
716 | { | ||
717 | return 0x0U; | ||
718 | } | ||
719 | static inline u32 pwr_pmu_queue_head_r(u32 i) | ||
720 | { | ||
721 | return 0x0010a800U + i*4U; | ||
722 | } | ||
723 | static inline u32 pwr_pmu_queue_head__size_1_v(void) | ||
724 | { | ||
725 | return 0x00000008U; | ||
726 | } | ||
727 | static inline u32 pwr_pmu_queue_head_address_f(u32 v) | ||
728 | { | ||
729 | return (v & 0xffffffffU) << 0U; | ||
730 | } | ||
731 | static inline u32 pwr_pmu_queue_head_address_v(u32 r) | ||
732 | { | ||
733 | return (r >> 0U) & 0xffffffffU; | ||
734 | } | ||
735 | static inline u32 pwr_pmu_queue_tail_r(u32 i) | ||
736 | { | ||
737 | return 0x0010a820U + i*4U; | ||
738 | } | ||
739 | static inline u32 pwr_pmu_queue_tail__size_1_v(void) | ||
740 | { | ||
741 | return 0x00000008U; | ||
742 | } | ||
743 | static inline u32 pwr_pmu_queue_tail_address_f(u32 v) | ||
744 | { | ||
745 | return (v & 0xffffffffU) << 0U; | ||
746 | } | ||
747 | static inline u32 pwr_pmu_queue_tail_address_v(u32 r) | ||
748 | { | ||
749 | return (r >> 0U) & 0xffffffffU; | ||
750 | } | ||
751 | static inline u32 pwr_pmu_msgq_head_r(void) | ||
752 | { | ||
753 | return 0x0010a4c8U; | ||
754 | } | ||
755 | static inline u32 pwr_pmu_msgq_head_val_f(u32 v) | ||
756 | { | ||
757 | return (v & 0xffffffffU) << 0U; | ||
758 | } | ||
759 | static inline u32 pwr_pmu_msgq_head_val_v(u32 r) | ||
760 | { | ||
761 | return (r >> 0U) & 0xffffffffU; | ||
762 | } | ||
763 | static inline u32 pwr_pmu_msgq_tail_r(void) | ||
764 | { | ||
765 | return 0x0010a4ccU; | ||
766 | } | ||
767 | static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) | ||
768 | { | ||
769 | return (v & 0xffffffffU) << 0U; | ||
770 | } | ||
771 | static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) | ||
772 | { | ||
773 | return (r >> 0U) & 0xffffffffU; | ||
774 | } | ||
775 | static inline u32 pwr_pmu_idle_mask_r(u32 i) | ||
776 | { | ||
777 | return 0x0010a504U + i*16U; | ||
778 | } | ||
779 | static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) | ||
780 | { | ||
781 | return 0x1U; | ||
782 | } | ||
783 | static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) | ||
784 | { | ||
785 | return 0x200000U; | ||
786 | } | ||
787 | static inline u32 pwr_pmu_idle_count_r(u32 i) | ||
788 | { | ||
789 | return 0x0010a508U + i*16U; | ||
790 | } | ||
791 | static inline u32 pwr_pmu_idle_count_value_f(u32 v) | ||
792 | { | ||
793 | return (v & 0x7fffffffU) << 0U; | ||
794 | } | ||
795 | static inline u32 pwr_pmu_idle_count_value_v(u32 r) | ||
796 | { | ||
797 | return (r >> 0U) & 0x7fffffffU; | ||
798 | } | ||
799 | static inline u32 pwr_pmu_idle_count_reset_f(u32 v) | ||
800 | { | ||
801 | return (v & 0x1U) << 31U; | ||
802 | } | ||
803 | static inline u32 pwr_pmu_idle_ctrl_r(u32 i) | ||
804 | { | ||
805 | return 0x0010a50cU + i*16U; | ||
806 | } | ||
807 | static inline u32 pwr_pmu_idle_ctrl_value_m(void) | ||
808 | { | ||
809 | return 0x3U << 0U; | ||
810 | } | ||
811 | static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) | ||
812 | { | ||
813 | return 0x2U; | ||
814 | } | ||
815 | static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) | ||
816 | { | ||
817 | return 0x3U; | ||
818 | } | ||
819 | static inline u32 pwr_pmu_idle_ctrl_filter_m(void) | ||
820 | { | ||
821 | return 0x1U << 2U; | ||
822 | } | ||
823 | static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) | ||
824 | { | ||
825 | return 0x0U; | ||
826 | } | ||
827 | static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) | ||
828 | { | ||
829 | return 0x0010a9f0U + i*8U; | ||
830 | } | ||
831 | static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) | ||
832 | { | ||
833 | return 0x0010a9f4U + i*8U; | ||
834 | } | ||
835 | static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) | ||
836 | { | ||
837 | return 0x0010aa30U + i*8U; | ||
838 | } | ||
839 | static inline u32 pwr_pmu_debug_r(u32 i) | ||
840 | { | ||
841 | return 0x0010a5c0U + i*4U; | ||
842 | } | ||
843 | static inline u32 pwr_pmu_debug__size_1_v(void) | ||
844 | { | ||
845 | return 0x00000004U; | ||
846 | } | ||
847 | static inline u32 pwr_pmu_mailbox_r(u32 i) | ||
848 | { | ||
849 | return 0x0010a450U + i*4U; | ||
850 | } | ||
851 | static inline u32 pwr_pmu_mailbox__size_1_v(void) | ||
852 | { | ||
853 | return 0x0000000cU; | ||
854 | } | ||
855 | static inline u32 pwr_pmu_bar0_addr_r(void) | ||
856 | { | ||
857 | return 0x0010a7a0U; | ||
858 | } | ||
859 | static inline u32 pwr_pmu_bar0_data_r(void) | ||
860 | { | ||
861 | return 0x0010a7a4U; | ||
862 | } | ||
863 | static inline u32 pwr_pmu_bar0_ctl_r(void) | ||
864 | { | ||
865 | return 0x0010a7acU; | ||
866 | } | ||
867 | static inline u32 pwr_pmu_bar0_timeout_r(void) | ||
868 | { | ||
869 | return 0x0010a7a8U; | ||
870 | } | ||
871 | static inline u32 pwr_pmu_bar0_fecs_error_r(void) | ||
872 | { | ||
873 | return 0x0010a988U; | ||
874 | } | ||
875 | static inline u32 pwr_pmu_bar0_error_status_r(void) | ||
876 | { | ||
877 | return 0x0010a7b0U; | ||
878 | } | ||
879 | static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) | ||
880 | { | ||
881 | return 0x0010a6c0U + i*4U; | ||
882 | } | ||
883 | static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) | ||
884 | { | ||
885 | return 0x0010a6e8U + i*4U; | ||
886 | } | ||
887 | static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) | ||
888 | { | ||
889 | return 0x0010a710U + i*4U; | ||
890 | } | ||
891 | static inline u32 pwr_pmu_pg_intren_r(u32 i) | ||
892 | { | ||
893 | return 0x0010a760U + i*4U; | ||
894 | } | ||
895 | static inline u32 pwr_fbif_transcfg_r(u32 i) | ||
896 | { | ||
897 | return 0x0010ae00U + i*4U; | ||
898 | } | ||
899 | static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) | ||
900 | { | ||
901 | return 0x0U; | ||
902 | } | ||
903 | static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) | ||
904 | { | ||
905 | return 0x1U; | ||
906 | } | ||
907 | static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) | ||
908 | { | ||
909 | return 0x2U; | ||
910 | } | ||
911 | static inline u32 pwr_fbif_transcfg_mem_type_s(void) | ||
912 | { | ||
913 | return 1U; | ||
914 | } | ||
915 | static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) | ||
916 | { | ||
917 | return (v & 0x1U) << 2U; | ||
918 | } | ||
919 | static inline u32 pwr_fbif_transcfg_mem_type_m(void) | ||
920 | { | ||
921 | return 0x1U << 2U; | ||
922 | } | ||
923 | static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) | ||
924 | { | ||
925 | return (r >> 2U) & 0x1U; | ||
926 | } | ||
927 | static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) | ||
928 | { | ||
929 | return 0x0U; | ||
930 | } | ||
931 | static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) | ||
932 | { | ||
933 | return 0x4U; | ||
934 | } | ||
935 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h new file mode 100644 index 00000000..6b3e8aa6 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | |||
@@ -0,0 +1,775 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ram_gv100_h_ | ||
57 | #define _hw_ram_gv100_h_ | ||
58 | |||
59 | static inline u32 ram_in_ramfc_s(void) | ||
60 | { | ||
61 | return 4096U; | ||
62 | } | ||
63 | static inline u32 ram_in_ramfc_w(void) | ||
64 | { | ||
65 | return 0U; | ||
66 | } | ||
67 | static inline u32 ram_in_page_dir_base_target_f(u32 v) | ||
68 | { | ||
69 | return (v & 0x3U) << 0U; | ||
70 | } | ||
71 | static inline u32 ram_in_page_dir_base_target_w(void) | ||
72 | { | ||
73 | return 128U; | ||
74 | } | ||
75 | static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) | ||
76 | { | ||
77 | return 0x0U; | ||
78 | } | ||
79 | static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) | ||
80 | { | ||
81 | return 0x2U; | ||
82 | } | ||
83 | static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) | ||
84 | { | ||
85 | return 0x3U; | ||
86 | } | ||
87 | static inline u32 ram_in_page_dir_base_vol_w(void) | ||
88 | { | ||
89 | return 128U; | ||
90 | } | ||
91 | static inline u32 ram_in_page_dir_base_vol_true_f(void) | ||
92 | { | ||
93 | return 0x4U; | ||
94 | } | ||
95 | static inline u32 ram_in_page_dir_base_vol_false_f(void) | ||
96 | { | ||
97 | return 0x0U; | ||
98 | } | ||
99 | static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 4U; | ||
102 | } | ||
103 | static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) | ||
104 | { | ||
105 | return 0x1U << 4U; | ||
106 | } | ||
107 | static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) | ||
108 | { | ||
109 | return 128U; | ||
110 | } | ||
111 | static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) | ||
112 | { | ||
113 | return 0x10U; | ||
114 | } | ||
115 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 5U; | ||
118 | } | ||
119 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) | ||
120 | { | ||
121 | return 0x1U << 5U; | ||
122 | } | ||
123 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) | ||
124 | { | ||
125 | return 128U; | ||
126 | } | ||
127 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) | ||
128 | { | ||
129 | return 0x20U; | ||
130 | } | ||
131 | static inline u32 ram_in_big_page_size_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 11U; | ||
134 | } | ||
135 | static inline u32 ram_in_big_page_size_m(void) | ||
136 | { | ||
137 | return 0x1U << 11U; | ||
138 | } | ||
139 | static inline u32 ram_in_big_page_size_w(void) | ||
140 | { | ||
141 | return 128U; | ||
142 | } | ||
143 | static inline u32 ram_in_big_page_size_128kb_f(void) | ||
144 | { | ||
145 | return 0x0U; | ||
146 | } | ||
147 | static inline u32 ram_in_big_page_size_64kb_f(void) | ||
148 | { | ||
149 | return 0x800U; | ||
150 | } | ||
151 | static inline u32 ram_in_page_dir_base_lo_f(u32 v) | ||
152 | { | ||
153 | return (v & 0xfffffU) << 12U; | ||
154 | } | ||
155 | static inline u32 ram_in_page_dir_base_lo_w(void) | ||
156 | { | ||
157 | return 128U; | ||
158 | } | ||
159 | static inline u32 ram_in_page_dir_base_hi_f(u32 v) | ||
160 | { | ||
161 | return (v & 0xffffffffU) << 0U; | ||
162 | } | ||
163 | static inline u32 ram_in_page_dir_base_hi_w(void) | ||
164 | { | ||
165 | return 129U; | ||
166 | } | ||
167 | static inline u32 ram_in_engine_cs_w(void) | ||
168 | { | ||
169 | return 132U; | ||
170 | } | ||
171 | static inline u32 ram_in_engine_cs_wfi_v(void) | ||
172 | { | ||
173 | return 0x00000000U; | ||
174 | } | ||
175 | static inline u32 ram_in_engine_cs_wfi_f(void) | ||
176 | { | ||
177 | return 0x0U; | ||
178 | } | ||
179 | static inline u32 ram_in_engine_cs_fg_v(void) | ||
180 | { | ||
181 | return 0x00000001U; | ||
182 | } | ||
183 | static inline u32 ram_in_engine_cs_fg_f(void) | ||
184 | { | ||
185 | return 0x8U; | ||
186 | } | ||
187 | static inline u32 ram_in_engine_wfi_mode_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 2U; | ||
190 | } | ||
191 | static inline u32 ram_in_engine_wfi_mode_w(void) | ||
192 | { | ||
193 | return 132U; | ||
194 | } | ||
195 | static inline u32 ram_in_engine_wfi_mode_physical_v(void) | ||
196 | { | ||
197 | return 0x00000000U; | ||
198 | } | ||
199 | static inline u32 ram_in_engine_wfi_mode_virtual_v(void) | ||
200 | { | ||
201 | return 0x00000001U; | ||
202 | } | ||
203 | static inline u32 ram_in_engine_wfi_target_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x3U) << 0U; | ||
206 | } | ||
207 | static inline u32 ram_in_engine_wfi_target_w(void) | ||
208 | { | ||
209 | return 132U; | ||
210 | } | ||
211 | static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) | ||
212 | { | ||
213 | return 0x00000002U; | ||
214 | } | ||
215 | static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) | ||
216 | { | ||
217 | return 0x00000003U; | ||
218 | } | ||
219 | static inline u32 ram_in_engine_wfi_target_local_mem_v(void) | ||
220 | { | ||
221 | return 0x00000000U; | ||
222 | } | ||
223 | static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) | ||
224 | { | ||
225 | return (v & 0xfffffU) << 12U; | ||
226 | } | ||
227 | static inline u32 ram_in_engine_wfi_ptr_lo_w(void) | ||
228 | { | ||
229 | return 132U; | ||
230 | } | ||
231 | static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) | ||
232 | { | ||
233 | return (v & 0xffU) << 0U; | ||
234 | } | ||
235 | static inline u32 ram_in_engine_wfi_ptr_hi_w(void) | ||
236 | { | ||
237 | return 133U; | ||
238 | } | ||
239 | static inline u32 ram_in_engine_wfi_veid_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x3fU) << 0U; | ||
242 | } | ||
243 | static inline u32 ram_in_engine_wfi_veid_w(void) | ||
244 | { | ||
245 | return 134U; | ||
246 | } | ||
247 | static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) | ||
248 | { | ||
249 | return (v & 0xffffffffU) << 0U; | ||
250 | } | ||
251 | static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) | ||
252 | { | ||
253 | return 136U; | ||
254 | } | ||
255 | static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) | ||
256 | { | ||
257 | return (v & 0x1ffffU) << 0U; | ||
258 | } | ||
259 | static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) | ||
260 | { | ||
261 | return 137U; | ||
262 | } | ||
263 | static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) | ||
264 | { | ||
265 | return (v & 0x3U) << (0U + i*0U); | ||
266 | } | ||
267 | static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) | ||
268 | { | ||
269 | return 0x00000040U; | ||
270 | } | ||
271 | static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) | ||
272 | { | ||
273 | return 0x00000000U; | ||
274 | } | ||
275 | static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) | ||
276 | { | ||
277 | return 0x00000001U; | ||
278 | } | ||
279 | static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) | ||
280 | { | ||
281 | return 0x00000002U; | ||
282 | } | ||
283 | static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) | ||
284 | { | ||
285 | return 0x00000003U; | ||
286 | } | ||
287 | static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) | ||
288 | { | ||
289 | return (v & 0x1U) << (2U + i*0U); | ||
290 | } | ||
291 | static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) | ||
292 | { | ||
293 | return 0x00000040U; | ||
294 | } | ||
295 | static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) | ||
296 | { | ||
297 | return 0x00000001U; | ||
298 | } | ||
299 | static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) | ||
300 | { | ||
301 | return 0x00000000U; | ||
302 | } | ||
303 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) | ||
304 | { | ||
305 | return (v & 0x1U) << (4U + i*0U); | ||
306 | } | ||
307 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) | ||
308 | { | ||
309 | return 0x00000040U; | ||
310 | } | ||
311 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) | ||
312 | { | ||
313 | return 0x00000001U; | ||
314 | } | ||
315 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) | ||
316 | { | ||
317 | return 0x00000000U; | ||
318 | } | ||
319 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) | ||
320 | { | ||
321 | return (v & 0x1U) << (5U + i*0U); | ||
322 | } | ||
323 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) | ||
324 | { | ||
325 | return 0x00000040U; | ||
326 | } | ||
327 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) | ||
328 | { | ||
329 | return 0x00000001U; | ||
330 | } | ||
331 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) | ||
332 | { | ||
333 | return 0x00000000U; | ||
334 | } | ||
335 | static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) | ||
336 | { | ||
337 | return (v & 0x1U) << (10U + i*0U); | ||
338 | } | ||
339 | static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) | ||
340 | { | ||
341 | return 0x00000040U; | ||
342 | } | ||
343 | static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) | ||
344 | { | ||
345 | return 0x00000000U; | ||
346 | } | ||
347 | static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) | ||
348 | { | ||
349 | return 0x00000001U; | ||
350 | } | ||
351 | static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) | ||
352 | { | ||
353 | return (v & 0x1U) << (11U + i*0U); | ||
354 | } | ||
355 | static inline u32 ram_in_sc_big_page_size__size_1_v(void) | ||
356 | { | ||
357 | return 0x00000040U; | ||
358 | } | ||
359 | static inline u32 ram_in_sc_big_page_size_64kb_v(void) | ||
360 | { | ||
361 | return 0x00000001U; | ||
362 | } | ||
363 | static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) | ||
364 | { | ||
365 | return (v & 0xfffffU) << (12U + i*0U); | ||
366 | } | ||
367 | static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) | ||
368 | { | ||
369 | return 0x00000040U; | ||
370 | } | ||
371 | static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) | ||
372 | { | ||
373 | return (v & 0xffffffffU) << (0U + i*0U); | ||
374 | } | ||
375 | static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) | ||
376 | { | ||
377 | return 0x00000040U; | ||
378 | } | ||
379 | static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) | ||
380 | { | ||
381 | return (v & 0x3U) << 0U; | ||
382 | } | ||
383 | static inline u32 ram_in_sc_page_dir_base_target_0_w(void) | ||
384 | { | ||
385 | return 168U; | ||
386 | } | ||
387 | static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) | ||
388 | { | ||
389 | return (v & 0x1U) << 2U; | ||
390 | } | ||
391 | static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) | ||
392 | { | ||
393 | return 168U; | ||
394 | } | ||
395 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) | ||
396 | { | ||
397 | return (v & 0x1U) << 4U; | ||
398 | } | ||
399 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) | ||
400 | { | ||
401 | return 168U; | ||
402 | } | ||
403 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) | ||
404 | { | ||
405 | return (v & 0x1U) << 5U; | ||
406 | } | ||
407 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) | ||
408 | { | ||
409 | return 168U; | ||
410 | } | ||
411 | static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) | ||
412 | { | ||
413 | return (v & 0x1U) << 10U; | ||
414 | } | ||
415 | static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) | ||
416 | { | ||
417 | return 168U; | ||
418 | } | ||
419 | static inline u32 ram_in_sc_big_page_size_0_f(u32 v) | ||
420 | { | ||
421 | return (v & 0x1U) << 11U; | ||
422 | } | ||
423 | static inline u32 ram_in_sc_big_page_size_0_w(void) | ||
424 | { | ||
425 | return 168U; | ||
426 | } | ||
427 | static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) | ||
428 | { | ||
429 | return (v & 0xfffffU) << 12U; | ||
430 | } | ||
431 | static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) | ||
432 | { | ||
433 | return 168U; | ||
434 | } | ||
435 | static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) | ||
436 | { | ||
437 | return (v & 0xffffffffU) << 0U; | ||
438 | } | ||
439 | static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) | ||
440 | { | ||
441 | return 169U; | ||
442 | } | ||
443 | static inline u32 ram_in_base_shift_v(void) | ||
444 | { | ||
445 | return 0x0000000cU; | ||
446 | } | ||
447 | static inline u32 ram_in_alloc_size_v(void) | ||
448 | { | ||
449 | return 0x00001000U; | ||
450 | } | ||
451 | static inline u32 ram_fc_size_val_v(void) | ||
452 | { | ||
453 | return 0x00000200U; | ||
454 | } | ||
455 | static inline u32 ram_fc_gp_put_w(void) | ||
456 | { | ||
457 | return 0U; | ||
458 | } | ||
459 | static inline u32 ram_fc_userd_w(void) | ||
460 | { | ||
461 | return 2U; | ||
462 | } | ||
463 | static inline u32 ram_fc_userd_hi_w(void) | ||
464 | { | ||
465 | return 3U; | ||
466 | } | ||
467 | static inline u32 ram_fc_signature_w(void) | ||
468 | { | ||
469 | return 4U; | ||
470 | } | ||
471 | static inline u32 ram_fc_gp_get_w(void) | ||
472 | { | ||
473 | return 5U; | ||
474 | } | ||
475 | static inline u32 ram_fc_pb_get_w(void) | ||
476 | { | ||
477 | return 6U; | ||
478 | } | ||
479 | static inline u32 ram_fc_pb_get_hi_w(void) | ||
480 | { | ||
481 | return 7U; | ||
482 | } | ||
483 | static inline u32 ram_fc_pb_top_level_get_w(void) | ||
484 | { | ||
485 | return 8U; | ||
486 | } | ||
487 | static inline u32 ram_fc_pb_top_level_get_hi_w(void) | ||
488 | { | ||
489 | return 9U; | ||
490 | } | ||
491 | static inline u32 ram_fc_acquire_w(void) | ||
492 | { | ||
493 | return 12U; | ||
494 | } | ||
495 | static inline u32 ram_fc_sem_addr_hi_w(void) | ||
496 | { | ||
497 | return 14U; | ||
498 | } | ||
499 | static inline u32 ram_fc_sem_addr_lo_w(void) | ||
500 | { | ||
501 | return 15U; | ||
502 | } | ||
503 | static inline u32 ram_fc_sem_payload_lo_w(void) | ||
504 | { | ||
505 | return 16U; | ||
506 | } | ||
507 | static inline u32 ram_fc_sem_payload_hi_w(void) | ||
508 | { | ||
509 | return 39U; | ||
510 | } | ||
511 | static inline u32 ram_fc_sem_execute_w(void) | ||
512 | { | ||
513 | return 17U; | ||
514 | } | ||
515 | static inline u32 ram_fc_gp_base_w(void) | ||
516 | { | ||
517 | return 18U; | ||
518 | } | ||
519 | static inline u32 ram_fc_gp_base_hi_w(void) | ||
520 | { | ||
521 | return 19U; | ||
522 | } | ||
523 | static inline u32 ram_fc_gp_fetch_w(void) | ||
524 | { | ||
525 | return 20U; | ||
526 | } | ||
527 | static inline u32 ram_fc_pb_fetch_w(void) | ||
528 | { | ||
529 | return 21U; | ||
530 | } | ||
531 | static inline u32 ram_fc_pb_fetch_hi_w(void) | ||
532 | { | ||
533 | return 22U; | ||
534 | } | ||
535 | static inline u32 ram_fc_pb_put_w(void) | ||
536 | { | ||
537 | return 23U; | ||
538 | } | ||
539 | static inline u32 ram_fc_pb_put_hi_w(void) | ||
540 | { | ||
541 | return 24U; | ||
542 | } | ||
543 | static inline u32 ram_fc_pb_header_w(void) | ||
544 | { | ||
545 | return 33U; | ||
546 | } | ||
547 | static inline u32 ram_fc_pb_count_w(void) | ||
548 | { | ||
549 | return 34U; | ||
550 | } | ||
551 | static inline u32 ram_fc_subdevice_w(void) | ||
552 | { | ||
553 | return 37U; | ||
554 | } | ||
555 | static inline u32 ram_fc_target_w(void) | ||
556 | { | ||
557 | return 43U; | ||
558 | } | ||
559 | static inline u32 ram_fc_hce_ctrl_w(void) | ||
560 | { | ||
561 | return 57U; | ||
562 | } | ||
563 | static inline u32 ram_fc_chid_w(void) | ||
564 | { | ||
565 | return 58U; | ||
566 | } | ||
567 | static inline u32 ram_fc_chid_id_f(u32 v) | ||
568 | { | ||
569 | return (v & 0xfffU) << 0U; | ||
570 | } | ||
571 | static inline u32 ram_fc_chid_id_w(void) | ||
572 | { | ||
573 | return 0U; | ||
574 | } | ||
575 | static inline u32 ram_fc_config_w(void) | ||
576 | { | ||
577 | return 61U; | ||
578 | } | ||
579 | static inline u32 ram_fc_runlist_timeslice_w(void) | ||
580 | { | ||
581 | return 62U; | ||
582 | } | ||
583 | static inline u32 ram_fc_set_channel_info_w(void) | ||
584 | { | ||
585 | return 63U; | ||
586 | } | ||
587 | static inline u32 ram_userd_base_shift_v(void) | ||
588 | { | ||
589 | return 0x00000009U; | ||
590 | } | ||
591 | static inline u32 ram_userd_chan_size_v(void) | ||
592 | { | ||
593 | return 0x00000200U; | ||
594 | } | ||
595 | static inline u32 ram_userd_put_w(void) | ||
596 | { | ||
597 | return 16U; | ||
598 | } | ||
599 | static inline u32 ram_userd_get_w(void) | ||
600 | { | ||
601 | return 17U; | ||
602 | } | ||
603 | static inline u32 ram_userd_ref_w(void) | ||
604 | { | ||
605 | return 18U; | ||
606 | } | ||
607 | static inline u32 ram_userd_put_hi_w(void) | ||
608 | { | ||
609 | return 19U; | ||
610 | } | ||
611 | static inline u32 ram_userd_ref_threshold_w(void) | ||
612 | { | ||
613 | return 20U; | ||
614 | } | ||
615 | static inline u32 ram_userd_top_level_get_w(void) | ||
616 | { | ||
617 | return 22U; | ||
618 | } | ||
619 | static inline u32 ram_userd_top_level_get_hi_w(void) | ||
620 | { | ||
621 | return 23U; | ||
622 | } | ||
623 | static inline u32 ram_userd_get_hi_w(void) | ||
624 | { | ||
625 | return 24U; | ||
626 | } | ||
627 | static inline u32 ram_userd_gp_get_w(void) | ||
628 | { | ||
629 | return 34U; | ||
630 | } | ||
631 | static inline u32 ram_userd_gp_put_w(void) | ||
632 | { | ||
633 | return 35U; | ||
634 | } | ||
635 | static inline u32 ram_userd_gp_top_level_get_w(void) | ||
636 | { | ||
637 | return 22U; | ||
638 | } | ||
639 | static inline u32 ram_userd_gp_top_level_get_hi_w(void) | ||
640 | { | ||
641 | return 23U; | ||
642 | } | ||
643 | static inline u32 ram_rl_entry_size_v(void) | ||
644 | { | ||
645 | return 0x00000010U; | ||
646 | } | ||
647 | static inline u32 ram_rl_entry_type_f(u32 v) | ||
648 | { | ||
649 | return (v & 0x1U) << 0U; | ||
650 | } | ||
651 | static inline u32 ram_rl_entry_type_channel_v(void) | ||
652 | { | ||
653 | return 0x00000000U; | ||
654 | } | ||
655 | static inline u32 ram_rl_entry_type_tsg_v(void) | ||
656 | { | ||
657 | return 0x00000001U; | ||
658 | } | ||
659 | static inline u32 ram_rl_entry_id_f(u32 v) | ||
660 | { | ||
661 | return (v & 0xfffU) << 0U; | ||
662 | } | ||
663 | static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) | ||
664 | { | ||
665 | return (v & 0x1U) << 1U; | ||
666 | } | ||
667 | static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) | ||
668 | { | ||
669 | return (v & 0x3U) << 4U; | ||
670 | } | ||
671 | static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) | ||
672 | { | ||
673 | return 0x00000003U; | ||
674 | } | ||
675 | static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) | ||
676 | { | ||
677 | return 0x00000002U; | ||
678 | } | ||
679 | static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) | ||
680 | { | ||
681 | return 0x00000000U; | ||
682 | } | ||
683 | static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) | ||
684 | { | ||
685 | return (v & 0x3U) << 6U; | ||
686 | } | ||
687 | static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) | ||
688 | { | ||
689 | return 0x00000000U; | ||
690 | } | ||
691 | static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) | ||
692 | { | ||
693 | return 0x00000001U; | ||
694 | } | ||
695 | static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) | ||
696 | { | ||
697 | return 0x00000002U; | ||
698 | } | ||
699 | static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) | ||
700 | { | ||
701 | return 0x00000003U; | ||
702 | } | ||
703 | static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) | ||
704 | { | ||
705 | return (v & 0xffffffU) << 8U; | ||
706 | } | ||
707 | static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) | ||
708 | { | ||
709 | return (v & 0xffffffffU) << 0U; | ||
710 | } | ||
711 | static inline u32 ram_rl_entry_chid_f(u32 v) | ||
712 | { | ||
713 | return (v & 0xfffU) << 0U; | ||
714 | } | ||
715 | static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) | ||
716 | { | ||
717 | return (v & 0xfffffU) << 12U; | ||
718 | } | ||
719 | static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) | ||
720 | { | ||
721 | return (v & 0xffffffffU) << 0U; | ||
722 | } | ||
723 | static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) | ||
724 | { | ||
725 | return (v & 0xfU) << 16U; | ||
726 | } | ||
727 | static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) | ||
728 | { | ||
729 | return 0x00000003U; | ||
730 | } | ||
731 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) | ||
732 | { | ||
733 | return (v & 0xffU) << 24U; | ||
734 | } | ||
735 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) | ||
736 | { | ||
737 | return 0x00000080U; | ||
738 | } | ||
739 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) | ||
740 | { | ||
741 | return 0x00000000U; | ||
742 | } | ||
743 | static inline u32 ram_rl_entry_tsg_length_f(u32 v) | ||
744 | { | ||
745 | return (v & 0xffU) << 0U; | ||
746 | } | ||
747 | static inline u32 ram_rl_entry_tsg_length_init_v(void) | ||
748 | { | ||
749 | return 0x00000000U; | ||
750 | } | ||
751 | static inline u32 ram_rl_entry_tsg_length_min_v(void) | ||
752 | { | ||
753 | return 0x00000001U; | ||
754 | } | ||
755 | static inline u32 ram_rl_entry_tsg_length_max_v(void) | ||
756 | { | ||
757 | return 0x00000080U; | ||
758 | } | ||
759 | static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) | ||
760 | { | ||
761 | return (v & 0xfffU) << 0U; | ||
762 | } | ||
763 | static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) | ||
764 | { | ||
765 | return 0x00000008U; | ||
766 | } | ||
767 | static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) | ||
768 | { | ||
769 | return 0x00000008U; | ||
770 | } | ||
771 | static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) | ||
772 | { | ||
773 | return 0x0000000cU; | ||
774 | } | ||
775 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h new file mode 100644 index 00000000..2ea71ef1 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h | |||
@@ -0,0 +1,299 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_therm_gv100_h_ | ||
57 | #define _hw_therm_gv100_h_ | ||
58 | |||
59 | static inline u32 therm_weight_1_r(void) | ||
60 | { | ||
61 | return 0x00020024U; | ||
62 | } | ||
63 | static inline u32 therm_config1_r(void) | ||
64 | { | ||
65 | return 0x00020050U; | ||
66 | } | ||
67 | static inline u32 therm_config2_r(void) | ||
68 | { | ||
69 | return 0x00020130U; | ||
70 | } | ||
71 | static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) | ||
72 | { | ||
73 | return (v & 0x1U) << 24U; | ||
74 | } | ||
75 | static inline u32 therm_config2_grad_enable_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x1U) << 31U; | ||
78 | } | ||
79 | static inline u32 therm_gate_ctrl_r(u32 i) | ||
80 | { | ||
81 | return 0x00020200U + i*4U; | ||
82 | } | ||
83 | static inline u32 therm_gate_ctrl_eng_clk_m(void) | ||
84 | { | ||
85 | return 0x3U << 0U; | ||
86 | } | ||
87 | static inline u32 therm_gate_ctrl_eng_clk_run_f(void) | ||
88 | { | ||
89 | return 0x0U; | ||
90 | } | ||
91 | static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) | ||
92 | { | ||
93 | return 0x1U; | ||
94 | } | ||
95 | static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) | ||
96 | { | ||
97 | return 0x2U; | ||
98 | } | ||
99 | static inline u32 therm_gate_ctrl_blk_clk_m(void) | ||
100 | { | ||
101 | return 0x3U << 2U; | ||
102 | } | ||
103 | static inline u32 therm_gate_ctrl_blk_clk_run_f(void) | ||
104 | { | ||
105 | return 0x0U; | ||
106 | } | ||
107 | static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) | ||
108 | { | ||
109 | return 0x4U; | ||
110 | } | ||
111 | static inline u32 therm_gate_ctrl_idle_holdoff_m(void) | ||
112 | { | ||
113 | return 0x1U << 4U; | ||
114 | } | ||
115 | static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) | ||
116 | { | ||
117 | return 0x0U; | ||
118 | } | ||
119 | static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) | ||
120 | { | ||
121 | return 0x10U; | ||
122 | } | ||
123 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) | ||
124 | { | ||
125 | return (v & 0x1fU) << 8U; | ||
126 | } | ||
127 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) | ||
128 | { | ||
129 | return 0x1fU << 8U; | ||
130 | } | ||
131 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x7U) << 13U; | ||
134 | } | ||
135 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) | ||
136 | { | ||
137 | return 0x7U << 13U; | ||
138 | } | ||
139 | static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) | ||
140 | { | ||
141 | return (v & 0xfU) << 16U; | ||
142 | } | ||
143 | static inline u32 therm_gate_ctrl_eng_delay_before_m(void) | ||
144 | { | ||
145 | return 0xfU << 16U; | ||
146 | } | ||
147 | static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) | ||
148 | { | ||
149 | return (v & 0xfU) << 20U; | ||
150 | } | ||
151 | static inline u32 therm_gate_ctrl_eng_delay_after_m(void) | ||
152 | { | ||
153 | return 0xfU << 20U; | ||
154 | } | ||
155 | static inline u32 therm_fecs_idle_filter_r(void) | ||
156 | { | ||
157 | return 0x00020288U; | ||
158 | } | ||
159 | static inline u32 therm_fecs_idle_filter_value_m(void) | ||
160 | { | ||
161 | return 0xffffffffU << 0U; | ||
162 | } | ||
163 | static inline u32 therm_hubmmu_idle_filter_r(void) | ||
164 | { | ||
165 | return 0x0002028cU; | ||
166 | } | ||
167 | static inline u32 therm_hubmmu_idle_filter_value_m(void) | ||
168 | { | ||
169 | return 0xffffffffU << 0U; | ||
170 | } | ||
171 | static inline u32 therm_clk_slowdown_r(u32 i) | ||
172 | { | ||
173 | return 0x00020160U + i*4U; | ||
174 | } | ||
175 | static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x3fU) << 16U; | ||
178 | } | ||
179 | static inline u32 therm_clk_slowdown_idle_factor_m(void) | ||
180 | { | ||
181 | return 0x3fU << 16U; | ||
182 | } | ||
183 | static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) | ||
184 | { | ||
185 | return (r >> 16U) & 0x3fU; | ||
186 | } | ||
187 | static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) | ||
188 | { | ||
189 | return 0x0U; | ||
190 | } | ||
191 | static inline u32 therm_grad_stepping_table_r(u32 i) | ||
192 | { | ||
193 | return 0x000202c8U + i*4U; | ||
194 | } | ||
195 | static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x3fU) << 0U; | ||
198 | } | ||
199 | static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) | ||
200 | { | ||
201 | return 0x3fU << 0U; | ||
202 | } | ||
203 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) | ||
204 | { | ||
205 | return 0x1U; | ||
206 | } | ||
207 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) | ||
208 | { | ||
209 | return 0x2U; | ||
210 | } | ||
211 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) | ||
212 | { | ||
213 | return 0x6U; | ||
214 | } | ||
215 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) | ||
216 | { | ||
217 | return 0xeU; | ||
218 | } | ||
219 | static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x3fU) << 6U; | ||
222 | } | ||
223 | static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) | ||
224 | { | ||
225 | return 0x3fU << 6U; | ||
226 | } | ||
227 | static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x3fU) << 12U; | ||
230 | } | ||
231 | static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) | ||
232 | { | ||
233 | return 0x3fU << 12U; | ||
234 | } | ||
235 | static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x3fU) << 18U; | ||
238 | } | ||
239 | static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) | ||
240 | { | ||
241 | return 0x3fU << 18U; | ||
242 | } | ||
243 | static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) | ||
244 | { | ||
245 | return (v & 0x3fU) << 24U; | ||
246 | } | ||
247 | static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) | ||
248 | { | ||
249 | return 0x3fU << 24U; | ||
250 | } | ||
251 | static inline u32 therm_grad_stepping0_r(void) | ||
252 | { | ||
253 | return 0x000202c0U; | ||
254 | } | ||
255 | static inline u32 therm_grad_stepping0_feature_s(void) | ||
256 | { | ||
257 | return 1U; | ||
258 | } | ||
259 | static inline u32 therm_grad_stepping0_feature_f(u32 v) | ||
260 | { | ||
261 | return (v & 0x1U) << 0U; | ||
262 | } | ||
263 | static inline u32 therm_grad_stepping0_feature_m(void) | ||
264 | { | ||
265 | return 0x1U << 0U; | ||
266 | } | ||
267 | static inline u32 therm_grad_stepping0_feature_v(u32 r) | ||
268 | { | ||
269 | return (r >> 0U) & 0x1U; | ||
270 | } | ||
271 | static inline u32 therm_grad_stepping0_feature_enable_f(void) | ||
272 | { | ||
273 | return 0x1U; | ||
274 | } | ||
275 | static inline u32 therm_grad_stepping1_r(void) | ||
276 | { | ||
277 | return 0x000202c4U; | ||
278 | } | ||
279 | static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) | ||
280 | { | ||
281 | return (v & 0x1ffffU) << 0U; | ||
282 | } | ||
283 | static inline u32 therm_clk_timing_r(u32 i) | ||
284 | { | ||
285 | return 0x000203c0U + i*4U; | ||
286 | } | ||
287 | static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) | ||
288 | { | ||
289 | return (v & 0x1U) << 16U; | ||
290 | } | ||
291 | static inline u32 therm_clk_timing_grad_slowdown_m(void) | ||
292 | { | ||
293 | return 0x1U << 16U; | ||
294 | } | ||
295 | static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) | ||
296 | { | ||
297 | return 0x10000U; | ||
298 | } | ||
299 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h new file mode 100644 index 00000000..9d76e241 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h | |||
@@ -0,0 +1,115 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_timer_gv100_h_ | ||
57 | #define _hw_timer_gv100_h_ | ||
58 | |||
59 | static inline u32 timer_pri_timeout_r(void) | ||
60 | { | ||
61 | return 0x00009080U; | ||
62 | } | ||
63 | static inline u32 timer_pri_timeout_period_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xffffffU) << 0U; | ||
66 | } | ||
67 | static inline u32 timer_pri_timeout_period_m(void) | ||
68 | { | ||
69 | return 0xffffffU << 0U; | ||
70 | } | ||
71 | static inline u32 timer_pri_timeout_period_v(u32 r) | ||
72 | { | ||
73 | return (r >> 0U) & 0xffffffU; | ||
74 | } | ||
75 | static inline u32 timer_pri_timeout_en_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x1U) << 31U; | ||
78 | } | ||
79 | static inline u32 timer_pri_timeout_en_m(void) | ||
80 | { | ||
81 | return 0x1U << 31U; | ||
82 | } | ||
83 | static inline u32 timer_pri_timeout_en_v(u32 r) | ||
84 | { | ||
85 | return (r >> 31U) & 0x1U; | ||
86 | } | ||
87 | static inline u32 timer_pri_timeout_en_en_enabled_f(void) | ||
88 | { | ||
89 | return 0x80000000U; | ||
90 | } | ||
91 | static inline u32 timer_pri_timeout_en_en_disabled_f(void) | ||
92 | { | ||
93 | return 0x0U; | ||
94 | } | ||
95 | static inline u32 timer_pri_timeout_save_0_r(void) | ||
96 | { | ||
97 | return 0x00009084U; | ||
98 | } | ||
99 | static inline u32 timer_pri_timeout_save_1_r(void) | ||
100 | { | ||
101 | return 0x00009088U; | ||
102 | } | ||
103 | static inline u32 timer_pri_timeout_fecs_errcode_r(void) | ||
104 | { | ||
105 | return 0x0000908cU; | ||
106 | } | ||
107 | static inline u32 timer_time_0_r(void) | ||
108 | { | ||
109 | return 0x00009400U; | ||
110 | } | ||
111 | static inline u32 timer_time_1_r(void) | ||
112 | { | ||
113 | return 0x00009410U; | ||
114 | } | ||
115 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h new file mode 100644 index 00000000..da297b72 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | |||
@@ -0,0 +1,235 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_top_gv100_h_ | ||
57 | #define _hw_top_gv100_h_ | ||
58 | |||
59 | static inline u32 top_num_gpcs_r(void) | ||
60 | { | ||
61 | return 0x00022430U; | ||
62 | } | ||
63 | static inline u32 top_num_gpcs_value_v(u32 r) | ||
64 | { | ||
65 | return (r >> 0U) & 0x1fU; | ||
66 | } | ||
67 | static inline u32 top_tpc_per_gpc_r(void) | ||
68 | { | ||
69 | return 0x00022434U; | ||
70 | } | ||
71 | static inline u32 top_tpc_per_gpc_value_v(u32 r) | ||
72 | { | ||
73 | return (r >> 0U) & 0x1fU; | ||
74 | } | ||
75 | static inline u32 top_num_fbps_r(void) | ||
76 | { | ||
77 | return 0x00022438U; | ||
78 | } | ||
79 | static inline u32 top_num_fbps_value_v(u32 r) | ||
80 | { | ||
81 | return (r >> 0U) & 0x1fU; | ||
82 | } | ||
83 | static inline u32 top_ltc_per_fbp_r(void) | ||
84 | { | ||
85 | return 0x00022450U; | ||
86 | } | ||
87 | static inline u32 top_ltc_per_fbp_value_v(u32 r) | ||
88 | { | ||
89 | return (r >> 0U) & 0x1fU; | ||
90 | } | ||
91 | static inline u32 top_slices_per_ltc_r(void) | ||
92 | { | ||
93 | return 0x0002245cU; | ||
94 | } | ||
95 | static inline u32 top_slices_per_ltc_value_v(u32 r) | ||
96 | { | ||
97 | return (r >> 0U) & 0x1fU; | ||
98 | } | ||
99 | static inline u32 top_num_ltcs_r(void) | ||
100 | { | ||
101 | return 0x00022454U; | ||
102 | } | ||
103 | static inline u32 top_num_ces_r(void) | ||
104 | { | ||
105 | return 0x00022444U; | ||
106 | } | ||
107 | static inline u32 top_num_ces_value_v(u32 r) | ||
108 | { | ||
109 | return (r >> 0U) & 0x1fU; | ||
110 | } | ||
111 | static inline u32 top_device_info_r(u32 i) | ||
112 | { | ||
113 | return 0x00022700U + i*4U; | ||
114 | } | ||
115 | static inline u32 top_device_info__size_1_v(void) | ||
116 | { | ||
117 | return 0x00000040U; | ||
118 | } | ||
119 | static inline u32 top_device_info_chain_v(u32 r) | ||
120 | { | ||
121 | return (r >> 31U) & 0x1U; | ||
122 | } | ||
123 | static inline u32 top_device_info_chain_enable_v(void) | ||
124 | { | ||
125 | return 0x00000001U; | ||
126 | } | ||
127 | static inline u32 top_device_info_engine_enum_v(u32 r) | ||
128 | { | ||
129 | return (r >> 26U) & 0xfU; | ||
130 | } | ||
131 | static inline u32 top_device_info_runlist_enum_v(u32 r) | ||
132 | { | ||
133 | return (r >> 21U) & 0xfU; | ||
134 | } | ||
135 | static inline u32 top_device_info_intr_enum_v(u32 r) | ||
136 | { | ||
137 | return (r >> 15U) & 0x1fU; | ||
138 | } | ||
139 | static inline u32 top_device_info_reset_enum_v(u32 r) | ||
140 | { | ||
141 | return (r >> 9U) & 0x1fU; | ||
142 | } | ||
143 | static inline u32 top_device_info_type_enum_v(u32 r) | ||
144 | { | ||
145 | return (r >> 2U) & 0x1fffffffU; | ||
146 | } | ||
147 | static inline u32 top_device_info_type_enum_graphics_v(void) | ||
148 | { | ||
149 | return 0x00000000U; | ||
150 | } | ||
151 | static inline u32 top_device_info_type_enum_graphics_f(void) | ||
152 | { | ||
153 | return 0x0U; | ||
154 | } | ||
155 | static inline u32 top_device_info_type_enum_copy2_v(void) | ||
156 | { | ||
157 | return 0x00000003U; | ||
158 | } | ||
159 | static inline u32 top_device_info_type_enum_copy2_f(void) | ||
160 | { | ||
161 | return 0xcU; | ||
162 | } | ||
163 | static inline u32 top_device_info_type_enum_lce_v(void) | ||
164 | { | ||
165 | return 0x00000013U; | ||
166 | } | ||
167 | static inline u32 top_device_info_type_enum_lce_f(void) | ||
168 | { | ||
169 | return 0x4cU; | ||
170 | } | ||
171 | static inline u32 top_device_info_engine_v(u32 r) | ||
172 | { | ||
173 | return (r >> 5U) & 0x1U; | ||
174 | } | ||
175 | static inline u32 top_device_info_runlist_v(u32 r) | ||
176 | { | ||
177 | return (r >> 4U) & 0x1U; | ||
178 | } | ||
179 | static inline u32 top_device_info_intr_v(u32 r) | ||
180 | { | ||
181 | return (r >> 3U) & 0x1U; | ||
182 | } | ||
183 | static inline u32 top_device_info_reset_v(u32 r) | ||
184 | { | ||
185 | return (r >> 2U) & 0x1U; | ||
186 | } | ||
187 | static inline u32 top_device_info_entry_v(u32 r) | ||
188 | { | ||
189 | return (r >> 0U) & 0x3U; | ||
190 | } | ||
191 | static inline u32 top_device_info_entry_not_valid_v(void) | ||
192 | { | ||
193 | return 0x00000000U; | ||
194 | } | ||
195 | static inline u32 top_device_info_entry_enum_v(void) | ||
196 | { | ||
197 | return 0x00000002U; | ||
198 | } | ||
199 | static inline u32 top_device_info_entry_data_v(void) | ||
200 | { | ||
201 | return 0x00000001U; | ||
202 | } | ||
203 | static inline u32 top_device_info_data_type_v(u32 r) | ||
204 | { | ||
205 | return (r >> 30U) & 0x1U; | ||
206 | } | ||
207 | static inline u32 top_device_info_data_type_enum2_v(void) | ||
208 | { | ||
209 | return 0x00000000U; | ||
210 | } | ||
211 | static inline u32 top_device_info_data_inst_id_v(u32 r) | ||
212 | { | ||
213 | return (r >> 26U) & 0xfU; | ||
214 | } | ||
215 | static inline u32 top_device_info_data_pri_base_v(u32 r) | ||
216 | { | ||
217 | return (r >> 12U) & 0xfffU; | ||
218 | } | ||
219 | static inline u32 top_device_info_data_pri_base_align_v(void) | ||
220 | { | ||
221 | return 0x0000000cU; | ||
222 | } | ||
223 | static inline u32 top_device_info_data_fault_id_enum_v(u32 r) | ||
224 | { | ||
225 | return (r >> 3U) & 0x7fU; | ||
226 | } | ||
227 | static inline u32 top_device_info_data_fault_id_v(u32 r) | ||
228 | { | ||
229 | return (r >> 2U) & 0x1U; | ||
230 | } | ||
231 | static inline u32 top_device_info_data_fault_id_valid_v(void) | ||
232 | { | ||
233 | return 0x00000001U; | ||
234 | } | ||
235 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h new file mode 100644 index 00000000..7b1d861e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h | |||
@@ -0,0 +1,95 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_usermode_gv100_h_ | ||
57 | #define _hw_usermode_gv100_h_ | ||
58 | |||
59 | static inline u32 usermode_cfg0_r(void) | ||
60 | { | ||
61 | return 0x00810000U; | ||
62 | } | ||
63 | static inline u32 usermode_cfg0_class_id_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xffffU) << 0U; | ||
66 | } | ||
67 | static inline u32 usermode_cfg0_class_id_value_v(void) | ||
68 | { | ||
69 | return 0x0000c361U; | ||
70 | } | ||
71 | static inline u32 usermode_time_0_r(void) | ||
72 | { | ||
73 | return 0x00810080U; | ||
74 | } | ||
75 | static inline u32 usermode_time_0_nsec_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x7ffffffU) << 5U; | ||
78 | } | ||
79 | static inline u32 usermode_time_1_r(void) | ||
80 | { | ||
81 | return 0x00810084U; | ||
82 | } | ||
83 | static inline u32 usermode_time_1_nsec_f(u32 v) | ||
84 | { | ||
85 | return (v & 0x1fffffffU) << 0U; | ||
86 | } | ||
87 | static inline u32 usermode_notify_channel_pending_r(void) | ||
88 | { | ||
89 | return 0x00810090U; | ||
90 | } | ||
91 | static inline u32 usermode_notify_channel_pending_id_f(u32 v) | ||
92 | { | ||
93 | return (v & 0xffffffffU) << 0U; | ||
94 | } | ||
95 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h new file mode 100644 index 00000000..4296e043 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h | |||
@@ -0,0 +1,143 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_xp_gv100_h_ | ||
57 | #define _hw_xp_gv100_h_ | ||
58 | |||
59 | static inline u32 xp_dl_mgr_r(u32 i) | ||
60 | { | ||
61 | return 0x0008b8c0U + i*4U; | ||
62 | } | ||
63 | static inline u32 xp_dl_mgr_safe_timing_f(u32 v) | ||
64 | { | ||
65 | return (v & 0x1U) << 2U; | ||
66 | } | ||
67 | static inline u32 xp_pl_link_config_r(u32 i) | ||
68 | { | ||
69 | return 0x0008c040U + i*4U; | ||
70 | } | ||
71 | static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) | ||
72 | { | ||
73 | return (v & 0x1U) << 4U; | ||
74 | } | ||
75 | static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) | ||
76 | { | ||
77 | return 0x00000000U; | ||
78 | } | ||
79 | static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) | ||
80 | { | ||
81 | return (v & 0xfU) << 0U; | ||
82 | } | ||
83 | static inline u32 xp_pl_link_config_ltssm_directive_m(void) | ||
84 | { | ||
85 | return 0xfU << 0U; | ||
86 | } | ||
87 | static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) | ||
88 | { | ||
89 | return 0x00000000U; | ||
90 | } | ||
91 | static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) | ||
92 | { | ||
93 | return 0x00000001U; | ||
94 | } | ||
95 | static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) | ||
96 | { | ||
97 | return (v & 0x3U) << 18U; | ||
98 | } | ||
99 | static inline u32 xp_pl_link_config_max_link_rate_m(void) | ||
100 | { | ||
101 | return 0x3U << 18U; | ||
102 | } | ||
103 | static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) | ||
104 | { | ||
105 | return 0x00000002U; | ||
106 | } | ||
107 | static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) | ||
108 | { | ||
109 | return 0x00000001U; | ||
110 | } | ||
111 | static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) | ||
112 | { | ||
113 | return 0x00000000U; | ||
114 | } | ||
115 | static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x7U) << 20U; | ||
118 | } | ||
119 | static inline u32 xp_pl_link_config_target_tx_width_m(void) | ||
120 | { | ||
121 | return 0x7U << 20U; | ||
122 | } | ||
123 | static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) | ||
124 | { | ||
125 | return 0x00000007U; | ||
126 | } | ||
127 | static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) | ||
128 | { | ||
129 | return 0x00000006U; | ||
130 | } | ||
131 | static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) | ||
132 | { | ||
133 | return 0x00000005U; | ||
134 | } | ||
135 | static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) | ||
136 | { | ||
137 | return 0x00000004U; | ||
138 | } | ||
139 | static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) | ||
140 | { | ||
141 | return 0x00000000U; | ||
142 | } | ||
143 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h new file mode 100644 index 00000000..fc7aa72e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h | |||
@@ -0,0 +1,207 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_xve_gv100_h_ | ||
57 | #define _hw_xve_gv100_h_ | ||
58 | |||
59 | static inline u32 xve_rom_ctrl_r(void) | ||
60 | { | ||
61 | return 0x00000050U; | ||
62 | } | ||
63 | static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) | ||
64 | { | ||
65 | return (v & 0x1U) << 0U; | ||
66 | } | ||
67 | static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) | ||
68 | { | ||
69 | return 0x0U; | ||
70 | } | ||
71 | static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) | ||
72 | { | ||
73 | return 0x1U; | ||
74 | } | ||
75 | static inline u32 xve_link_control_status_r(void) | ||
76 | { | ||
77 | return 0x00000088U; | ||
78 | } | ||
79 | static inline u32 xve_link_control_status_link_speed_m(void) | ||
80 | { | ||
81 | return 0xfU << 16U; | ||
82 | } | ||
83 | static inline u32 xve_link_control_status_link_speed_v(u32 r) | ||
84 | { | ||
85 | return (r >> 16U) & 0xfU; | ||
86 | } | ||
87 | static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) | ||
88 | { | ||
89 | return 0x00000001U; | ||
90 | } | ||
91 | static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) | ||
92 | { | ||
93 | return 0x00000002U; | ||
94 | } | ||
95 | static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) | ||
96 | { | ||
97 | return 0x00000003U; | ||
98 | } | ||
99 | static inline u32 xve_link_control_status_link_width_m(void) | ||
100 | { | ||
101 | return 0x3fU << 20U; | ||
102 | } | ||
103 | static inline u32 xve_link_control_status_link_width_v(u32 r) | ||
104 | { | ||
105 | return (r >> 20U) & 0x3fU; | ||
106 | } | ||
107 | static inline u32 xve_link_control_status_link_width_x1_v(void) | ||
108 | { | ||
109 | return 0x00000001U; | ||
110 | } | ||
111 | static inline u32 xve_link_control_status_link_width_x2_v(void) | ||
112 | { | ||
113 | return 0x00000002U; | ||
114 | } | ||
115 | static inline u32 xve_link_control_status_link_width_x4_v(void) | ||
116 | { | ||
117 | return 0x00000004U; | ||
118 | } | ||
119 | static inline u32 xve_link_control_status_link_width_x8_v(void) | ||
120 | { | ||
121 | return 0x00000008U; | ||
122 | } | ||
123 | static inline u32 xve_link_control_status_link_width_x16_v(void) | ||
124 | { | ||
125 | return 0x00000010U; | ||
126 | } | ||
127 | static inline u32 xve_priv_xv_r(void) | ||
128 | { | ||
129 | return 0x00000150U; | ||
130 | } | ||
131 | static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 7U; | ||
134 | } | ||
135 | static inline u32 xve_priv_xv_cya_l0s_enable_m(void) | ||
136 | { | ||
137 | return 0x1U << 7U; | ||
138 | } | ||
139 | static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) | ||
140 | { | ||
141 | return (r >> 7U) & 0x1U; | ||
142 | } | ||
143 | static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1U) << 8U; | ||
146 | } | ||
147 | static inline u32 xve_priv_xv_cya_l1_enable_m(void) | ||
148 | { | ||
149 | return 0x1U << 8U; | ||
150 | } | ||
151 | static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) | ||
152 | { | ||
153 | return (r >> 8U) & 0x1U; | ||
154 | } | ||
155 | static inline u32 xve_cya_2_r(void) | ||
156 | { | ||
157 | return 0x00000704U; | ||
158 | } | ||
159 | static inline u32 xve_reset_r(void) | ||
160 | { | ||
161 | return 0x00000718U; | ||
162 | } | ||
163 | static inline u32 xve_reset_reset_m(void) | ||
164 | { | ||
165 | return 0x1U << 0U; | ||
166 | } | ||
167 | static inline u32 xve_reset_gpu_on_sw_reset_m(void) | ||
168 | { | ||
169 | return 0x1U << 1U; | ||
170 | } | ||
171 | static inline u32 xve_reset_counter_en_m(void) | ||
172 | { | ||
173 | return 0x1U << 2U; | ||
174 | } | ||
175 | static inline u32 xve_reset_counter_val_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x7ffU) << 4U; | ||
178 | } | ||
179 | static inline u32 xve_reset_counter_val_m(void) | ||
180 | { | ||
181 | return 0x7ffU << 4U; | ||
182 | } | ||
183 | static inline u32 xve_reset_counter_val_v(u32 r) | ||
184 | { | ||
185 | return (r >> 4U) & 0x7ffU; | ||
186 | } | ||
187 | static inline u32 xve_reset_clock_on_sw_reset_m(void) | ||
188 | { | ||
189 | return 0x1U << 15U; | ||
190 | } | ||
191 | static inline u32 xve_reset_clock_counter_en_m(void) | ||
192 | { | ||
193 | return 0x1U << 16U; | ||
194 | } | ||
195 | static inline u32 xve_reset_clock_counter_val_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x7ffU) << 17U; | ||
198 | } | ||
199 | static inline u32 xve_reset_clock_counter_val_m(void) | ||
200 | { | ||
201 | return 0x7ffU << 17U; | ||
202 | } | ||
203 | static inline u32 xve_reset_clock_counter_val_v(u32 r) | ||
204 | { | ||
205 | return (r >> 17U) & 0x7ffU; | ||
206 | } | ||
207 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h new file mode 100644 index 00000000..d1d9b34a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h | |||
@@ -0,0 +1,223 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_bus_gv11b_h_ | ||
57 | #define _hw_bus_gv11b_h_ | ||
58 | |||
59 | static inline u32 bus_bar0_window_r(void) | ||
60 | { | ||
61 | return 0x00001700U; | ||
62 | } | ||
63 | static inline u32 bus_bar0_window_base_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xffffffU) << 0U; | ||
66 | } | ||
67 | static inline u32 bus_bar0_window_target_vid_mem_f(void) | ||
68 | { | ||
69 | return 0x0U; | ||
70 | } | ||
71 | static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) | ||
72 | { | ||
73 | return 0x2000000U; | ||
74 | } | ||
75 | static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) | ||
76 | { | ||
77 | return 0x3000000U; | ||
78 | } | ||
79 | static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) | ||
80 | { | ||
81 | return 0x00000010U; | ||
82 | } | ||
83 | static inline u32 bus_bar1_block_r(void) | ||
84 | { | ||
85 | return 0x00001704U; | ||
86 | } | ||
87 | static inline u32 bus_bar1_block_ptr_f(u32 v) | ||
88 | { | ||
89 | return (v & 0xfffffffU) << 0U; | ||
90 | } | ||
91 | static inline u32 bus_bar1_block_target_vid_mem_f(void) | ||
92 | { | ||
93 | return 0x0U; | ||
94 | } | ||
95 | static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) | ||
96 | { | ||
97 | return 0x20000000U; | ||
98 | } | ||
99 | static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) | ||
100 | { | ||
101 | return 0x30000000U; | ||
102 | } | ||
103 | static inline u32 bus_bar1_block_mode_virtual_f(void) | ||
104 | { | ||
105 | return 0x80000000U; | ||
106 | } | ||
107 | static inline u32 bus_bar2_block_r(void) | ||
108 | { | ||
109 | return 0x00001714U; | ||
110 | } | ||
111 | static inline u32 bus_bar2_block_ptr_f(u32 v) | ||
112 | { | ||
113 | return (v & 0xfffffffU) << 0U; | ||
114 | } | ||
115 | static inline u32 bus_bar2_block_target_vid_mem_f(void) | ||
116 | { | ||
117 | return 0x0U; | ||
118 | } | ||
119 | static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) | ||
120 | { | ||
121 | return 0x20000000U; | ||
122 | } | ||
123 | static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) | ||
124 | { | ||
125 | return 0x30000000U; | ||
126 | } | ||
127 | static inline u32 bus_bar2_block_mode_virtual_f(void) | ||
128 | { | ||
129 | return 0x80000000U; | ||
130 | } | ||
131 | static inline u32 bus_bar1_block_ptr_shift_v(void) | ||
132 | { | ||
133 | return 0x0000000cU; | ||
134 | } | ||
135 | static inline u32 bus_bar2_block_ptr_shift_v(void) | ||
136 | { | ||
137 | return 0x0000000cU; | ||
138 | } | ||
139 | static inline u32 bus_bind_status_r(void) | ||
140 | { | ||
141 | return 0x00001710U; | ||
142 | } | ||
143 | static inline u32 bus_bind_status_bar1_pending_v(u32 r) | ||
144 | { | ||
145 | return (r >> 0U) & 0x1U; | ||
146 | } | ||
147 | static inline u32 bus_bind_status_bar1_pending_empty_f(void) | ||
148 | { | ||
149 | return 0x0U; | ||
150 | } | ||
151 | static inline u32 bus_bind_status_bar1_pending_busy_f(void) | ||
152 | { | ||
153 | return 0x1U; | ||
154 | } | ||
155 | static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) | ||
156 | { | ||
157 | return (r >> 1U) & 0x1U; | ||
158 | } | ||
159 | static inline u32 bus_bind_status_bar1_outstanding_false_f(void) | ||
160 | { | ||
161 | return 0x0U; | ||
162 | } | ||
163 | static inline u32 bus_bind_status_bar1_outstanding_true_f(void) | ||
164 | { | ||
165 | return 0x2U; | ||
166 | } | ||
167 | static inline u32 bus_bind_status_bar2_pending_v(u32 r) | ||
168 | { | ||
169 | return (r >> 2U) & 0x1U; | ||
170 | } | ||
171 | static inline u32 bus_bind_status_bar2_pending_empty_f(void) | ||
172 | { | ||
173 | return 0x0U; | ||
174 | } | ||
175 | static inline u32 bus_bind_status_bar2_pending_busy_f(void) | ||
176 | { | ||
177 | return 0x4U; | ||
178 | } | ||
179 | static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) | ||
180 | { | ||
181 | return (r >> 3U) & 0x1U; | ||
182 | } | ||
183 | static inline u32 bus_bind_status_bar2_outstanding_false_f(void) | ||
184 | { | ||
185 | return 0x0U; | ||
186 | } | ||
187 | static inline u32 bus_bind_status_bar2_outstanding_true_f(void) | ||
188 | { | ||
189 | return 0x8U; | ||
190 | } | ||
191 | static inline u32 bus_intr_0_r(void) | ||
192 | { | ||
193 | return 0x00001100U; | ||
194 | } | ||
195 | static inline u32 bus_intr_0_pri_squash_m(void) | ||
196 | { | ||
197 | return 0x1U << 1U; | ||
198 | } | ||
199 | static inline u32 bus_intr_0_pri_fecserr_m(void) | ||
200 | { | ||
201 | return 0x1U << 2U; | ||
202 | } | ||
203 | static inline u32 bus_intr_0_pri_timeout_m(void) | ||
204 | { | ||
205 | return 0x1U << 3U; | ||
206 | } | ||
207 | static inline u32 bus_intr_en_0_r(void) | ||
208 | { | ||
209 | return 0x00001140U; | ||
210 | } | ||
211 | static inline u32 bus_intr_en_0_pri_squash_m(void) | ||
212 | { | ||
213 | return 0x1U << 1U; | ||
214 | } | ||
215 | static inline u32 bus_intr_en_0_pri_fecserr_m(void) | ||
216 | { | ||
217 | return 0x1U << 2U; | ||
218 | } | ||
219 | static inline u32 bus_intr_en_0_pri_timeout_m(void) | ||
220 | { | ||
221 | return 0x1U << 3U; | ||
222 | } | ||
223 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h new file mode 100644 index 00000000..e21a4738 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | |||
@@ -0,0 +1,187 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ccsr_gv11b_h_ | ||
57 | #define _hw_ccsr_gv11b_h_ | ||
58 | |||
59 | static inline u32 ccsr_channel_inst_r(u32 i) | ||
60 | { | ||
61 | return 0x00800000U + i*8U; | ||
62 | } | ||
63 | static inline u32 ccsr_channel_inst__size_1_v(void) | ||
64 | { | ||
65 | return 0x00000200U; | ||
66 | } | ||
67 | static inline u32 ccsr_channel_inst_ptr_f(u32 v) | ||
68 | { | ||
69 | return (v & 0xfffffffU) << 0U; | ||
70 | } | ||
71 | static inline u32 ccsr_channel_inst_target_vid_mem_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) | ||
76 | { | ||
77 | return 0x20000000U; | ||
78 | } | ||
79 | static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) | ||
80 | { | ||
81 | return 0x30000000U; | ||
82 | } | ||
83 | static inline u32 ccsr_channel_inst_bind_false_f(void) | ||
84 | { | ||
85 | return 0x0U; | ||
86 | } | ||
87 | static inline u32 ccsr_channel_inst_bind_true_f(void) | ||
88 | { | ||
89 | return 0x80000000U; | ||
90 | } | ||
91 | static inline u32 ccsr_channel_r(u32 i) | ||
92 | { | ||
93 | return 0x00800004U + i*8U; | ||
94 | } | ||
95 | static inline u32 ccsr_channel__size_1_v(void) | ||
96 | { | ||
97 | return 0x00000200U; | ||
98 | } | ||
99 | static inline u32 ccsr_channel_enable_v(u32 r) | ||
100 | { | ||
101 | return (r >> 0U) & 0x1U; | ||
102 | } | ||
103 | static inline u32 ccsr_channel_enable_set_f(u32 v) | ||
104 | { | ||
105 | return (v & 0x1U) << 10U; | ||
106 | } | ||
107 | static inline u32 ccsr_channel_enable_set_true_f(void) | ||
108 | { | ||
109 | return 0x400U; | ||
110 | } | ||
111 | static inline u32 ccsr_channel_enable_clr_true_f(void) | ||
112 | { | ||
113 | return 0x800U; | ||
114 | } | ||
115 | static inline u32 ccsr_channel_status_v(u32 r) | ||
116 | { | ||
117 | return (r >> 24U) & 0xfU; | ||
118 | } | ||
119 | static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | ||
120 | { | ||
121 | return 0x00000002U; | ||
122 | } | ||
123 | static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) | ||
124 | { | ||
125 | return 0x00000004U; | ||
126 | } | ||
127 | static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) | ||
128 | { | ||
129 | return 0x0000000aU; | ||
130 | } | ||
131 | static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) | ||
132 | { | ||
133 | return 0x0000000bU; | ||
134 | } | ||
135 | static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) | ||
136 | { | ||
137 | return 0x0000000cU; | ||
138 | } | ||
139 | static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) | ||
140 | { | ||
141 | return 0x0000000dU; | ||
142 | } | ||
143 | static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) | ||
144 | { | ||
145 | return 0x0000000eU; | ||
146 | } | ||
147 | static inline u32 ccsr_channel_next_v(u32 r) | ||
148 | { | ||
149 | return (r >> 1U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 ccsr_channel_next_true_v(void) | ||
152 | { | ||
153 | return 0x00000001U; | ||
154 | } | ||
155 | static inline u32 ccsr_channel_force_ctx_reload_true_f(void) | ||
156 | { | ||
157 | return 0x100U; | ||
158 | } | ||
159 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x1U) << 22U; | ||
162 | } | ||
163 | static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) | ||
164 | { | ||
165 | return 0x400000U; | ||
166 | } | ||
167 | static inline u32 ccsr_channel_eng_faulted_f(u32 v) | ||
168 | { | ||
169 | return (v & 0x1U) << 23U; | ||
170 | } | ||
171 | static inline u32 ccsr_channel_eng_faulted_v(u32 r) | ||
172 | { | ||
173 | return (r >> 23U) & 0x1U; | ||
174 | } | ||
175 | static inline u32 ccsr_channel_eng_faulted_reset_f(void) | ||
176 | { | ||
177 | return 0x800000U; | ||
178 | } | ||
179 | static inline u32 ccsr_channel_eng_faulted_true_v(void) | ||
180 | { | ||
181 | return 0x00000001U; | ||
182 | } | ||
183 | static inline u32 ccsr_channel_busy_v(u32 r) | ||
184 | { | ||
185 | return (r >> 28U) & 0x1U; | ||
186 | } | ||
187 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h new file mode 100644 index 00000000..efc14d00 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | |||
@@ -0,0 +1,107 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ce_gv11b_h_ | ||
57 | #define _hw_ce_gv11b_h_ | ||
58 | |||
59 | static inline u32 ce_intr_status_r(u32 i) | ||
60 | { | ||
61 | return 0x00104410U + i*128U; | ||
62 | } | ||
63 | static inline u32 ce_intr_status_blockpipe_pending_f(void) | ||
64 | { | ||
65 | return 0x1U; | ||
66 | } | ||
67 | static inline u32 ce_intr_status_blockpipe_reset_f(void) | ||
68 | { | ||
69 | return 0x1U; | ||
70 | } | ||
71 | static inline u32 ce_intr_status_nonblockpipe_pending_f(void) | ||
72 | { | ||
73 | return 0x2U; | ||
74 | } | ||
75 | static inline u32 ce_intr_status_nonblockpipe_reset_f(void) | ||
76 | { | ||
77 | return 0x2U; | ||
78 | } | ||
79 | static inline u32 ce_intr_status_launcherr_pending_f(void) | ||
80 | { | ||
81 | return 0x4U; | ||
82 | } | ||
83 | static inline u32 ce_intr_status_launcherr_reset_f(void) | ||
84 | { | ||
85 | return 0x4U; | ||
86 | } | ||
87 | static inline u32 ce_intr_status_invalid_config_pending_f(void) | ||
88 | { | ||
89 | return 0x8U; | ||
90 | } | ||
91 | static inline u32 ce_intr_status_invalid_config_reset_f(void) | ||
92 | { | ||
93 | return 0x8U; | ||
94 | } | ||
95 | static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) | ||
96 | { | ||
97 | return 0x10U; | ||
98 | } | ||
99 | static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) | ||
100 | { | ||
101 | return 0x10U; | ||
102 | } | ||
103 | static inline u32 ce_pce_map_r(void) | ||
104 | { | ||
105 | return 0x00104028U; | ||
106 | } | ||
107 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h new file mode 100644 index 00000000..623a8c15 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | |||
@@ -0,0 +1,455 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ctxsw_prog_gv11b_h_ | ||
57 | #define _hw_ctxsw_prog_gv11b_h_ | ||
58 | |||
59 | static inline u32 ctxsw_prog_fecs_header_v(void) | ||
60 | { | ||
61 | return 0x00000100U; | ||
62 | } | ||
63 | static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) | ||
64 | { | ||
65 | return 0x00000008U; | ||
66 | } | ||
67 | static inline u32 ctxsw_prog_main_image_ctl_o(void) | ||
68 | { | ||
69 | return 0x0000000cU; | ||
70 | } | ||
71 | static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) | ||
72 | { | ||
73 | return (v & 0x3fU) << 0U; | ||
74 | } | ||
75 | static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) | ||
76 | { | ||
77 | return 0x00000000U; | ||
78 | } | ||
79 | static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) | ||
80 | { | ||
81 | return 0x00000008U; | ||
82 | } | ||
83 | static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) | ||
84 | { | ||
85 | return 0x00000010U; | ||
86 | } | ||
87 | static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) | ||
88 | { | ||
89 | return 0x00000011U; | ||
90 | } | ||
91 | static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) | ||
92 | { | ||
93 | return 0x00000012U; | ||
94 | } | ||
95 | static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) | ||
96 | { | ||
97 | return 0x00000020U; | ||
98 | } | ||
99 | static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) | ||
100 | { | ||
101 | return 0x00000021U; | ||
102 | } | ||
103 | static inline u32 ctxsw_prog_main_image_patch_count_o(void) | ||
104 | { | ||
105 | return 0x00000010U; | ||
106 | } | ||
107 | static inline u32 ctxsw_prog_main_image_context_id_o(void) | ||
108 | { | ||
109 | return 0x000000f0U; | ||
110 | } | ||
111 | static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) | ||
112 | { | ||
113 | return 0x00000014U; | ||
114 | } | ||
115 | static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) | ||
116 | { | ||
117 | return 0x00000018U; | ||
118 | } | ||
119 | static inline u32 ctxsw_prog_main_image_zcull_o(void) | ||
120 | { | ||
121 | return 0x0000001cU; | ||
122 | } | ||
123 | static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) | ||
124 | { | ||
125 | return 0x00000001U; | ||
126 | } | ||
127 | static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) | ||
128 | { | ||
129 | return 0x00000002U; | ||
130 | } | ||
131 | static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) | ||
132 | { | ||
133 | return 0x00000020U; | ||
134 | } | ||
135 | static inline u32 ctxsw_prog_main_image_pm_o(void) | ||
136 | { | ||
137 | return 0x00000028U; | ||
138 | } | ||
139 | static inline u32 ctxsw_prog_main_image_pm_mode_m(void) | ||
140 | { | ||
141 | return 0x7U << 0U; | ||
142 | } | ||
143 | static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) | ||
144 | { | ||
145 | return 0x0U; | ||
146 | } | ||
147 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) | ||
148 | { | ||
149 | return 0x7U << 3U; | ||
150 | } | ||
151 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) | ||
152 | { | ||
153 | return 0x8U; | ||
154 | } | ||
155 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) | ||
156 | { | ||
157 | return 0x0U; | ||
158 | } | ||
159 | static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) | ||
160 | { | ||
161 | return 0x0000002cU; | ||
162 | } | ||
163 | static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) | ||
164 | { | ||
165 | return 0x000000f4U; | ||
166 | } | ||
167 | static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) | ||
168 | { | ||
169 | return 0x000000d0U; | ||
170 | } | ||
171 | static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) | ||
172 | { | ||
173 | return 0x000000d4U; | ||
174 | } | ||
175 | static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) | ||
176 | { | ||
177 | return 0x000000d8U; | ||
178 | } | ||
179 | static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) | ||
180 | { | ||
181 | return 0x000000dcU; | ||
182 | } | ||
183 | static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) | ||
184 | { | ||
185 | return 0x000000f8U; | ||
186 | } | ||
187 | static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) | ||
188 | { | ||
189 | return 0x00000060U; | ||
190 | } | ||
191 | static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1ffffU) << 0U; | ||
194 | } | ||
195 | static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) | ||
196 | { | ||
197 | return 0x00000094U; | ||
198 | } | ||
199 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) | ||
200 | { | ||
201 | return 0x00000064U; | ||
202 | } | ||
203 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1ffffU) << 0U; | ||
206 | } | ||
207 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) | ||
208 | { | ||
209 | return 0x00000068U; | ||
210 | } | ||
211 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) | ||
212 | { | ||
213 | return (v & 0xffffffffU) << 0U; | ||
214 | } | ||
215 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) | ||
216 | { | ||
217 | return 0x00000070U; | ||
218 | } | ||
219 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1ffffU) << 0U; | ||
222 | } | ||
223 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) | ||
224 | { | ||
225 | return 0x00000074U; | ||
226 | } | ||
227 | static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) | ||
228 | { | ||
229 | return (v & 0xffffffffU) << 0U; | ||
230 | } | ||
231 | static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) | ||
232 | { | ||
233 | return 0x00000078U; | ||
234 | } | ||
235 | static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1ffffU) << 0U; | ||
238 | } | ||
239 | static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) | ||
240 | { | ||
241 | return 0x0000007cU; | ||
242 | } | ||
243 | static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xffffffffU) << 0U; | ||
246 | } | ||
247 | static inline u32 ctxsw_prog_main_image_magic_value_o(void) | ||
248 | { | ||
249 | return 0x000000fcU; | ||
250 | } | ||
251 | static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) | ||
252 | { | ||
253 | return 0x600dc0deU; | ||
254 | } | ||
255 | static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) | ||
256 | { | ||
257 | return 0x0000000cU; | ||
258 | } | ||
259 | static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) | ||
260 | { | ||
261 | return (r >> 0U) & 0xffffU; | ||
262 | } | ||
263 | static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) | ||
264 | { | ||
265 | return 0x000000b8U; | ||
266 | } | ||
267 | static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) | ||
268 | { | ||
269 | return (v & 0xffffffffU) << 0U; | ||
270 | } | ||
271 | static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) | ||
272 | { | ||
273 | return 0x000000bcU; | ||
274 | } | ||
275 | static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) | ||
276 | { | ||
277 | return (v & 0x1ffffU) << 0U; | ||
278 | } | ||
279 | static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) | ||
280 | { | ||
281 | return 0x000000c0U; | ||
282 | } | ||
283 | static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) | ||
284 | { | ||
285 | return (v & 0xffffffffU) << 0U; | ||
286 | } | ||
287 | static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) | ||
288 | { | ||
289 | return 0x000000c4U; | ||
290 | } | ||
291 | static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) | ||
292 | { | ||
293 | return (v & 0x1ffffU) << 0U; | ||
294 | } | ||
295 | static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) | ||
296 | { | ||
297 | return 0x000000c8U; | ||
298 | } | ||
299 | static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) | ||
300 | { | ||
301 | return (v & 0xffffffffU) << 0U; | ||
302 | } | ||
303 | static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) | ||
304 | { | ||
305 | return 0x000000ccU; | ||
306 | } | ||
307 | static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1ffffU) << 0U; | ||
310 | } | ||
311 | static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) | ||
312 | { | ||
313 | return 0x000000e0U; | ||
314 | } | ||
315 | static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) | ||
316 | { | ||
317 | return (v & 0xffffffffU) << 0U; | ||
318 | } | ||
319 | static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) | ||
320 | { | ||
321 | return 0x000000e4U; | ||
322 | } | ||
323 | static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1ffffU) << 0U; | ||
326 | } | ||
327 | static inline u32 ctxsw_prog_local_image_ppc_info_o(void) | ||
328 | { | ||
329 | return 0x000000f4U; | ||
330 | } | ||
331 | static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) | ||
332 | { | ||
333 | return (r >> 0U) & 0xffffU; | ||
334 | } | ||
335 | static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) | ||
336 | { | ||
337 | return (r >> 16U) & 0xffffU; | ||
338 | } | ||
339 | static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) | ||
340 | { | ||
341 | return 0x000000f8U; | ||
342 | } | ||
343 | static inline u32 ctxsw_prog_local_magic_value_o(void) | ||
344 | { | ||
345 | return 0x000000fcU; | ||
346 | } | ||
347 | static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) | ||
348 | { | ||
349 | return 0xad0becabU; | ||
350 | } | ||
351 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) | ||
352 | { | ||
353 | return 0x000000ecU; | ||
354 | } | ||
355 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) | ||
356 | { | ||
357 | return (r >> 0U) & 0xffffU; | ||
358 | } | ||
359 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) | ||
360 | { | ||
361 | return (r >> 16U) & 0xffU; | ||
362 | } | ||
363 | static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) | ||
364 | { | ||
365 | return 0x00000100U; | ||
366 | } | ||
367 | static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) | ||
368 | { | ||
369 | return 0x00000004U; | ||
370 | } | ||
371 | static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) | ||
372 | { | ||
373 | return 0x00000000U; | ||
374 | } | ||
375 | static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) | ||
376 | { | ||
377 | return 0x00000002U; | ||
378 | } | ||
379 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) | ||
380 | { | ||
381 | return 0x000000a0U; | ||
382 | } | ||
383 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) | ||
384 | { | ||
385 | return 2U; | ||
386 | } | ||
387 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) | ||
388 | { | ||
389 | return (v & 0x3U) << 0U; | ||
390 | } | ||
391 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) | ||
392 | { | ||
393 | return 0x3U << 0U; | ||
394 | } | ||
395 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) | ||
396 | { | ||
397 | return (r >> 0U) & 0x3U; | ||
398 | } | ||
399 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) | ||
400 | { | ||
401 | return 0x0U; | ||
402 | } | ||
403 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) | ||
404 | { | ||
405 | return 0x2U; | ||
406 | } | ||
407 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) | ||
408 | { | ||
409 | return 0x000000a4U; | ||
410 | } | ||
411 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) | ||
412 | { | ||
413 | return 0x000000a8U; | ||
414 | } | ||
415 | static inline u32 ctxsw_prog_main_image_misc_options_o(void) | ||
416 | { | ||
417 | return 0x0000003cU; | ||
418 | } | ||
419 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) | ||
420 | { | ||
421 | return 0x1U << 3U; | ||
422 | } | ||
423 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) | ||
424 | { | ||
425 | return 0x0U; | ||
426 | } | ||
427 | static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) | ||
428 | { | ||
429 | return 0x00000080U; | ||
430 | } | ||
431 | static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) | ||
432 | { | ||
433 | return (v & 0x3U) << 0U; | ||
434 | } | ||
435 | static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) | ||
436 | { | ||
437 | return 0x1U; | ||
438 | } | ||
439 | static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) | ||
440 | { | ||
441 | return 0x00000084U; | ||
442 | } | ||
443 | static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) | ||
444 | { | ||
445 | return (v & 0x3U) << 0U; | ||
446 | } | ||
447 | static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) | ||
448 | { | ||
449 | return 0x1U; | ||
450 | } | ||
451 | static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) | ||
452 | { | ||
453 | return 0x2U; | ||
454 | } | ||
455 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h new file mode 100644 index 00000000..4bb8f2de --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | |||
@@ -0,0 +1,599 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_falcon_gv11b_h_ | ||
57 | #define _hw_falcon_gv11b_h_ | ||
58 | |||
59 | static inline u32 falcon_falcon_irqsset_r(void) | ||
60 | { | ||
61 | return 0x00000000U; | ||
62 | } | ||
63 | static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) | ||
64 | { | ||
65 | return 0x40U; | ||
66 | } | ||
67 | static inline u32 falcon_falcon_irqsclr_r(void) | ||
68 | { | ||
69 | return 0x00000004U; | ||
70 | } | ||
71 | static inline u32 falcon_falcon_irqstat_r(void) | ||
72 | { | ||
73 | return 0x00000008U; | ||
74 | } | ||
75 | static inline u32 falcon_falcon_irqstat_halt_true_f(void) | ||
76 | { | ||
77 | return 0x10U; | ||
78 | } | ||
79 | static inline u32 falcon_falcon_irqstat_exterr_true_f(void) | ||
80 | { | ||
81 | return 0x20U; | ||
82 | } | ||
83 | static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) | ||
84 | { | ||
85 | return 0x40U; | ||
86 | } | ||
87 | static inline u32 falcon_falcon_irqmode_r(void) | ||
88 | { | ||
89 | return 0x0000000cU; | ||
90 | } | ||
91 | static inline u32 falcon_falcon_irqmset_r(void) | ||
92 | { | ||
93 | return 0x00000010U; | ||
94 | } | ||
95 | static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) | ||
96 | { | ||
97 | return (v & 0x1U) << 0U; | ||
98 | } | ||
99 | static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 1U; | ||
102 | } | ||
103 | static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) | ||
104 | { | ||
105 | return (v & 0x1U) << 2U; | ||
106 | } | ||
107 | static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x1U) << 3U; | ||
110 | } | ||
111 | static inline u32 falcon_falcon_irqmset_halt_f(u32 v) | ||
112 | { | ||
113 | return (v & 0x1U) << 4U; | ||
114 | } | ||
115 | static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 5U; | ||
118 | } | ||
119 | static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) | ||
120 | { | ||
121 | return (v & 0x1U) << 6U; | ||
122 | } | ||
123 | static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) | ||
124 | { | ||
125 | return (v & 0x1U) << 7U; | ||
126 | } | ||
127 | static inline u32 falcon_falcon_irqmclr_r(void) | ||
128 | { | ||
129 | return 0x00000014U; | ||
130 | } | ||
131 | static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 0U; | ||
134 | } | ||
135 | static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) | ||
136 | { | ||
137 | return (v & 0x1U) << 1U; | ||
138 | } | ||
139 | static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 2U; | ||
142 | } | ||
143 | static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1U) << 3U; | ||
146 | } | ||
147 | static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) | ||
148 | { | ||
149 | return (v & 0x1U) << 4U; | ||
150 | } | ||
151 | static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x1U) << 5U; | ||
154 | } | ||
155 | static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) | ||
156 | { | ||
157 | return (v & 0x1U) << 6U; | ||
158 | } | ||
159 | static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x1U) << 7U; | ||
162 | } | ||
163 | static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) | ||
164 | { | ||
165 | return (v & 0xffU) << 8U; | ||
166 | } | ||
167 | static inline u32 falcon_falcon_irqmask_r(void) | ||
168 | { | ||
169 | return 0x00000018U; | ||
170 | } | ||
171 | static inline u32 falcon_falcon_irqdest_r(void) | ||
172 | { | ||
173 | return 0x0000001cU; | ||
174 | } | ||
175 | static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x1U) << 0U; | ||
178 | } | ||
179 | static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) | ||
180 | { | ||
181 | return (v & 0x1U) << 1U; | ||
182 | } | ||
183 | static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1U) << 2U; | ||
186 | } | ||
187 | static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 3U; | ||
190 | } | ||
191 | static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1U) << 4U; | ||
194 | } | ||
195 | static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x1U) << 5U; | ||
198 | } | ||
199 | static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) | ||
200 | { | ||
201 | return (v & 0x1U) << 6U; | ||
202 | } | ||
203 | static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1U) << 7U; | ||
206 | } | ||
207 | static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) | ||
208 | { | ||
209 | return (v & 0xffU) << 8U; | ||
210 | } | ||
211 | static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x1U) << 16U; | ||
214 | } | ||
215 | static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) | ||
216 | { | ||
217 | return (v & 0x1U) << 17U; | ||
218 | } | ||
219 | static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1U) << 18U; | ||
222 | } | ||
223 | static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) | ||
224 | { | ||
225 | return (v & 0x1U) << 19U; | ||
226 | } | ||
227 | static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x1U) << 20U; | ||
230 | } | ||
231 | static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) | ||
232 | { | ||
233 | return (v & 0x1U) << 21U; | ||
234 | } | ||
235 | static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1U) << 22U; | ||
238 | } | ||
239 | static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x1U) << 23U; | ||
242 | } | ||
243 | static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xffU) << 24U; | ||
246 | } | ||
247 | static inline u32 falcon_falcon_curctx_r(void) | ||
248 | { | ||
249 | return 0x00000050U; | ||
250 | } | ||
251 | static inline u32 falcon_falcon_nxtctx_r(void) | ||
252 | { | ||
253 | return 0x00000054U; | ||
254 | } | ||
255 | static inline u32 falcon_falcon_mailbox0_r(void) | ||
256 | { | ||
257 | return 0x00000040U; | ||
258 | } | ||
259 | static inline u32 falcon_falcon_mailbox1_r(void) | ||
260 | { | ||
261 | return 0x00000044U; | ||
262 | } | ||
263 | static inline u32 falcon_falcon_itfen_r(void) | ||
264 | { | ||
265 | return 0x00000048U; | ||
266 | } | ||
267 | static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) | ||
268 | { | ||
269 | return 0x1U; | ||
270 | } | ||
271 | static inline u32 falcon_falcon_idlestate_r(void) | ||
272 | { | ||
273 | return 0x0000004cU; | ||
274 | } | ||
275 | static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) | ||
276 | { | ||
277 | return (r >> 0U) & 0x1U; | ||
278 | } | ||
279 | static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) | ||
280 | { | ||
281 | return (r >> 1U) & 0x7fffU; | ||
282 | } | ||
283 | static inline u32 falcon_falcon_os_r(void) | ||
284 | { | ||
285 | return 0x00000080U; | ||
286 | } | ||
287 | static inline u32 falcon_falcon_engctl_r(void) | ||
288 | { | ||
289 | return 0x000000a4U; | ||
290 | } | ||
291 | static inline u32 falcon_falcon_cpuctl_r(void) | ||
292 | { | ||
293 | return 0x00000100U; | ||
294 | } | ||
295 | static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x1U) << 1U; | ||
298 | } | ||
299 | static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) | ||
300 | { | ||
301 | return (v & 0x1U) << 2U; | ||
302 | } | ||
303 | static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) | ||
304 | { | ||
305 | return (v & 0x1U) << 3U; | ||
306 | } | ||
307 | static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1U) << 4U; | ||
310 | } | ||
311 | static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) | ||
312 | { | ||
313 | return 0x1U << 4U; | ||
314 | } | ||
315 | static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) | ||
316 | { | ||
317 | return (r >> 4U) & 0x1U; | ||
318 | } | ||
319 | static inline u32 falcon_falcon_cpuctl_stopped_m(void) | ||
320 | { | ||
321 | return 0x1U << 5U; | ||
322 | } | ||
323 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1U) << 6U; | ||
326 | } | ||
327 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) | ||
328 | { | ||
329 | return 0x1U << 6U; | ||
330 | } | ||
331 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) | ||
332 | { | ||
333 | return (r >> 6U) & 0x1U; | ||
334 | } | ||
335 | static inline u32 falcon_falcon_cpuctl_alias_r(void) | ||
336 | { | ||
337 | return 0x00000130U; | ||
338 | } | ||
339 | static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) | ||
340 | { | ||
341 | return (v & 0x1U) << 1U; | ||
342 | } | ||
343 | static inline u32 falcon_falcon_imemc_r(u32 i) | ||
344 | { | ||
345 | return 0x00000180U + i*16U; | ||
346 | } | ||
347 | static inline u32 falcon_falcon_imemc_offs_f(u32 v) | ||
348 | { | ||
349 | return (v & 0x3fU) << 2U; | ||
350 | } | ||
351 | static inline u32 falcon_falcon_imemc_blk_f(u32 v) | ||
352 | { | ||
353 | return (v & 0xffU) << 8U; | ||
354 | } | ||
355 | static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | ||
356 | { | ||
357 | return (v & 0x1U) << 24U; | ||
358 | } | ||
359 | static inline u32 falcon_falcon_imemd_r(u32 i) | ||
360 | { | ||
361 | return 0x00000184U + i*16U; | ||
362 | } | ||
363 | static inline u32 falcon_falcon_imemt_r(u32 i) | ||
364 | { | ||
365 | return 0x00000188U + i*16U; | ||
366 | } | ||
367 | static inline u32 falcon_falcon_sctl_r(void) | ||
368 | { | ||
369 | return 0x00000240U; | ||
370 | } | ||
371 | static inline u32 falcon_falcon_mmu_phys_sec_r(void) | ||
372 | { | ||
373 | return 0x00100ce4U; | ||
374 | } | ||
375 | static inline u32 falcon_falcon_bootvec_r(void) | ||
376 | { | ||
377 | return 0x00000104U; | ||
378 | } | ||
379 | static inline u32 falcon_falcon_bootvec_vec_f(u32 v) | ||
380 | { | ||
381 | return (v & 0xffffffffU) << 0U; | ||
382 | } | ||
383 | static inline u32 falcon_falcon_dmactl_r(void) | ||
384 | { | ||
385 | return 0x0000010cU; | ||
386 | } | ||
387 | static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) | ||
388 | { | ||
389 | return 0x1U << 1U; | ||
390 | } | ||
391 | static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) | ||
392 | { | ||
393 | return 0x1U << 2U; | ||
394 | } | ||
395 | static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) | ||
396 | { | ||
397 | return (v & 0x1U) << 0U; | ||
398 | } | ||
399 | static inline u32 falcon_falcon_hwcfg_r(void) | ||
400 | { | ||
401 | return 0x00000108U; | ||
402 | } | ||
403 | static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) | ||
404 | { | ||
405 | return (r >> 0U) & 0x1ffU; | ||
406 | } | ||
407 | static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) | ||
408 | { | ||
409 | return (r >> 9U) & 0x1ffU; | ||
410 | } | ||
411 | static inline u32 falcon_falcon_dmatrfbase_r(void) | ||
412 | { | ||
413 | return 0x00000110U; | ||
414 | } | ||
415 | static inline u32 falcon_falcon_dmatrfbase1_r(void) | ||
416 | { | ||
417 | return 0x00000128U; | ||
418 | } | ||
419 | static inline u32 falcon_falcon_dmatrfmoffs_r(void) | ||
420 | { | ||
421 | return 0x00000114U; | ||
422 | } | ||
423 | static inline u32 falcon_falcon_dmatrfcmd_r(void) | ||
424 | { | ||
425 | return 0x00000118U; | ||
426 | } | ||
427 | static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) | ||
428 | { | ||
429 | return (v & 0x1U) << 4U; | ||
430 | } | ||
431 | static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) | ||
432 | { | ||
433 | return (v & 0x1U) << 5U; | ||
434 | } | ||
435 | static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) | ||
436 | { | ||
437 | return (v & 0x7U) << 8U; | ||
438 | } | ||
439 | static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) | ||
440 | { | ||
441 | return (v & 0x7U) << 12U; | ||
442 | } | ||
443 | static inline u32 falcon_falcon_dmatrffboffs_r(void) | ||
444 | { | ||
445 | return 0x0000011cU; | ||
446 | } | ||
447 | static inline u32 falcon_falcon_imctl_debug_r(void) | ||
448 | { | ||
449 | return 0x0000015cU; | ||
450 | } | ||
451 | static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) | ||
452 | { | ||
453 | return (v & 0xffffffU) << 0U; | ||
454 | } | ||
455 | static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) | ||
456 | { | ||
457 | return (v & 0x7U) << 24U; | ||
458 | } | ||
459 | static inline u32 falcon_falcon_imstat_r(void) | ||
460 | { | ||
461 | return 0x00000144U; | ||
462 | } | ||
463 | static inline u32 falcon_falcon_traceidx_r(void) | ||
464 | { | ||
465 | return 0x00000148U; | ||
466 | } | ||
467 | static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) | ||
468 | { | ||
469 | return (r >> 16U) & 0xffU; | ||
470 | } | ||
471 | static inline u32 falcon_falcon_traceidx_idx_f(u32 v) | ||
472 | { | ||
473 | return (v & 0xffU) << 0U; | ||
474 | } | ||
475 | static inline u32 falcon_falcon_tracepc_r(void) | ||
476 | { | ||
477 | return 0x0000014cU; | ||
478 | } | ||
479 | static inline u32 falcon_falcon_tracepc_pc_v(u32 r) | ||
480 | { | ||
481 | return (r >> 0U) & 0xffffffU; | ||
482 | } | ||
483 | static inline u32 falcon_falcon_exterraddr_r(void) | ||
484 | { | ||
485 | return 0x00000168U; | ||
486 | } | ||
487 | static inline u32 falcon_falcon_exterrstat_r(void) | ||
488 | { | ||
489 | return 0x0000016cU; | ||
490 | } | ||
491 | static inline u32 falcon_falcon_exterrstat_valid_m(void) | ||
492 | { | ||
493 | return 0x1U << 31U; | ||
494 | } | ||
495 | static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) | ||
496 | { | ||
497 | return (r >> 31U) & 0x1U; | ||
498 | } | ||
499 | static inline u32 falcon_falcon_exterrstat_valid_true_v(void) | ||
500 | { | ||
501 | return 0x00000001U; | ||
502 | } | ||
503 | static inline u32 falcon_falcon_icd_cmd_r(void) | ||
504 | { | ||
505 | return 0x00000200U; | ||
506 | } | ||
507 | static inline u32 falcon_falcon_icd_cmd_opc_s(void) | ||
508 | { | ||
509 | return 4U; | ||
510 | } | ||
511 | static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) | ||
512 | { | ||
513 | return (v & 0xfU) << 0U; | ||
514 | } | ||
515 | static inline u32 falcon_falcon_icd_cmd_opc_m(void) | ||
516 | { | ||
517 | return 0xfU << 0U; | ||
518 | } | ||
519 | static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) | ||
520 | { | ||
521 | return (r >> 0U) & 0xfU; | ||
522 | } | ||
523 | static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) | ||
524 | { | ||
525 | return 0x8U; | ||
526 | } | ||
527 | static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) | ||
528 | { | ||
529 | return 0xeU; | ||
530 | } | ||
531 | static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) | ||
532 | { | ||
533 | return (v & 0x1fU) << 8U; | ||
534 | } | ||
535 | static inline u32 falcon_falcon_icd_rdata_r(void) | ||
536 | { | ||
537 | return 0x0000020cU; | ||
538 | } | ||
539 | static inline u32 falcon_falcon_dmemc_r(u32 i) | ||
540 | { | ||
541 | return 0x000001c0U + i*8U; | ||
542 | } | ||
543 | static inline u32 falcon_falcon_dmemc_offs_f(u32 v) | ||
544 | { | ||
545 | return (v & 0x3fU) << 2U; | ||
546 | } | ||
547 | static inline u32 falcon_falcon_dmemc_offs_m(void) | ||
548 | { | ||
549 | return 0x3fU << 2U; | ||
550 | } | ||
551 | static inline u32 falcon_falcon_dmemc_blk_f(u32 v) | ||
552 | { | ||
553 | return (v & 0xffU) << 8U; | ||
554 | } | ||
555 | static inline u32 falcon_falcon_dmemc_blk_m(void) | ||
556 | { | ||
557 | return 0xffU << 8U; | ||
558 | } | ||
559 | static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) | ||
560 | { | ||
561 | return (v & 0x1U) << 24U; | ||
562 | } | ||
563 | static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) | ||
564 | { | ||
565 | return (v & 0x1U) << 25U; | ||
566 | } | ||
567 | static inline u32 falcon_falcon_dmemd_r(u32 i) | ||
568 | { | ||
569 | return 0x000001c4U + i*8U; | ||
570 | } | ||
571 | static inline u32 falcon_falcon_debug1_r(void) | ||
572 | { | ||
573 | return 0x00000090U; | ||
574 | } | ||
575 | static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) | ||
576 | { | ||
577 | return 1U; | ||
578 | } | ||
579 | static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) | ||
580 | { | ||
581 | return (v & 0x1U) << 16U; | ||
582 | } | ||
583 | static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) | ||
584 | { | ||
585 | return 0x1U << 16U; | ||
586 | } | ||
587 | static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) | ||
588 | { | ||
589 | return (r >> 16U) & 0x1U; | ||
590 | } | ||
591 | static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) | ||
592 | { | ||
593 | return 0x0U; | ||
594 | } | ||
595 | static inline u32 falcon_falcon_debuginfo_r(void) | ||
596 | { | ||
597 | return 0x00000094U; | ||
598 | } | ||
599 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h new file mode 100644 index 00000000..ea3c7939 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | |||
@@ -0,0 +1,1827 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_fb_gv11b_h_ | ||
57 | #define _hw_fb_gv11b_h_ | ||
58 | |||
59 | static inline u32 fb_fbhub_num_active_ltcs_r(void) | ||
60 | { | ||
61 | return 0x00100800U; | ||
62 | } | ||
63 | static inline u32 fb_mmu_ctrl_r(void) | ||
64 | { | ||
65 | return 0x00100c80U; | ||
66 | } | ||
67 | static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) | ||
68 | { | ||
69 | return (v & 0x1U) << 0U; | ||
70 | } | ||
71 | static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) | ||
76 | { | ||
77 | return 0x1U; | ||
78 | } | ||
79 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) | ||
80 | { | ||
81 | return (r >> 15U) & 0x1U; | ||
82 | } | ||
83 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) | ||
84 | { | ||
85 | return 0x0U; | ||
86 | } | ||
87 | static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) | ||
88 | { | ||
89 | return (r >> 16U) & 0xffU; | ||
90 | } | ||
91 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) | ||
92 | { | ||
93 | return (r >> 11U) & 0x1U; | ||
94 | } | ||
95 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) | ||
96 | { | ||
97 | return 0x800U; | ||
98 | } | ||
99 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) | ||
100 | { | ||
101 | return 0x0U; | ||
102 | } | ||
103 | static inline u32 fb_priv_mmu_phy_secure_r(void) | ||
104 | { | ||
105 | return 0x00100ce4U; | ||
106 | } | ||
107 | static inline u32 fb_mmu_invalidate_pdb_r(void) | ||
108 | { | ||
109 | return 0x00100cb8U; | ||
110 | } | ||
111 | static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) | ||
112 | { | ||
113 | return 0x0U; | ||
114 | } | ||
115 | static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) | ||
116 | { | ||
117 | return 0x2U; | ||
118 | } | ||
119 | static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) | ||
120 | { | ||
121 | return (v & 0xfffffffU) << 4U; | ||
122 | } | ||
123 | static inline u32 fb_mmu_invalidate_r(void) | ||
124 | { | ||
125 | return 0x00100cbcU; | ||
126 | } | ||
127 | static inline u32 fb_mmu_invalidate_all_va_true_f(void) | ||
128 | { | ||
129 | return 0x1U; | ||
130 | } | ||
131 | static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) | ||
132 | { | ||
133 | return 0x2U; | ||
134 | } | ||
135 | static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) | ||
136 | { | ||
137 | return 1U; | ||
138 | } | ||
139 | static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 2U; | ||
142 | } | ||
143 | static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) | ||
144 | { | ||
145 | return 0x1U << 2U; | ||
146 | } | ||
147 | static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) | ||
148 | { | ||
149 | return (r >> 2U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) | ||
152 | { | ||
153 | return 0x4U; | ||
154 | } | ||
155 | static inline u32 fb_mmu_invalidate_replay_s(void) | ||
156 | { | ||
157 | return 3U; | ||
158 | } | ||
159 | static inline u32 fb_mmu_invalidate_replay_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x7U) << 3U; | ||
162 | } | ||
163 | static inline u32 fb_mmu_invalidate_replay_m(void) | ||
164 | { | ||
165 | return 0x7U << 3U; | ||
166 | } | ||
167 | static inline u32 fb_mmu_invalidate_replay_v(u32 r) | ||
168 | { | ||
169 | return (r >> 3U) & 0x7U; | ||
170 | } | ||
171 | static inline u32 fb_mmu_invalidate_replay_none_f(void) | ||
172 | { | ||
173 | return 0x0U; | ||
174 | } | ||
175 | static inline u32 fb_mmu_invalidate_replay_start_f(void) | ||
176 | { | ||
177 | return 0x8U; | ||
178 | } | ||
179 | static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) | ||
180 | { | ||
181 | return 0x10U; | ||
182 | } | ||
183 | static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) | ||
184 | { | ||
185 | return 0x20U; | ||
186 | } | ||
187 | static inline u32 fb_mmu_invalidate_sys_membar_s(void) | ||
188 | { | ||
189 | return 1U; | ||
190 | } | ||
191 | static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1U) << 6U; | ||
194 | } | ||
195 | static inline u32 fb_mmu_invalidate_sys_membar_m(void) | ||
196 | { | ||
197 | return 0x1U << 6U; | ||
198 | } | ||
199 | static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) | ||
200 | { | ||
201 | return (r >> 6U) & 0x1U; | ||
202 | } | ||
203 | static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) | ||
204 | { | ||
205 | return 0x40U; | ||
206 | } | ||
207 | static inline u32 fb_mmu_invalidate_ack_s(void) | ||
208 | { | ||
209 | return 2U; | ||
210 | } | ||
211 | static inline u32 fb_mmu_invalidate_ack_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x3U) << 7U; | ||
214 | } | ||
215 | static inline u32 fb_mmu_invalidate_ack_m(void) | ||
216 | { | ||
217 | return 0x3U << 7U; | ||
218 | } | ||
219 | static inline u32 fb_mmu_invalidate_ack_v(u32 r) | ||
220 | { | ||
221 | return (r >> 7U) & 0x3U; | ||
222 | } | ||
223 | static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) | ||
224 | { | ||
225 | return 0x0U; | ||
226 | } | ||
227 | static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) | ||
228 | { | ||
229 | return 0x100U; | ||
230 | } | ||
231 | static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) | ||
232 | { | ||
233 | return 0x80U; | ||
234 | } | ||
235 | static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) | ||
236 | { | ||
237 | return 6U; | ||
238 | } | ||
239 | static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x3fU) << 9U; | ||
242 | } | ||
243 | static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) | ||
244 | { | ||
245 | return 0x3fU << 9U; | ||
246 | } | ||
247 | static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) | ||
248 | { | ||
249 | return (r >> 9U) & 0x3fU; | ||
250 | } | ||
251 | static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) | ||
252 | { | ||
253 | return 5U; | ||
254 | } | ||
255 | static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) | ||
256 | { | ||
257 | return (v & 0x1fU) << 15U; | ||
258 | } | ||
259 | static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) | ||
260 | { | ||
261 | return 0x1fU << 15U; | ||
262 | } | ||
263 | static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) | ||
264 | { | ||
265 | return (r >> 15U) & 0x1fU; | ||
266 | } | ||
267 | static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) | ||
268 | { | ||
269 | return 1U; | ||
270 | } | ||
271 | static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) | ||
272 | { | ||
273 | return (v & 0x1U) << 20U; | ||
274 | } | ||
275 | static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) | ||
276 | { | ||
277 | return 0x1U << 20U; | ||
278 | } | ||
279 | static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) | ||
280 | { | ||
281 | return (r >> 20U) & 0x1U; | ||
282 | } | ||
283 | static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) | ||
284 | { | ||
285 | return 0x0U; | ||
286 | } | ||
287 | static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) | ||
288 | { | ||
289 | return 0x100000U; | ||
290 | } | ||
291 | static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) | ||
292 | { | ||
293 | return 3U; | ||
294 | } | ||
295 | static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x7U) << 24U; | ||
298 | } | ||
299 | static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) | ||
300 | { | ||
301 | return 0x7U << 24U; | ||
302 | } | ||
303 | static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) | ||
304 | { | ||
305 | return (r >> 24U) & 0x7U; | ||
306 | } | ||
307 | static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) | ||
308 | { | ||
309 | return 0x0U; | ||
310 | } | ||
311 | static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) | ||
312 | { | ||
313 | return 0x1000000U; | ||
314 | } | ||
315 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) | ||
316 | { | ||
317 | return 0x2000000U; | ||
318 | } | ||
319 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) | ||
320 | { | ||
321 | return 0x3000000U; | ||
322 | } | ||
323 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) | ||
324 | { | ||
325 | return 0x4000000U; | ||
326 | } | ||
327 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) | ||
328 | { | ||
329 | return 0x5000000U; | ||
330 | } | ||
331 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) | ||
332 | { | ||
333 | return 0x6000000U; | ||
334 | } | ||
335 | static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) | ||
336 | { | ||
337 | return 0x7000000U; | ||
338 | } | ||
339 | static inline u32 fb_mmu_invalidate_trigger_s(void) | ||
340 | { | ||
341 | return 1U; | ||
342 | } | ||
343 | static inline u32 fb_mmu_invalidate_trigger_f(u32 v) | ||
344 | { | ||
345 | return (v & 0x1U) << 31U; | ||
346 | } | ||
347 | static inline u32 fb_mmu_invalidate_trigger_m(void) | ||
348 | { | ||
349 | return 0x1U << 31U; | ||
350 | } | ||
351 | static inline u32 fb_mmu_invalidate_trigger_v(u32 r) | ||
352 | { | ||
353 | return (r >> 31U) & 0x1U; | ||
354 | } | ||
355 | static inline u32 fb_mmu_invalidate_trigger_true_f(void) | ||
356 | { | ||
357 | return 0x80000000U; | ||
358 | } | ||
359 | static inline u32 fb_mmu_debug_wr_r(void) | ||
360 | { | ||
361 | return 0x00100cc8U; | ||
362 | } | ||
363 | static inline u32 fb_mmu_debug_wr_aperture_s(void) | ||
364 | { | ||
365 | return 2U; | ||
366 | } | ||
367 | static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) | ||
368 | { | ||
369 | return (v & 0x3U) << 0U; | ||
370 | } | ||
371 | static inline u32 fb_mmu_debug_wr_aperture_m(void) | ||
372 | { | ||
373 | return 0x3U << 0U; | ||
374 | } | ||
375 | static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) | ||
376 | { | ||
377 | return (r >> 0U) & 0x3U; | ||
378 | } | ||
379 | static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) | ||
380 | { | ||
381 | return 0x0U; | ||
382 | } | ||
383 | static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) | ||
384 | { | ||
385 | return 0x2U; | ||
386 | } | ||
387 | static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) | ||
388 | { | ||
389 | return 0x3U; | ||
390 | } | ||
391 | static inline u32 fb_mmu_debug_wr_vol_false_f(void) | ||
392 | { | ||
393 | return 0x0U; | ||
394 | } | ||
395 | static inline u32 fb_mmu_debug_wr_vol_true_v(void) | ||
396 | { | ||
397 | return 0x00000001U; | ||
398 | } | ||
399 | static inline u32 fb_mmu_debug_wr_vol_true_f(void) | ||
400 | { | ||
401 | return 0x4U; | ||
402 | } | ||
403 | static inline u32 fb_mmu_debug_wr_addr_f(u32 v) | ||
404 | { | ||
405 | return (v & 0xfffffffU) << 4U; | ||
406 | } | ||
407 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) | ||
408 | { | ||
409 | return 0x0000000cU; | ||
410 | } | ||
411 | static inline u32 fb_mmu_debug_rd_r(void) | ||
412 | { | ||
413 | return 0x00100cccU; | ||
414 | } | ||
415 | static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) | ||
416 | { | ||
417 | return 0x0U; | ||
418 | } | ||
419 | static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) | ||
420 | { | ||
421 | return 0x2U; | ||
422 | } | ||
423 | static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) | ||
424 | { | ||
425 | return 0x3U; | ||
426 | } | ||
427 | static inline u32 fb_mmu_debug_rd_vol_false_f(void) | ||
428 | { | ||
429 | return 0x0U; | ||
430 | } | ||
431 | static inline u32 fb_mmu_debug_rd_addr_f(u32 v) | ||
432 | { | ||
433 | return (v & 0xfffffffU) << 4U; | ||
434 | } | ||
435 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) | ||
436 | { | ||
437 | return 0x0000000cU; | ||
438 | } | ||
439 | static inline u32 fb_mmu_debug_ctrl_r(void) | ||
440 | { | ||
441 | return 0x00100cc4U; | ||
442 | } | ||
443 | static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) | ||
444 | { | ||
445 | return (r >> 16U) & 0x1U; | ||
446 | } | ||
447 | static inline u32 fb_mmu_debug_ctrl_debug_m(void) | ||
448 | { | ||
449 | return 0x1U << 16U; | ||
450 | } | ||
451 | static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) | ||
452 | { | ||
453 | return 0x00000001U; | ||
454 | } | ||
455 | static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) | ||
456 | { | ||
457 | return 0x00000000U; | ||
458 | } | ||
459 | static inline u32 fb_mmu_vpr_info_r(void) | ||
460 | { | ||
461 | return 0x00100cd0U; | ||
462 | } | ||
463 | static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) | ||
464 | { | ||
465 | return (r >> 2U) & 0x1U; | ||
466 | } | ||
467 | static inline u32 fb_mmu_vpr_info_fetch_false_v(void) | ||
468 | { | ||
469 | return 0x00000000U; | ||
470 | } | ||
471 | static inline u32 fb_mmu_vpr_info_fetch_true_v(void) | ||
472 | { | ||
473 | return 0x00000001U; | ||
474 | } | ||
475 | static inline u32 fb_mmu_l2tlb_ecc_status_r(void) | ||
476 | { | ||
477 | return 0x00100e70U; | ||
478 | } | ||
479 | static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) | ||
480 | { | ||
481 | return 0x1U << 0U; | ||
482 | } | ||
483 | static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) | ||
484 | { | ||
485 | return 0x1U << 1U; | ||
486 | } | ||
487 | static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
488 | { | ||
489 | return 0x1U << 16U; | ||
490 | } | ||
491 | static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
492 | { | ||
493 | return 0x1U << 18U; | ||
494 | } | ||
495 | static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) | ||
496 | { | ||
497 | return (v & 0x1U) << 30U; | ||
498 | } | ||
499 | static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) | ||
500 | { | ||
501 | return 0x40000000U; | ||
502 | } | ||
503 | static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) | ||
504 | { | ||
505 | return 0x00100e74U; | ||
506 | } | ||
507 | static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) | ||
508 | { | ||
509 | return 16U; | ||
510 | } | ||
511 | static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) | ||
512 | { | ||
513 | return (v & 0xffffU) << 0U; | ||
514 | } | ||
515 | static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) | ||
516 | { | ||
517 | return 0xffffU << 0U; | ||
518 | } | ||
519 | static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) | ||
520 | { | ||
521 | return (r >> 0U) & 0xffffU; | ||
522 | } | ||
523 | static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) | ||
524 | { | ||
525 | return 0x00100e78U; | ||
526 | } | ||
527 | static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) | ||
528 | { | ||
529 | return 16U; | ||
530 | } | ||
531 | static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) | ||
532 | { | ||
533 | return (v & 0xffffU) << 0U; | ||
534 | } | ||
535 | static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) | ||
536 | { | ||
537 | return 0xffffU << 0U; | ||
538 | } | ||
539 | static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) | ||
540 | { | ||
541 | return (r >> 0U) & 0xffffU; | ||
542 | } | ||
543 | static inline u32 fb_mmu_l2tlb_ecc_address_r(void) | ||
544 | { | ||
545 | return 0x00100e7cU; | ||
546 | } | ||
547 | static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) | ||
548 | { | ||
549 | return 32U; | ||
550 | } | ||
551 | static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) | ||
552 | { | ||
553 | return (v & 0xffffffffU) << 0U; | ||
554 | } | ||
555 | static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) | ||
556 | { | ||
557 | return 0xffffffffU << 0U; | ||
558 | } | ||
559 | static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) | ||
560 | { | ||
561 | return (r >> 0U) & 0xffffffffU; | ||
562 | } | ||
563 | static inline u32 fb_mmu_hubtlb_ecc_status_r(void) | ||
564 | { | ||
565 | return 0x00100e84U; | ||
566 | } | ||
567 | static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) | ||
568 | { | ||
569 | return 0x1U << 0U; | ||
570 | } | ||
571 | static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) | ||
572 | { | ||
573 | return 0x1U << 1U; | ||
574 | } | ||
575 | static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
576 | { | ||
577 | return 0x1U << 16U; | ||
578 | } | ||
579 | static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
580 | { | ||
581 | return 0x1U << 18U; | ||
582 | } | ||
583 | static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) | ||
584 | { | ||
585 | return (v & 0x1U) << 30U; | ||
586 | } | ||
587 | static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) | ||
588 | { | ||
589 | return 0x40000000U; | ||
590 | } | ||
591 | static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) | ||
592 | { | ||
593 | return 0x00100e88U; | ||
594 | } | ||
595 | static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) | ||
596 | { | ||
597 | return 16U; | ||
598 | } | ||
599 | static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) | ||
600 | { | ||
601 | return (v & 0xffffU) << 0U; | ||
602 | } | ||
603 | static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) | ||
604 | { | ||
605 | return 0xffffU << 0U; | ||
606 | } | ||
607 | static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) | ||
608 | { | ||
609 | return (r >> 0U) & 0xffffU; | ||
610 | } | ||
611 | static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) | ||
612 | { | ||
613 | return 0x00100e8cU; | ||
614 | } | ||
615 | static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) | ||
616 | { | ||
617 | return 16U; | ||
618 | } | ||
619 | static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) | ||
620 | { | ||
621 | return (v & 0xffffU) << 0U; | ||
622 | } | ||
623 | static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) | ||
624 | { | ||
625 | return 0xffffU << 0U; | ||
626 | } | ||
627 | static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) | ||
628 | { | ||
629 | return (r >> 0U) & 0xffffU; | ||
630 | } | ||
631 | static inline u32 fb_mmu_hubtlb_ecc_address_r(void) | ||
632 | { | ||
633 | return 0x00100e90U; | ||
634 | } | ||
635 | static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) | ||
636 | { | ||
637 | return 32U; | ||
638 | } | ||
639 | static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) | ||
640 | { | ||
641 | return (v & 0xffffffffU) << 0U; | ||
642 | } | ||
643 | static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) | ||
644 | { | ||
645 | return 0xffffffffU << 0U; | ||
646 | } | ||
647 | static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) | ||
648 | { | ||
649 | return (r >> 0U) & 0xffffffffU; | ||
650 | } | ||
651 | static inline u32 fb_mmu_fillunit_ecc_status_r(void) | ||
652 | { | ||
653 | return 0x00100e98U; | ||
654 | } | ||
655 | static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) | ||
656 | { | ||
657 | return 0x1U << 0U; | ||
658 | } | ||
659 | static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) | ||
660 | { | ||
661 | return 0x1U << 1U; | ||
662 | } | ||
663 | static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) | ||
664 | { | ||
665 | return 0x1U << 2U; | ||
666 | } | ||
667 | static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) | ||
668 | { | ||
669 | return 0x1U << 3U; | ||
670 | } | ||
671 | static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
672 | { | ||
673 | return 0x1U << 16U; | ||
674 | } | ||
675 | static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
676 | { | ||
677 | return 0x1U << 18U; | ||
678 | } | ||
679 | static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) | ||
680 | { | ||
681 | return (v & 0x1U) << 30U; | ||
682 | } | ||
683 | static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) | ||
684 | { | ||
685 | return 0x40000000U; | ||
686 | } | ||
687 | static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) | ||
688 | { | ||
689 | return 0x00100e9cU; | ||
690 | } | ||
691 | static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) | ||
692 | { | ||
693 | return 16U; | ||
694 | } | ||
695 | static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) | ||
696 | { | ||
697 | return (v & 0xffffU) << 0U; | ||
698 | } | ||
699 | static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) | ||
700 | { | ||
701 | return 0xffffU << 0U; | ||
702 | } | ||
703 | static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) | ||
704 | { | ||
705 | return (r >> 0U) & 0xffffU; | ||
706 | } | ||
707 | static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) | ||
708 | { | ||
709 | return 0x00100ea0U; | ||
710 | } | ||
711 | static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) | ||
712 | { | ||
713 | return 16U; | ||
714 | } | ||
715 | static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) | ||
716 | { | ||
717 | return (v & 0xffffU) << 0U; | ||
718 | } | ||
719 | static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) | ||
720 | { | ||
721 | return 0xffffU << 0U; | ||
722 | } | ||
723 | static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) | ||
724 | { | ||
725 | return (r >> 0U) & 0xffffU; | ||
726 | } | ||
727 | static inline u32 fb_mmu_fillunit_ecc_address_r(void) | ||
728 | { | ||
729 | return 0x00100ea4U; | ||
730 | } | ||
731 | static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) | ||
732 | { | ||
733 | return 32U; | ||
734 | } | ||
735 | static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) | ||
736 | { | ||
737 | return (v & 0xffffffffU) << 0U; | ||
738 | } | ||
739 | static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) | ||
740 | { | ||
741 | return 0xffffffffU << 0U; | ||
742 | } | ||
743 | static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) | ||
744 | { | ||
745 | return (r >> 0U) & 0xffffffffU; | ||
746 | } | ||
747 | static inline u32 fb_niso_flush_sysmem_addr_r(void) | ||
748 | { | ||
749 | return 0x00100c10U; | ||
750 | } | ||
751 | static inline u32 fb_niso_intr_r(void) | ||
752 | { | ||
753 | return 0x00100a20U; | ||
754 | } | ||
755 | static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) | ||
756 | { | ||
757 | return 0x1U << 0U; | ||
758 | } | ||
759 | static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) | ||
760 | { | ||
761 | return 0x1U; | ||
762 | } | ||
763 | static inline u32 fb_niso_intr_hub_access_counter_error_m(void) | ||
764 | { | ||
765 | return 0x1U << 1U; | ||
766 | } | ||
767 | static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) | ||
768 | { | ||
769 | return 0x2U; | ||
770 | } | ||
771 | static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) | ||
772 | { | ||
773 | return 0x1U << 27U; | ||
774 | } | ||
775 | static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) | ||
776 | { | ||
777 | return 0x8000000U; | ||
778 | } | ||
779 | static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) | ||
780 | { | ||
781 | return 0x1U << 28U; | ||
782 | } | ||
783 | static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) | ||
784 | { | ||
785 | return 0x10000000U; | ||
786 | } | ||
787 | static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) | ||
788 | { | ||
789 | return 0x1U << 29U; | ||
790 | } | ||
791 | static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) | ||
792 | { | ||
793 | return 0x20000000U; | ||
794 | } | ||
795 | static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) | ||
796 | { | ||
797 | return 0x1U << 30U; | ||
798 | } | ||
799 | static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) | ||
800 | { | ||
801 | return 0x40000000U; | ||
802 | } | ||
803 | static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) | ||
804 | { | ||
805 | return 0x1U << 31U; | ||
806 | } | ||
807 | static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) | ||
808 | { | ||
809 | return 0x80000000U; | ||
810 | } | ||
811 | static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) | ||
812 | { | ||
813 | return 0x1U << 26U; | ||
814 | } | ||
815 | static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) | ||
816 | { | ||
817 | return 0x4000000U; | ||
818 | } | ||
819 | static inline u32 fb_niso_intr_en_r(u32 i) | ||
820 | { | ||
821 | return 0x00100a24U + i*4U; | ||
822 | } | ||
823 | static inline u32 fb_niso_intr_en__size_1_v(void) | ||
824 | { | ||
825 | return 0x00000002U; | ||
826 | } | ||
827 | static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) | ||
828 | { | ||
829 | return (v & 0x1U) << 0U; | ||
830 | } | ||
831 | static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) | ||
832 | { | ||
833 | return 0x1U; | ||
834 | } | ||
835 | static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) | ||
836 | { | ||
837 | return (v & 0x1U) << 1U; | ||
838 | } | ||
839 | static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) | ||
840 | { | ||
841 | return 0x2U; | ||
842 | } | ||
843 | static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) | ||
844 | { | ||
845 | return (v & 0x1U) << 27U; | ||
846 | } | ||
847 | static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) | ||
848 | { | ||
849 | return 0x8000000U; | ||
850 | } | ||
851 | static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) | ||
852 | { | ||
853 | return (v & 0x1U) << 28U; | ||
854 | } | ||
855 | static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) | ||
856 | { | ||
857 | return 0x10000000U; | ||
858 | } | ||
859 | static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) | ||
860 | { | ||
861 | return (v & 0x1U) << 29U; | ||
862 | } | ||
863 | static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) | ||
864 | { | ||
865 | return 0x20000000U; | ||
866 | } | ||
867 | static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) | ||
868 | { | ||
869 | return (v & 0x1U) << 30U; | ||
870 | } | ||
871 | static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) | ||
872 | { | ||
873 | return 0x40000000U; | ||
874 | } | ||
875 | static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) | ||
876 | { | ||
877 | return (v & 0x1U) << 31U; | ||
878 | } | ||
879 | static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) | ||
880 | { | ||
881 | return 0x80000000U; | ||
882 | } | ||
883 | static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v) | ||
884 | { | ||
885 | return (v & 0x1U) << 26U; | ||
886 | } | ||
887 | static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void) | ||
888 | { | ||
889 | return 0x4000000U; | ||
890 | } | ||
891 | static inline u32 fb_niso_intr_en_set_r(u32 i) | ||
892 | { | ||
893 | return 0x00100a2cU + i*4U; | ||
894 | } | ||
895 | static inline u32 fb_niso_intr_en_set__size_1_v(void) | ||
896 | { | ||
897 | return 0x00000002U; | ||
898 | } | ||
899 | static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) | ||
900 | { | ||
901 | return 0x1U << 0U; | ||
902 | } | ||
903 | static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) | ||
904 | { | ||
905 | return 0x1U; | ||
906 | } | ||
907 | static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) | ||
908 | { | ||
909 | return 0x1U << 1U; | ||
910 | } | ||
911 | static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) | ||
912 | { | ||
913 | return 0x2U; | ||
914 | } | ||
915 | static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) | ||
916 | { | ||
917 | return 0x1U << 27U; | ||
918 | } | ||
919 | static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) | ||
920 | { | ||
921 | return 0x8000000U; | ||
922 | } | ||
923 | static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) | ||
924 | { | ||
925 | return 0x1U << 28U; | ||
926 | } | ||
927 | static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) | ||
928 | { | ||
929 | return 0x10000000U; | ||
930 | } | ||
931 | static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) | ||
932 | { | ||
933 | return 0x1U << 29U; | ||
934 | } | ||
935 | static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) | ||
936 | { | ||
937 | return 0x20000000U; | ||
938 | } | ||
939 | static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) | ||
940 | { | ||
941 | return 0x1U << 30U; | ||
942 | } | ||
943 | static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) | ||
944 | { | ||
945 | return 0x40000000U; | ||
946 | } | ||
947 | static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) | ||
948 | { | ||
949 | return 0x1U << 31U; | ||
950 | } | ||
951 | static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) | ||
952 | { | ||
953 | return 0x80000000U; | ||
954 | } | ||
955 | static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) | ||
956 | { | ||
957 | return 0x1U << 26U; | ||
958 | } | ||
959 | static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) | ||
960 | { | ||
961 | return 0x4000000U; | ||
962 | } | ||
963 | static inline u32 fb_niso_intr_en_clr_r(u32 i) | ||
964 | { | ||
965 | return 0x00100a34U + i*4U; | ||
966 | } | ||
967 | static inline u32 fb_niso_intr_en_clr__size_1_v(void) | ||
968 | { | ||
969 | return 0x00000002U; | ||
970 | } | ||
971 | static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) | ||
972 | { | ||
973 | return 0x1U << 0U; | ||
974 | } | ||
975 | static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) | ||
976 | { | ||
977 | return 0x1U; | ||
978 | } | ||
979 | static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) | ||
980 | { | ||
981 | return 0x1U << 1U; | ||
982 | } | ||
983 | static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) | ||
984 | { | ||
985 | return 0x2U; | ||
986 | } | ||
987 | static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) | ||
988 | { | ||
989 | return 0x1U << 27U; | ||
990 | } | ||
991 | static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) | ||
992 | { | ||
993 | return 0x8000000U; | ||
994 | } | ||
995 | static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) | ||
996 | { | ||
997 | return 0x1U << 28U; | ||
998 | } | ||
999 | static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) | ||
1000 | { | ||
1001 | return 0x10000000U; | ||
1002 | } | ||
1003 | static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) | ||
1004 | { | ||
1005 | return 0x1U << 29U; | ||
1006 | } | ||
1007 | static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) | ||
1008 | { | ||
1009 | return 0x20000000U; | ||
1010 | } | ||
1011 | static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) | ||
1012 | { | ||
1013 | return 0x1U << 30U; | ||
1014 | } | ||
1015 | static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) | ||
1016 | { | ||
1017 | return 0x40000000U; | ||
1018 | } | ||
1019 | static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) | ||
1020 | { | ||
1021 | return 0x1U << 31U; | ||
1022 | } | ||
1023 | static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) | ||
1024 | { | ||
1025 | return 0x80000000U; | ||
1026 | } | ||
1027 | static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) | ||
1028 | { | ||
1029 | return 0x1U << 26U; | ||
1030 | } | ||
1031 | static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) | ||
1032 | { | ||
1033 | return 0x4000000U; | ||
1034 | } | ||
1035 | static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) | ||
1036 | { | ||
1037 | return 0x00000000U; | ||
1038 | } | ||
1039 | static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) | ||
1040 | { | ||
1041 | return 0x00000001U; | ||
1042 | } | ||
1043 | static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) | ||
1044 | { | ||
1045 | return 0x00100e24U + i*20U; | ||
1046 | } | ||
1047 | static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) | ||
1048 | { | ||
1049 | return 0x00000002U; | ||
1050 | } | ||
1051 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) | ||
1052 | { | ||
1053 | return (v & 0x1U) << 0U; | ||
1054 | } | ||
1055 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) | ||
1056 | { | ||
1057 | return (r >> 0U) & 0x1U; | ||
1058 | } | ||
1059 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) | ||
1060 | { | ||
1061 | return 0x00000000U; | ||
1062 | } | ||
1063 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) | ||
1064 | { | ||
1065 | return 0x0U; | ||
1066 | } | ||
1067 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) | ||
1068 | { | ||
1069 | return 0x00000001U; | ||
1070 | } | ||
1071 | static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) | ||
1072 | { | ||
1073 | return 0x1U; | ||
1074 | } | ||
1075 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) | ||
1076 | { | ||
1077 | return (v & 0x3U) << 1U; | ||
1078 | } | ||
1079 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) | ||
1080 | { | ||
1081 | return (r >> 1U) & 0x3U; | ||
1082 | } | ||
1083 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) | ||
1084 | { | ||
1085 | return 0x00000002U; | ||
1086 | } | ||
1087 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) | ||
1088 | { | ||
1089 | return 0x4U; | ||
1090 | } | ||
1091 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) | ||
1092 | { | ||
1093 | return 0x00000003U; | ||
1094 | } | ||
1095 | static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) | ||
1096 | { | ||
1097 | return 0x6U; | ||
1098 | } | ||
1099 | static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) | ||
1100 | { | ||
1101 | return (v & 0x1U) << 3U; | ||
1102 | } | ||
1103 | static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) | ||
1104 | { | ||
1105 | return (r >> 3U) & 0x1U; | ||
1106 | } | ||
1107 | static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) | ||
1108 | { | ||
1109 | return (v & 0xfffffU) << 12U; | ||
1110 | } | ||
1111 | static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) | ||
1112 | { | ||
1113 | return (r >> 12U) & 0xfffffU; | ||
1114 | } | ||
1115 | static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) | ||
1116 | { | ||
1117 | return 0x00100e28U + i*20U; | ||
1118 | } | ||
1119 | static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) | ||
1120 | { | ||
1121 | return 0x00000002U; | ||
1122 | } | ||
1123 | static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) | ||
1124 | { | ||
1125 | return (v & 0xffffffffU) << 0U; | ||
1126 | } | ||
1127 | static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) | ||
1128 | { | ||
1129 | return (r >> 0U) & 0xffffffffU; | ||
1130 | } | ||
1131 | static inline u32 fb_mmu_fault_buffer_get_r(u32 i) | ||
1132 | { | ||
1133 | return 0x00100e2cU + i*20U; | ||
1134 | } | ||
1135 | static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) | ||
1136 | { | ||
1137 | return 0x00000002U; | ||
1138 | } | ||
1139 | static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) | ||
1140 | { | ||
1141 | return (v & 0xfffffU) << 0U; | ||
1142 | } | ||
1143 | static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) | ||
1144 | { | ||
1145 | return 0xfffffU << 0U; | ||
1146 | } | ||
1147 | static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) | ||
1148 | { | ||
1149 | return (r >> 0U) & 0xfffffU; | ||
1150 | } | ||
1151 | static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) | ||
1152 | { | ||
1153 | return (v & 0x1U) << 30U; | ||
1154 | } | ||
1155 | static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) | ||
1156 | { | ||
1157 | return 0x1U << 30U; | ||
1158 | } | ||
1159 | static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) | ||
1160 | { | ||
1161 | return 0x00000001U; | ||
1162 | } | ||
1163 | static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) | ||
1164 | { | ||
1165 | return 0x40000000U; | ||
1166 | } | ||
1167 | static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) | ||
1168 | { | ||
1169 | return (v & 0x1U) << 31U; | ||
1170 | } | ||
1171 | static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) | ||
1172 | { | ||
1173 | return 0x1U << 31U; | ||
1174 | } | ||
1175 | static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) | ||
1176 | { | ||
1177 | return 0x00000001U; | ||
1178 | } | ||
1179 | static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) | ||
1180 | { | ||
1181 | return 0x80000000U; | ||
1182 | } | ||
1183 | static inline u32 fb_mmu_fault_buffer_put_r(u32 i) | ||
1184 | { | ||
1185 | return 0x00100e30U + i*20U; | ||
1186 | } | ||
1187 | static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) | ||
1188 | { | ||
1189 | return 0x00000002U; | ||
1190 | } | ||
1191 | static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) | ||
1192 | { | ||
1193 | return (v & 0xfffffU) << 0U; | ||
1194 | } | ||
1195 | static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) | ||
1196 | { | ||
1197 | return (r >> 0U) & 0xfffffU; | ||
1198 | } | ||
1199 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) | ||
1200 | { | ||
1201 | return (v & 0x1U) << 30U; | ||
1202 | } | ||
1203 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) | ||
1204 | { | ||
1205 | return (r >> 30U) & 0x1U; | ||
1206 | } | ||
1207 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) | ||
1208 | { | ||
1209 | return 0x00000001U; | ||
1210 | } | ||
1211 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) | ||
1212 | { | ||
1213 | return 0x40000000U; | ||
1214 | } | ||
1215 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) | ||
1216 | { | ||
1217 | return 0x00000000U; | ||
1218 | } | ||
1219 | static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) | ||
1220 | { | ||
1221 | return 0x0U; | ||
1222 | } | ||
1223 | static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) | ||
1224 | { | ||
1225 | return (v & 0x1U) << 31U; | ||
1226 | } | ||
1227 | static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) | ||
1228 | { | ||
1229 | return (r >> 31U) & 0x1U; | ||
1230 | } | ||
1231 | static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) | ||
1232 | { | ||
1233 | return 0x00000001U; | ||
1234 | } | ||
1235 | static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) | ||
1236 | { | ||
1237 | return 0x80000000U; | ||
1238 | } | ||
1239 | static inline u32 fb_mmu_fault_buffer_size_r(u32 i) | ||
1240 | { | ||
1241 | return 0x00100e34U + i*20U; | ||
1242 | } | ||
1243 | static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) | ||
1244 | { | ||
1245 | return 0x00000002U; | ||
1246 | } | ||
1247 | static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) | ||
1248 | { | ||
1249 | return (v & 0xfffffU) << 0U; | ||
1250 | } | ||
1251 | static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) | ||
1252 | { | ||
1253 | return (r >> 0U) & 0xfffffU; | ||
1254 | } | ||
1255 | static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) | ||
1256 | { | ||
1257 | return (v & 0x1U) << 29U; | ||
1258 | } | ||
1259 | static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) | ||
1260 | { | ||
1261 | return (r >> 29U) & 0x1U; | ||
1262 | } | ||
1263 | static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) | ||
1264 | { | ||
1265 | return 0x00000001U; | ||
1266 | } | ||
1267 | static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) | ||
1268 | { | ||
1269 | return 0x20000000U; | ||
1270 | } | ||
1271 | static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) | ||
1272 | { | ||
1273 | return (v & 0x1U) << 30U; | ||
1274 | } | ||
1275 | static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) | ||
1276 | { | ||
1277 | return (r >> 30U) & 0x1U; | ||
1278 | } | ||
1279 | static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) | ||
1280 | { | ||
1281 | return 0x00000001U; | ||
1282 | } | ||
1283 | static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) | ||
1284 | { | ||
1285 | return 0x40000000U; | ||
1286 | } | ||
1287 | static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) | ||
1288 | { | ||
1289 | return (v & 0x1U) << 31U; | ||
1290 | } | ||
1291 | static inline u32 fb_mmu_fault_buffer_size_enable_m(void) | ||
1292 | { | ||
1293 | return 0x1U << 31U; | ||
1294 | } | ||
1295 | static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) | ||
1296 | { | ||
1297 | return (r >> 31U) & 0x1U; | ||
1298 | } | ||
1299 | static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) | ||
1300 | { | ||
1301 | return 0x00000001U; | ||
1302 | } | ||
1303 | static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) | ||
1304 | { | ||
1305 | return 0x80000000U; | ||
1306 | } | ||
1307 | static inline u32 fb_mmu_fault_addr_lo_r(void) | ||
1308 | { | ||
1309 | return 0x00100e4cU; | ||
1310 | } | ||
1311 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) | ||
1312 | { | ||
1313 | return (v & 0x3U) << 0U; | ||
1314 | } | ||
1315 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) | ||
1316 | { | ||
1317 | return (r >> 0U) & 0x3U; | ||
1318 | } | ||
1319 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) | ||
1320 | { | ||
1321 | return 0x00000002U; | ||
1322 | } | ||
1323 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) | ||
1324 | { | ||
1325 | return 0x2U; | ||
1326 | } | ||
1327 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) | ||
1328 | { | ||
1329 | return 0x00000003U; | ||
1330 | } | ||
1331 | static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) | ||
1332 | { | ||
1333 | return 0x3U; | ||
1334 | } | ||
1335 | static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) | ||
1336 | { | ||
1337 | return (v & 0xfffffU) << 12U; | ||
1338 | } | ||
1339 | static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) | ||
1340 | { | ||
1341 | return (r >> 12U) & 0xfffffU; | ||
1342 | } | ||
1343 | static inline u32 fb_mmu_fault_addr_hi_r(void) | ||
1344 | { | ||
1345 | return 0x00100e50U; | ||
1346 | } | ||
1347 | static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) | ||
1348 | { | ||
1349 | return (v & 0xffffffffU) << 0U; | ||
1350 | } | ||
1351 | static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) | ||
1352 | { | ||
1353 | return (r >> 0U) & 0xffffffffU; | ||
1354 | } | ||
1355 | static inline u32 fb_mmu_fault_inst_lo_r(void) | ||
1356 | { | ||
1357 | return 0x00100e54U; | ||
1358 | } | ||
1359 | static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) | ||
1360 | { | ||
1361 | return (r >> 0U) & 0x1ffU; | ||
1362 | } | ||
1363 | static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) | ||
1364 | { | ||
1365 | return (r >> 10U) & 0x3U; | ||
1366 | } | ||
1367 | static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) | ||
1368 | { | ||
1369 | return 0x00000002U; | ||
1370 | } | ||
1371 | static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) | ||
1372 | { | ||
1373 | return 0x00000003U; | ||
1374 | } | ||
1375 | static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) | ||
1376 | { | ||
1377 | return (v & 0xfffffU) << 12U; | ||
1378 | } | ||
1379 | static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) | ||
1380 | { | ||
1381 | return (r >> 12U) & 0xfffffU; | ||
1382 | } | ||
1383 | static inline u32 fb_mmu_fault_inst_hi_r(void) | ||
1384 | { | ||
1385 | return 0x00100e58U; | ||
1386 | } | ||
1387 | static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) | ||
1388 | { | ||
1389 | return (r >> 0U) & 0xffffffffU; | ||
1390 | } | ||
1391 | static inline u32 fb_mmu_fault_info_r(void) | ||
1392 | { | ||
1393 | return 0x00100e5cU; | ||
1394 | } | ||
1395 | static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) | ||
1396 | { | ||
1397 | return (r >> 0U) & 0x1fU; | ||
1398 | } | ||
1399 | static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) | ||
1400 | { | ||
1401 | return (r >> 7U) & 0x1U; | ||
1402 | } | ||
1403 | static inline u32 fb_mmu_fault_info_client_v(u32 r) | ||
1404 | { | ||
1405 | return (r >> 8U) & 0x7fU; | ||
1406 | } | ||
1407 | static inline u32 fb_mmu_fault_info_access_type_v(u32 r) | ||
1408 | { | ||
1409 | return (r >> 16U) & 0xfU; | ||
1410 | } | ||
1411 | static inline u32 fb_mmu_fault_info_client_type_v(u32 r) | ||
1412 | { | ||
1413 | return (r >> 20U) & 0x1U; | ||
1414 | } | ||
1415 | static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) | ||
1416 | { | ||
1417 | return (r >> 24U) & 0x1fU; | ||
1418 | } | ||
1419 | static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) | ||
1420 | { | ||
1421 | return (r >> 29U) & 0x1U; | ||
1422 | } | ||
1423 | static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) | ||
1424 | { | ||
1425 | return (r >> 30U) & 0x1U; | ||
1426 | } | ||
1427 | static inline u32 fb_mmu_fault_info_valid_v(u32 r) | ||
1428 | { | ||
1429 | return (r >> 31U) & 0x1U; | ||
1430 | } | ||
1431 | static inline u32 fb_mmu_fault_status_r(void) | ||
1432 | { | ||
1433 | return 0x00100e60U; | ||
1434 | } | ||
1435 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) | ||
1436 | { | ||
1437 | return 0x1U << 0U; | ||
1438 | } | ||
1439 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) | ||
1440 | { | ||
1441 | return 0x00000001U; | ||
1442 | } | ||
1443 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) | ||
1444 | { | ||
1445 | return 0x1U; | ||
1446 | } | ||
1447 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) | ||
1448 | { | ||
1449 | return 0x00000001U; | ||
1450 | } | ||
1451 | static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) | ||
1452 | { | ||
1453 | return 0x1U; | ||
1454 | } | ||
1455 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) | ||
1456 | { | ||
1457 | return 0x1U << 1U; | ||
1458 | } | ||
1459 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) | ||
1460 | { | ||
1461 | return 0x00000001U; | ||
1462 | } | ||
1463 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) | ||
1464 | { | ||
1465 | return 0x2U; | ||
1466 | } | ||
1467 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) | ||
1468 | { | ||
1469 | return 0x00000001U; | ||
1470 | } | ||
1471 | static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) | ||
1472 | { | ||
1473 | return 0x2U; | ||
1474 | } | ||
1475 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) | ||
1476 | { | ||
1477 | return 0x1U << 2U; | ||
1478 | } | ||
1479 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) | ||
1480 | { | ||
1481 | return 0x00000001U; | ||
1482 | } | ||
1483 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) | ||
1484 | { | ||
1485 | return 0x4U; | ||
1486 | } | ||
1487 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) | ||
1488 | { | ||
1489 | return 0x00000001U; | ||
1490 | } | ||
1491 | static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) | ||
1492 | { | ||
1493 | return 0x4U; | ||
1494 | } | ||
1495 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) | ||
1496 | { | ||
1497 | return 0x1U << 3U; | ||
1498 | } | ||
1499 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) | ||
1500 | { | ||
1501 | return 0x00000001U; | ||
1502 | } | ||
1503 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) | ||
1504 | { | ||
1505 | return 0x8U; | ||
1506 | } | ||
1507 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) | ||
1508 | { | ||
1509 | return 0x00000001U; | ||
1510 | } | ||
1511 | static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) | ||
1512 | { | ||
1513 | return 0x8U; | ||
1514 | } | ||
1515 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) | ||
1516 | { | ||
1517 | return 0x1U << 4U; | ||
1518 | } | ||
1519 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) | ||
1520 | { | ||
1521 | return 0x00000001U; | ||
1522 | } | ||
1523 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) | ||
1524 | { | ||
1525 | return 0x10U; | ||
1526 | } | ||
1527 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) | ||
1528 | { | ||
1529 | return 0x00000001U; | ||
1530 | } | ||
1531 | static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) | ||
1532 | { | ||
1533 | return 0x10U; | ||
1534 | } | ||
1535 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) | ||
1536 | { | ||
1537 | return 0x1U << 5U; | ||
1538 | } | ||
1539 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) | ||
1540 | { | ||
1541 | return 0x00000001U; | ||
1542 | } | ||
1543 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) | ||
1544 | { | ||
1545 | return 0x20U; | ||
1546 | } | ||
1547 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) | ||
1548 | { | ||
1549 | return 0x00000001U; | ||
1550 | } | ||
1551 | static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) | ||
1552 | { | ||
1553 | return 0x20U; | ||
1554 | } | ||
1555 | static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) | ||
1556 | { | ||
1557 | return 0x1U << 6U; | ||
1558 | } | ||
1559 | static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) | ||
1560 | { | ||
1561 | return 0x00000001U; | ||
1562 | } | ||
1563 | static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) | ||
1564 | { | ||
1565 | return 0x40U; | ||
1566 | } | ||
1567 | static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) | ||
1568 | { | ||
1569 | return 0x00000001U; | ||
1570 | } | ||
1571 | static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) | ||
1572 | { | ||
1573 | return 0x40U; | ||
1574 | } | ||
1575 | static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) | ||
1576 | { | ||
1577 | return 0x1U << 7U; | ||
1578 | } | ||
1579 | static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) | ||
1580 | { | ||
1581 | return 0x00000001U; | ||
1582 | } | ||
1583 | static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) | ||
1584 | { | ||
1585 | return 0x80U; | ||
1586 | } | ||
1587 | static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) | ||
1588 | { | ||
1589 | return 0x00000001U; | ||
1590 | } | ||
1591 | static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) | ||
1592 | { | ||
1593 | return 0x80U; | ||
1594 | } | ||
1595 | static inline u32 fb_mmu_fault_status_replayable_m(void) | ||
1596 | { | ||
1597 | return 0x1U << 8U; | ||
1598 | } | ||
1599 | static inline u32 fb_mmu_fault_status_replayable_set_v(void) | ||
1600 | { | ||
1601 | return 0x00000001U; | ||
1602 | } | ||
1603 | static inline u32 fb_mmu_fault_status_replayable_set_f(void) | ||
1604 | { | ||
1605 | return 0x100U; | ||
1606 | } | ||
1607 | static inline u32 fb_mmu_fault_status_replayable_reset_f(void) | ||
1608 | { | ||
1609 | return 0x0U; | ||
1610 | } | ||
1611 | static inline u32 fb_mmu_fault_status_non_replayable_m(void) | ||
1612 | { | ||
1613 | return 0x1U << 9U; | ||
1614 | } | ||
1615 | static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) | ||
1616 | { | ||
1617 | return 0x00000001U; | ||
1618 | } | ||
1619 | static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) | ||
1620 | { | ||
1621 | return 0x200U; | ||
1622 | } | ||
1623 | static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) | ||
1624 | { | ||
1625 | return 0x0U; | ||
1626 | } | ||
1627 | static inline u32 fb_mmu_fault_status_replayable_error_m(void) | ||
1628 | { | ||
1629 | return 0x1U << 10U; | ||
1630 | } | ||
1631 | static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) | ||
1632 | { | ||
1633 | return 0x00000001U; | ||
1634 | } | ||
1635 | static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) | ||
1636 | { | ||
1637 | return 0x400U; | ||
1638 | } | ||
1639 | static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) | ||
1640 | { | ||
1641 | return 0x0U; | ||
1642 | } | ||
1643 | static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) | ||
1644 | { | ||
1645 | return 0x1U << 11U; | ||
1646 | } | ||
1647 | static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) | ||
1648 | { | ||
1649 | return 0x00000001U; | ||
1650 | } | ||
1651 | static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) | ||
1652 | { | ||
1653 | return 0x800U; | ||
1654 | } | ||
1655 | static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) | ||
1656 | { | ||
1657 | return 0x0U; | ||
1658 | } | ||
1659 | static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) | ||
1660 | { | ||
1661 | return 0x1U << 12U; | ||
1662 | } | ||
1663 | static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) | ||
1664 | { | ||
1665 | return 0x00000001U; | ||
1666 | } | ||
1667 | static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) | ||
1668 | { | ||
1669 | return 0x1000U; | ||
1670 | } | ||
1671 | static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) | ||
1672 | { | ||
1673 | return 0x0U; | ||
1674 | } | ||
1675 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) | ||
1676 | { | ||
1677 | return 0x1U << 13U; | ||
1678 | } | ||
1679 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) | ||
1680 | { | ||
1681 | return 0x00000001U; | ||
1682 | } | ||
1683 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) | ||
1684 | { | ||
1685 | return 0x2000U; | ||
1686 | } | ||
1687 | static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) | ||
1688 | { | ||
1689 | return 0x0U; | ||
1690 | } | ||
1691 | static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) | ||
1692 | { | ||
1693 | return 0x1U << 14U; | ||
1694 | } | ||
1695 | static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) | ||
1696 | { | ||
1697 | return 0x00000001U; | ||
1698 | } | ||
1699 | static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) | ||
1700 | { | ||
1701 | return 0x4000U; | ||
1702 | } | ||
1703 | static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) | ||
1704 | { | ||
1705 | return 0x1U << 15U; | ||
1706 | } | ||
1707 | static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) | ||
1708 | { | ||
1709 | return 0x00000001U; | ||
1710 | } | ||
1711 | static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) | ||
1712 | { | ||
1713 | return 0x8000U; | ||
1714 | } | ||
1715 | static inline u32 fb_mmu_fault_status_busy_m(void) | ||
1716 | { | ||
1717 | return 0x1U << 30U; | ||
1718 | } | ||
1719 | static inline u32 fb_mmu_fault_status_busy_true_v(void) | ||
1720 | { | ||
1721 | return 0x00000001U; | ||
1722 | } | ||
1723 | static inline u32 fb_mmu_fault_status_busy_true_f(void) | ||
1724 | { | ||
1725 | return 0x40000000U; | ||
1726 | } | ||
1727 | static inline u32 fb_mmu_fault_status_valid_m(void) | ||
1728 | { | ||
1729 | return 0x1U << 31U; | ||
1730 | } | ||
1731 | static inline u32 fb_mmu_fault_status_valid_set_v(void) | ||
1732 | { | ||
1733 | return 0x00000001U; | ||
1734 | } | ||
1735 | static inline u32 fb_mmu_fault_status_valid_set_f(void) | ||
1736 | { | ||
1737 | return 0x80000000U; | ||
1738 | } | ||
1739 | static inline u32 fb_mmu_fault_status_valid_clear_v(void) | ||
1740 | { | ||
1741 | return 0x00000001U; | ||
1742 | } | ||
1743 | static inline u32 fb_mmu_fault_status_valid_clear_f(void) | ||
1744 | { | ||
1745 | return 0x80000000U; | ||
1746 | } | ||
1747 | static inline u32 fb_mmu_num_active_ltcs_r(void) | ||
1748 | { | ||
1749 | return 0x00100ec0U; | ||
1750 | } | ||
1751 | static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) | ||
1752 | { | ||
1753 | return (v & 0x1fU) << 0U; | ||
1754 | } | ||
1755 | static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) | ||
1756 | { | ||
1757 | return (r >> 0U) & 0x1fU; | ||
1758 | } | ||
1759 | static inline u32 fb_mmu_cbc_base_r(void) | ||
1760 | { | ||
1761 | return 0x00100ec4U; | ||
1762 | } | ||
1763 | static inline u32 fb_mmu_cbc_base_address_f(u32 v) | ||
1764 | { | ||
1765 | return (v & 0x3ffffffU) << 0U; | ||
1766 | } | ||
1767 | static inline u32 fb_mmu_cbc_base_address_v(u32 r) | ||
1768 | { | ||
1769 | return (r >> 0U) & 0x3ffffffU; | ||
1770 | } | ||
1771 | static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) | ||
1772 | { | ||
1773 | return 0x0000000bU; | ||
1774 | } | ||
1775 | static inline u32 fb_mmu_cbc_top_r(void) | ||
1776 | { | ||
1777 | return 0x00100ec8U; | ||
1778 | } | ||
1779 | static inline u32 fb_mmu_cbc_top_size_f(u32 v) | ||
1780 | { | ||
1781 | return (v & 0x7fffU) << 0U; | ||
1782 | } | ||
1783 | static inline u32 fb_mmu_cbc_top_size_v(u32 r) | ||
1784 | { | ||
1785 | return (r >> 0U) & 0x7fffU; | ||
1786 | } | ||
1787 | static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) | ||
1788 | { | ||
1789 | return 0x0000000bU; | ||
1790 | } | ||
1791 | static inline u32 fb_mmu_cbc_max_r(void) | ||
1792 | { | ||
1793 | return 0x00100eccU; | ||
1794 | } | ||
1795 | static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) | ||
1796 | { | ||
1797 | return (v & 0xffffffU) << 0U; | ||
1798 | } | ||
1799 | static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) | ||
1800 | { | ||
1801 | return (r >> 0U) & 0xffffffU; | ||
1802 | } | ||
1803 | static inline u32 fb_mmu_cbc_max_safe_f(u32 v) | ||
1804 | { | ||
1805 | return (v & 0x1U) << 30U; | ||
1806 | } | ||
1807 | static inline u32 fb_mmu_cbc_max_safe_true_v(void) | ||
1808 | { | ||
1809 | return 0x00000001U; | ||
1810 | } | ||
1811 | static inline u32 fb_mmu_cbc_max_safe_false_v(void) | ||
1812 | { | ||
1813 | return 0x00000000U; | ||
1814 | } | ||
1815 | static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) | ||
1816 | { | ||
1817 | return (v & 0x1U) << 31U; | ||
1818 | } | ||
1819 | static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) | ||
1820 | { | ||
1821 | return 0x00000000U; | ||
1822 | } | ||
1823 | static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) | ||
1824 | { | ||
1825 | return 0x00000001U; | ||
1826 | } | ||
1827 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h new file mode 100644 index 00000000..59cc7a1d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | |||
@@ -0,0 +1,687 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_fifo_gv11b_h_ | ||
57 | #define _hw_fifo_gv11b_h_ | ||
58 | |||
59 | static inline u32 fifo_bar1_base_r(void) | ||
60 | { | ||
61 | return 0x00002254U; | ||
62 | } | ||
63 | static inline u32 fifo_bar1_base_ptr_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xfffffffU) << 0U; | ||
66 | } | ||
67 | static inline u32 fifo_bar1_base_ptr_align_shift_v(void) | ||
68 | { | ||
69 | return 0x0000000cU; | ||
70 | } | ||
71 | static inline u32 fifo_bar1_base_valid_false_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 fifo_bar1_base_valid_true_f(void) | ||
76 | { | ||
77 | return 0x10000000U; | ||
78 | } | ||
79 | static inline u32 fifo_userd_writeback_r(void) | ||
80 | { | ||
81 | return 0x0000225cU; | ||
82 | } | ||
83 | static inline u32 fifo_userd_writeback_timer_f(u32 v) | ||
84 | { | ||
85 | return (v & 0xffU) << 0U; | ||
86 | } | ||
87 | static inline u32 fifo_userd_writeback_timer_disabled_v(void) | ||
88 | { | ||
89 | return 0x00000000U; | ||
90 | } | ||
91 | static inline u32 fifo_userd_writeback_timer_shorter_v(void) | ||
92 | { | ||
93 | return 0x00000003U; | ||
94 | } | ||
95 | static inline u32 fifo_userd_writeback_timer_100us_v(void) | ||
96 | { | ||
97 | return 0x00000064U; | ||
98 | } | ||
99 | static inline u32 fifo_userd_writeback_timescale_f(u32 v) | ||
100 | { | ||
101 | return (v & 0xfU) << 12U; | ||
102 | } | ||
103 | static inline u32 fifo_userd_writeback_timescale_0_v(void) | ||
104 | { | ||
105 | return 0x00000000U; | ||
106 | } | ||
107 | static inline u32 fifo_runlist_base_r(void) | ||
108 | { | ||
109 | return 0x00002270U; | ||
110 | } | ||
111 | static inline u32 fifo_runlist_base_ptr_f(u32 v) | ||
112 | { | ||
113 | return (v & 0xfffffffU) << 0U; | ||
114 | } | ||
115 | static inline u32 fifo_runlist_base_target_vid_mem_f(void) | ||
116 | { | ||
117 | return 0x0U; | ||
118 | } | ||
119 | static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) | ||
120 | { | ||
121 | return 0x20000000U; | ||
122 | } | ||
123 | static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) | ||
124 | { | ||
125 | return 0x30000000U; | ||
126 | } | ||
127 | static inline u32 fifo_runlist_r(void) | ||
128 | { | ||
129 | return 0x00002274U; | ||
130 | } | ||
131 | static inline u32 fifo_runlist_engine_f(u32 v) | ||
132 | { | ||
133 | return (v & 0xfU) << 20U; | ||
134 | } | ||
135 | static inline u32 fifo_eng_runlist_base_r(u32 i) | ||
136 | { | ||
137 | return 0x00002280U + i*8U; | ||
138 | } | ||
139 | static inline u32 fifo_eng_runlist_base__size_1_v(void) | ||
140 | { | ||
141 | return 0x00000002U; | ||
142 | } | ||
143 | static inline u32 fifo_eng_runlist_r(u32 i) | ||
144 | { | ||
145 | return 0x00002284U + i*8U; | ||
146 | } | ||
147 | static inline u32 fifo_eng_runlist__size_1_v(void) | ||
148 | { | ||
149 | return 0x00000002U; | ||
150 | } | ||
151 | static inline u32 fifo_eng_runlist_length_f(u32 v) | ||
152 | { | ||
153 | return (v & 0xffffU) << 0U; | ||
154 | } | ||
155 | static inline u32 fifo_eng_runlist_length_max_v(void) | ||
156 | { | ||
157 | return 0x0000ffffU; | ||
158 | } | ||
159 | static inline u32 fifo_eng_runlist_pending_true_f(void) | ||
160 | { | ||
161 | return 0x100000U; | ||
162 | } | ||
163 | static inline u32 fifo_pb_timeslice_r(u32 i) | ||
164 | { | ||
165 | return 0x00002350U + i*4U; | ||
166 | } | ||
167 | static inline u32 fifo_pb_timeslice_timeout_16_f(void) | ||
168 | { | ||
169 | return 0x10U; | ||
170 | } | ||
171 | static inline u32 fifo_pb_timeslice_timescale_0_f(void) | ||
172 | { | ||
173 | return 0x0U; | ||
174 | } | ||
175 | static inline u32 fifo_pb_timeslice_enable_true_f(void) | ||
176 | { | ||
177 | return 0x10000000U; | ||
178 | } | ||
179 | static inline u32 fifo_pbdma_map_r(u32 i) | ||
180 | { | ||
181 | return 0x00002390U + i*4U; | ||
182 | } | ||
183 | static inline u32 fifo_intr_0_r(void) | ||
184 | { | ||
185 | return 0x00002100U; | ||
186 | } | ||
187 | static inline u32 fifo_intr_0_bind_error_pending_f(void) | ||
188 | { | ||
189 | return 0x1U; | ||
190 | } | ||
191 | static inline u32 fifo_intr_0_bind_error_reset_f(void) | ||
192 | { | ||
193 | return 0x1U; | ||
194 | } | ||
195 | static inline u32 fifo_intr_0_sched_error_pending_f(void) | ||
196 | { | ||
197 | return 0x100U; | ||
198 | } | ||
199 | static inline u32 fifo_intr_0_sched_error_reset_f(void) | ||
200 | { | ||
201 | return 0x100U; | ||
202 | } | ||
203 | static inline u32 fifo_intr_0_chsw_error_pending_f(void) | ||
204 | { | ||
205 | return 0x10000U; | ||
206 | } | ||
207 | static inline u32 fifo_intr_0_chsw_error_reset_f(void) | ||
208 | { | ||
209 | return 0x10000U; | ||
210 | } | ||
211 | static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) | ||
212 | { | ||
213 | return 0x800000U; | ||
214 | } | ||
215 | static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) | ||
216 | { | ||
217 | return 0x800000U; | ||
218 | } | ||
219 | static inline u32 fifo_intr_0_lb_error_pending_f(void) | ||
220 | { | ||
221 | return 0x1000000U; | ||
222 | } | ||
223 | static inline u32 fifo_intr_0_lb_error_reset_f(void) | ||
224 | { | ||
225 | return 0x1000000U; | ||
226 | } | ||
227 | static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) | ||
228 | { | ||
229 | return 0x20000000U; | ||
230 | } | ||
231 | static inline u32 fifo_intr_0_runlist_event_pending_f(void) | ||
232 | { | ||
233 | return 0x40000000U; | ||
234 | } | ||
235 | static inline u32 fifo_intr_0_channel_intr_pending_f(void) | ||
236 | { | ||
237 | return 0x80000000U; | ||
238 | } | ||
239 | static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) | ||
240 | { | ||
241 | return 0x2U; | ||
242 | } | ||
243 | static inline u32 fifo_intr_en_0_r(void) | ||
244 | { | ||
245 | return 0x00002140U; | ||
246 | } | ||
247 | static inline u32 fifo_intr_en_0_sched_error_f(u32 v) | ||
248 | { | ||
249 | return (v & 0x1U) << 8U; | ||
250 | } | ||
251 | static inline u32 fifo_intr_en_0_sched_error_m(void) | ||
252 | { | ||
253 | return 0x1U << 8U; | ||
254 | } | ||
255 | static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) | ||
256 | { | ||
257 | return 0x2U; | ||
258 | } | ||
259 | static inline u32 fifo_intr_en_1_r(void) | ||
260 | { | ||
261 | return 0x00002528U; | ||
262 | } | ||
263 | static inline u32 fifo_intr_bind_error_r(void) | ||
264 | { | ||
265 | return 0x0000252cU; | ||
266 | } | ||
267 | static inline u32 fifo_intr_sched_error_r(void) | ||
268 | { | ||
269 | return 0x0000254cU; | ||
270 | } | ||
271 | static inline u32 fifo_intr_sched_error_code_f(u32 v) | ||
272 | { | ||
273 | return (v & 0xffU) << 0U; | ||
274 | } | ||
275 | static inline u32 fifo_intr_chsw_error_r(void) | ||
276 | { | ||
277 | return 0x0000256cU; | ||
278 | } | ||
279 | static inline u32 fifo_intr_ctxsw_timeout_r(void) | ||
280 | { | ||
281 | return 0x00002a30U; | ||
282 | } | ||
283 | static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) | ||
284 | { | ||
285 | return (v & 0x1U) << (0U + i*1U); | ||
286 | } | ||
287 | static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) | ||
288 | { | ||
289 | return (r >> (0U + i*1U)) & 0x1U; | ||
290 | } | ||
291 | static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) | ||
292 | { | ||
293 | return 0x00000020U; | ||
294 | } | ||
295 | static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) | ||
296 | { | ||
297 | return 0x00000001U; | ||
298 | } | ||
299 | static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) | ||
300 | { | ||
301 | return 0x1U << (0U + i*1U); | ||
302 | } | ||
303 | static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) | ||
304 | { | ||
305 | return 0x00003200U + i*4U; | ||
306 | } | ||
307 | static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) | ||
308 | { | ||
309 | return 0x00000004U; | ||
310 | } | ||
311 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) | ||
312 | { | ||
313 | return (r >> 14U) & 0x3U; | ||
314 | } | ||
315 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) | ||
316 | { | ||
317 | return 0x00000001U; | ||
318 | } | ||
319 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) | ||
320 | { | ||
321 | return 0x00000002U; | ||
322 | } | ||
323 | static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) | ||
324 | { | ||
325 | return 0x00000003U; | ||
326 | } | ||
327 | static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) | ||
328 | { | ||
329 | return (r >> 0U) & 0x3fffU; | ||
330 | } | ||
331 | static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) | ||
332 | { | ||
333 | return (r >> 16U) & 0x3fffU; | ||
334 | } | ||
335 | static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) | ||
336 | { | ||
337 | return (r >> 30U) & 0x3U; | ||
338 | } | ||
339 | static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) | ||
340 | { | ||
341 | return 0x00000000U; | ||
342 | } | ||
343 | static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) | ||
344 | { | ||
345 | return 0x00000001U; | ||
346 | } | ||
347 | static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) | ||
348 | { | ||
349 | return 0x00000002U; | ||
350 | } | ||
351 | static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) | ||
352 | { | ||
353 | return 0x00000003U; | ||
354 | } | ||
355 | static inline u32 fifo_intr_pbdma_id_r(void) | ||
356 | { | ||
357 | return 0x000025a0U; | ||
358 | } | ||
359 | static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) | ||
360 | { | ||
361 | return (v & 0x1U) << (0U + i*1U); | ||
362 | } | ||
363 | static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) | ||
364 | { | ||
365 | return (r >> (0U + i*1U)) & 0x1U; | ||
366 | } | ||
367 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) | ||
368 | { | ||
369 | return 0x00000003U; | ||
370 | } | ||
371 | static inline u32 fifo_intr_runlist_r(void) | ||
372 | { | ||
373 | return 0x00002a00U; | ||
374 | } | ||
375 | static inline u32 fifo_fb_timeout_r(void) | ||
376 | { | ||
377 | return 0x00002a04U; | ||
378 | } | ||
379 | static inline u32 fifo_fb_timeout_period_m(void) | ||
380 | { | ||
381 | return 0x3fffffffU << 0U; | ||
382 | } | ||
383 | static inline u32 fifo_fb_timeout_period_max_f(void) | ||
384 | { | ||
385 | return 0x3fffffffU; | ||
386 | } | ||
387 | static inline u32 fifo_fb_timeout_period_init_f(void) | ||
388 | { | ||
389 | return 0x3c00U; | ||
390 | } | ||
391 | static inline u32 fifo_fb_timeout_detection_m(void) | ||
392 | { | ||
393 | return 0x1U << 31U; | ||
394 | } | ||
395 | static inline u32 fifo_fb_timeout_detection_enabled_f(void) | ||
396 | { | ||
397 | return 0x80000000U; | ||
398 | } | ||
399 | static inline u32 fifo_fb_timeout_detection_disabled_f(void) | ||
400 | { | ||
401 | return 0x0U; | ||
402 | } | ||
403 | static inline u32 fifo_sched_disable_r(void) | ||
404 | { | ||
405 | return 0x00002630U; | ||
406 | } | ||
407 | static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) | ||
408 | { | ||
409 | return (v & 0x1U) << (0U + i*1U); | ||
410 | } | ||
411 | static inline u32 fifo_sched_disable_runlist_m(u32 i) | ||
412 | { | ||
413 | return 0x1U << (0U + i*1U); | ||
414 | } | ||
415 | static inline u32 fifo_sched_disable_true_v(void) | ||
416 | { | ||
417 | return 0x00000001U; | ||
418 | } | ||
419 | static inline u32 fifo_runlist_preempt_r(void) | ||
420 | { | ||
421 | return 0x00002638U; | ||
422 | } | ||
423 | static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) | ||
424 | { | ||
425 | return (v & 0x1U) << (0U + i*1U); | ||
426 | } | ||
427 | static inline u32 fifo_runlist_preempt_runlist_m(u32 i) | ||
428 | { | ||
429 | return 0x1U << (0U + i*1U); | ||
430 | } | ||
431 | static inline u32 fifo_runlist_preempt_runlist_pending_v(void) | ||
432 | { | ||
433 | return 0x00000001U; | ||
434 | } | ||
435 | static inline u32 fifo_preempt_r(void) | ||
436 | { | ||
437 | return 0x00002634U; | ||
438 | } | ||
439 | static inline u32 fifo_preempt_pending_true_f(void) | ||
440 | { | ||
441 | return 0x100000U; | ||
442 | } | ||
443 | static inline u32 fifo_preempt_type_channel_f(void) | ||
444 | { | ||
445 | return 0x0U; | ||
446 | } | ||
447 | static inline u32 fifo_preempt_type_tsg_f(void) | ||
448 | { | ||
449 | return 0x1000000U; | ||
450 | } | ||
451 | static inline u32 fifo_preempt_chid_f(u32 v) | ||
452 | { | ||
453 | return (v & 0xfffU) << 0U; | ||
454 | } | ||
455 | static inline u32 fifo_preempt_id_f(u32 v) | ||
456 | { | ||
457 | return (v & 0xfffU) << 0U; | ||
458 | } | ||
459 | static inline u32 fifo_engine_status_r(u32 i) | ||
460 | { | ||
461 | return 0x00002640U + i*8U; | ||
462 | } | ||
463 | static inline u32 fifo_engine_status__size_1_v(void) | ||
464 | { | ||
465 | return 0x00000004U; | ||
466 | } | ||
467 | static inline u32 fifo_engine_status_id_v(u32 r) | ||
468 | { | ||
469 | return (r >> 0U) & 0xfffU; | ||
470 | } | ||
471 | static inline u32 fifo_engine_status_id_type_v(u32 r) | ||
472 | { | ||
473 | return (r >> 12U) & 0x1U; | ||
474 | } | ||
475 | static inline u32 fifo_engine_status_id_type_chid_v(void) | ||
476 | { | ||
477 | return 0x00000000U; | ||
478 | } | ||
479 | static inline u32 fifo_engine_status_id_type_tsgid_v(void) | ||
480 | { | ||
481 | return 0x00000001U; | ||
482 | } | ||
483 | static inline u32 fifo_engine_status_ctx_status_v(u32 r) | ||
484 | { | ||
485 | return (r >> 13U) & 0x7U; | ||
486 | } | ||
487 | static inline u32 fifo_engine_status_ctx_status_valid_v(void) | ||
488 | { | ||
489 | return 0x00000001U; | ||
490 | } | ||
491 | static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) | ||
492 | { | ||
493 | return 0x00000005U; | ||
494 | } | ||
495 | static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) | ||
496 | { | ||
497 | return 0x00000006U; | ||
498 | } | ||
499 | static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) | ||
500 | { | ||
501 | return 0x00000007U; | ||
502 | } | ||
503 | static inline u32 fifo_engine_status_next_id_v(u32 r) | ||
504 | { | ||
505 | return (r >> 16U) & 0xfffU; | ||
506 | } | ||
507 | static inline u32 fifo_engine_status_next_id_type_v(u32 r) | ||
508 | { | ||
509 | return (r >> 28U) & 0x1U; | ||
510 | } | ||
511 | static inline u32 fifo_engine_status_next_id_type_chid_v(void) | ||
512 | { | ||
513 | return 0x00000000U; | ||
514 | } | ||
515 | static inline u32 fifo_engine_status_eng_reload_v(u32 r) | ||
516 | { | ||
517 | return (r >> 29U) & 0x1U; | ||
518 | } | ||
519 | static inline u32 fifo_engine_status_faulted_v(u32 r) | ||
520 | { | ||
521 | return (r >> 30U) & 0x1U; | ||
522 | } | ||
523 | static inline u32 fifo_engine_status_faulted_true_v(void) | ||
524 | { | ||
525 | return 0x00000001U; | ||
526 | } | ||
527 | static inline u32 fifo_engine_status_engine_v(u32 r) | ||
528 | { | ||
529 | return (r >> 31U) & 0x1U; | ||
530 | } | ||
531 | static inline u32 fifo_engine_status_engine_idle_v(void) | ||
532 | { | ||
533 | return 0x00000000U; | ||
534 | } | ||
535 | static inline u32 fifo_engine_status_engine_busy_v(void) | ||
536 | { | ||
537 | return 0x00000001U; | ||
538 | } | ||
539 | static inline u32 fifo_engine_status_ctxsw_v(u32 r) | ||
540 | { | ||
541 | return (r >> 15U) & 0x1U; | ||
542 | } | ||
543 | static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) | ||
544 | { | ||
545 | return 0x00000001U; | ||
546 | } | ||
547 | static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) | ||
548 | { | ||
549 | return 0x8000U; | ||
550 | } | ||
551 | static inline u32 fifo_eng_ctxsw_timeout_r(void) | ||
552 | { | ||
553 | return 0x00002a0cU; | ||
554 | } | ||
555 | static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) | ||
556 | { | ||
557 | return (v & 0x7fffffffU) << 0U; | ||
558 | } | ||
559 | static inline u32 fifo_eng_ctxsw_timeout_period_m(void) | ||
560 | { | ||
561 | return 0x7fffffffU << 0U; | ||
562 | } | ||
563 | static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) | ||
564 | { | ||
565 | return (r >> 0U) & 0x7fffffffU; | ||
566 | } | ||
567 | static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) | ||
568 | { | ||
569 | return 0x3fffffU; | ||
570 | } | ||
571 | static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) | ||
572 | { | ||
573 | return 0x7fffffffU; | ||
574 | } | ||
575 | static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) | ||
576 | { | ||
577 | return (v & 0x1U) << 31U; | ||
578 | } | ||
579 | static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) | ||
580 | { | ||
581 | return 0x1U << 31U; | ||
582 | } | ||
583 | static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) | ||
584 | { | ||
585 | return 0x80000000U; | ||
586 | } | ||
587 | static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) | ||
588 | { | ||
589 | return 0x0U; | ||
590 | } | ||
591 | static inline u32 fifo_pbdma_status_r(u32 i) | ||
592 | { | ||
593 | return 0x00003080U + i*4U; | ||
594 | } | ||
595 | static inline u32 fifo_pbdma_status__size_1_v(void) | ||
596 | { | ||
597 | return 0x00000003U; | ||
598 | } | ||
599 | static inline u32 fifo_pbdma_status_id_v(u32 r) | ||
600 | { | ||
601 | return (r >> 0U) & 0xfffU; | ||
602 | } | ||
603 | static inline u32 fifo_pbdma_status_id_type_v(u32 r) | ||
604 | { | ||
605 | return (r >> 12U) & 0x1U; | ||
606 | } | ||
607 | static inline u32 fifo_pbdma_status_id_type_chid_v(void) | ||
608 | { | ||
609 | return 0x00000000U; | ||
610 | } | ||
611 | static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) | ||
612 | { | ||
613 | return 0x00000001U; | ||
614 | } | ||
615 | static inline u32 fifo_pbdma_status_chan_status_v(u32 r) | ||
616 | { | ||
617 | return (r >> 13U) & 0x7U; | ||
618 | } | ||
619 | static inline u32 fifo_pbdma_status_chan_status_valid_v(void) | ||
620 | { | ||
621 | return 0x00000001U; | ||
622 | } | ||
623 | static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) | ||
624 | { | ||
625 | return 0x00000005U; | ||
626 | } | ||
627 | static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) | ||
628 | { | ||
629 | return 0x00000006U; | ||
630 | } | ||
631 | static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) | ||
632 | { | ||
633 | return 0x00000007U; | ||
634 | } | ||
635 | static inline u32 fifo_pbdma_status_next_id_v(u32 r) | ||
636 | { | ||
637 | return (r >> 16U) & 0xfffU; | ||
638 | } | ||
639 | static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) | ||
640 | { | ||
641 | return (r >> 28U) & 0x1U; | ||
642 | } | ||
643 | static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) | ||
644 | { | ||
645 | return 0x00000000U; | ||
646 | } | ||
647 | static inline u32 fifo_pbdma_status_chsw_v(u32 r) | ||
648 | { | ||
649 | return (r >> 15U) & 0x1U; | ||
650 | } | ||
651 | static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) | ||
652 | { | ||
653 | return 0x00000001U; | ||
654 | } | ||
655 | static inline u32 fifo_cfg0_r(void) | ||
656 | { | ||
657 | return 0x00002004U; | ||
658 | } | ||
659 | static inline u32 fifo_cfg0_num_pbdma_v(u32 r) | ||
660 | { | ||
661 | return (r >> 0U) & 0xffU; | ||
662 | } | ||
663 | static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) | ||
664 | { | ||
665 | return (r >> 16U) & 0xffU; | ||
666 | } | ||
667 | static inline u32 fifo_fb_iface_r(void) | ||
668 | { | ||
669 | return 0x000026f0U; | ||
670 | } | ||
671 | static inline u32 fifo_fb_iface_control_v(u32 r) | ||
672 | { | ||
673 | return (r >> 0U) & 0x1U; | ||
674 | } | ||
675 | static inline u32 fifo_fb_iface_control_enable_f(void) | ||
676 | { | ||
677 | return 0x1U; | ||
678 | } | ||
679 | static inline u32 fifo_fb_iface_status_v(u32 r) | ||
680 | { | ||
681 | return (r >> 4U) & 0x1U; | ||
682 | } | ||
683 | static inline u32 fifo_fb_iface_status_enabled_f(void) | ||
684 | { | ||
685 | return 0x10U; | ||
686 | } | ||
687 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h new file mode 100644 index 00000000..45c01de0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h | |||
@@ -0,0 +1,187 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_flush_gv11b_h_ | ||
57 | #define _hw_flush_gv11b_h_ | ||
58 | |||
59 | static inline u32 flush_l2_system_invalidate_r(void) | ||
60 | { | ||
61 | return 0x00070004U; | ||
62 | } | ||
63 | static inline u32 flush_l2_system_invalidate_pending_v(u32 r) | ||
64 | { | ||
65 | return (r >> 0U) & 0x1U; | ||
66 | } | ||
67 | static inline u32 flush_l2_system_invalidate_pending_busy_v(void) | ||
68 | { | ||
69 | return 0x00000001U; | ||
70 | } | ||
71 | static inline u32 flush_l2_system_invalidate_pending_busy_f(void) | ||
72 | { | ||
73 | return 0x1U; | ||
74 | } | ||
75 | static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) | ||
76 | { | ||
77 | return (r >> 1U) & 0x1U; | ||
78 | } | ||
79 | static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) | ||
80 | { | ||
81 | return 0x00000001U; | ||
82 | } | ||
83 | static inline u32 flush_l2_flush_dirty_r(void) | ||
84 | { | ||
85 | return 0x00070010U; | ||
86 | } | ||
87 | static inline u32 flush_l2_flush_dirty_pending_v(u32 r) | ||
88 | { | ||
89 | return (r >> 0U) & 0x1U; | ||
90 | } | ||
91 | static inline u32 flush_l2_flush_dirty_pending_empty_v(void) | ||
92 | { | ||
93 | return 0x00000000U; | ||
94 | } | ||
95 | static inline u32 flush_l2_flush_dirty_pending_empty_f(void) | ||
96 | { | ||
97 | return 0x0U; | ||
98 | } | ||
99 | static inline u32 flush_l2_flush_dirty_pending_busy_v(void) | ||
100 | { | ||
101 | return 0x00000001U; | ||
102 | } | ||
103 | static inline u32 flush_l2_flush_dirty_pending_busy_f(void) | ||
104 | { | ||
105 | return 0x1U; | ||
106 | } | ||
107 | static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) | ||
108 | { | ||
109 | return (r >> 1U) & 0x1U; | ||
110 | } | ||
111 | static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) | ||
112 | { | ||
113 | return 0x00000000U; | ||
114 | } | ||
115 | static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) | ||
116 | { | ||
117 | return 0x0U; | ||
118 | } | ||
119 | static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) | ||
120 | { | ||
121 | return 0x00000001U; | ||
122 | } | ||
123 | static inline u32 flush_l2_clean_comptags_r(void) | ||
124 | { | ||
125 | return 0x0007000cU; | ||
126 | } | ||
127 | static inline u32 flush_l2_clean_comptags_pending_v(u32 r) | ||
128 | { | ||
129 | return (r >> 0U) & 0x1U; | ||
130 | } | ||
131 | static inline u32 flush_l2_clean_comptags_pending_empty_v(void) | ||
132 | { | ||
133 | return 0x00000000U; | ||
134 | } | ||
135 | static inline u32 flush_l2_clean_comptags_pending_empty_f(void) | ||
136 | { | ||
137 | return 0x0U; | ||
138 | } | ||
139 | static inline u32 flush_l2_clean_comptags_pending_busy_v(void) | ||
140 | { | ||
141 | return 0x00000001U; | ||
142 | } | ||
143 | static inline u32 flush_l2_clean_comptags_pending_busy_f(void) | ||
144 | { | ||
145 | return 0x1U; | ||
146 | } | ||
147 | static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) | ||
148 | { | ||
149 | return (r >> 1U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) | ||
152 | { | ||
153 | return 0x00000000U; | ||
154 | } | ||
155 | static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) | ||
156 | { | ||
157 | return 0x0U; | ||
158 | } | ||
159 | static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) | ||
160 | { | ||
161 | return 0x00000001U; | ||
162 | } | ||
163 | static inline u32 flush_fb_flush_r(void) | ||
164 | { | ||
165 | return 0x00070000U; | ||
166 | } | ||
167 | static inline u32 flush_fb_flush_pending_v(u32 r) | ||
168 | { | ||
169 | return (r >> 0U) & 0x1U; | ||
170 | } | ||
171 | static inline u32 flush_fb_flush_pending_busy_v(void) | ||
172 | { | ||
173 | return 0x00000001U; | ||
174 | } | ||
175 | static inline u32 flush_fb_flush_pending_busy_f(void) | ||
176 | { | ||
177 | return 0x1U; | ||
178 | } | ||
179 | static inline u32 flush_fb_flush_outstanding_v(u32 r) | ||
180 | { | ||
181 | return (r >> 1U) & 0x1U; | ||
182 | } | ||
183 | static inline u32 flush_fb_flush_outstanding_true_v(void) | ||
184 | { | ||
185 | return 0x00000001U; | ||
186 | } | ||
187 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h new file mode 100644 index 00000000..f8d9b196 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | |||
@@ -0,0 +1,151 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_fuse_gv11b_h_ | ||
57 | #define _hw_fuse_gv11b_h_ | ||
58 | |||
59 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) | ||
60 | { | ||
61 | return 0x00021c38U + i*4U; | ||
62 | } | ||
63 | static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) | ||
64 | { | ||
65 | return 0x00021838U + i*4U; | ||
66 | } | ||
67 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) | ||
68 | { | ||
69 | return 0x00021944U; | ||
70 | } | ||
71 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) | ||
72 | { | ||
73 | return (v & 0xffU) << 0U; | ||
74 | } | ||
75 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) | ||
76 | { | ||
77 | return 0xffU << 0U; | ||
78 | } | ||
79 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) | ||
80 | { | ||
81 | return (r >> 0U) & 0xffU; | ||
82 | } | ||
83 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) | ||
84 | { | ||
85 | return 0x00021948U; | ||
86 | } | ||
87 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) | ||
88 | { | ||
89 | return (v & 0x1U) << 0U; | ||
90 | } | ||
91 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) | ||
92 | { | ||
93 | return 0x1U << 0U; | ||
94 | } | ||
95 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) | ||
96 | { | ||
97 | return (r >> 0U) & 0x1U; | ||
98 | } | ||
99 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) | ||
100 | { | ||
101 | return 0x1U; | ||
102 | } | ||
103 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) | ||
104 | { | ||
105 | return 0x0U; | ||
106 | } | ||
107 | static inline u32 fuse_status_opt_fbio_r(void) | ||
108 | { | ||
109 | return 0x00021c14U; | ||
110 | } | ||
111 | static inline u32 fuse_status_opt_fbio_data_f(u32 v) | ||
112 | { | ||
113 | return (v & 0xffffU) << 0U; | ||
114 | } | ||
115 | static inline u32 fuse_status_opt_fbio_data_m(void) | ||
116 | { | ||
117 | return 0xffffU << 0U; | ||
118 | } | ||
119 | static inline u32 fuse_status_opt_fbio_data_v(u32 r) | ||
120 | { | ||
121 | return (r >> 0U) & 0xffffU; | ||
122 | } | ||
123 | static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) | ||
124 | { | ||
125 | return 0x00021d70U + i*4U; | ||
126 | } | ||
127 | static inline u32 fuse_status_opt_fbp_r(void) | ||
128 | { | ||
129 | return 0x00021d38U; | ||
130 | } | ||
131 | static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) | ||
132 | { | ||
133 | return (r >> (0U + i*1U)) & 0x1U; | ||
134 | } | ||
135 | static inline u32 fuse_opt_ecc_en_r(void) | ||
136 | { | ||
137 | return 0x00021228U; | ||
138 | } | ||
139 | static inline u32 fuse_opt_feature_fuses_override_disable_r(void) | ||
140 | { | ||
141 | return 0x000213f0U; | ||
142 | } | ||
143 | static inline u32 fuse_opt_sec_debug_en_r(void) | ||
144 | { | ||
145 | return 0x00021218U; | ||
146 | } | ||
147 | static inline u32 fuse_opt_priv_sec_en_r(void) | ||
148 | { | ||
149 | return 0x00021434U; | ||
150 | } | ||
151 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h new file mode 100644 index 00000000..0a442b1f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | |||
@@ -0,0 +1,1495 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_gmmu_gv11b_h_ | ||
57 | #define _hw_gmmu_gv11b_h_ | ||
58 | |||
59 | static inline u32 gmmu_new_pde_is_pte_w(void) | ||
60 | { | ||
61 | return 0U; | ||
62 | } | ||
63 | static inline u32 gmmu_new_pde_is_pte_false_f(void) | ||
64 | { | ||
65 | return 0x0U; | ||
66 | } | ||
67 | static inline u32 gmmu_new_pde_aperture_w(void) | ||
68 | { | ||
69 | return 0U; | ||
70 | } | ||
71 | static inline u32 gmmu_new_pde_aperture_invalid_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 gmmu_new_pde_aperture_video_memory_f(void) | ||
76 | { | ||
77 | return 0x2U; | ||
78 | } | ||
79 | static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) | ||
80 | { | ||
81 | return 0x4U; | ||
82 | } | ||
83 | static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) | ||
84 | { | ||
85 | return 0x6U; | ||
86 | } | ||
87 | static inline u32 gmmu_new_pde_address_sys_f(u32 v) | ||
88 | { | ||
89 | return (v & 0xffffffU) << 8U; | ||
90 | } | ||
91 | static inline u32 gmmu_new_pde_address_sys_w(void) | ||
92 | { | ||
93 | return 0U; | ||
94 | } | ||
95 | static inline u32 gmmu_new_pde_vol_w(void) | ||
96 | { | ||
97 | return 0U; | ||
98 | } | ||
99 | static inline u32 gmmu_new_pde_vol_true_f(void) | ||
100 | { | ||
101 | return 0x8U; | ||
102 | } | ||
103 | static inline u32 gmmu_new_pde_vol_false_f(void) | ||
104 | { | ||
105 | return 0x0U; | ||
106 | } | ||
107 | static inline u32 gmmu_new_pde_address_shift_v(void) | ||
108 | { | ||
109 | return 0x0000000cU; | ||
110 | } | ||
111 | static inline u32 gmmu_new_pde__size_v(void) | ||
112 | { | ||
113 | return 0x00000008U; | ||
114 | } | ||
115 | static inline u32 gmmu_new_dual_pde_is_pte_w(void) | ||
116 | { | ||
117 | return 0U; | ||
118 | } | ||
119 | static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) | ||
120 | { | ||
121 | return 0x0U; | ||
122 | } | ||
123 | static inline u32 gmmu_new_dual_pde_aperture_big_w(void) | ||
124 | { | ||
125 | return 0U; | ||
126 | } | ||
127 | static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) | ||
128 | { | ||
129 | return 0x0U; | ||
130 | } | ||
131 | static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) | ||
132 | { | ||
133 | return 0x2U; | ||
134 | } | ||
135 | static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) | ||
136 | { | ||
137 | return 0x4U; | ||
138 | } | ||
139 | static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) | ||
140 | { | ||
141 | return 0x6U; | ||
142 | } | ||
143 | static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) | ||
144 | { | ||
145 | return (v & 0xfffffffU) << 4U; | ||
146 | } | ||
147 | static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) | ||
148 | { | ||
149 | return 0U; | ||
150 | } | ||
151 | static inline u32 gmmu_new_dual_pde_aperture_small_w(void) | ||
152 | { | ||
153 | return 2U; | ||
154 | } | ||
155 | static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) | ||
156 | { | ||
157 | return 0x0U; | ||
158 | } | ||
159 | static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) | ||
160 | { | ||
161 | return 0x2U; | ||
162 | } | ||
163 | static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) | ||
164 | { | ||
165 | return 0x4U; | ||
166 | } | ||
167 | static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) | ||
168 | { | ||
169 | return 0x6U; | ||
170 | } | ||
171 | static inline u32 gmmu_new_dual_pde_vol_small_w(void) | ||
172 | { | ||
173 | return 2U; | ||
174 | } | ||
175 | static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) | ||
176 | { | ||
177 | return 0x8U; | ||
178 | } | ||
179 | static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) | ||
180 | { | ||
181 | return 0x0U; | ||
182 | } | ||
183 | static inline u32 gmmu_new_dual_pde_vol_big_w(void) | ||
184 | { | ||
185 | return 0U; | ||
186 | } | ||
187 | static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) | ||
188 | { | ||
189 | return 0x8U; | ||
190 | } | ||
191 | static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) | ||
192 | { | ||
193 | return 0x0U; | ||
194 | } | ||
195 | static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) | ||
196 | { | ||
197 | return (v & 0xffffffU) << 8U; | ||
198 | } | ||
199 | static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) | ||
200 | { | ||
201 | return 2U; | ||
202 | } | ||
203 | static inline u32 gmmu_new_dual_pde_address_shift_v(void) | ||
204 | { | ||
205 | return 0x0000000cU; | ||
206 | } | ||
207 | static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) | ||
208 | { | ||
209 | return 0x00000008U; | ||
210 | } | ||
211 | static inline u32 gmmu_new_dual_pde__size_v(void) | ||
212 | { | ||
213 | return 0x00000010U; | ||
214 | } | ||
215 | static inline u32 gmmu_new_pte__size_v(void) | ||
216 | { | ||
217 | return 0x00000008U; | ||
218 | } | ||
219 | static inline u32 gmmu_new_pte_valid_w(void) | ||
220 | { | ||
221 | return 0U; | ||
222 | } | ||
223 | static inline u32 gmmu_new_pte_valid_true_f(void) | ||
224 | { | ||
225 | return 0x1U; | ||
226 | } | ||
227 | static inline u32 gmmu_new_pte_valid_false_f(void) | ||
228 | { | ||
229 | return 0x0U; | ||
230 | } | ||
231 | static inline u32 gmmu_new_pte_privilege_w(void) | ||
232 | { | ||
233 | return 0U; | ||
234 | } | ||
235 | static inline u32 gmmu_new_pte_privilege_true_f(void) | ||
236 | { | ||
237 | return 0x20U; | ||
238 | } | ||
239 | static inline u32 gmmu_new_pte_privilege_false_f(void) | ||
240 | { | ||
241 | return 0x0U; | ||
242 | } | ||
243 | static inline u32 gmmu_new_pte_address_sys_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xffffffU) << 8U; | ||
246 | } | ||
247 | static inline u32 gmmu_new_pte_address_sys_w(void) | ||
248 | { | ||
249 | return 0U; | ||
250 | } | ||
251 | static inline u32 gmmu_new_pte_address_vid_f(u32 v) | ||
252 | { | ||
253 | return (v & 0xffffffU) << 8U; | ||
254 | } | ||
255 | static inline u32 gmmu_new_pte_address_vid_w(void) | ||
256 | { | ||
257 | return 0U; | ||
258 | } | ||
259 | static inline u32 gmmu_new_pte_vol_w(void) | ||
260 | { | ||
261 | return 0U; | ||
262 | } | ||
263 | static inline u32 gmmu_new_pte_vol_true_f(void) | ||
264 | { | ||
265 | return 0x8U; | ||
266 | } | ||
267 | static inline u32 gmmu_new_pte_vol_false_f(void) | ||
268 | { | ||
269 | return 0x0U; | ||
270 | } | ||
271 | static inline u32 gmmu_new_pte_aperture_w(void) | ||
272 | { | ||
273 | return 0U; | ||
274 | } | ||
275 | static inline u32 gmmu_new_pte_aperture_video_memory_f(void) | ||
276 | { | ||
277 | return 0x0U; | ||
278 | } | ||
279 | static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) | ||
280 | { | ||
281 | return 0x4U; | ||
282 | } | ||
283 | static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) | ||
284 | { | ||
285 | return 0x6U; | ||
286 | } | ||
287 | static inline u32 gmmu_new_pte_read_only_w(void) | ||
288 | { | ||
289 | return 0U; | ||
290 | } | ||
291 | static inline u32 gmmu_new_pte_read_only_true_f(void) | ||
292 | { | ||
293 | return 0x40U; | ||
294 | } | ||
295 | static inline u32 gmmu_new_pte_comptagline_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x3ffffU) << 4U; | ||
298 | } | ||
299 | static inline u32 gmmu_new_pte_comptagline_w(void) | ||
300 | { | ||
301 | return 1U; | ||
302 | } | ||
303 | static inline u32 gmmu_new_pte_kind_f(u32 v) | ||
304 | { | ||
305 | return (v & 0xffU) << 24U; | ||
306 | } | ||
307 | static inline u32 gmmu_new_pte_kind_w(void) | ||
308 | { | ||
309 | return 1U; | ||
310 | } | ||
311 | static inline u32 gmmu_new_pte_address_shift_v(void) | ||
312 | { | ||
313 | return 0x0000000cU; | ||
314 | } | ||
315 | static inline u32 gmmu_pte_kind_f(u32 v) | ||
316 | { | ||
317 | return (v & 0xffU) << 4U; | ||
318 | } | ||
319 | static inline u32 gmmu_pte_kind_w(void) | ||
320 | { | ||
321 | return 1U; | ||
322 | } | ||
323 | static inline u32 gmmu_pte_kind_invalid_v(void) | ||
324 | { | ||
325 | return 0x000000ffU; | ||
326 | } | ||
327 | static inline u32 gmmu_pte_kind_pitch_v(void) | ||
328 | { | ||
329 | return 0x00000000U; | ||
330 | } | ||
331 | static inline u32 gmmu_pte_kind_z16_v(void) | ||
332 | { | ||
333 | return 0x00000001U; | ||
334 | } | ||
335 | static inline u32 gmmu_pte_kind_z16_2c_v(void) | ||
336 | { | ||
337 | return 0x00000002U; | ||
338 | } | ||
339 | static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) | ||
340 | { | ||
341 | return 0x00000003U; | ||
342 | } | ||
343 | static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) | ||
344 | { | ||
345 | return 0x00000004U; | ||
346 | } | ||
347 | static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) | ||
348 | { | ||
349 | return 0x00000005U; | ||
350 | } | ||
351 | static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) | ||
352 | { | ||
353 | return 0x00000006U; | ||
354 | } | ||
355 | static inline u32 gmmu_pte_kind_z16_2z_v(void) | ||
356 | { | ||
357 | return 0x00000007U; | ||
358 | } | ||
359 | static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) | ||
360 | { | ||
361 | return 0x00000008U; | ||
362 | } | ||
363 | static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) | ||
364 | { | ||
365 | return 0x00000009U; | ||
366 | } | ||
367 | static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) | ||
368 | { | ||
369 | return 0x0000000aU; | ||
370 | } | ||
371 | static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) | ||
372 | { | ||
373 | return 0x0000000bU; | ||
374 | } | ||
375 | static inline u32 gmmu_pte_kind_z16_2cz_v(void) | ||
376 | { | ||
377 | return 0x00000036U; | ||
378 | } | ||
379 | static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) | ||
380 | { | ||
381 | return 0x00000037U; | ||
382 | } | ||
383 | static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) | ||
384 | { | ||
385 | return 0x00000038U; | ||
386 | } | ||
387 | static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) | ||
388 | { | ||
389 | return 0x00000039U; | ||
390 | } | ||
391 | static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) | ||
392 | { | ||
393 | return 0x0000005fU; | ||
394 | } | ||
395 | static inline u32 gmmu_pte_kind_s8z24_v(void) | ||
396 | { | ||
397 | return 0x00000011U; | ||
398 | } | ||
399 | static inline u32 gmmu_pte_kind_s8z24_1z_v(void) | ||
400 | { | ||
401 | return 0x00000012U; | ||
402 | } | ||
403 | static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) | ||
404 | { | ||
405 | return 0x00000013U; | ||
406 | } | ||
407 | static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) | ||
408 | { | ||
409 | return 0x00000014U; | ||
410 | } | ||
411 | static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) | ||
412 | { | ||
413 | return 0x00000015U; | ||
414 | } | ||
415 | static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) | ||
416 | { | ||
417 | return 0x00000016U; | ||
418 | } | ||
419 | static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) | ||
420 | { | ||
421 | return 0x00000017U; | ||
422 | } | ||
423 | static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) | ||
424 | { | ||
425 | return 0x00000018U; | ||
426 | } | ||
427 | static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) | ||
428 | { | ||
429 | return 0x00000019U; | ||
430 | } | ||
431 | static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) | ||
432 | { | ||
433 | return 0x0000001aU; | ||
434 | } | ||
435 | static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) | ||
436 | { | ||
437 | return 0x0000001bU; | ||
438 | } | ||
439 | static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) | ||
440 | { | ||
441 | return 0x0000001cU; | ||
442 | } | ||
443 | static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) | ||
444 | { | ||
445 | return 0x0000001dU; | ||
446 | } | ||
447 | static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) | ||
448 | { | ||
449 | return 0x0000001eU; | ||
450 | } | ||
451 | static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) | ||
452 | { | ||
453 | return 0x0000001fU; | ||
454 | } | ||
455 | static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) | ||
456 | { | ||
457 | return 0x00000020U; | ||
458 | } | ||
459 | static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) | ||
460 | { | ||
461 | return 0x00000021U; | ||
462 | } | ||
463 | static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) | ||
464 | { | ||
465 | return 0x00000022U; | ||
466 | } | ||
467 | static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) | ||
468 | { | ||
469 | return 0x00000023U; | ||
470 | } | ||
471 | static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) | ||
472 | { | ||
473 | return 0x00000024U; | ||
474 | } | ||
475 | static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) | ||
476 | { | ||
477 | return 0x00000025U; | ||
478 | } | ||
479 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) | ||
480 | { | ||
481 | return 0x00000026U; | ||
482 | } | ||
483 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) | ||
484 | { | ||
485 | return 0x00000027U; | ||
486 | } | ||
487 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) | ||
488 | { | ||
489 | return 0x00000028U; | ||
490 | } | ||
491 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) | ||
492 | { | ||
493 | return 0x00000029U; | ||
494 | } | ||
495 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) | ||
496 | { | ||
497 | return 0x0000002eU; | ||
498 | } | ||
499 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) | ||
500 | { | ||
501 | return 0x0000002fU; | ||
502 | } | ||
503 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) | ||
504 | { | ||
505 | return 0x00000030U; | ||
506 | } | ||
507 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) | ||
508 | { | ||
509 | return 0x00000031U; | ||
510 | } | ||
511 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) | ||
512 | { | ||
513 | return 0x00000032U; | ||
514 | } | ||
515 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) | ||
516 | { | ||
517 | return 0x00000033U; | ||
518 | } | ||
519 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) | ||
520 | { | ||
521 | return 0x00000034U; | ||
522 | } | ||
523 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) | ||
524 | { | ||
525 | return 0x00000035U; | ||
526 | } | ||
527 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) | ||
528 | { | ||
529 | return 0x0000003aU; | ||
530 | } | ||
531 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) | ||
532 | { | ||
533 | return 0x0000003bU; | ||
534 | } | ||
535 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) | ||
536 | { | ||
537 | return 0x0000003cU; | ||
538 | } | ||
539 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) | ||
540 | { | ||
541 | return 0x0000003dU; | ||
542 | } | ||
543 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) | ||
544 | { | ||
545 | return 0x0000003eU; | ||
546 | } | ||
547 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) | ||
548 | { | ||
549 | return 0x0000003fU; | ||
550 | } | ||
551 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) | ||
552 | { | ||
553 | return 0x00000040U; | ||
554 | } | ||
555 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) | ||
556 | { | ||
557 | return 0x00000041U; | ||
558 | } | ||
559 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) | ||
560 | { | ||
561 | return 0x00000042U; | ||
562 | } | ||
563 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) | ||
564 | { | ||
565 | return 0x00000043U; | ||
566 | } | ||
567 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) | ||
568 | { | ||
569 | return 0x00000044U; | ||
570 | } | ||
571 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) | ||
572 | { | ||
573 | return 0x00000045U; | ||
574 | } | ||
575 | static inline u32 gmmu_pte_kind_z24s8_v(void) | ||
576 | { | ||
577 | return 0x00000046U; | ||
578 | } | ||
579 | static inline u32 gmmu_pte_kind_z24s8_1z_v(void) | ||
580 | { | ||
581 | return 0x00000047U; | ||
582 | } | ||
583 | static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) | ||
584 | { | ||
585 | return 0x00000048U; | ||
586 | } | ||
587 | static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) | ||
588 | { | ||
589 | return 0x00000049U; | ||
590 | } | ||
591 | static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) | ||
592 | { | ||
593 | return 0x0000004aU; | ||
594 | } | ||
595 | static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) | ||
596 | { | ||
597 | return 0x0000004bU; | ||
598 | } | ||
599 | static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) | ||
600 | { | ||
601 | return 0x0000004cU; | ||
602 | } | ||
603 | static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) | ||
604 | { | ||
605 | return 0x0000004dU; | ||
606 | } | ||
607 | static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) | ||
608 | { | ||
609 | return 0x0000004eU; | ||
610 | } | ||
611 | static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) | ||
612 | { | ||
613 | return 0x0000004fU; | ||
614 | } | ||
615 | static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) | ||
616 | { | ||
617 | return 0x00000050U; | ||
618 | } | ||
619 | static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) | ||
620 | { | ||
621 | return 0x00000051U; | ||
622 | } | ||
623 | static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) | ||
624 | { | ||
625 | return 0x00000052U; | ||
626 | } | ||
627 | static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) | ||
628 | { | ||
629 | return 0x00000053U; | ||
630 | } | ||
631 | static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) | ||
632 | { | ||
633 | return 0x00000054U; | ||
634 | } | ||
635 | static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) | ||
636 | { | ||
637 | return 0x00000055U; | ||
638 | } | ||
639 | static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) | ||
640 | { | ||
641 | return 0x00000056U; | ||
642 | } | ||
643 | static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) | ||
644 | { | ||
645 | return 0x00000057U; | ||
646 | } | ||
647 | static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) | ||
648 | { | ||
649 | return 0x00000058U; | ||
650 | } | ||
651 | static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) | ||
652 | { | ||
653 | return 0x00000059U; | ||
654 | } | ||
655 | static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) | ||
656 | { | ||
657 | return 0x0000005aU; | ||
658 | } | ||
659 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) | ||
660 | { | ||
661 | return 0x0000005bU; | ||
662 | } | ||
663 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) | ||
664 | { | ||
665 | return 0x0000005cU; | ||
666 | } | ||
667 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) | ||
668 | { | ||
669 | return 0x0000005dU; | ||
670 | } | ||
671 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) | ||
672 | { | ||
673 | return 0x0000005eU; | ||
674 | } | ||
675 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) | ||
676 | { | ||
677 | return 0x00000063U; | ||
678 | } | ||
679 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) | ||
680 | { | ||
681 | return 0x00000064U; | ||
682 | } | ||
683 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) | ||
684 | { | ||
685 | return 0x00000065U; | ||
686 | } | ||
687 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) | ||
688 | { | ||
689 | return 0x00000066U; | ||
690 | } | ||
691 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) | ||
692 | { | ||
693 | return 0x00000067U; | ||
694 | } | ||
695 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) | ||
696 | { | ||
697 | return 0x00000068U; | ||
698 | } | ||
699 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) | ||
700 | { | ||
701 | return 0x00000069U; | ||
702 | } | ||
703 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) | ||
704 | { | ||
705 | return 0x0000006aU; | ||
706 | } | ||
707 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) | ||
708 | { | ||
709 | return 0x0000006fU; | ||
710 | } | ||
711 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) | ||
712 | { | ||
713 | return 0x00000070U; | ||
714 | } | ||
715 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) | ||
716 | { | ||
717 | return 0x00000071U; | ||
718 | } | ||
719 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) | ||
720 | { | ||
721 | return 0x00000072U; | ||
722 | } | ||
723 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) | ||
724 | { | ||
725 | return 0x00000073U; | ||
726 | } | ||
727 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) | ||
728 | { | ||
729 | return 0x00000074U; | ||
730 | } | ||
731 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) | ||
732 | { | ||
733 | return 0x00000075U; | ||
734 | } | ||
735 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) | ||
736 | { | ||
737 | return 0x00000076U; | ||
738 | } | ||
739 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) | ||
740 | { | ||
741 | return 0x00000077U; | ||
742 | } | ||
743 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) | ||
744 | { | ||
745 | return 0x00000078U; | ||
746 | } | ||
747 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) | ||
748 | { | ||
749 | return 0x00000079U; | ||
750 | } | ||
751 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) | ||
752 | { | ||
753 | return 0x0000007aU; | ||
754 | } | ||
755 | static inline u32 gmmu_pte_kind_zf32_v(void) | ||
756 | { | ||
757 | return 0x0000007bU; | ||
758 | } | ||
759 | static inline u32 gmmu_pte_kind_zf32_1z_v(void) | ||
760 | { | ||
761 | return 0x0000007cU; | ||
762 | } | ||
763 | static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) | ||
764 | { | ||
765 | return 0x0000007dU; | ||
766 | } | ||
767 | static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) | ||
768 | { | ||
769 | return 0x0000007eU; | ||
770 | } | ||
771 | static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) | ||
772 | { | ||
773 | return 0x0000007fU; | ||
774 | } | ||
775 | static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) | ||
776 | { | ||
777 | return 0x00000080U; | ||
778 | } | ||
779 | static inline u32 gmmu_pte_kind_zf32_2cs_v(void) | ||
780 | { | ||
781 | return 0x00000081U; | ||
782 | } | ||
783 | static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) | ||
784 | { | ||
785 | return 0x00000082U; | ||
786 | } | ||
787 | static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) | ||
788 | { | ||
789 | return 0x00000083U; | ||
790 | } | ||
791 | static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) | ||
792 | { | ||
793 | return 0x00000084U; | ||
794 | } | ||
795 | static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) | ||
796 | { | ||
797 | return 0x00000085U; | ||
798 | } | ||
799 | static inline u32 gmmu_pte_kind_zf32_2cz_v(void) | ||
800 | { | ||
801 | return 0x00000086U; | ||
802 | } | ||
803 | static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) | ||
804 | { | ||
805 | return 0x00000087U; | ||
806 | } | ||
807 | static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) | ||
808 | { | ||
809 | return 0x00000088U; | ||
810 | } | ||
811 | static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) | ||
812 | { | ||
813 | return 0x00000089U; | ||
814 | } | ||
815 | static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) | ||
816 | { | ||
817 | return 0x0000008aU; | ||
818 | } | ||
819 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) | ||
820 | { | ||
821 | return 0x0000008bU; | ||
822 | } | ||
823 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) | ||
824 | { | ||
825 | return 0x0000008cU; | ||
826 | } | ||
827 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) | ||
828 | { | ||
829 | return 0x0000008dU; | ||
830 | } | ||
831 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) | ||
832 | { | ||
833 | return 0x0000008eU; | ||
834 | } | ||
835 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) | ||
836 | { | ||
837 | return 0x0000008fU; | ||
838 | } | ||
839 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) | ||
840 | { | ||
841 | return 0x00000090U; | ||
842 | } | ||
843 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) | ||
844 | { | ||
845 | return 0x00000091U; | ||
846 | } | ||
847 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) | ||
848 | { | ||
849 | return 0x00000092U; | ||
850 | } | ||
851 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) | ||
852 | { | ||
853 | return 0x00000097U; | ||
854 | } | ||
855 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) | ||
856 | { | ||
857 | return 0x00000098U; | ||
858 | } | ||
859 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) | ||
860 | { | ||
861 | return 0x00000099U; | ||
862 | } | ||
863 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) | ||
864 | { | ||
865 | return 0x0000009aU; | ||
866 | } | ||
867 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) | ||
868 | { | ||
869 | return 0x0000009bU; | ||
870 | } | ||
871 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) | ||
872 | { | ||
873 | return 0x0000009cU; | ||
874 | } | ||
875 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) | ||
876 | { | ||
877 | return 0x0000009dU; | ||
878 | } | ||
879 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) | ||
880 | { | ||
881 | return 0x0000009eU; | ||
882 | } | ||
883 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) | ||
884 | { | ||
885 | return 0x0000009fU; | ||
886 | } | ||
887 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) | ||
888 | { | ||
889 | return 0x000000a0U; | ||
890 | } | ||
891 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) | ||
892 | { | ||
893 | return 0x000000a1U; | ||
894 | } | ||
895 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) | ||
896 | { | ||
897 | return 0x000000a2U; | ||
898 | } | ||
899 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) | ||
900 | { | ||
901 | return 0x000000a3U; | ||
902 | } | ||
903 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) | ||
904 | { | ||
905 | return 0x000000a4U; | ||
906 | } | ||
907 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) | ||
908 | { | ||
909 | return 0x000000a5U; | ||
910 | } | ||
911 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) | ||
912 | { | ||
913 | return 0x000000a6U; | ||
914 | } | ||
915 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) | ||
916 | { | ||
917 | return 0x000000a7U; | ||
918 | } | ||
919 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) | ||
920 | { | ||
921 | return 0x000000a8U; | ||
922 | } | ||
923 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) | ||
924 | { | ||
925 | return 0x000000a9U; | ||
926 | } | ||
927 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) | ||
928 | { | ||
929 | return 0x000000aaU; | ||
930 | } | ||
931 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) | ||
932 | { | ||
933 | return 0x000000abU; | ||
934 | } | ||
935 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) | ||
936 | { | ||
937 | return 0x000000acU; | ||
938 | } | ||
939 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) | ||
940 | { | ||
941 | return 0x000000adU; | ||
942 | } | ||
943 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) | ||
944 | { | ||
945 | return 0x000000aeU; | ||
946 | } | ||
947 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) | ||
948 | { | ||
949 | return 0x000000b3U; | ||
950 | } | ||
951 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) | ||
952 | { | ||
953 | return 0x000000b4U; | ||
954 | } | ||
955 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) | ||
956 | { | ||
957 | return 0x000000b5U; | ||
958 | } | ||
959 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) | ||
960 | { | ||
961 | return 0x000000b6U; | ||
962 | } | ||
963 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) | ||
964 | { | ||
965 | return 0x000000b7U; | ||
966 | } | ||
967 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) | ||
968 | { | ||
969 | return 0x000000b8U; | ||
970 | } | ||
971 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) | ||
972 | { | ||
973 | return 0x000000b9U; | ||
974 | } | ||
975 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) | ||
976 | { | ||
977 | return 0x000000baU; | ||
978 | } | ||
979 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) | ||
980 | { | ||
981 | return 0x000000bbU; | ||
982 | } | ||
983 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) | ||
984 | { | ||
985 | return 0x000000bcU; | ||
986 | } | ||
987 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) | ||
988 | { | ||
989 | return 0x000000bdU; | ||
990 | } | ||
991 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) | ||
992 | { | ||
993 | return 0x000000beU; | ||
994 | } | ||
995 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) | ||
996 | { | ||
997 | return 0x000000bfU; | ||
998 | } | ||
999 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) | ||
1000 | { | ||
1001 | return 0x000000c0U; | ||
1002 | } | ||
1003 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) | ||
1004 | { | ||
1005 | return 0x000000c1U; | ||
1006 | } | ||
1007 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) | ||
1008 | { | ||
1009 | return 0x000000c2U; | ||
1010 | } | ||
1011 | static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) | ||
1012 | { | ||
1013 | return 0x000000c3U; | ||
1014 | } | ||
1015 | static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) | ||
1016 | { | ||
1017 | return 0x000000c4U; | ||
1018 | } | ||
1019 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) | ||
1020 | { | ||
1021 | return 0x000000c5U; | ||
1022 | } | ||
1023 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) | ||
1024 | { | ||
1025 | return 0x000000c6U; | ||
1026 | } | ||
1027 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) | ||
1028 | { | ||
1029 | return 0x000000c7U; | ||
1030 | } | ||
1031 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) | ||
1032 | { | ||
1033 | return 0x000000c8U; | ||
1034 | } | ||
1035 | static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) | ||
1036 | { | ||
1037 | return 0x000000ceU; | ||
1038 | } | ||
1039 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) | ||
1040 | { | ||
1041 | return 0x000000cfU; | ||
1042 | } | ||
1043 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) | ||
1044 | { | ||
1045 | return 0x000000d0U; | ||
1046 | } | ||
1047 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) | ||
1048 | { | ||
1049 | return 0x000000d1U; | ||
1050 | } | ||
1051 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) | ||
1052 | { | ||
1053 | return 0x000000d2U; | ||
1054 | } | ||
1055 | static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) | ||
1056 | { | ||
1057 | return 0x000000d3U; | ||
1058 | } | ||
1059 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) | ||
1060 | { | ||
1061 | return 0x000000d4U; | ||
1062 | } | ||
1063 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) | ||
1064 | { | ||
1065 | return 0x000000d5U; | ||
1066 | } | ||
1067 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) | ||
1068 | { | ||
1069 | return 0x000000d6U; | ||
1070 | } | ||
1071 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) | ||
1072 | { | ||
1073 | return 0x000000d7U; | ||
1074 | } | ||
1075 | static inline u32 gmmu_pte_kind_generic_16bx2_v(void) | ||
1076 | { | ||
1077 | return 0x000000feU; | ||
1078 | } | ||
1079 | static inline u32 gmmu_pte_kind_c32_2c_v(void) | ||
1080 | { | ||
1081 | return 0x000000d8U; | ||
1082 | } | ||
1083 | static inline u32 gmmu_pte_kind_c32_2cbr_v(void) | ||
1084 | { | ||
1085 | return 0x000000d9U; | ||
1086 | } | ||
1087 | static inline u32 gmmu_pte_kind_c32_2cba_v(void) | ||
1088 | { | ||
1089 | return 0x000000daU; | ||
1090 | } | ||
1091 | static inline u32 gmmu_pte_kind_c32_2cra_v(void) | ||
1092 | { | ||
1093 | return 0x000000dbU; | ||
1094 | } | ||
1095 | static inline u32 gmmu_pte_kind_c32_2bra_v(void) | ||
1096 | { | ||
1097 | return 0x000000dcU; | ||
1098 | } | ||
1099 | static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) | ||
1100 | { | ||
1101 | return 0x000000ddU; | ||
1102 | } | ||
1103 | static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) | ||
1104 | { | ||
1105 | return 0x000000deU; | ||
1106 | } | ||
1107 | static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) | ||
1108 | { | ||
1109 | return 0x000000ccU; | ||
1110 | } | ||
1111 | static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) | ||
1112 | { | ||
1113 | return 0x000000dfU; | ||
1114 | } | ||
1115 | static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) | ||
1116 | { | ||
1117 | return 0x000000e0U; | ||
1118 | } | ||
1119 | static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) | ||
1120 | { | ||
1121 | return 0x000000e1U; | ||
1122 | } | ||
1123 | static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) | ||
1124 | { | ||
1125 | return 0x000000e2U; | ||
1126 | } | ||
1127 | static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) | ||
1128 | { | ||
1129 | return 0x000000e3U; | ||
1130 | } | ||
1131 | static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) | ||
1132 | { | ||
1133 | return 0x0000002cU; | ||
1134 | } | ||
1135 | static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) | ||
1136 | { | ||
1137 | return 0x000000e4U; | ||
1138 | } | ||
1139 | static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) | ||
1140 | { | ||
1141 | return 0x000000e5U; | ||
1142 | } | ||
1143 | static inline u32 gmmu_pte_kind_c64_2c_v(void) | ||
1144 | { | ||
1145 | return 0x000000e6U; | ||
1146 | } | ||
1147 | static inline u32 gmmu_pte_kind_c64_2cbr_v(void) | ||
1148 | { | ||
1149 | return 0x000000e7U; | ||
1150 | } | ||
1151 | static inline u32 gmmu_pte_kind_c64_2cba_v(void) | ||
1152 | { | ||
1153 | return 0x000000e8U; | ||
1154 | } | ||
1155 | static inline u32 gmmu_pte_kind_c64_2cra_v(void) | ||
1156 | { | ||
1157 | return 0x000000e9U; | ||
1158 | } | ||
1159 | static inline u32 gmmu_pte_kind_c64_2bra_v(void) | ||
1160 | { | ||
1161 | return 0x000000eaU; | ||
1162 | } | ||
1163 | static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) | ||
1164 | { | ||
1165 | return 0x000000ebU; | ||
1166 | } | ||
1167 | static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) | ||
1168 | { | ||
1169 | return 0x000000ecU; | ||
1170 | } | ||
1171 | static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) | ||
1172 | { | ||
1173 | return 0x000000cdU; | ||
1174 | } | ||
1175 | static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) | ||
1176 | { | ||
1177 | return 0x000000edU; | ||
1178 | } | ||
1179 | static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) | ||
1180 | { | ||
1181 | return 0x000000eeU; | ||
1182 | } | ||
1183 | static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) | ||
1184 | { | ||
1185 | return 0x000000efU; | ||
1186 | } | ||
1187 | static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) | ||
1188 | { | ||
1189 | return 0x000000f0U; | ||
1190 | } | ||
1191 | static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) | ||
1192 | { | ||
1193 | return 0x000000f1U; | ||
1194 | } | ||
1195 | static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) | ||
1196 | { | ||
1197 | return 0x0000002dU; | ||
1198 | } | ||
1199 | static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) | ||
1200 | { | ||
1201 | return 0x000000f2U; | ||
1202 | } | ||
1203 | static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) | ||
1204 | { | ||
1205 | return 0x000000f3U; | ||
1206 | } | ||
1207 | static inline u32 gmmu_pte_kind_c128_2c_v(void) | ||
1208 | { | ||
1209 | return 0x000000f4U; | ||
1210 | } | ||
1211 | static inline u32 gmmu_pte_kind_c128_2cr_v(void) | ||
1212 | { | ||
1213 | return 0x000000f5U; | ||
1214 | } | ||
1215 | static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) | ||
1216 | { | ||
1217 | return 0x000000f6U; | ||
1218 | } | ||
1219 | static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) | ||
1220 | { | ||
1221 | return 0x000000f7U; | ||
1222 | } | ||
1223 | static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) | ||
1224 | { | ||
1225 | return 0x000000f8U; | ||
1226 | } | ||
1227 | static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) | ||
1228 | { | ||
1229 | return 0x000000f9U; | ||
1230 | } | ||
1231 | static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) | ||
1232 | { | ||
1233 | return 0x000000faU; | ||
1234 | } | ||
1235 | static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) | ||
1236 | { | ||
1237 | return 0x000000fbU; | ||
1238 | } | ||
1239 | static inline u32 gmmu_pte_kind_x8c24_v(void) | ||
1240 | { | ||
1241 | return 0x000000fcU; | ||
1242 | } | ||
1243 | static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) | ||
1244 | { | ||
1245 | return 0x000000fdU; | ||
1246 | } | ||
1247 | static inline u32 gmmu_pte_kind_smsked_message_v(void) | ||
1248 | { | ||
1249 | return 0x000000caU; | ||
1250 | } | ||
1251 | static inline u32 gmmu_pte_kind_smhost_message_v(void) | ||
1252 | { | ||
1253 | return 0x000000cbU; | ||
1254 | } | ||
1255 | static inline u32 gmmu_pte_kind_s8_v(void) | ||
1256 | { | ||
1257 | return 0x0000002aU; | ||
1258 | } | ||
1259 | static inline u32 gmmu_pte_kind_s8_2s_v(void) | ||
1260 | { | ||
1261 | return 0x0000002bU; | ||
1262 | } | ||
1263 | static inline u32 gmmu_fault_client_type_gpc_v(void) | ||
1264 | { | ||
1265 | return 0x00000000U; | ||
1266 | } | ||
1267 | static inline u32 gmmu_fault_client_type_hub_v(void) | ||
1268 | { | ||
1269 | return 0x00000001U; | ||
1270 | } | ||
1271 | static inline u32 gmmu_fault_type_unbound_inst_block_v(void) | ||
1272 | { | ||
1273 | return 0x00000004U; | ||
1274 | } | ||
1275 | static inline u32 gmmu_fault_type_pte_v(void) | ||
1276 | { | ||
1277 | return 0x00000002U; | ||
1278 | } | ||
1279 | static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) | ||
1280 | { | ||
1281 | return 0x00000005U; | ||
1282 | } | ||
1283 | static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) | ||
1284 | { | ||
1285 | return 0x0000001fU; | ||
1286 | } | ||
1287 | static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) | ||
1288 | { | ||
1289 | return 0x0000000fU; | ||
1290 | } | ||
1291 | static inline u32 gmmu_fault_buf_size_v(void) | ||
1292 | { | ||
1293 | return 0x00000020U; | ||
1294 | } | ||
1295 | static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) | ||
1296 | { | ||
1297 | return (r >> 8U) & 0x3U; | ||
1298 | } | ||
1299 | static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) | ||
1300 | { | ||
1301 | return 0U; | ||
1302 | } | ||
1303 | static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) | ||
1304 | { | ||
1305 | return 0x00000000U; | ||
1306 | } | ||
1307 | static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) | ||
1308 | { | ||
1309 | return 0x00000002U; | ||
1310 | } | ||
1311 | static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) | ||
1312 | { | ||
1313 | return 0x00000003U; | ||
1314 | } | ||
1315 | static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) | ||
1316 | { | ||
1317 | return (v & 0xfffffU) << 12U; | ||
1318 | } | ||
1319 | static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) | ||
1320 | { | ||
1321 | return (r >> 12U) & 0xfffffU; | ||
1322 | } | ||
1323 | static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) | ||
1324 | { | ||
1325 | return 0U; | ||
1326 | } | ||
1327 | static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) | ||
1328 | { | ||
1329 | return (r >> 0U) & 0xffffffffU; | ||
1330 | } | ||
1331 | static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) | ||
1332 | { | ||
1333 | return 1U; | ||
1334 | } | ||
1335 | static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) | ||
1336 | { | ||
1337 | return (r >> 0U) & 0x3U; | ||
1338 | } | ||
1339 | static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) | ||
1340 | { | ||
1341 | return 2U; | ||
1342 | } | ||
1343 | static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) | ||
1344 | { | ||
1345 | return (v & 0xfffffU) << 12U; | ||
1346 | } | ||
1347 | static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) | ||
1348 | { | ||
1349 | return (r >> 12U) & 0xfffffU; | ||
1350 | } | ||
1351 | static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) | ||
1352 | { | ||
1353 | return 2U; | ||
1354 | } | ||
1355 | static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) | ||
1356 | { | ||
1357 | return (r >> 0U) & 0xffffffffU; | ||
1358 | } | ||
1359 | static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) | ||
1360 | { | ||
1361 | return 3U; | ||
1362 | } | ||
1363 | static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) | ||
1364 | { | ||
1365 | return (r >> 0U) & 0xffffffffU; | ||
1366 | } | ||
1367 | static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) | ||
1368 | { | ||
1369 | return 4U; | ||
1370 | } | ||
1371 | static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) | ||
1372 | { | ||
1373 | return (r >> 0U) & 0xffffffffU; | ||
1374 | } | ||
1375 | static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) | ||
1376 | { | ||
1377 | return 5U; | ||
1378 | } | ||
1379 | static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) | ||
1380 | { | ||
1381 | return (r >> 0U) & 0x1ffU; | ||
1382 | } | ||
1383 | static inline u32 gmmu_fault_buf_entry_engine_id_w(void) | ||
1384 | { | ||
1385 | return 6U; | ||
1386 | } | ||
1387 | static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) | ||
1388 | { | ||
1389 | return (r >> 0U) & 0x1fU; | ||
1390 | } | ||
1391 | static inline u32 gmmu_fault_buf_entry_fault_type_w(void) | ||
1392 | { | ||
1393 | return 7U; | ||
1394 | } | ||
1395 | static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) | ||
1396 | { | ||
1397 | return (r >> 7U) & 0x1U; | ||
1398 | } | ||
1399 | static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) | ||
1400 | { | ||
1401 | return 7U; | ||
1402 | } | ||
1403 | static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) | ||
1404 | { | ||
1405 | return 0x00000001U; | ||
1406 | } | ||
1407 | static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) | ||
1408 | { | ||
1409 | return 0x80U; | ||
1410 | } | ||
1411 | static inline u32 gmmu_fault_buf_entry_client_v(u32 r) | ||
1412 | { | ||
1413 | return (r >> 8U) & 0x7fU; | ||
1414 | } | ||
1415 | static inline u32 gmmu_fault_buf_entry_client_w(void) | ||
1416 | { | ||
1417 | return 7U; | ||
1418 | } | ||
1419 | static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) | ||
1420 | { | ||
1421 | return (r >> 16U) & 0xfU; | ||
1422 | } | ||
1423 | static inline u32 gmmu_fault_buf_entry_access_type_w(void) | ||
1424 | { | ||
1425 | return 7U; | ||
1426 | } | ||
1427 | static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) | ||
1428 | { | ||
1429 | return (r >> 20U) & 0x1U; | ||
1430 | } | ||
1431 | static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) | ||
1432 | { | ||
1433 | return 7U; | ||
1434 | } | ||
1435 | static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) | ||
1436 | { | ||
1437 | return (r >> 24U) & 0x1fU; | ||
1438 | } | ||
1439 | static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) | ||
1440 | { | ||
1441 | return 7U; | ||
1442 | } | ||
1443 | static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) | ||
1444 | { | ||
1445 | return (r >> 29U) & 0x1U; | ||
1446 | } | ||
1447 | static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) | ||
1448 | { | ||
1449 | return 7U; | ||
1450 | } | ||
1451 | static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) | ||
1452 | { | ||
1453 | return 0x00000001U; | ||
1454 | } | ||
1455 | static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) | ||
1456 | { | ||
1457 | return 0x20000000U; | ||
1458 | } | ||
1459 | static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) | ||
1460 | { | ||
1461 | return (r >> 30U) & 0x1U; | ||
1462 | } | ||
1463 | static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) | ||
1464 | { | ||
1465 | return 7U; | ||
1466 | } | ||
1467 | static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) | ||
1468 | { | ||
1469 | return 0x00000001U; | ||
1470 | } | ||
1471 | static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) | ||
1472 | { | ||
1473 | return 0x40000000U; | ||
1474 | } | ||
1475 | static inline u32 gmmu_fault_buf_entry_valid_m(void) | ||
1476 | { | ||
1477 | return 0x1U << 31U; | ||
1478 | } | ||
1479 | static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) | ||
1480 | { | ||
1481 | return (r >> 31U) & 0x1U; | ||
1482 | } | ||
1483 | static inline u32 gmmu_fault_buf_entry_valid_w(void) | ||
1484 | { | ||
1485 | return 7U; | ||
1486 | } | ||
1487 | static inline u32 gmmu_fault_buf_entry_valid_true_v(void) | ||
1488 | { | ||
1489 | return 0x00000001U; | ||
1490 | } | ||
1491 | static inline u32 gmmu_fault_buf_entry_valid_true_f(void) | ||
1492 | { | ||
1493 | return 0x80000000U; | ||
1494 | } | ||
1495 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h new file mode 100644 index 00000000..692b7ba3 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -0,0 +1,4939 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_gr_gv11b_h_ | ||
57 | #define _hw_gr_gv11b_h_ | ||
58 | |||
59 | static inline u32 gr_intr_r(void) | ||
60 | { | ||
61 | return 0x00400100U; | ||
62 | } | ||
63 | static inline u32 gr_intr_notify_pending_f(void) | ||
64 | { | ||
65 | return 0x1U; | ||
66 | } | ||
67 | static inline u32 gr_intr_notify_reset_f(void) | ||
68 | { | ||
69 | return 0x1U; | ||
70 | } | ||
71 | static inline u32 gr_intr_semaphore_pending_f(void) | ||
72 | { | ||
73 | return 0x2U; | ||
74 | } | ||
75 | static inline u32 gr_intr_semaphore_reset_f(void) | ||
76 | { | ||
77 | return 0x2U; | ||
78 | } | ||
79 | static inline u32 gr_intr_illegal_method_pending_f(void) | ||
80 | { | ||
81 | return 0x10U; | ||
82 | } | ||
83 | static inline u32 gr_intr_illegal_method_reset_f(void) | ||
84 | { | ||
85 | return 0x10U; | ||
86 | } | ||
87 | static inline u32 gr_intr_illegal_notify_pending_f(void) | ||
88 | { | ||
89 | return 0x40U; | ||
90 | } | ||
91 | static inline u32 gr_intr_illegal_notify_reset_f(void) | ||
92 | { | ||
93 | return 0x40U; | ||
94 | } | ||
95 | static inline u32 gr_intr_firmware_method_f(u32 v) | ||
96 | { | ||
97 | return (v & 0x1U) << 8U; | ||
98 | } | ||
99 | static inline u32 gr_intr_firmware_method_pending_f(void) | ||
100 | { | ||
101 | return 0x100U; | ||
102 | } | ||
103 | static inline u32 gr_intr_firmware_method_reset_f(void) | ||
104 | { | ||
105 | return 0x100U; | ||
106 | } | ||
107 | static inline u32 gr_intr_illegal_class_pending_f(void) | ||
108 | { | ||
109 | return 0x20U; | ||
110 | } | ||
111 | static inline u32 gr_intr_illegal_class_reset_f(void) | ||
112 | { | ||
113 | return 0x20U; | ||
114 | } | ||
115 | static inline u32 gr_intr_fecs_error_pending_f(void) | ||
116 | { | ||
117 | return 0x80000U; | ||
118 | } | ||
119 | static inline u32 gr_intr_fecs_error_reset_f(void) | ||
120 | { | ||
121 | return 0x80000U; | ||
122 | } | ||
123 | static inline u32 gr_intr_class_error_pending_f(void) | ||
124 | { | ||
125 | return 0x100000U; | ||
126 | } | ||
127 | static inline u32 gr_intr_class_error_reset_f(void) | ||
128 | { | ||
129 | return 0x100000U; | ||
130 | } | ||
131 | static inline u32 gr_intr_exception_pending_f(void) | ||
132 | { | ||
133 | return 0x200000U; | ||
134 | } | ||
135 | static inline u32 gr_intr_exception_reset_f(void) | ||
136 | { | ||
137 | return 0x200000U; | ||
138 | } | ||
139 | static inline u32 gr_fecs_intr_r(void) | ||
140 | { | ||
141 | return 0x00400144U; | ||
142 | } | ||
143 | static inline u32 gr_class_error_r(void) | ||
144 | { | ||
145 | return 0x00400110U; | ||
146 | } | ||
147 | static inline u32 gr_class_error_code_v(u32 r) | ||
148 | { | ||
149 | return (r >> 0U) & 0xffffU; | ||
150 | } | ||
151 | static inline u32 gr_intr_nonstall_r(void) | ||
152 | { | ||
153 | return 0x00400120U; | ||
154 | } | ||
155 | static inline u32 gr_intr_nonstall_trap_pending_f(void) | ||
156 | { | ||
157 | return 0x2U; | ||
158 | } | ||
159 | static inline u32 gr_intr_en_r(void) | ||
160 | { | ||
161 | return 0x0040013cU; | ||
162 | } | ||
163 | static inline u32 gr_exception_r(void) | ||
164 | { | ||
165 | return 0x00400108U; | ||
166 | } | ||
167 | static inline u32 gr_exception_fe_m(void) | ||
168 | { | ||
169 | return 0x1U << 0U; | ||
170 | } | ||
171 | static inline u32 gr_exception_gpc_m(void) | ||
172 | { | ||
173 | return 0x1U << 24U; | ||
174 | } | ||
175 | static inline u32 gr_exception_memfmt_m(void) | ||
176 | { | ||
177 | return 0x1U << 1U; | ||
178 | } | ||
179 | static inline u32 gr_exception_ds_m(void) | ||
180 | { | ||
181 | return 0x1U << 4U; | ||
182 | } | ||
183 | static inline u32 gr_exception_sked_m(void) | ||
184 | { | ||
185 | return 0x1U << 8U; | ||
186 | } | ||
187 | static inline u32 gr_exception1_r(void) | ||
188 | { | ||
189 | return 0x00400118U; | ||
190 | } | ||
191 | static inline u32 gr_exception1_gpc_0_pending_f(void) | ||
192 | { | ||
193 | return 0x1U; | ||
194 | } | ||
195 | static inline u32 gr_exception2_r(void) | ||
196 | { | ||
197 | return 0x0040011cU; | ||
198 | } | ||
199 | static inline u32 gr_exception_en_r(void) | ||
200 | { | ||
201 | return 0x00400138U; | ||
202 | } | ||
203 | static inline u32 gr_exception_en_fe_m(void) | ||
204 | { | ||
205 | return 0x1U << 0U; | ||
206 | } | ||
207 | static inline u32 gr_exception_en_fe_enabled_f(void) | ||
208 | { | ||
209 | return 0x1U; | ||
210 | } | ||
211 | static inline u32 gr_exception_en_gpc_m(void) | ||
212 | { | ||
213 | return 0x1U << 24U; | ||
214 | } | ||
215 | static inline u32 gr_exception_en_gpc_enabled_f(void) | ||
216 | { | ||
217 | return 0x1000000U; | ||
218 | } | ||
219 | static inline u32 gr_exception_en_memfmt_m(void) | ||
220 | { | ||
221 | return 0x1U << 1U; | ||
222 | } | ||
223 | static inline u32 gr_exception_en_memfmt_enabled_f(void) | ||
224 | { | ||
225 | return 0x2U; | ||
226 | } | ||
227 | static inline u32 gr_exception_en_ds_m(void) | ||
228 | { | ||
229 | return 0x1U << 4U; | ||
230 | } | ||
231 | static inline u32 gr_exception_en_ds_enabled_f(void) | ||
232 | { | ||
233 | return 0x10U; | ||
234 | } | ||
235 | static inline u32 gr_exception1_en_r(void) | ||
236 | { | ||
237 | return 0x00400130U; | ||
238 | } | ||
239 | static inline u32 gr_exception2_en_r(void) | ||
240 | { | ||
241 | return 0x00400134U; | ||
242 | } | ||
243 | static inline u32 gr_gpfifo_ctl_r(void) | ||
244 | { | ||
245 | return 0x00400500U; | ||
246 | } | ||
247 | static inline u32 gr_gpfifo_ctl_access_f(u32 v) | ||
248 | { | ||
249 | return (v & 0x1U) << 0U; | ||
250 | } | ||
251 | static inline u32 gr_gpfifo_ctl_access_disabled_f(void) | ||
252 | { | ||
253 | return 0x0U; | ||
254 | } | ||
255 | static inline u32 gr_gpfifo_ctl_access_enabled_f(void) | ||
256 | { | ||
257 | return 0x1U; | ||
258 | } | ||
259 | static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) | ||
260 | { | ||
261 | return (v & 0x1U) << 16U; | ||
262 | } | ||
263 | static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) | ||
264 | { | ||
265 | return 0x00000001U; | ||
266 | } | ||
267 | static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) | ||
268 | { | ||
269 | return 0x10000U; | ||
270 | } | ||
271 | static inline u32 gr_gpfifo_status_r(void) | ||
272 | { | ||
273 | return 0x00400504U; | ||
274 | } | ||
275 | static inline u32 gr_trapped_addr_r(void) | ||
276 | { | ||
277 | return 0x00400704U; | ||
278 | } | ||
279 | static inline u32 gr_trapped_addr_mthd_v(u32 r) | ||
280 | { | ||
281 | return (r >> 2U) & 0xfffU; | ||
282 | } | ||
283 | static inline u32 gr_trapped_addr_subch_v(u32 r) | ||
284 | { | ||
285 | return (r >> 16U) & 0x7U; | ||
286 | } | ||
287 | static inline u32 gr_trapped_addr_mme_generated_v(u32 r) | ||
288 | { | ||
289 | return (r >> 20U) & 0x1U; | ||
290 | } | ||
291 | static inline u32 gr_trapped_addr_datahigh_v(u32 r) | ||
292 | { | ||
293 | return (r >> 24U) & 0x1U; | ||
294 | } | ||
295 | static inline u32 gr_trapped_addr_priv_v(u32 r) | ||
296 | { | ||
297 | return (r >> 28U) & 0x1U; | ||
298 | } | ||
299 | static inline u32 gr_trapped_addr_status_v(u32 r) | ||
300 | { | ||
301 | return (r >> 31U) & 0x1U; | ||
302 | } | ||
303 | static inline u32 gr_trapped_data_lo_r(void) | ||
304 | { | ||
305 | return 0x00400708U; | ||
306 | } | ||
307 | static inline u32 gr_trapped_data_hi_r(void) | ||
308 | { | ||
309 | return 0x0040070cU; | ||
310 | } | ||
311 | static inline u32 gr_trapped_data_mme_r(void) | ||
312 | { | ||
313 | return 0x00400710U; | ||
314 | } | ||
315 | static inline u32 gr_trapped_data_mme_pc_v(u32 r) | ||
316 | { | ||
317 | return (r >> 0U) & 0xfffU; | ||
318 | } | ||
319 | static inline u32 gr_status_r(void) | ||
320 | { | ||
321 | return 0x00400700U; | ||
322 | } | ||
323 | static inline u32 gr_status_fe_method_upper_v(u32 r) | ||
324 | { | ||
325 | return (r >> 1U) & 0x1U; | ||
326 | } | ||
327 | static inline u32 gr_status_fe_method_lower_v(u32 r) | ||
328 | { | ||
329 | return (r >> 2U) & 0x1U; | ||
330 | } | ||
331 | static inline u32 gr_status_fe_method_lower_idle_v(void) | ||
332 | { | ||
333 | return 0x00000000U; | ||
334 | } | ||
335 | static inline u32 gr_status_fe_gi_v(u32 r) | ||
336 | { | ||
337 | return (r >> 21U) & 0x1U; | ||
338 | } | ||
339 | static inline u32 gr_status_mask_r(void) | ||
340 | { | ||
341 | return 0x00400610U; | ||
342 | } | ||
343 | static inline u32 gr_status_1_r(void) | ||
344 | { | ||
345 | return 0x00400604U; | ||
346 | } | ||
347 | static inline u32 gr_status_2_r(void) | ||
348 | { | ||
349 | return 0x00400608U; | ||
350 | } | ||
351 | static inline u32 gr_engine_status_r(void) | ||
352 | { | ||
353 | return 0x0040060cU; | ||
354 | } | ||
355 | static inline u32 gr_engine_status_value_busy_f(void) | ||
356 | { | ||
357 | return 0x1U; | ||
358 | } | ||
359 | static inline u32 gr_pri_be0_becs_be_exception_r(void) | ||
360 | { | ||
361 | return 0x00410204U; | ||
362 | } | ||
363 | static inline u32 gr_pri_be0_becs_be_exception_en_r(void) | ||
364 | { | ||
365 | return 0x00410208U; | ||
366 | } | ||
367 | static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) | ||
368 | { | ||
369 | return 0x00502c90U; | ||
370 | } | ||
371 | static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) | ||
372 | { | ||
373 | return 0x00502c94U; | ||
374 | } | ||
375 | static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) | ||
376 | { | ||
377 | return 0x00504508U; | ||
378 | } | ||
379 | static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | ||
380 | { | ||
381 | return 0x0050450cU; | ||
382 | } | ||
383 | static inline u32 gr_activity_0_r(void) | ||
384 | { | ||
385 | return 0x00400380U; | ||
386 | } | ||
387 | static inline u32 gr_activity_1_r(void) | ||
388 | { | ||
389 | return 0x00400384U; | ||
390 | } | ||
391 | static inline u32 gr_activity_2_r(void) | ||
392 | { | ||
393 | return 0x00400388U; | ||
394 | } | ||
395 | static inline u32 gr_activity_4_r(void) | ||
396 | { | ||
397 | return 0x00400390U; | ||
398 | } | ||
399 | static inline u32 gr_activity_4_gpc0_s(void) | ||
400 | { | ||
401 | return 3U; | ||
402 | } | ||
403 | static inline u32 gr_activity_4_gpc0_f(u32 v) | ||
404 | { | ||
405 | return (v & 0x7U) << 0U; | ||
406 | } | ||
407 | static inline u32 gr_activity_4_gpc0_m(void) | ||
408 | { | ||
409 | return 0x7U << 0U; | ||
410 | } | ||
411 | static inline u32 gr_activity_4_gpc0_v(u32 r) | ||
412 | { | ||
413 | return (r >> 0U) & 0x7U; | ||
414 | } | ||
415 | static inline u32 gr_activity_4_gpc0_empty_v(void) | ||
416 | { | ||
417 | return 0x00000000U; | ||
418 | } | ||
419 | static inline u32 gr_activity_4_gpc0_preempted_v(void) | ||
420 | { | ||
421 | return 0x00000004U; | ||
422 | } | ||
423 | static inline u32 gr_pri_gpc0_gcc_dbg_r(void) | ||
424 | { | ||
425 | return 0x00501000U; | ||
426 | } | ||
427 | static inline u32 gr_pri_gpcs_gcc_dbg_r(void) | ||
428 | { | ||
429 | return 0x00419000U; | ||
430 | } | ||
431 | static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) | ||
432 | { | ||
433 | return 0x1U << 1U; | ||
434 | } | ||
435 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) | ||
436 | { | ||
437 | return 0x0050433cU; | ||
438 | } | ||
439 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) | ||
440 | { | ||
441 | return 0x00419b3cU; | ||
442 | } | ||
443 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) | ||
444 | { | ||
445 | return 0x1U << 0U; | ||
446 | } | ||
447 | static inline u32 gr_pri_sked_activity_r(void) | ||
448 | { | ||
449 | return 0x00407054U; | ||
450 | } | ||
451 | static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) | ||
452 | { | ||
453 | return 0x00502c80U; | ||
454 | } | ||
455 | static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) | ||
456 | { | ||
457 | return 0x00502c84U; | ||
458 | } | ||
459 | static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) | ||
460 | { | ||
461 | return 0x00502c88U; | ||
462 | } | ||
463 | static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) | ||
464 | { | ||
465 | return 0x00502c8cU; | ||
466 | } | ||
467 | static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) | ||
468 | { | ||
469 | return 0x00504500U; | ||
470 | } | ||
471 | static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) | ||
472 | { | ||
473 | return 0x00504d00U; | ||
474 | } | ||
475 | static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) | ||
476 | { | ||
477 | return 0x00501d00U; | ||
478 | } | ||
479 | static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) | ||
480 | { | ||
481 | return 0x0041ac80U; | ||
482 | } | ||
483 | static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) | ||
484 | { | ||
485 | return 0x0041ac84U; | ||
486 | } | ||
487 | static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) | ||
488 | { | ||
489 | return 0x0041ac88U; | ||
490 | } | ||
491 | static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) | ||
492 | { | ||
493 | return 0x0041ac8cU; | ||
494 | } | ||
495 | static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) | ||
496 | { | ||
497 | return 0x0041c500U; | ||
498 | } | ||
499 | static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) | ||
500 | { | ||
501 | return 0x0041cd00U; | ||
502 | } | ||
503 | static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) | ||
504 | { | ||
505 | return 0x00419d00U; | ||
506 | } | ||
507 | static inline u32 gr_pri_be0_becs_be_activity0_r(void) | ||
508 | { | ||
509 | return 0x00410200U; | ||
510 | } | ||
511 | static inline u32 gr_pri_be1_becs_be_activity0_r(void) | ||
512 | { | ||
513 | return 0x00410600U; | ||
514 | } | ||
515 | static inline u32 gr_pri_bes_becs_be_activity0_r(void) | ||
516 | { | ||
517 | return 0x00408a00U; | ||
518 | } | ||
519 | static inline u32 gr_pri_ds_mpipe_status_r(void) | ||
520 | { | ||
521 | return 0x00405858U; | ||
522 | } | ||
523 | static inline u32 gr_pri_fe_go_idle_info_r(void) | ||
524 | { | ||
525 | return 0x00404194U; | ||
526 | } | ||
527 | static inline u32 gr_pri_fe_chip_def_info_r(void) | ||
528 | { | ||
529 | return 0x00404030U; | ||
530 | } | ||
531 | static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) | ||
532 | { | ||
533 | return (r >> 0U) & 0xfffU; | ||
534 | } | ||
535 | static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) | ||
536 | { | ||
537 | return 0x00000040U; | ||
538 | } | ||
539 | static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) | ||
540 | { | ||
541 | return 0x00504238U; | ||
542 | } | ||
543 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) | ||
544 | { | ||
545 | return 0x00504358U; | ||
546 | } | ||
547 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) | ||
548 | { | ||
549 | return 0x1U << 0U; | ||
550 | } | ||
551 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) | ||
552 | { | ||
553 | return 0x1U << 1U; | ||
554 | } | ||
555 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) | ||
556 | { | ||
557 | return 0x1U << 2U; | ||
558 | } | ||
559 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) | ||
560 | { | ||
561 | return 0x1U << 3U; | ||
562 | } | ||
563 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) | ||
564 | { | ||
565 | return 0x1U << 4U; | ||
566 | } | ||
567 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) | ||
568 | { | ||
569 | return 0x1U << 5U; | ||
570 | } | ||
571 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) | ||
572 | { | ||
573 | return 0x1U << 6U; | ||
574 | } | ||
575 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) | ||
576 | { | ||
577 | return 0x1U << 7U; | ||
578 | } | ||
579 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) | ||
580 | { | ||
581 | return 0x1U << 8U; | ||
582 | } | ||
583 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) | ||
584 | { | ||
585 | return 0x1U << 9U; | ||
586 | } | ||
587 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) | ||
588 | { | ||
589 | return 0x1U << 10U; | ||
590 | } | ||
591 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) | ||
592 | { | ||
593 | return 0x1U << 11U; | ||
594 | } | ||
595 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) | ||
596 | { | ||
597 | return 0x1U << 12U; | ||
598 | } | ||
599 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) | ||
600 | { | ||
601 | return 0x1U << 13U; | ||
602 | } | ||
603 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) | ||
604 | { | ||
605 | return 0x1U << 14U; | ||
606 | } | ||
607 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) | ||
608 | { | ||
609 | return 0x1U << 15U; | ||
610 | } | ||
611 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
612 | { | ||
613 | return (r >> 24U) & 0x1U; | ||
614 | } | ||
615 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
616 | { | ||
617 | return (r >> 26U) & 0x1U; | ||
618 | } | ||
619 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) | ||
620 | { | ||
621 | return 0x40000000U; | ||
622 | } | ||
623 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) | ||
624 | { | ||
625 | return 0x0050435cU; | ||
626 | } | ||
627 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) | ||
628 | { | ||
629 | return 16U; | ||
630 | } | ||
631 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) | ||
632 | { | ||
633 | return (r >> 0U) & 0xffffU; | ||
634 | } | ||
635 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) | ||
636 | { | ||
637 | return 0x00504360U; | ||
638 | } | ||
639 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) | ||
640 | { | ||
641 | return 16U; | ||
642 | } | ||
643 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) | ||
644 | { | ||
645 | return (r >> 0U) & 0xffffU; | ||
646 | } | ||
647 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) | ||
648 | { | ||
649 | return 0x0050436cU; | ||
650 | } | ||
651 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) | ||
652 | { | ||
653 | return 0x1U << 0U; | ||
654 | } | ||
655 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) | ||
656 | { | ||
657 | return 0x1U << 1U; | ||
658 | } | ||
659 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) | ||
660 | { | ||
661 | return 0x1U << 2U; | ||
662 | } | ||
663 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) | ||
664 | { | ||
665 | return 0x1U << 3U; | ||
666 | } | ||
667 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
668 | { | ||
669 | return (r >> 8U) & 0x1U; | ||
670 | } | ||
671 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
672 | { | ||
673 | return (r >> 10U) & 0x1U; | ||
674 | } | ||
675 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) | ||
676 | { | ||
677 | return 0x40000000U; | ||
678 | } | ||
679 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) | ||
680 | { | ||
681 | return 0x00504370U; | ||
682 | } | ||
683 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) | ||
684 | { | ||
685 | return 16U; | ||
686 | } | ||
687 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) | ||
688 | { | ||
689 | return (r >> 0U) & 0xffffU; | ||
690 | } | ||
691 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) | ||
692 | { | ||
693 | return 0x00504374U; | ||
694 | } | ||
695 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) | ||
696 | { | ||
697 | return 16U; | ||
698 | } | ||
699 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) | ||
700 | { | ||
701 | return (r >> 0U) & 0xffffU; | ||
702 | } | ||
703 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) | ||
704 | { | ||
705 | return 0x0050464cU; | ||
706 | } | ||
707 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) | ||
708 | { | ||
709 | return 0x1U << 0U; | ||
710 | } | ||
711 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) | ||
712 | { | ||
713 | return 0x1U << 1U; | ||
714 | } | ||
715 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) | ||
716 | { | ||
717 | return 0x1U << 2U; | ||
718 | } | ||
719 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) | ||
720 | { | ||
721 | return 0x1U << 3U; | ||
722 | } | ||
723 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) | ||
724 | { | ||
725 | return 0x1U << 4U; | ||
726 | } | ||
727 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) | ||
728 | { | ||
729 | return 0x1U << 5U; | ||
730 | } | ||
731 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) | ||
732 | { | ||
733 | return 0x1U << 6U; | ||
734 | } | ||
735 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) | ||
736 | { | ||
737 | return 0x1U << 7U; | ||
738 | } | ||
739 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
740 | { | ||
741 | return (r >> 16U) & 0x1U; | ||
742 | } | ||
743 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
744 | { | ||
745 | return (r >> 18U) & 0x1U; | ||
746 | } | ||
747 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) | ||
748 | { | ||
749 | return 0x40000000U; | ||
750 | } | ||
751 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) | ||
752 | { | ||
753 | return 0x00504650U; | ||
754 | } | ||
755 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) | ||
756 | { | ||
757 | return 16U; | ||
758 | } | ||
759 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) | ||
760 | { | ||
761 | return (r >> 0U) & 0xffffU; | ||
762 | } | ||
763 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) | ||
764 | { | ||
765 | return 0x00504654U; | ||
766 | } | ||
767 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) | ||
768 | { | ||
769 | return 16U; | ||
770 | } | ||
771 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) | ||
772 | { | ||
773 | return (r >> 0U) & 0xffffU; | ||
774 | } | ||
775 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) | ||
776 | { | ||
777 | return 0x00504624U; | ||
778 | } | ||
779 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) | ||
780 | { | ||
781 | return 0x1U << 0U; | ||
782 | } | ||
783 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) | ||
784 | { | ||
785 | return 0x1U << 1U; | ||
786 | } | ||
787 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) | ||
788 | { | ||
789 | return 0x1U << 2U; | ||
790 | } | ||
791 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) | ||
792 | { | ||
793 | return 0x1U << 3U; | ||
794 | } | ||
795 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) | ||
796 | { | ||
797 | return 0x1U << 4U; | ||
798 | } | ||
799 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) | ||
800 | { | ||
801 | return 0x1U << 5U; | ||
802 | } | ||
803 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) | ||
804 | { | ||
805 | return 0x1U << 6U; | ||
806 | } | ||
807 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) | ||
808 | { | ||
809 | return 0x1U << 7U; | ||
810 | } | ||
811 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
812 | { | ||
813 | return (r >> 8U) & 0x1U; | ||
814 | } | ||
815 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
816 | { | ||
817 | return (r >> 10U) & 0x1U; | ||
818 | } | ||
819 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void) | ||
820 | { | ||
821 | return 0x40000000U; | ||
822 | } | ||
823 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void) | ||
824 | { | ||
825 | return 0x00504628U; | ||
826 | } | ||
827 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void) | ||
828 | { | ||
829 | return 16U; | ||
830 | } | ||
831 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r) | ||
832 | { | ||
833 | return (r >> 0U) & 0xffffU; | ||
834 | } | ||
835 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void) | ||
836 | { | ||
837 | return 0x0050462cU; | ||
838 | } | ||
839 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void) | ||
840 | { | ||
841 | return 16U; | ||
842 | } | ||
843 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r) | ||
844 | { | ||
845 | return (r >> 0U) & 0xffffU; | ||
846 | } | ||
847 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) | ||
848 | { | ||
849 | return 0x00504638U; | ||
850 | } | ||
851 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) | ||
852 | { | ||
853 | return 0x1U << 0U; | ||
854 | } | ||
855 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) | ||
856 | { | ||
857 | return 0x1U << 1U; | ||
858 | } | ||
859 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) | ||
860 | { | ||
861 | return 0x1U << 2U; | ||
862 | } | ||
863 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) | ||
864 | { | ||
865 | return 0x1U << 3U; | ||
866 | } | ||
867 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) | ||
868 | { | ||
869 | return 0x1U << 4U; | ||
870 | } | ||
871 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) | ||
872 | { | ||
873 | return 0x1U << 5U; | ||
874 | } | ||
875 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) | ||
876 | { | ||
877 | return 0x1U << 6U; | ||
878 | } | ||
879 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) | ||
880 | { | ||
881 | return 0x1U << 7U; | ||
882 | } | ||
883 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
884 | { | ||
885 | return (r >> 16U) & 0x1U; | ||
886 | } | ||
887 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
888 | { | ||
889 | return (r >> 18U) & 0x1U; | ||
890 | } | ||
891 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) | ||
892 | { | ||
893 | return 0x40000000U; | ||
894 | } | ||
895 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) | ||
896 | { | ||
897 | return 0x0050463cU; | ||
898 | } | ||
899 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) | ||
900 | { | ||
901 | return 16U; | ||
902 | } | ||
903 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) | ||
904 | { | ||
905 | return (r >> 0U) & 0xffffU; | ||
906 | } | ||
907 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) | ||
908 | { | ||
909 | return 0x00504640U; | ||
910 | } | ||
911 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) | ||
912 | { | ||
913 | return 16U; | ||
914 | } | ||
915 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) | ||
916 | { | ||
917 | return (r >> 0U) & 0xffffU; | ||
918 | } | ||
919 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) | ||
920 | { | ||
921 | return 0x005042c4U; | ||
922 | } | ||
923 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) | ||
924 | { | ||
925 | return 0x0U; | ||
926 | } | ||
927 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) | ||
928 | { | ||
929 | return 0x1U; | ||
930 | } | ||
931 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) | ||
932 | { | ||
933 | return 0x2U; | ||
934 | } | ||
935 | static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) | ||
936 | { | ||
937 | return 0x00504430U; | ||
938 | } | ||
939 | static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) | ||
940 | { | ||
941 | return 0x40000000U; | ||
942 | } | ||
943 | static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) | ||
944 | { | ||
945 | return 0x00504434U; | ||
946 | } | ||
947 | static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) | ||
948 | { | ||
949 | return (r >> 0U) & 0x3fU; | ||
950 | } | ||
951 | static inline u32 gr_pri_be0_crop_status1_r(void) | ||
952 | { | ||
953 | return 0x00410134U; | ||
954 | } | ||
955 | static inline u32 gr_pri_bes_crop_status1_r(void) | ||
956 | { | ||
957 | return 0x00408934U; | ||
958 | } | ||
959 | static inline u32 gr_pri_be0_zrop_status_r(void) | ||
960 | { | ||
961 | return 0x00410048U; | ||
962 | } | ||
963 | static inline u32 gr_pri_be0_zrop_status2_r(void) | ||
964 | { | ||
965 | return 0x0041004cU; | ||
966 | } | ||
967 | static inline u32 gr_pri_bes_zrop_status_r(void) | ||
968 | { | ||
969 | return 0x00408848U; | ||
970 | } | ||
971 | static inline u32 gr_pri_bes_zrop_status2_r(void) | ||
972 | { | ||
973 | return 0x0040884cU; | ||
974 | } | ||
975 | static inline u32 gr_pipe_bundle_address_r(void) | ||
976 | { | ||
977 | return 0x00400200U; | ||
978 | } | ||
979 | static inline u32 gr_pipe_bundle_address_value_v(u32 r) | ||
980 | { | ||
981 | return (r >> 0U) & 0xffffU; | ||
982 | } | ||
983 | static inline u32 gr_pipe_bundle_address_veid_f(u32 v) | ||
984 | { | ||
985 | return (v & 0x3fU) << 20U; | ||
986 | } | ||
987 | static inline u32 gr_pipe_bundle_address_veid_w(void) | ||
988 | { | ||
989 | return 0U; | ||
990 | } | ||
991 | static inline u32 gr_pipe_bundle_data_r(void) | ||
992 | { | ||
993 | return 0x00400204U; | ||
994 | } | ||
995 | static inline u32 gr_pipe_bundle_config_r(void) | ||
996 | { | ||
997 | return 0x00400208U; | ||
998 | } | ||
999 | static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) | ||
1000 | { | ||
1001 | return 0x0U; | ||
1002 | } | ||
1003 | static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) | ||
1004 | { | ||
1005 | return 0x80000000U; | ||
1006 | } | ||
1007 | static inline u32 gr_fe_hww_esr_r(void) | ||
1008 | { | ||
1009 | return 0x00404000U; | ||
1010 | } | ||
1011 | static inline u32 gr_fe_hww_esr_reset_active_f(void) | ||
1012 | { | ||
1013 | return 0x40000000U; | ||
1014 | } | ||
1015 | static inline u32 gr_fe_hww_esr_en_enable_f(void) | ||
1016 | { | ||
1017 | return 0x80000000U; | ||
1018 | } | ||
1019 | static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) | ||
1020 | { | ||
1021 | return 0x00419eacU; | ||
1022 | } | ||
1023 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) | ||
1024 | { | ||
1025 | return 0x0050472cU; | ||
1026 | } | ||
1027 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) | ||
1028 | { | ||
1029 | return 0x4U; | ||
1030 | } | ||
1031 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) | ||
1032 | { | ||
1033 | return 0x10U; | ||
1034 | } | ||
1035 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) | ||
1036 | { | ||
1037 | return 0x20U; | ||
1038 | } | ||
1039 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) | ||
1040 | { | ||
1041 | return 0x40U; | ||
1042 | } | ||
1043 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) | ||
1044 | { | ||
1045 | return 0x100U; | ||
1046 | } | ||
1047 | static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) | ||
1048 | { | ||
1049 | return 0x00419eb4U; | ||
1050 | } | ||
1051 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) | ||
1052 | { | ||
1053 | return 0x00504734U; | ||
1054 | } | ||
1055 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) | ||
1056 | { | ||
1057 | return 0x1U << 4U; | ||
1058 | } | ||
1059 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) | ||
1060 | { | ||
1061 | return 0x10U; | ||
1062 | } | ||
1063 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) | ||
1064 | { | ||
1065 | return 0x1U << 5U; | ||
1066 | } | ||
1067 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) | ||
1068 | { | ||
1069 | return 0x20U; | ||
1070 | } | ||
1071 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) | ||
1072 | { | ||
1073 | return 0x1U << 6U; | ||
1074 | } | ||
1075 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) | ||
1076 | { | ||
1077 | return 0x40U; | ||
1078 | } | ||
1079 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) | ||
1080 | { | ||
1081 | return 0x1U << 2U; | ||
1082 | } | ||
1083 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
1084 | { | ||
1085 | return 0x4U; | ||
1086 | } | ||
1087 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) | ||
1088 | { | ||
1089 | return 0x1U << 8U; | ||
1090 | } | ||
1091 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) | ||
1092 | { | ||
1093 | return 0x100U; | ||
1094 | } | ||
1095 | static inline u32 gr_fe_go_idle_timeout_r(void) | ||
1096 | { | ||
1097 | return 0x00404154U; | ||
1098 | } | ||
1099 | static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) | ||
1100 | { | ||
1101 | return (v & 0xffffffffU) << 0U; | ||
1102 | } | ||
1103 | static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) | ||
1104 | { | ||
1105 | return 0x0U; | ||
1106 | } | ||
1107 | static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) | ||
1108 | { | ||
1109 | return 0x1800U; | ||
1110 | } | ||
1111 | static inline u32 gr_fe_object_table_r(u32 i) | ||
1112 | { | ||
1113 | return 0x00404200U + i*4U; | ||
1114 | } | ||
1115 | static inline u32 gr_fe_object_table_nvclass_v(u32 r) | ||
1116 | { | ||
1117 | return (r >> 0U) & 0xffffU; | ||
1118 | } | ||
1119 | static inline u32 gr_fe_tpc_fs_r(u32 i) | ||
1120 | { | ||
1121 | return 0x0040a200U + i*4U; | ||
1122 | } | ||
1123 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) | ||
1124 | { | ||
1125 | return 0x00404488U; | ||
1126 | } | ||
1127 | static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) | ||
1128 | { | ||
1129 | return 0x80000000U; | ||
1130 | } | ||
1131 | static inline u32 gr_pri_mme_shadow_raw_data_r(void) | ||
1132 | { | ||
1133 | return 0x0040448cU; | ||
1134 | } | ||
1135 | static inline u32 gr_mme_hww_esr_r(void) | ||
1136 | { | ||
1137 | return 0x00404490U; | ||
1138 | } | ||
1139 | static inline u32 gr_mme_hww_esr_reset_active_f(void) | ||
1140 | { | ||
1141 | return 0x40000000U; | ||
1142 | } | ||
1143 | static inline u32 gr_mme_hww_esr_en_enable_f(void) | ||
1144 | { | ||
1145 | return 0x80000000U; | ||
1146 | } | ||
1147 | static inline u32 gr_memfmt_hww_esr_r(void) | ||
1148 | { | ||
1149 | return 0x00404600U; | ||
1150 | } | ||
1151 | static inline u32 gr_memfmt_hww_esr_reset_active_f(void) | ||
1152 | { | ||
1153 | return 0x40000000U; | ||
1154 | } | ||
1155 | static inline u32 gr_memfmt_hww_esr_en_enable_f(void) | ||
1156 | { | ||
1157 | return 0x80000000U; | ||
1158 | } | ||
1159 | static inline u32 gr_fecs_cpuctl_r(void) | ||
1160 | { | ||
1161 | return 0x00409100U; | ||
1162 | } | ||
1163 | static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) | ||
1164 | { | ||
1165 | return (v & 0x1U) << 1U; | ||
1166 | } | ||
1167 | static inline u32 gr_fecs_cpuctl_alias_r(void) | ||
1168 | { | ||
1169 | return 0x00409130U; | ||
1170 | } | ||
1171 | static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) | ||
1172 | { | ||
1173 | return (v & 0x1U) << 1U; | ||
1174 | } | ||
1175 | static inline u32 gr_fecs_dmactl_r(void) | ||
1176 | { | ||
1177 | return 0x0040910cU; | ||
1178 | } | ||
1179 | static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) | ||
1180 | { | ||
1181 | return (v & 0x1U) << 0U; | ||
1182 | } | ||
1183 | static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) | ||
1184 | { | ||
1185 | return 0x1U << 1U; | ||
1186 | } | ||
1187 | static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) | ||
1188 | { | ||
1189 | return 0x1U << 2U; | ||
1190 | } | ||
1191 | static inline u32 gr_fecs_os_r(void) | ||
1192 | { | ||
1193 | return 0x00409080U; | ||
1194 | } | ||
1195 | static inline u32 gr_fecs_idlestate_r(void) | ||
1196 | { | ||
1197 | return 0x0040904cU; | ||
1198 | } | ||
1199 | static inline u32 gr_fecs_mailbox0_r(void) | ||
1200 | { | ||
1201 | return 0x00409040U; | ||
1202 | } | ||
1203 | static inline u32 gr_fecs_mailbox1_r(void) | ||
1204 | { | ||
1205 | return 0x00409044U; | ||
1206 | } | ||
1207 | static inline u32 gr_fecs_irqstat_r(void) | ||
1208 | { | ||
1209 | return 0x00409008U; | ||
1210 | } | ||
1211 | static inline u32 gr_fecs_irqmode_r(void) | ||
1212 | { | ||
1213 | return 0x0040900cU; | ||
1214 | } | ||
1215 | static inline u32 gr_fecs_irqmask_r(void) | ||
1216 | { | ||
1217 | return 0x00409018U; | ||
1218 | } | ||
1219 | static inline u32 gr_fecs_irqdest_r(void) | ||
1220 | { | ||
1221 | return 0x0040901cU; | ||
1222 | } | ||
1223 | static inline u32 gr_fecs_curctx_r(void) | ||
1224 | { | ||
1225 | return 0x00409050U; | ||
1226 | } | ||
1227 | static inline u32 gr_fecs_nxtctx_r(void) | ||
1228 | { | ||
1229 | return 0x00409054U; | ||
1230 | } | ||
1231 | static inline u32 gr_fecs_engctl_r(void) | ||
1232 | { | ||
1233 | return 0x004090a4U; | ||
1234 | } | ||
1235 | static inline u32 gr_fecs_debug1_r(void) | ||
1236 | { | ||
1237 | return 0x00409090U; | ||
1238 | } | ||
1239 | static inline u32 gr_fecs_debuginfo_r(void) | ||
1240 | { | ||
1241 | return 0x00409094U; | ||
1242 | } | ||
1243 | static inline u32 gr_fecs_icd_cmd_r(void) | ||
1244 | { | ||
1245 | return 0x00409200U; | ||
1246 | } | ||
1247 | static inline u32 gr_fecs_icd_cmd_opc_s(void) | ||
1248 | { | ||
1249 | return 4U; | ||
1250 | } | ||
1251 | static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) | ||
1252 | { | ||
1253 | return (v & 0xfU) << 0U; | ||
1254 | } | ||
1255 | static inline u32 gr_fecs_icd_cmd_opc_m(void) | ||
1256 | { | ||
1257 | return 0xfU << 0U; | ||
1258 | } | ||
1259 | static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) | ||
1260 | { | ||
1261 | return (r >> 0U) & 0xfU; | ||
1262 | } | ||
1263 | static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) | ||
1264 | { | ||
1265 | return 0x8U; | ||
1266 | } | ||
1267 | static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) | ||
1268 | { | ||
1269 | return 0xeU; | ||
1270 | } | ||
1271 | static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) | ||
1272 | { | ||
1273 | return (v & 0x1fU) << 8U; | ||
1274 | } | ||
1275 | static inline u32 gr_fecs_icd_rdata_r(void) | ||
1276 | { | ||
1277 | return 0x0040920cU; | ||
1278 | } | ||
1279 | static inline u32 gr_fecs_imemc_r(u32 i) | ||
1280 | { | ||
1281 | return 0x00409180U + i*16U; | ||
1282 | } | ||
1283 | static inline u32 gr_fecs_imemc_offs_f(u32 v) | ||
1284 | { | ||
1285 | return (v & 0x3fU) << 2U; | ||
1286 | } | ||
1287 | static inline u32 gr_fecs_imemc_blk_f(u32 v) | ||
1288 | { | ||
1289 | return (v & 0xffU) << 8U; | ||
1290 | } | ||
1291 | static inline u32 gr_fecs_imemc_aincw_f(u32 v) | ||
1292 | { | ||
1293 | return (v & 0x1U) << 24U; | ||
1294 | } | ||
1295 | static inline u32 gr_fecs_imemd_r(u32 i) | ||
1296 | { | ||
1297 | return 0x00409184U + i*16U; | ||
1298 | } | ||
1299 | static inline u32 gr_fecs_imemt_r(u32 i) | ||
1300 | { | ||
1301 | return 0x00409188U + i*16U; | ||
1302 | } | ||
1303 | static inline u32 gr_fecs_imemt_tag_f(u32 v) | ||
1304 | { | ||
1305 | return (v & 0xffffU) << 0U; | ||
1306 | } | ||
1307 | static inline u32 gr_fecs_dmemc_r(u32 i) | ||
1308 | { | ||
1309 | return 0x004091c0U + i*8U; | ||
1310 | } | ||
1311 | static inline u32 gr_fecs_dmemc_offs_s(void) | ||
1312 | { | ||
1313 | return 6U; | ||
1314 | } | ||
1315 | static inline u32 gr_fecs_dmemc_offs_f(u32 v) | ||
1316 | { | ||
1317 | return (v & 0x3fU) << 2U; | ||
1318 | } | ||
1319 | static inline u32 gr_fecs_dmemc_offs_m(void) | ||
1320 | { | ||
1321 | return 0x3fU << 2U; | ||
1322 | } | ||
1323 | static inline u32 gr_fecs_dmemc_offs_v(u32 r) | ||
1324 | { | ||
1325 | return (r >> 2U) & 0x3fU; | ||
1326 | } | ||
1327 | static inline u32 gr_fecs_dmemc_blk_f(u32 v) | ||
1328 | { | ||
1329 | return (v & 0xffU) << 8U; | ||
1330 | } | ||
1331 | static inline u32 gr_fecs_dmemc_aincw_f(u32 v) | ||
1332 | { | ||
1333 | return (v & 0x1U) << 24U; | ||
1334 | } | ||
1335 | static inline u32 gr_fecs_dmemd_r(u32 i) | ||
1336 | { | ||
1337 | return 0x004091c4U + i*8U; | ||
1338 | } | ||
1339 | static inline u32 gr_fecs_dmatrfbase_r(void) | ||
1340 | { | ||
1341 | return 0x00409110U; | ||
1342 | } | ||
1343 | static inline u32 gr_fecs_dmatrfmoffs_r(void) | ||
1344 | { | ||
1345 | return 0x00409114U; | ||
1346 | } | ||
1347 | static inline u32 gr_fecs_dmatrffboffs_r(void) | ||
1348 | { | ||
1349 | return 0x0040911cU; | ||
1350 | } | ||
1351 | static inline u32 gr_fecs_dmatrfcmd_r(void) | ||
1352 | { | ||
1353 | return 0x00409118U; | ||
1354 | } | ||
1355 | static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) | ||
1356 | { | ||
1357 | return (v & 0x1U) << 4U; | ||
1358 | } | ||
1359 | static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) | ||
1360 | { | ||
1361 | return (v & 0x1U) << 5U; | ||
1362 | } | ||
1363 | static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) | ||
1364 | { | ||
1365 | return (v & 0x7U) << 8U; | ||
1366 | } | ||
1367 | static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) | ||
1368 | { | ||
1369 | return (v & 0x7U) << 12U; | ||
1370 | } | ||
1371 | static inline u32 gr_fecs_bootvec_r(void) | ||
1372 | { | ||
1373 | return 0x00409104U; | ||
1374 | } | ||
1375 | static inline u32 gr_fecs_bootvec_vec_f(u32 v) | ||
1376 | { | ||
1377 | return (v & 0xffffffffU) << 0U; | ||
1378 | } | ||
1379 | static inline u32 gr_fecs_falcon_hwcfg_r(void) | ||
1380 | { | ||
1381 | return 0x00409108U; | ||
1382 | } | ||
1383 | static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) | ||
1384 | { | ||
1385 | return 0x0041a108U; | ||
1386 | } | ||
1387 | static inline u32 gr_fecs_falcon_rm_r(void) | ||
1388 | { | ||
1389 | return 0x00409084U; | ||
1390 | } | ||
1391 | static inline u32 gr_fecs_current_ctx_r(void) | ||
1392 | { | ||
1393 | return 0x00409b00U; | ||
1394 | } | ||
1395 | static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) | ||
1396 | { | ||
1397 | return (v & 0xfffffffU) << 0U; | ||
1398 | } | ||
1399 | static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) | ||
1400 | { | ||
1401 | return (r >> 0U) & 0xfffffffU; | ||
1402 | } | ||
1403 | static inline u32 gr_fecs_current_ctx_target_s(void) | ||
1404 | { | ||
1405 | return 2U; | ||
1406 | } | ||
1407 | static inline u32 gr_fecs_current_ctx_target_f(u32 v) | ||
1408 | { | ||
1409 | return (v & 0x3U) << 28U; | ||
1410 | } | ||
1411 | static inline u32 gr_fecs_current_ctx_target_m(void) | ||
1412 | { | ||
1413 | return 0x3U << 28U; | ||
1414 | } | ||
1415 | static inline u32 gr_fecs_current_ctx_target_v(u32 r) | ||
1416 | { | ||
1417 | return (r >> 28U) & 0x3U; | ||
1418 | } | ||
1419 | static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) | ||
1420 | { | ||
1421 | return 0x0U; | ||
1422 | } | ||
1423 | static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) | ||
1424 | { | ||
1425 | return 0x20000000U; | ||
1426 | } | ||
1427 | static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) | ||
1428 | { | ||
1429 | return 0x30000000U; | ||
1430 | } | ||
1431 | static inline u32 gr_fecs_current_ctx_valid_s(void) | ||
1432 | { | ||
1433 | return 1U; | ||
1434 | } | ||
1435 | static inline u32 gr_fecs_current_ctx_valid_f(u32 v) | ||
1436 | { | ||
1437 | return (v & 0x1U) << 31U; | ||
1438 | } | ||
1439 | static inline u32 gr_fecs_current_ctx_valid_m(void) | ||
1440 | { | ||
1441 | return 0x1U << 31U; | ||
1442 | } | ||
1443 | static inline u32 gr_fecs_current_ctx_valid_v(u32 r) | ||
1444 | { | ||
1445 | return (r >> 31U) & 0x1U; | ||
1446 | } | ||
1447 | static inline u32 gr_fecs_current_ctx_valid_false_f(void) | ||
1448 | { | ||
1449 | return 0x0U; | ||
1450 | } | ||
1451 | static inline u32 gr_fecs_method_data_r(void) | ||
1452 | { | ||
1453 | return 0x00409500U; | ||
1454 | } | ||
1455 | static inline u32 gr_fecs_method_push_r(void) | ||
1456 | { | ||
1457 | return 0x00409504U; | ||
1458 | } | ||
1459 | static inline u32 gr_fecs_method_push_adr_f(u32 v) | ||
1460 | { | ||
1461 | return (v & 0xfffU) << 0U; | ||
1462 | } | ||
1463 | static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) | ||
1464 | { | ||
1465 | return 0x00000003U; | ||
1466 | } | ||
1467 | static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) | ||
1468 | { | ||
1469 | return 0x3U; | ||
1470 | } | ||
1471 | static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) | ||
1472 | { | ||
1473 | return 0x00000010U; | ||
1474 | } | ||
1475 | static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) | ||
1476 | { | ||
1477 | return 0x00000009U; | ||
1478 | } | ||
1479 | static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) | ||
1480 | { | ||
1481 | return 0x00000015U; | ||
1482 | } | ||
1483 | static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) | ||
1484 | { | ||
1485 | return 0x00000016U; | ||
1486 | } | ||
1487 | static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) | ||
1488 | { | ||
1489 | return 0x00000025U; | ||
1490 | } | ||
1491 | static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) | ||
1492 | { | ||
1493 | return 0x00000030U; | ||
1494 | } | ||
1495 | static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) | ||
1496 | { | ||
1497 | return 0x00000031U; | ||
1498 | } | ||
1499 | static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) | ||
1500 | { | ||
1501 | return 0x00000032U; | ||
1502 | } | ||
1503 | static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) | ||
1504 | { | ||
1505 | return 0x00000038U; | ||
1506 | } | ||
1507 | static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) | ||
1508 | { | ||
1509 | return 0x00000039U; | ||
1510 | } | ||
1511 | static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | ||
1512 | { | ||
1513 | return 0x21U; | ||
1514 | } | ||
1515 | static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) | ||
1516 | { | ||
1517 | return 0x0000001aU; | ||
1518 | } | ||
1519 | static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) | ||
1520 | { | ||
1521 | return 0x00000004U; | ||
1522 | } | ||
1523 | static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) | ||
1524 | { | ||
1525 | return 0x0000003aU; | ||
1526 | } | ||
1527 | static inline u32 gr_fecs_host_int_status_r(void) | ||
1528 | { | ||
1529 | return 0x00409c18U; | ||
1530 | } | ||
1531 | static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) | ||
1532 | { | ||
1533 | return (v & 0x1U) << 16U; | ||
1534 | } | ||
1535 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | ||
1536 | { | ||
1537 | return (v & 0x1U) << 17U; | ||
1538 | } | ||
1539 | static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | ||
1540 | { | ||
1541 | return (v & 0x1U) << 18U; | ||
1542 | } | ||
1543 | static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) | ||
1544 | { | ||
1545 | return (v & 0xffffU) << 0U; | ||
1546 | } | ||
1547 | static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) | ||
1548 | { | ||
1549 | return (v & 0x1U) << 21U; | ||
1550 | } | ||
1551 | static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) | ||
1552 | { | ||
1553 | return 0x1U << 21U; | ||
1554 | } | ||
1555 | static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) | ||
1556 | { | ||
1557 | return (v & 0x1U) << 22U; | ||
1558 | } | ||
1559 | static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) | ||
1560 | { | ||
1561 | return 0x1U << 22U; | ||
1562 | } | ||
1563 | static inline u32 gr_fecs_host_int_clear_r(void) | ||
1564 | { | ||
1565 | return 0x00409c20U; | ||
1566 | } | ||
1567 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) | ||
1568 | { | ||
1569 | return (v & 0x1U) << 1U; | ||
1570 | } | ||
1571 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) | ||
1572 | { | ||
1573 | return 0x2U; | ||
1574 | } | ||
1575 | static inline u32 gr_fecs_host_int_enable_r(void) | ||
1576 | { | ||
1577 | return 0x00409c24U; | ||
1578 | } | ||
1579 | static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) | ||
1580 | { | ||
1581 | return 0x2U; | ||
1582 | } | ||
1583 | static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) | ||
1584 | { | ||
1585 | return 0x10000U; | ||
1586 | } | ||
1587 | static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) | ||
1588 | { | ||
1589 | return 0x20000U; | ||
1590 | } | ||
1591 | static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) | ||
1592 | { | ||
1593 | return 0x40000U; | ||
1594 | } | ||
1595 | static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) | ||
1596 | { | ||
1597 | return 0x80000U; | ||
1598 | } | ||
1599 | static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) | ||
1600 | { | ||
1601 | return 0x00409614U; | ||
1602 | } | ||
1603 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) | ||
1604 | { | ||
1605 | return 0x0U; | ||
1606 | } | ||
1607 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) | ||
1608 | { | ||
1609 | return 0x0U; | ||
1610 | } | ||
1611 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) | ||
1612 | { | ||
1613 | return 0x0U; | ||
1614 | } | ||
1615 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) | ||
1616 | { | ||
1617 | return 0x10U; | ||
1618 | } | ||
1619 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) | ||
1620 | { | ||
1621 | return 0x20U; | ||
1622 | } | ||
1623 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) | ||
1624 | { | ||
1625 | return 0x40U; | ||
1626 | } | ||
1627 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) | ||
1628 | { | ||
1629 | return 0x0U; | ||
1630 | } | ||
1631 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) | ||
1632 | { | ||
1633 | return 0x100U; | ||
1634 | } | ||
1635 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) | ||
1636 | { | ||
1637 | return 0x0U; | ||
1638 | } | ||
1639 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) | ||
1640 | { | ||
1641 | return 0x200U; | ||
1642 | } | ||
1643 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) | ||
1644 | { | ||
1645 | return 1U; | ||
1646 | } | ||
1647 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) | ||
1648 | { | ||
1649 | return (v & 0x1U) << 10U; | ||
1650 | } | ||
1651 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) | ||
1652 | { | ||
1653 | return 0x1U << 10U; | ||
1654 | } | ||
1655 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) | ||
1656 | { | ||
1657 | return (r >> 10U) & 0x1U; | ||
1658 | } | ||
1659 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) | ||
1660 | { | ||
1661 | return 0x0U; | ||
1662 | } | ||
1663 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) | ||
1664 | { | ||
1665 | return 0x400U; | ||
1666 | } | ||
1667 | static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) | ||
1668 | { | ||
1669 | return 0x0040960cU; | ||
1670 | } | ||
1671 | static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) | ||
1672 | { | ||
1673 | return 0x00409800U + i*4U; | ||
1674 | } | ||
1675 | static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) | ||
1676 | { | ||
1677 | return 0x00000010U; | ||
1678 | } | ||
1679 | static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) | ||
1680 | { | ||
1681 | return (v & 0xffffffffU) << 0U; | ||
1682 | } | ||
1683 | static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) | ||
1684 | { | ||
1685 | return 0x00000001U; | ||
1686 | } | ||
1687 | static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) | ||
1688 | { | ||
1689 | return 0x00000002U; | ||
1690 | } | ||
1691 | static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) | ||
1692 | { | ||
1693 | return 0x004098c0U + i*4U; | ||
1694 | } | ||
1695 | static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) | ||
1696 | { | ||
1697 | return (v & 0xffffffffU) << 0U; | ||
1698 | } | ||
1699 | static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) | ||
1700 | { | ||
1701 | return 0x00409840U + i*4U; | ||
1702 | } | ||
1703 | static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) | ||
1704 | { | ||
1705 | return (v & 0xffffffffU) << 0U; | ||
1706 | } | ||
1707 | static inline u32 gr_fecs_fs_r(void) | ||
1708 | { | ||
1709 | return 0x00409604U; | ||
1710 | } | ||
1711 | static inline u32 gr_fecs_fs_num_available_gpcs_s(void) | ||
1712 | { | ||
1713 | return 5U; | ||
1714 | } | ||
1715 | static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) | ||
1716 | { | ||
1717 | return (v & 0x1fU) << 0U; | ||
1718 | } | ||
1719 | static inline u32 gr_fecs_fs_num_available_gpcs_m(void) | ||
1720 | { | ||
1721 | return 0x1fU << 0U; | ||
1722 | } | ||
1723 | static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) | ||
1724 | { | ||
1725 | return (r >> 0U) & 0x1fU; | ||
1726 | } | ||
1727 | static inline u32 gr_fecs_fs_num_available_fbps_s(void) | ||
1728 | { | ||
1729 | return 5U; | ||
1730 | } | ||
1731 | static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) | ||
1732 | { | ||
1733 | return (v & 0x1fU) << 16U; | ||
1734 | } | ||
1735 | static inline u32 gr_fecs_fs_num_available_fbps_m(void) | ||
1736 | { | ||
1737 | return 0x1fU << 16U; | ||
1738 | } | ||
1739 | static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) | ||
1740 | { | ||
1741 | return (r >> 16U) & 0x1fU; | ||
1742 | } | ||
1743 | static inline u32 gr_fecs_cfg_r(void) | ||
1744 | { | ||
1745 | return 0x00409620U; | ||
1746 | } | ||
1747 | static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) | ||
1748 | { | ||
1749 | return (r >> 0U) & 0xffU; | ||
1750 | } | ||
1751 | static inline u32 gr_fecs_rc_lanes_r(void) | ||
1752 | { | ||
1753 | return 0x00409880U; | ||
1754 | } | ||
1755 | static inline u32 gr_fecs_rc_lanes_num_chains_s(void) | ||
1756 | { | ||
1757 | return 6U; | ||
1758 | } | ||
1759 | static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) | ||
1760 | { | ||
1761 | return (v & 0x3fU) << 0U; | ||
1762 | } | ||
1763 | static inline u32 gr_fecs_rc_lanes_num_chains_m(void) | ||
1764 | { | ||
1765 | return 0x3fU << 0U; | ||
1766 | } | ||
1767 | static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) | ||
1768 | { | ||
1769 | return (r >> 0U) & 0x3fU; | ||
1770 | } | ||
1771 | static inline u32 gr_fecs_ctxsw_status_1_r(void) | ||
1772 | { | ||
1773 | return 0x00409400U; | ||
1774 | } | ||
1775 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) | ||
1776 | { | ||
1777 | return 1U; | ||
1778 | } | ||
1779 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) | ||
1780 | { | ||
1781 | return (v & 0x1U) << 12U; | ||
1782 | } | ||
1783 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) | ||
1784 | { | ||
1785 | return 0x1U << 12U; | ||
1786 | } | ||
1787 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) | ||
1788 | { | ||
1789 | return (r >> 12U) & 0x1U; | ||
1790 | } | ||
1791 | static inline u32 gr_fecs_arb_ctx_adr_r(void) | ||
1792 | { | ||
1793 | return 0x00409a24U; | ||
1794 | } | ||
1795 | static inline u32 gr_fecs_new_ctx_r(void) | ||
1796 | { | ||
1797 | return 0x00409b04U; | ||
1798 | } | ||
1799 | static inline u32 gr_fecs_new_ctx_ptr_s(void) | ||
1800 | { | ||
1801 | return 28U; | ||
1802 | } | ||
1803 | static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) | ||
1804 | { | ||
1805 | return (v & 0xfffffffU) << 0U; | ||
1806 | } | ||
1807 | static inline u32 gr_fecs_new_ctx_ptr_m(void) | ||
1808 | { | ||
1809 | return 0xfffffffU << 0U; | ||
1810 | } | ||
1811 | static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) | ||
1812 | { | ||
1813 | return (r >> 0U) & 0xfffffffU; | ||
1814 | } | ||
1815 | static inline u32 gr_fecs_new_ctx_target_s(void) | ||
1816 | { | ||
1817 | return 2U; | ||
1818 | } | ||
1819 | static inline u32 gr_fecs_new_ctx_target_f(u32 v) | ||
1820 | { | ||
1821 | return (v & 0x3U) << 28U; | ||
1822 | } | ||
1823 | static inline u32 gr_fecs_new_ctx_target_m(void) | ||
1824 | { | ||
1825 | return 0x3U << 28U; | ||
1826 | } | ||
1827 | static inline u32 gr_fecs_new_ctx_target_v(u32 r) | ||
1828 | { | ||
1829 | return (r >> 28U) & 0x3U; | ||
1830 | } | ||
1831 | static inline u32 gr_fecs_new_ctx_valid_s(void) | ||
1832 | { | ||
1833 | return 1U; | ||
1834 | } | ||
1835 | static inline u32 gr_fecs_new_ctx_valid_f(u32 v) | ||
1836 | { | ||
1837 | return (v & 0x1U) << 31U; | ||
1838 | } | ||
1839 | static inline u32 gr_fecs_new_ctx_valid_m(void) | ||
1840 | { | ||
1841 | return 0x1U << 31U; | ||
1842 | } | ||
1843 | static inline u32 gr_fecs_new_ctx_valid_v(u32 r) | ||
1844 | { | ||
1845 | return (r >> 31U) & 0x1U; | ||
1846 | } | ||
1847 | static inline u32 gr_fecs_arb_ctx_ptr_r(void) | ||
1848 | { | ||
1849 | return 0x00409a0cU; | ||
1850 | } | ||
1851 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) | ||
1852 | { | ||
1853 | return 28U; | ||
1854 | } | ||
1855 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) | ||
1856 | { | ||
1857 | return (v & 0xfffffffU) << 0U; | ||
1858 | } | ||
1859 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) | ||
1860 | { | ||
1861 | return 0xfffffffU << 0U; | ||
1862 | } | ||
1863 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) | ||
1864 | { | ||
1865 | return (r >> 0U) & 0xfffffffU; | ||
1866 | } | ||
1867 | static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) | ||
1868 | { | ||
1869 | return 2U; | ||
1870 | } | ||
1871 | static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) | ||
1872 | { | ||
1873 | return (v & 0x3U) << 28U; | ||
1874 | } | ||
1875 | static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) | ||
1876 | { | ||
1877 | return 0x3U << 28U; | ||
1878 | } | ||
1879 | static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) | ||
1880 | { | ||
1881 | return (r >> 28U) & 0x3U; | ||
1882 | } | ||
1883 | static inline u32 gr_fecs_arb_ctx_cmd_r(void) | ||
1884 | { | ||
1885 | return 0x00409a10U; | ||
1886 | } | ||
1887 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) | ||
1888 | { | ||
1889 | return 5U; | ||
1890 | } | ||
1891 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) | ||
1892 | { | ||
1893 | return (v & 0x1fU) << 0U; | ||
1894 | } | ||
1895 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) | ||
1896 | { | ||
1897 | return 0x1fU << 0U; | ||
1898 | } | ||
1899 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) | ||
1900 | { | ||
1901 | return (r >> 0U) & 0x1fU; | ||
1902 | } | ||
1903 | static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) | ||
1904 | { | ||
1905 | return 0x00409c00U; | ||
1906 | } | ||
1907 | static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) | ||
1908 | { | ||
1909 | return 0x00502c04U; | ||
1910 | } | ||
1911 | static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) | ||
1912 | { | ||
1913 | return 0x00502400U; | ||
1914 | } | ||
1915 | static inline u32 gr_fecs_ctxsw_idlestate_r(void) | ||
1916 | { | ||
1917 | return 0x00409420U; | ||
1918 | } | ||
1919 | static inline u32 gr_fecs_feature_override_ecc_r(void) | ||
1920 | { | ||
1921 | return 0x00409658U; | ||
1922 | } | ||
1923 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) | ||
1924 | { | ||
1925 | return (r >> 3U) & 0x1U; | ||
1926 | } | ||
1927 | static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) | ||
1928 | { | ||
1929 | return (r >> 15U) & 0x1U; | ||
1930 | } | ||
1931 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) | ||
1932 | { | ||
1933 | return (r >> 0U) & 0x1U; | ||
1934 | } | ||
1935 | static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) | ||
1936 | { | ||
1937 | return (r >> 12U) & 0x1U; | ||
1938 | } | ||
1939 | static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) | ||
1940 | { | ||
1941 | return 0x00502420U; | ||
1942 | } | ||
1943 | static inline u32 gr_rstr2d_gpc_map_r(u32 i) | ||
1944 | { | ||
1945 | return 0x0040780cU + i*4U; | ||
1946 | } | ||
1947 | static inline u32 gr_rstr2d_map_table_cfg_r(void) | ||
1948 | { | ||
1949 | return 0x004078bcU; | ||
1950 | } | ||
1951 | static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) | ||
1952 | { | ||
1953 | return (v & 0xffU) << 0U; | ||
1954 | } | ||
1955 | static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) | ||
1956 | { | ||
1957 | return (v & 0xffU) << 8U; | ||
1958 | } | ||
1959 | static inline u32 gr_pd_hww_esr_r(void) | ||
1960 | { | ||
1961 | return 0x00406018U; | ||
1962 | } | ||
1963 | static inline u32 gr_pd_hww_esr_reset_active_f(void) | ||
1964 | { | ||
1965 | return 0x40000000U; | ||
1966 | } | ||
1967 | static inline u32 gr_pd_hww_esr_en_enable_f(void) | ||
1968 | { | ||
1969 | return 0x80000000U; | ||
1970 | } | ||
1971 | static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) | ||
1972 | { | ||
1973 | return 0x00406028U + i*4U; | ||
1974 | } | ||
1975 | static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) | ||
1976 | { | ||
1977 | return 0x00000004U; | ||
1978 | } | ||
1979 | static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) | ||
1980 | { | ||
1981 | return (v & 0xfU) << 0U; | ||
1982 | } | ||
1983 | static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) | ||
1984 | { | ||
1985 | return (v & 0xfU) << 4U; | ||
1986 | } | ||
1987 | static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) | ||
1988 | { | ||
1989 | return (v & 0xfU) << 8U; | ||
1990 | } | ||
1991 | static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) | ||
1992 | { | ||
1993 | return (v & 0xfU) << 12U; | ||
1994 | } | ||
1995 | static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) | ||
1996 | { | ||
1997 | return (v & 0xfU) << 16U; | ||
1998 | } | ||
1999 | static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) | ||
2000 | { | ||
2001 | return (v & 0xfU) << 20U; | ||
2002 | } | ||
2003 | static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) | ||
2004 | { | ||
2005 | return (v & 0xfU) << 24U; | ||
2006 | } | ||
2007 | static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) | ||
2008 | { | ||
2009 | return (v & 0xfU) << 28U; | ||
2010 | } | ||
2011 | static inline u32 gr_pd_ab_dist_cfg0_r(void) | ||
2012 | { | ||
2013 | return 0x004064c0U; | ||
2014 | } | ||
2015 | static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) | ||
2016 | { | ||
2017 | return 0x80000000U; | ||
2018 | } | ||
2019 | static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) | ||
2020 | { | ||
2021 | return 0x0U; | ||
2022 | } | ||
2023 | static inline u32 gr_pd_ab_dist_cfg1_r(void) | ||
2024 | { | ||
2025 | return 0x004064c4U; | ||
2026 | } | ||
2027 | static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) | ||
2028 | { | ||
2029 | return 0xffffU; | ||
2030 | } | ||
2031 | static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) | ||
2032 | { | ||
2033 | return (v & 0xffffU) << 16U; | ||
2034 | } | ||
2035 | static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) | ||
2036 | { | ||
2037 | return 0x00000080U; | ||
2038 | } | ||
2039 | static inline u32 gr_pd_ab_dist_cfg2_r(void) | ||
2040 | { | ||
2041 | return 0x004064c8U; | ||
2042 | } | ||
2043 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) | ||
2044 | { | ||
2045 | return (v & 0x1fffU) << 0U; | ||
2046 | } | ||
2047 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) | ||
2048 | { | ||
2049 | return 0x00000380U; | ||
2050 | } | ||
2051 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) | ||
2052 | { | ||
2053 | return (v & 0x1fffU) << 16U; | ||
2054 | } | ||
2055 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) | ||
2056 | { | ||
2057 | return 0x00000020U; | ||
2058 | } | ||
2059 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) | ||
2060 | { | ||
2061 | return 0x00000302U; | ||
2062 | } | ||
2063 | static inline u32 gr_pd_dist_skip_table_r(u32 i) | ||
2064 | { | ||
2065 | return 0x004064d0U + i*4U; | ||
2066 | } | ||
2067 | static inline u32 gr_pd_dist_skip_table__size_1_v(void) | ||
2068 | { | ||
2069 | return 0x00000008U; | ||
2070 | } | ||
2071 | static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) | ||
2072 | { | ||
2073 | return (v & 0xffU) << 0U; | ||
2074 | } | ||
2075 | static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) | ||
2076 | { | ||
2077 | return (v & 0xffU) << 8U; | ||
2078 | } | ||
2079 | static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) | ||
2080 | { | ||
2081 | return (v & 0xffU) << 16U; | ||
2082 | } | ||
2083 | static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) | ||
2084 | { | ||
2085 | return (v & 0xffU) << 24U; | ||
2086 | } | ||
2087 | static inline u32 gr_ds_debug_r(void) | ||
2088 | { | ||
2089 | return 0x00405800U; | ||
2090 | } | ||
2091 | static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) | ||
2092 | { | ||
2093 | return 0x0U; | ||
2094 | } | ||
2095 | static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) | ||
2096 | { | ||
2097 | return 0x8000000U; | ||
2098 | } | ||
2099 | static inline u32 gr_ds_zbc_color_r_r(void) | ||
2100 | { | ||
2101 | return 0x00405804U; | ||
2102 | } | ||
2103 | static inline u32 gr_ds_zbc_color_r_val_f(u32 v) | ||
2104 | { | ||
2105 | return (v & 0xffffffffU) << 0U; | ||
2106 | } | ||
2107 | static inline u32 gr_ds_zbc_color_g_r(void) | ||
2108 | { | ||
2109 | return 0x00405808U; | ||
2110 | } | ||
2111 | static inline u32 gr_ds_zbc_color_g_val_f(u32 v) | ||
2112 | { | ||
2113 | return (v & 0xffffffffU) << 0U; | ||
2114 | } | ||
2115 | static inline u32 gr_ds_zbc_color_b_r(void) | ||
2116 | { | ||
2117 | return 0x0040580cU; | ||
2118 | } | ||
2119 | static inline u32 gr_ds_zbc_color_b_val_f(u32 v) | ||
2120 | { | ||
2121 | return (v & 0xffffffffU) << 0U; | ||
2122 | } | ||
2123 | static inline u32 gr_ds_zbc_color_a_r(void) | ||
2124 | { | ||
2125 | return 0x00405810U; | ||
2126 | } | ||
2127 | static inline u32 gr_ds_zbc_color_a_val_f(u32 v) | ||
2128 | { | ||
2129 | return (v & 0xffffffffU) << 0U; | ||
2130 | } | ||
2131 | static inline u32 gr_ds_zbc_color_fmt_r(void) | ||
2132 | { | ||
2133 | return 0x00405814U; | ||
2134 | } | ||
2135 | static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) | ||
2136 | { | ||
2137 | return (v & 0x7fU) << 0U; | ||
2138 | } | ||
2139 | static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) | ||
2140 | { | ||
2141 | return 0x0U; | ||
2142 | } | ||
2143 | static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) | ||
2144 | { | ||
2145 | return 0x00000001U; | ||
2146 | } | ||
2147 | static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) | ||
2148 | { | ||
2149 | return 0x00000002U; | ||
2150 | } | ||
2151 | static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | ||
2152 | { | ||
2153 | return 0x00000004U; | ||
2154 | } | ||
2155 | static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) | ||
2156 | { | ||
2157 | return 0x00000028U; | ||
2158 | } | ||
2159 | static inline u32 gr_ds_zbc_z_r(void) | ||
2160 | { | ||
2161 | return 0x00405818U; | ||
2162 | } | ||
2163 | static inline u32 gr_ds_zbc_z_val_s(void) | ||
2164 | { | ||
2165 | return 32U; | ||
2166 | } | ||
2167 | static inline u32 gr_ds_zbc_z_val_f(u32 v) | ||
2168 | { | ||
2169 | return (v & 0xffffffffU) << 0U; | ||
2170 | } | ||
2171 | static inline u32 gr_ds_zbc_z_val_m(void) | ||
2172 | { | ||
2173 | return 0xffffffffU << 0U; | ||
2174 | } | ||
2175 | static inline u32 gr_ds_zbc_z_val_v(u32 r) | ||
2176 | { | ||
2177 | return (r >> 0U) & 0xffffffffU; | ||
2178 | } | ||
2179 | static inline u32 gr_ds_zbc_z_val__init_v(void) | ||
2180 | { | ||
2181 | return 0x00000000U; | ||
2182 | } | ||
2183 | static inline u32 gr_ds_zbc_z_val__init_f(void) | ||
2184 | { | ||
2185 | return 0x0U; | ||
2186 | } | ||
2187 | static inline u32 gr_ds_zbc_z_fmt_r(void) | ||
2188 | { | ||
2189 | return 0x0040581cU; | ||
2190 | } | ||
2191 | static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) | ||
2192 | { | ||
2193 | return (v & 0x1U) << 0U; | ||
2194 | } | ||
2195 | static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) | ||
2196 | { | ||
2197 | return 0x0U; | ||
2198 | } | ||
2199 | static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) | ||
2200 | { | ||
2201 | return 0x00000001U; | ||
2202 | } | ||
2203 | static inline u32 gr_ds_zbc_tbl_index_r(void) | ||
2204 | { | ||
2205 | return 0x00405820U; | ||
2206 | } | ||
2207 | static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) | ||
2208 | { | ||
2209 | return (v & 0xfU) << 0U; | ||
2210 | } | ||
2211 | static inline u32 gr_ds_zbc_tbl_ld_r(void) | ||
2212 | { | ||
2213 | return 0x00405824U; | ||
2214 | } | ||
2215 | static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) | ||
2216 | { | ||
2217 | return 0x0U; | ||
2218 | } | ||
2219 | static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) | ||
2220 | { | ||
2221 | return 0x1U; | ||
2222 | } | ||
2223 | static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) | ||
2224 | { | ||
2225 | return 0x0U; | ||
2226 | } | ||
2227 | static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) | ||
2228 | { | ||
2229 | return 0x4U; | ||
2230 | } | ||
2231 | static inline u32 gr_ds_tga_constraintlogic_beta_r(void) | ||
2232 | { | ||
2233 | return 0x00405830U; | ||
2234 | } | ||
2235 | static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) | ||
2236 | { | ||
2237 | return (v & 0x3fffffU) << 0U; | ||
2238 | } | ||
2239 | static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) | ||
2240 | { | ||
2241 | return 0x0040585cU; | ||
2242 | } | ||
2243 | static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) | ||
2244 | { | ||
2245 | return (v & 0xffffU) << 0U; | ||
2246 | } | ||
2247 | static inline u32 gr_ds_hww_esr_r(void) | ||
2248 | { | ||
2249 | return 0x00405840U; | ||
2250 | } | ||
2251 | static inline u32 gr_ds_hww_esr_reset_s(void) | ||
2252 | { | ||
2253 | return 1U; | ||
2254 | } | ||
2255 | static inline u32 gr_ds_hww_esr_reset_f(u32 v) | ||
2256 | { | ||
2257 | return (v & 0x1U) << 30U; | ||
2258 | } | ||
2259 | static inline u32 gr_ds_hww_esr_reset_m(void) | ||
2260 | { | ||
2261 | return 0x1U << 30U; | ||
2262 | } | ||
2263 | static inline u32 gr_ds_hww_esr_reset_v(u32 r) | ||
2264 | { | ||
2265 | return (r >> 30U) & 0x1U; | ||
2266 | } | ||
2267 | static inline u32 gr_ds_hww_esr_reset_task_v(void) | ||
2268 | { | ||
2269 | return 0x00000001U; | ||
2270 | } | ||
2271 | static inline u32 gr_ds_hww_esr_reset_task_f(void) | ||
2272 | { | ||
2273 | return 0x40000000U; | ||
2274 | } | ||
2275 | static inline u32 gr_ds_hww_esr_en_enabled_f(void) | ||
2276 | { | ||
2277 | return 0x80000000U; | ||
2278 | } | ||
2279 | static inline u32 gr_ds_hww_esr_2_r(void) | ||
2280 | { | ||
2281 | return 0x00405848U; | ||
2282 | } | ||
2283 | static inline u32 gr_ds_hww_esr_2_reset_s(void) | ||
2284 | { | ||
2285 | return 1U; | ||
2286 | } | ||
2287 | static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) | ||
2288 | { | ||
2289 | return (v & 0x1U) << 30U; | ||
2290 | } | ||
2291 | static inline u32 gr_ds_hww_esr_2_reset_m(void) | ||
2292 | { | ||
2293 | return 0x1U << 30U; | ||
2294 | } | ||
2295 | static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) | ||
2296 | { | ||
2297 | return (r >> 30U) & 0x1U; | ||
2298 | } | ||
2299 | static inline u32 gr_ds_hww_esr_2_reset_task_v(void) | ||
2300 | { | ||
2301 | return 0x00000001U; | ||
2302 | } | ||
2303 | static inline u32 gr_ds_hww_esr_2_reset_task_f(void) | ||
2304 | { | ||
2305 | return 0x40000000U; | ||
2306 | } | ||
2307 | static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) | ||
2308 | { | ||
2309 | return 0x80000000U; | ||
2310 | } | ||
2311 | static inline u32 gr_ds_hww_report_mask_r(void) | ||
2312 | { | ||
2313 | return 0x00405844U; | ||
2314 | } | ||
2315 | static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) | ||
2316 | { | ||
2317 | return 0x1U; | ||
2318 | } | ||
2319 | static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) | ||
2320 | { | ||
2321 | return 0x2U; | ||
2322 | } | ||
2323 | static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) | ||
2324 | { | ||
2325 | return 0x4U; | ||
2326 | } | ||
2327 | static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) | ||
2328 | { | ||
2329 | return 0x8U; | ||
2330 | } | ||
2331 | static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) | ||
2332 | { | ||
2333 | return 0x10U; | ||
2334 | } | ||
2335 | static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) | ||
2336 | { | ||
2337 | return 0x20U; | ||
2338 | } | ||
2339 | static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) | ||
2340 | { | ||
2341 | return 0x40U; | ||
2342 | } | ||
2343 | static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) | ||
2344 | { | ||
2345 | return 0x80U; | ||
2346 | } | ||
2347 | static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) | ||
2348 | { | ||
2349 | return 0x100U; | ||
2350 | } | ||
2351 | static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) | ||
2352 | { | ||
2353 | return 0x200U; | ||
2354 | } | ||
2355 | static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) | ||
2356 | { | ||
2357 | return 0x400U; | ||
2358 | } | ||
2359 | static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) | ||
2360 | { | ||
2361 | return 0x800U; | ||
2362 | } | ||
2363 | static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) | ||
2364 | { | ||
2365 | return 0x1000U; | ||
2366 | } | ||
2367 | static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) | ||
2368 | { | ||
2369 | return 0x2000U; | ||
2370 | } | ||
2371 | static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) | ||
2372 | { | ||
2373 | return 0x4000U; | ||
2374 | } | ||
2375 | static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) | ||
2376 | { | ||
2377 | return 0x8000U; | ||
2378 | } | ||
2379 | static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) | ||
2380 | { | ||
2381 | return 0x10000U; | ||
2382 | } | ||
2383 | static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) | ||
2384 | { | ||
2385 | return 0x20000U; | ||
2386 | } | ||
2387 | static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) | ||
2388 | { | ||
2389 | return 0x40000U; | ||
2390 | } | ||
2391 | static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) | ||
2392 | { | ||
2393 | return 0x80000U; | ||
2394 | } | ||
2395 | static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) | ||
2396 | { | ||
2397 | return 0x100000U; | ||
2398 | } | ||
2399 | static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) | ||
2400 | { | ||
2401 | return 0x200000U; | ||
2402 | } | ||
2403 | static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) | ||
2404 | { | ||
2405 | return 0x400000U; | ||
2406 | } | ||
2407 | static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) | ||
2408 | { | ||
2409 | return 0x800000U; | ||
2410 | } | ||
2411 | static inline u32 gr_ds_hww_report_mask_2_r(void) | ||
2412 | { | ||
2413 | return 0x0040584cU; | ||
2414 | } | ||
2415 | static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) | ||
2416 | { | ||
2417 | return 0x1U; | ||
2418 | } | ||
2419 | static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) | ||
2420 | { | ||
2421 | return 0x00405870U + i*4U; | ||
2422 | } | ||
2423 | static inline u32 gr_scc_bundle_cb_base_r(void) | ||
2424 | { | ||
2425 | return 0x00408004U; | ||
2426 | } | ||
2427 | static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) | ||
2428 | { | ||
2429 | return (v & 0xffffffffU) << 0U; | ||
2430 | } | ||
2431 | static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) | ||
2432 | { | ||
2433 | return 0x00000008U; | ||
2434 | } | ||
2435 | static inline u32 gr_scc_bundle_cb_size_r(void) | ||
2436 | { | ||
2437 | return 0x00408008U; | ||
2438 | } | ||
2439 | static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) | ||
2440 | { | ||
2441 | return (v & 0x7ffU) << 0U; | ||
2442 | } | ||
2443 | static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) | ||
2444 | { | ||
2445 | return 0x00000030U; | ||
2446 | } | ||
2447 | static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) | ||
2448 | { | ||
2449 | return 0x00000100U; | ||
2450 | } | ||
2451 | static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) | ||
2452 | { | ||
2453 | return 0x00000000U; | ||
2454 | } | ||
2455 | static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) | ||
2456 | { | ||
2457 | return 0x0U; | ||
2458 | } | ||
2459 | static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) | ||
2460 | { | ||
2461 | return 0x80000000U; | ||
2462 | } | ||
2463 | static inline u32 gr_scc_pagepool_base_r(void) | ||
2464 | { | ||
2465 | return 0x0040800cU; | ||
2466 | } | ||
2467 | static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) | ||
2468 | { | ||
2469 | return (v & 0xffffffffU) << 0U; | ||
2470 | } | ||
2471 | static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) | ||
2472 | { | ||
2473 | return 0x00000008U; | ||
2474 | } | ||
2475 | static inline u32 gr_scc_pagepool_r(void) | ||
2476 | { | ||
2477 | return 0x00408010U; | ||
2478 | } | ||
2479 | static inline u32 gr_scc_pagepool_total_pages_f(u32 v) | ||
2480 | { | ||
2481 | return (v & 0x3ffU) << 0U; | ||
2482 | } | ||
2483 | static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) | ||
2484 | { | ||
2485 | return 0x00000000U; | ||
2486 | } | ||
2487 | static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) | ||
2488 | { | ||
2489 | return 0x00000200U; | ||
2490 | } | ||
2491 | static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) | ||
2492 | { | ||
2493 | return 0x00000100U; | ||
2494 | } | ||
2495 | static inline u32 gr_scc_pagepool_max_valid_pages_s(void) | ||
2496 | { | ||
2497 | return 10U; | ||
2498 | } | ||
2499 | static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) | ||
2500 | { | ||
2501 | return (v & 0x3ffU) << 10U; | ||
2502 | } | ||
2503 | static inline u32 gr_scc_pagepool_max_valid_pages_m(void) | ||
2504 | { | ||
2505 | return 0x3ffU << 10U; | ||
2506 | } | ||
2507 | static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) | ||
2508 | { | ||
2509 | return (r >> 10U) & 0x3ffU; | ||
2510 | } | ||
2511 | static inline u32 gr_scc_pagepool_valid_true_f(void) | ||
2512 | { | ||
2513 | return 0x80000000U; | ||
2514 | } | ||
2515 | static inline u32 gr_scc_init_r(void) | ||
2516 | { | ||
2517 | return 0x0040802cU; | ||
2518 | } | ||
2519 | static inline u32 gr_scc_init_ram_trigger_f(void) | ||
2520 | { | ||
2521 | return 0x1U; | ||
2522 | } | ||
2523 | static inline u32 gr_scc_hww_esr_r(void) | ||
2524 | { | ||
2525 | return 0x00408030U; | ||
2526 | } | ||
2527 | static inline u32 gr_scc_hww_esr_reset_active_f(void) | ||
2528 | { | ||
2529 | return 0x40000000U; | ||
2530 | } | ||
2531 | static inline u32 gr_scc_hww_esr_en_enable_f(void) | ||
2532 | { | ||
2533 | return 0x80000000U; | ||
2534 | } | ||
2535 | static inline u32 gr_sked_hww_esr_r(void) | ||
2536 | { | ||
2537 | return 0x00407020U; | ||
2538 | } | ||
2539 | static inline u32 gr_sked_hww_esr_reset_active_f(void) | ||
2540 | { | ||
2541 | return 0x40000000U; | ||
2542 | } | ||
2543 | static inline u32 gr_sked_hww_esr_en_r(void) | ||
2544 | { | ||
2545 | return 0x00407024U; | ||
2546 | } | ||
2547 | static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) | ||
2548 | { | ||
2549 | return 0x1U << 25U; | ||
2550 | } | ||
2551 | static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) | ||
2552 | { | ||
2553 | return 0x0U; | ||
2554 | } | ||
2555 | static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) | ||
2556 | { | ||
2557 | return 0x2000000U; | ||
2558 | } | ||
2559 | static inline u32 gr_cwd_fs_r(void) | ||
2560 | { | ||
2561 | return 0x00405b00U; | ||
2562 | } | ||
2563 | static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) | ||
2564 | { | ||
2565 | return (v & 0xffU) << 0U; | ||
2566 | } | ||
2567 | static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) | ||
2568 | { | ||
2569 | return (v & 0xffU) << 8U; | ||
2570 | } | ||
2571 | static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) | ||
2572 | { | ||
2573 | return 0x00405b60U + i*4U; | ||
2574 | } | ||
2575 | static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) | ||
2576 | { | ||
2577 | return 4U; | ||
2578 | } | ||
2579 | static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) | ||
2580 | { | ||
2581 | return (v & 0xfU) << 0U; | ||
2582 | } | ||
2583 | static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) | ||
2584 | { | ||
2585 | return 4U; | ||
2586 | } | ||
2587 | static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) | ||
2588 | { | ||
2589 | return (v & 0xfU) << 4U; | ||
2590 | } | ||
2591 | static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) | ||
2592 | { | ||
2593 | return (v & 0xfU) << 8U; | ||
2594 | } | ||
2595 | static inline u32 gr_cwd_sm_id_r(u32 i) | ||
2596 | { | ||
2597 | return 0x00405ba0U + i*4U; | ||
2598 | } | ||
2599 | static inline u32 gr_cwd_sm_id__size_1_v(void) | ||
2600 | { | ||
2601 | return 0x00000010U; | ||
2602 | } | ||
2603 | static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) | ||
2604 | { | ||
2605 | return (v & 0xffU) << 0U; | ||
2606 | } | ||
2607 | static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) | ||
2608 | { | ||
2609 | return (v & 0xffU) << 8U; | ||
2610 | } | ||
2611 | static inline u32 gr_gpc0_fs_gpc_r(void) | ||
2612 | { | ||
2613 | return 0x00502608U; | ||
2614 | } | ||
2615 | static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) | ||
2616 | { | ||
2617 | return (r >> 0U) & 0x1fU; | ||
2618 | } | ||
2619 | static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) | ||
2620 | { | ||
2621 | return (r >> 16U) & 0x1fU; | ||
2622 | } | ||
2623 | static inline u32 gr_gpc0_cfg_r(void) | ||
2624 | { | ||
2625 | return 0x00502620U; | ||
2626 | } | ||
2627 | static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) | ||
2628 | { | ||
2629 | return (r >> 0U) & 0xffU; | ||
2630 | } | ||
2631 | static inline u32 gr_gpccs_rc_lanes_r(void) | ||
2632 | { | ||
2633 | return 0x00502880U; | ||
2634 | } | ||
2635 | static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) | ||
2636 | { | ||
2637 | return 6U; | ||
2638 | } | ||
2639 | static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) | ||
2640 | { | ||
2641 | return (v & 0x3fU) << 0U; | ||
2642 | } | ||
2643 | static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) | ||
2644 | { | ||
2645 | return 0x3fU << 0U; | ||
2646 | } | ||
2647 | static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) | ||
2648 | { | ||
2649 | return (r >> 0U) & 0x3fU; | ||
2650 | } | ||
2651 | static inline u32 gr_gpccs_rc_lane_size_r(void) | ||
2652 | { | ||
2653 | return 0x00502910U; | ||
2654 | } | ||
2655 | static inline u32 gr_gpccs_rc_lane_size_v_s(void) | ||
2656 | { | ||
2657 | return 24U; | ||
2658 | } | ||
2659 | static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) | ||
2660 | { | ||
2661 | return (v & 0xffffffU) << 0U; | ||
2662 | } | ||
2663 | static inline u32 gr_gpccs_rc_lane_size_v_m(void) | ||
2664 | { | ||
2665 | return 0xffffffU << 0U; | ||
2666 | } | ||
2667 | static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) | ||
2668 | { | ||
2669 | return (r >> 0U) & 0xffffffU; | ||
2670 | } | ||
2671 | static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) | ||
2672 | { | ||
2673 | return 0x00000000U; | ||
2674 | } | ||
2675 | static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) | ||
2676 | { | ||
2677 | return 0x0U; | ||
2678 | } | ||
2679 | static inline u32 gr_gpc0_zcull_fs_r(void) | ||
2680 | { | ||
2681 | return 0x00500910U; | ||
2682 | } | ||
2683 | static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) | ||
2684 | { | ||
2685 | return (v & 0x1ffU) << 0U; | ||
2686 | } | ||
2687 | static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) | ||
2688 | { | ||
2689 | return (v & 0xfU) << 16U; | ||
2690 | } | ||
2691 | static inline u32 gr_gpc0_zcull_ram_addr_r(void) | ||
2692 | { | ||
2693 | return 0x00500914U; | ||
2694 | } | ||
2695 | static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) | ||
2696 | { | ||
2697 | return (v & 0xfU) << 0U; | ||
2698 | } | ||
2699 | static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) | ||
2700 | { | ||
2701 | return (v & 0xfU) << 8U; | ||
2702 | } | ||
2703 | static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) | ||
2704 | { | ||
2705 | return 0x00500918U; | ||
2706 | } | ||
2707 | static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) | ||
2708 | { | ||
2709 | return (v & 0xffffffU) << 0U; | ||
2710 | } | ||
2711 | static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) | ||
2712 | { | ||
2713 | return 0x00800000U; | ||
2714 | } | ||
2715 | static inline u32 gr_gpc0_zcull_total_ram_size_r(void) | ||
2716 | { | ||
2717 | return 0x00500920U; | ||
2718 | } | ||
2719 | static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) | ||
2720 | { | ||
2721 | return (v & 0xffffU) << 0U; | ||
2722 | } | ||
2723 | static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) | ||
2724 | { | ||
2725 | return 0x00500a04U + i*32U; | ||
2726 | } | ||
2727 | static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) | ||
2728 | { | ||
2729 | return 0x00000040U; | ||
2730 | } | ||
2731 | static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) | ||
2732 | { | ||
2733 | return 0x00000010U; | ||
2734 | } | ||
2735 | static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) | ||
2736 | { | ||
2737 | return 0x00500c10U + i*4U; | ||
2738 | } | ||
2739 | static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) | ||
2740 | { | ||
2741 | return (v & 0xffU) << 0U; | ||
2742 | } | ||
2743 | static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) | ||
2744 | { | ||
2745 | return 0x00500c30U + i*4U; | ||
2746 | } | ||
2747 | static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) | ||
2748 | { | ||
2749 | return (r >> 0U) & 0xffU; | ||
2750 | } | ||
2751 | static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) | ||
2752 | { | ||
2753 | return 0x00504088U; | ||
2754 | } | ||
2755 | static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) | ||
2756 | { | ||
2757 | return (v & 0xffffU) << 0U; | ||
2758 | } | ||
2759 | static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) | ||
2760 | { | ||
2761 | return 0x00504608U; | ||
2762 | } | ||
2763 | static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) | ||
2764 | { | ||
2765 | return (v & 0xffffU) << 0U; | ||
2766 | } | ||
2767 | static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) | ||
2768 | { | ||
2769 | return (r >> 0U) & 0xffffU; | ||
2770 | } | ||
2771 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) | ||
2772 | { | ||
2773 | return 0x00504330U; | ||
2774 | } | ||
2775 | static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) | ||
2776 | { | ||
2777 | return (r >> 0U) & 0xffU; | ||
2778 | } | ||
2779 | static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) | ||
2780 | { | ||
2781 | return (r >> 8U) & 0xfffU; | ||
2782 | } | ||
2783 | static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) | ||
2784 | { | ||
2785 | return (r >> 20U) & 0xfffU; | ||
2786 | } | ||
2787 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) | ||
2788 | { | ||
2789 | return 0x00503018U; | ||
2790 | } | ||
2791 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) | ||
2792 | { | ||
2793 | return 0x1U << 0U; | ||
2794 | } | ||
2795 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) | ||
2796 | { | ||
2797 | return 0x1U; | ||
2798 | } | ||
2799 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) | ||
2800 | { | ||
2801 | return 0x005030c0U; | ||
2802 | } | ||
2803 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) | ||
2804 | { | ||
2805 | return (v & 0x3fffffU) << 0U; | ||
2806 | } | ||
2807 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) | ||
2808 | { | ||
2809 | return 0x3fffffU << 0U; | ||
2810 | } | ||
2811 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) | ||
2812 | { | ||
2813 | return 0x00000800U; | ||
2814 | } | ||
2815 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) | ||
2816 | { | ||
2817 | return 0x00001100U; | ||
2818 | } | ||
2819 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) | ||
2820 | { | ||
2821 | return 0x00000020U; | ||
2822 | } | ||
2823 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) | ||
2824 | { | ||
2825 | return 0x005030f4U; | ||
2826 | } | ||
2827 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) | ||
2828 | { | ||
2829 | return 0x005030e4U; | ||
2830 | } | ||
2831 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) | ||
2832 | { | ||
2833 | return (v & 0xffffU) << 0U; | ||
2834 | } | ||
2835 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) | ||
2836 | { | ||
2837 | return 0xffffU << 0U; | ||
2838 | } | ||
2839 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) | ||
2840 | { | ||
2841 | return 0x00000800U; | ||
2842 | } | ||
2843 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) | ||
2844 | { | ||
2845 | return 0x00000020U; | ||
2846 | } | ||
2847 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) | ||
2848 | { | ||
2849 | return 0x005030f8U; | ||
2850 | } | ||
2851 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) | ||
2852 | { | ||
2853 | return 0x005030f0U; | ||
2854 | } | ||
2855 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) | ||
2856 | { | ||
2857 | return (v & 0x3fffffU) << 0U; | ||
2858 | } | ||
2859 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) | ||
2860 | { | ||
2861 | return 0x00000800U; | ||
2862 | } | ||
2863 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) | ||
2864 | { | ||
2865 | return 0x00419e00U; | ||
2866 | } | ||
2867 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) | ||
2868 | { | ||
2869 | return (v & 0xffffffffU) << 0U; | ||
2870 | } | ||
2871 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) | ||
2872 | { | ||
2873 | return 0x00419e04U; | ||
2874 | } | ||
2875 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) | ||
2876 | { | ||
2877 | return 21U; | ||
2878 | } | ||
2879 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) | ||
2880 | { | ||
2881 | return (v & 0x1fffffU) << 0U; | ||
2882 | } | ||
2883 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) | ||
2884 | { | ||
2885 | return 0x1fffffU << 0U; | ||
2886 | } | ||
2887 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) | ||
2888 | { | ||
2889 | return (r >> 0U) & 0x1fffffU; | ||
2890 | } | ||
2891 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) | ||
2892 | { | ||
2893 | return 0x80U; | ||
2894 | } | ||
2895 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) | ||
2896 | { | ||
2897 | return 1U; | ||
2898 | } | ||
2899 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) | ||
2900 | { | ||
2901 | return (v & 0x1U) << 31U; | ||
2902 | } | ||
2903 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) | ||
2904 | { | ||
2905 | return 0x1U << 31U; | ||
2906 | } | ||
2907 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) | ||
2908 | { | ||
2909 | return (r >> 31U) & 0x1U; | ||
2910 | } | ||
2911 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) | ||
2912 | { | ||
2913 | return 0x80000000U; | ||
2914 | } | ||
2915 | static inline u32 gr_gpccs_falcon_addr_r(void) | ||
2916 | { | ||
2917 | return 0x0041a0acU; | ||
2918 | } | ||
2919 | static inline u32 gr_gpccs_falcon_addr_lsb_s(void) | ||
2920 | { | ||
2921 | return 6U; | ||
2922 | } | ||
2923 | static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) | ||
2924 | { | ||
2925 | return (v & 0x3fU) << 0U; | ||
2926 | } | ||
2927 | static inline u32 gr_gpccs_falcon_addr_lsb_m(void) | ||
2928 | { | ||
2929 | return 0x3fU << 0U; | ||
2930 | } | ||
2931 | static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) | ||
2932 | { | ||
2933 | return (r >> 0U) & 0x3fU; | ||
2934 | } | ||
2935 | static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) | ||
2936 | { | ||
2937 | return 0x00000000U; | ||
2938 | } | ||
2939 | static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) | ||
2940 | { | ||
2941 | return 0x0U; | ||
2942 | } | ||
2943 | static inline u32 gr_gpccs_falcon_addr_msb_s(void) | ||
2944 | { | ||
2945 | return 6U; | ||
2946 | } | ||
2947 | static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) | ||
2948 | { | ||
2949 | return (v & 0x3fU) << 6U; | ||
2950 | } | ||
2951 | static inline u32 gr_gpccs_falcon_addr_msb_m(void) | ||
2952 | { | ||
2953 | return 0x3fU << 6U; | ||
2954 | } | ||
2955 | static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) | ||
2956 | { | ||
2957 | return (r >> 6U) & 0x3fU; | ||
2958 | } | ||
2959 | static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) | ||
2960 | { | ||
2961 | return 0x00000000U; | ||
2962 | } | ||
2963 | static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) | ||
2964 | { | ||
2965 | return 0x0U; | ||
2966 | } | ||
2967 | static inline u32 gr_gpccs_falcon_addr_ext_s(void) | ||
2968 | { | ||
2969 | return 12U; | ||
2970 | } | ||
2971 | static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) | ||
2972 | { | ||
2973 | return (v & 0xfffU) << 0U; | ||
2974 | } | ||
2975 | static inline u32 gr_gpccs_falcon_addr_ext_m(void) | ||
2976 | { | ||
2977 | return 0xfffU << 0U; | ||
2978 | } | ||
2979 | static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) | ||
2980 | { | ||
2981 | return (r >> 0U) & 0xfffU; | ||
2982 | } | ||
2983 | static inline u32 gr_gpccs_cpuctl_r(void) | ||
2984 | { | ||
2985 | return 0x0041a100U; | ||
2986 | } | ||
2987 | static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) | ||
2988 | { | ||
2989 | return (v & 0x1U) << 1U; | ||
2990 | } | ||
2991 | static inline u32 gr_gpccs_dmactl_r(void) | ||
2992 | { | ||
2993 | return 0x0041a10cU; | ||
2994 | } | ||
2995 | static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) | ||
2996 | { | ||
2997 | return (v & 0x1U) << 0U; | ||
2998 | } | ||
2999 | static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) | ||
3000 | { | ||
3001 | return 0x1U << 1U; | ||
3002 | } | ||
3003 | static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) | ||
3004 | { | ||
3005 | return 0x1U << 2U; | ||
3006 | } | ||
3007 | static inline u32 gr_gpccs_imemc_r(u32 i) | ||
3008 | { | ||
3009 | return 0x0041a180U + i*16U; | ||
3010 | } | ||
3011 | static inline u32 gr_gpccs_imemc_offs_f(u32 v) | ||
3012 | { | ||
3013 | return (v & 0x3fU) << 2U; | ||
3014 | } | ||
3015 | static inline u32 gr_gpccs_imemc_blk_f(u32 v) | ||
3016 | { | ||
3017 | return (v & 0xffU) << 8U; | ||
3018 | } | ||
3019 | static inline u32 gr_gpccs_imemc_aincw_f(u32 v) | ||
3020 | { | ||
3021 | return (v & 0x1U) << 24U; | ||
3022 | } | ||
3023 | static inline u32 gr_gpccs_imemd_r(u32 i) | ||
3024 | { | ||
3025 | return 0x0041a184U + i*16U; | ||
3026 | } | ||
3027 | static inline u32 gr_gpccs_imemt_r(u32 i) | ||
3028 | { | ||
3029 | return 0x0041a188U + i*16U; | ||
3030 | } | ||
3031 | static inline u32 gr_gpccs_imemt__size_1_v(void) | ||
3032 | { | ||
3033 | return 0x00000004U; | ||
3034 | } | ||
3035 | static inline u32 gr_gpccs_imemt_tag_f(u32 v) | ||
3036 | { | ||
3037 | return (v & 0xffffU) << 0U; | ||
3038 | } | ||
3039 | static inline u32 gr_gpccs_dmemc_r(u32 i) | ||
3040 | { | ||
3041 | return 0x0041a1c0U + i*8U; | ||
3042 | } | ||
3043 | static inline u32 gr_gpccs_dmemc_offs_f(u32 v) | ||
3044 | { | ||
3045 | return (v & 0x3fU) << 2U; | ||
3046 | } | ||
3047 | static inline u32 gr_gpccs_dmemc_blk_f(u32 v) | ||
3048 | { | ||
3049 | return (v & 0xffU) << 8U; | ||
3050 | } | ||
3051 | static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) | ||
3052 | { | ||
3053 | return (v & 0x1U) << 24U; | ||
3054 | } | ||
3055 | static inline u32 gr_gpccs_dmemd_r(u32 i) | ||
3056 | { | ||
3057 | return 0x0041a1c4U + i*8U; | ||
3058 | } | ||
3059 | static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) | ||
3060 | { | ||
3061 | return 0x0041a800U + i*4U; | ||
3062 | } | ||
3063 | static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) | ||
3064 | { | ||
3065 | return (v & 0xffffffffU) << 0U; | ||
3066 | } | ||
3067 | static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) | ||
3068 | { | ||
3069 | return 0x00418e24U; | ||
3070 | } | ||
3071 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) | ||
3072 | { | ||
3073 | return 32U; | ||
3074 | } | ||
3075 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) | ||
3076 | { | ||
3077 | return (v & 0xffffffffU) << 0U; | ||
3078 | } | ||
3079 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) | ||
3080 | { | ||
3081 | return 0xffffffffU << 0U; | ||
3082 | } | ||
3083 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) | ||
3084 | { | ||
3085 | return (r >> 0U) & 0xffffffffU; | ||
3086 | } | ||
3087 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) | ||
3088 | { | ||
3089 | return 0x00000000U; | ||
3090 | } | ||
3091 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) | ||
3092 | { | ||
3093 | return 0x0U; | ||
3094 | } | ||
3095 | static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) | ||
3096 | { | ||
3097 | return 0x00418e28U; | ||
3098 | } | ||
3099 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) | ||
3100 | { | ||
3101 | return 11U; | ||
3102 | } | ||
3103 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) | ||
3104 | { | ||
3105 | return (v & 0x7ffU) << 0U; | ||
3106 | } | ||
3107 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) | ||
3108 | { | ||
3109 | return 0x7ffU << 0U; | ||
3110 | } | ||
3111 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) | ||
3112 | { | ||
3113 | return (r >> 0U) & 0x7ffU; | ||
3114 | } | ||
3115 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) | ||
3116 | { | ||
3117 | return 0x00000030U; | ||
3118 | } | ||
3119 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) | ||
3120 | { | ||
3121 | return 0x30U; | ||
3122 | } | ||
3123 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) | ||
3124 | { | ||
3125 | return 1U; | ||
3126 | } | ||
3127 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) | ||
3128 | { | ||
3129 | return (v & 0x1U) << 31U; | ||
3130 | } | ||
3131 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) | ||
3132 | { | ||
3133 | return 0x1U << 31U; | ||
3134 | } | ||
3135 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) | ||
3136 | { | ||
3137 | return (r >> 31U) & 0x1U; | ||
3138 | } | ||
3139 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) | ||
3140 | { | ||
3141 | return 0x00000000U; | ||
3142 | } | ||
3143 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) | ||
3144 | { | ||
3145 | return 0x0U; | ||
3146 | } | ||
3147 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) | ||
3148 | { | ||
3149 | return 0x00000001U; | ||
3150 | } | ||
3151 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) | ||
3152 | { | ||
3153 | return 0x80000000U; | ||
3154 | } | ||
3155 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) | ||
3156 | { | ||
3157 | return 0x005001dcU; | ||
3158 | } | ||
3159 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) | ||
3160 | { | ||
3161 | return (v & 0xffffU) << 0U; | ||
3162 | } | ||
3163 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) | ||
3164 | { | ||
3165 | return 0x00000170U; | ||
3166 | } | ||
3167 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) | ||
3168 | { | ||
3169 | return 0x00000100U; | ||
3170 | } | ||
3171 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) | ||
3172 | { | ||
3173 | return 0x005001d8U; | ||
3174 | } | ||
3175 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) | ||
3176 | { | ||
3177 | return (v & 0xffffffffU) << 0U; | ||
3178 | } | ||
3179 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) | ||
3180 | { | ||
3181 | return 0x00000008U; | ||
3182 | } | ||
3183 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) | ||
3184 | { | ||
3185 | return 0x004181e4U; | ||
3186 | } | ||
3187 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) | ||
3188 | { | ||
3189 | return (v & 0xfffU) << 0U; | ||
3190 | } | ||
3191 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) | ||
3192 | { | ||
3193 | return 0x00000100U; | ||
3194 | } | ||
3195 | static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) | ||
3196 | { | ||
3197 | return 0x0041befcU; | ||
3198 | } | ||
3199 | static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) | ||
3200 | { | ||
3201 | return (v & 0xfffU) << 0U; | ||
3202 | } | ||
3203 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) | ||
3204 | { | ||
3205 | return 0x00418ea0U + i*4U; | ||
3206 | } | ||
3207 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) | ||
3208 | { | ||
3209 | return (v & 0x3fffffU) << 0U; | ||
3210 | } | ||
3211 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) | ||
3212 | { | ||
3213 | return 0x3fffffU << 0U; | ||
3214 | } | ||
3215 | static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) | ||
3216 | { | ||
3217 | return 0x00418010U + i*4U; | ||
3218 | } | ||
3219 | static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) | ||
3220 | { | ||
3221 | return (v & 0xffffffffU) << 0U; | ||
3222 | } | ||
3223 | static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) | ||
3224 | { | ||
3225 | return 0x0041804cU + i*4U; | ||
3226 | } | ||
3227 | static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) | ||
3228 | { | ||
3229 | return (v & 0xffffffffU) << 0U; | ||
3230 | } | ||
3231 | static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) | ||
3232 | { | ||
3233 | return 0x00418088U + i*4U; | ||
3234 | } | ||
3235 | static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) | ||
3236 | { | ||
3237 | return (v & 0xffffffffU) << 0U; | ||
3238 | } | ||
3239 | static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) | ||
3240 | { | ||
3241 | return 0x004180c4U + i*4U; | ||
3242 | } | ||
3243 | static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) | ||
3244 | { | ||
3245 | return (v & 0xffffffffU) << 0U; | ||
3246 | } | ||
3247 | static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) | ||
3248 | { | ||
3249 | return 0x00418100U; | ||
3250 | } | ||
3251 | static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) | ||
3252 | { | ||
3253 | return 0x00418110U + i*4U; | ||
3254 | } | ||
3255 | static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) | ||
3256 | { | ||
3257 | return (v & 0xffffffffU) << 0U; | ||
3258 | } | ||
3259 | static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) | ||
3260 | { | ||
3261 | return 0x0041814cU; | ||
3262 | } | ||
3263 | static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) | ||
3264 | { | ||
3265 | return 0x0041815cU + i*4U; | ||
3266 | } | ||
3267 | static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) | ||
3268 | { | ||
3269 | return (v & 0xffU) << 0U; | ||
3270 | } | ||
3271 | static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) | ||
3272 | { | ||
3273 | return 0x00418198U; | ||
3274 | } | ||
3275 | static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) | ||
3276 | { | ||
3277 | return 0x00418810U; | ||
3278 | } | ||
3279 | static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) | ||
3280 | { | ||
3281 | return (v & 0xfffffffU) << 0U; | ||
3282 | } | ||
3283 | static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) | ||
3284 | { | ||
3285 | return 0x0000000cU; | ||
3286 | } | ||
3287 | static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) | ||
3288 | { | ||
3289 | return 0x80000000U; | ||
3290 | } | ||
3291 | static inline u32 gr_crstr_gpc_map_r(u32 i) | ||
3292 | { | ||
3293 | return 0x00418b08U + i*4U; | ||
3294 | } | ||
3295 | static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) | ||
3296 | { | ||
3297 | return (v & 0x1fU) << 0U; | ||
3298 | } | ||
3299 | static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) | ||
3300 | { | ||
3301 | return (v & 0x1fU) << 5U; | ||
3302 | } | ||
3303 | static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) | ||
3304 | { | ||
3305 | return (v & 0x1fU) << 10U; | ||
3306 | } | ||
3307 | static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) | ||
3308 | { | ||
3309 | return (v & 0x1fU) << 15U; | ||
3310 | } | ||
3311 | static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) | ||
3312 | { | ||
3313 | return (v & 0x1fU) << 20U; | ||
3314 | } | ||
3315 | static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) | ||
3316 | { | ||
3317 | return (v & 0x1fU) << 25U; | ||
3318 | } | ||
3319 | static inline u32 gr_crstr_map_table_cfg_r(void) | ||
3320 | { | ||
3321 | return 0x00418bb8U; | ||
3322 | } | ||
3323 | static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) | ||
3324 | { | ||
3325 | return (v & 0xffU) << 0U; | ||
3326 | } | ||
3327 | static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) | ||
3328 | { | ||
3329 | return (v & 0xffU) << 8U; | ||
3330 | } | ||
3331 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) | ||
3332 | { | ||
3333 | return 0x00418980U + i*4U; | ||
3334 | } | ||
3335 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) | ||
3336 | { | ||
3337 | return (v & 0x7U) << 0U; | ||
3338 | } | ||
3339 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) | ||
3340 | { | ||
3341 | return (v & 0x7U) << 4U; | ||
3342 | } | ||
3343 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) | ||
3344 | { | ||
3345 | return (v & 0x7U) << 8U; | ||
3346 | } | ||
3347 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) | ||
3348 | { | ||
3349 | return (v & 0x7U) << 12U; | ||
3350 | } | ||
3351 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) | ||
3352 | { | ||
3353 | return (v & 0x7U) << 16U; | ||
3354 | } | ||
3355 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) | ||
3356 | { | ||
3357 | return (v & 0x7U) << 20U; | ||
3358 | } | ||
3359 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) | ||
3360 | { | ||
3361 | return (v & 0x7U) << 24U; | ||
3362 | } | ||
3363 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) | ||
3364 | { | ||
3365 | return (v & 0x7U) << 28U; | ||
3366 | } | ||
3367 | static inline u32 gr_gpcs_gpm_pd_cfg_r(void) | ||
3368 | { | ||
3369 | return 0x00418c6cU; | ||
3370 | } | ||
3371 | static inline u32 gr_gpcs_gcc_pagepool_base_r(void) | ||
3372 | { | ||
3373 | return 0x00419004U; | ||
3374 | } | ||
3375 | static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) | ||
3376 | { | ||
3377 | return (v & 0xffffffffU) << 0U; | ||
3378 | } | ||
3379 | static inline u32 gr_gpcs_gcc_pagepool_r(void) | ||
3380 | { | ||
3381 | return 0x00419008U; | ||
3382 | } | ||
3383 | static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) | ||
3384 | { | ||
3385 | return (v & 0x3ffU) << 0U; | ||
3386 | } | ||
3387 | static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) | ||
3388 | { | ||
3389 | return 0x0041980cU; | ||
3390 | } | ||
3391 | static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) | ||
3392 | { | ||
3393 | return 0x10U; | ||
3394 | } | ||
3395 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) | ||
3396 | { | ||
3397 | return 0x00419848U; | ||
3398 | } | ||
3399 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) | ||
3400 | { | ||
3401 | return (v & 0xfffffffU) << 0U; | ||
3402 | } | ||
3403 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) | ||
3404 | { | ||
3405 | return (v & 0x1U) << 28U; | ||
3406 | } | ||
3407 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) | ||
3408 | { | ||
3409 | return 0x10000000U; | ||
3410 | } | ||
3411 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) | ||
3412 | { | ||
3413 | return 0x00419c00U; | ||
3414 | } | ||
3415 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) | ||
3416 | { | ||
3417 | return 0x0U; | ||
3418 | } | ||
3419 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) | ||
3420 | { | ||
3421 | return 0x8U; | ||
3422 | } | ||
3423 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) | ||
3424 | { | ||
3425 | return 0x00419c2cU; | ||
3426 | } | ||
3427 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) | ||
3428 | { | ||
3429 | return (v & 0xfffffffU) << 0U; | ||
3430 | } | ||
3431 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) | ||
3432 | { | ||
3433 | return (v & 0x1U) << 28U; | ||
3434 | } | ||
3435 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | ||
3436 | { | ||
3437 | return 0x10000000U; | ||
3438 | } | ||
3439 | static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) | ||
3440 | { | ||
3441 | return 0x00419ea8U; | ||
3442 | } | ||
3443 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) | ||
3444 | { | ||
3445 | return 0x00504728U; | ||
3446 | } | ||
3447 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) | ||
3448 | { | ||
3449 | return 0x2U; | ||
3450 | } | ||
3451 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) | ||
3452 | { | ||
3453 | return 0x4U; | ||
3454 | } | ||
3455 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) | ||
3456 | { | ||
3457 | return 0x10U; | ||
3458 | } | ||
3459 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) | ||
3460 | { | ||
3461 | return 0x20U; | ||
3462 | } | ||
3463 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) | ||
3464 | { | ||
3465 | return 0x40U; | ||
3466 | } | ||
3467 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) | ||
3468 | { | ||
3469 | return 0x100U; | ||
3470 | } | ||
3471 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) | ||
3472 | { | ||
3473 | return 0x200U; | ||
3474 | } | ||
3475 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) | ||
3476 | { | ||
3477 | return 0x800U; | ||
3478 | } | ||
3479 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) | ||
3480 | { | ||
3481 | return 0x2000U; | ||
3482 | } | ||
3483 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) | ||
3484 | { | ||
3485 | return 0x4000U; | ||
3486 | } | ||
3487 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) | ||
3488 | { | ||
3489 | return 0x8000U; | ||
3490 | } | ||
3491 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) | ||
3492 | { | ||
3493 | return 0x10000U; | ||
3494 | } | ||
3495 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) | ||
3496 | { | ||
3497 | return 0x40000U; | ||
3498 | } | ||
3499 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) | ||
3500 | { | ||
3501 | return 0x800000U; | ||
3502 | } | ||
3503 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) | ||
3504 | { | ||
3505 | return 0x400000U; | ||
3506 | } | ||
3507 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) | ||
3508 | { | ||
3509 | return 0x00419d0cU; | ||
3510 | } | ||
3511 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) | ||
3512 | { | ||
3513 | return 0x2U; | ||
3514 | } | ||
3515 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) | ||
3516 | { | ||
3517 | return 0x1U; | ||
3518 | } | ||
3519 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) | ||
3520 | { | ||
3521 | return 0x10U; | ||
3522 | } | ||
3523 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | ||
3524 | { | ||
3525 | return 0x0050450cU; | ||
3526 | } | ||
3527 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) | ||
3528 | { | ||
3529 | return (r >> 1U) & 0x1U; | ||
3530 | } | ||
3531 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | ||
3532 | { | ||
3533 | return 0x2U; | ||
3534 | } | ||
3535 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) | ||
3536 | { | ||
3537 | return 0x10U; | ||
3538 | } | ||
3539 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) | ||
3540 | { | ||
3541 | return 0x0041ac94U; | ||
3542 | } | ||
3543 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) | ||
3544 | { | ||
3545 | return (v & 0x1U) << 2U; | ||
3546 | } | ||
3547 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) | ||
3548 | { | ||
3549 | return (v & 0xffU) << 16U; | ||
3550 | } | ||
3551 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) | ||
3552 | { | ||
3553 | return (v & 0x1U) << 14U; | ||
3554 | } | ||
3555 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) | ||
3556 | { | ||
3557 | return (v & 0x1U) << 15U; | ||
3558 | } | ||
3559 | static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) | ||
3560 | { | ||
3561 | return 0x00502c90U; | ||
3562 | } | ||
3563 | static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) | ||
3564 | { | ||
3565 | return (r >> 2U) & 0x1U; | ||
3566 | } | ||
3567 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) | ||
3568 | { | ||
3569 | return (r >> 16U) & 0xffU; | ||
3570 | } | ||
3571 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) | ||
3572 | { | ||
3573 | return 0x00000001U; | ||
3574 | } | ||
3575 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) | ||
3576 | { | ||
3577 | return (v & 0x1U) << 14U; | ||
3578 | } | ||
3579 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) | ||
3580 | { | ||
3581 | return 0x1U << 14U; | ||
3582 | } | ||
3583 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) | ||
3584 | { | ||
3585 | return 0x4000U; | ||
3586 | } | ||
3587 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) | ||
3588 | { | ||
3589 | return (v & 0x1U) << 15U; | ||
3590 | } | ||
3591 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) | ||
3592 | { | ||
3593 | return 0x1U << 15U; | ||
3594 | } | ||
3595 | static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) | ||
3596 | { | ||
3597 | return 0x8000U; | ||
3598 | } | ||
3599 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) | ||
3600 | { | ||
3601 | return 0x00501048U; | ||
3602 | } | ||
3603 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) | ||
3604 | { | ||
3605 | return 0x1U << 0U; | ||
3606 | } | ||
3607 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) | ||
3608 | { | ||
3609 | return 0x1U << 1U; | ||
3610 | } | ||
3611 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) | ||
3612 | { | ||
3613 | return 0x1U << 4U; | ||
3614 | } | ||
3615 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) | ||
3616 | { | ||
3617 | return 0x1U << 5U; | ||
3618 | } | ||
3619 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
3620 | { | ||
3621 | return (r >> 8U) & 0x1U; | ||
3622 | } | ||
3623 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
3624 | { | ||
3625 | return (r >> 10U) & 0x1U; | ||
3626 | } | ||
3627 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void) | ||
3628 | { | ||
3629 | return 0x40000000U; | ||
3630 | } | ||
3631 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void) | ||
3632 | { | ||
3633 | return 0x0050104cU; | ||
3634 | } | ||
3635 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void) | ||
3636 | { | ||
3637 | return 16U; | ||
3638 | } | ||
3639 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r) | ||
3640 | { | ||
3641 | return (r >> 0U) & 0xffffU; | ||
3642 | } | ||
3643 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void) | ||
3644 | { | ||
3645 | return 0x00501054U; | ||
3646 | } | ||
3647 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void) | ||
3648 | { | ||
3649 | return 16U; | ||
3650 | } | ||
3651 | static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) | ||
3652 | { | ||
3653 | return (r >> 0U) & 0xffffU; | ||
3654 | } | ||
3655 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) | ||
3656 | { | ||
3657 | return 0x00504508U; | ||
3658 | } | ||
3659 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) | ||
3660 | { | ||
3661 | return (r >> 0U) & 0x1U; | ||
3662 | } | ||
3663 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) | ||
3664 | { | ||
3665 | return 0x00000001U; | ||
3666 | } | ||
3667 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) | ||
3668 | { | ||
3669 | return (r >> 1U) & 0x1U; | ||
3670 | } | ||
3671 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) | ||
3672 | { | ||
3673 | return 0x00000001U; | ||
3674 | } | ||
3675 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) | ||
3676 | { | ||
3677 | return 0x1U << 4U; | ||
3678 | } | ||
3679 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) | ||
3680 | { | ||
3681 | return 0x10U; | ||
3682 | } | ||
3683 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) | ||
3684 | { | ||
3685 | return 0x00504704U; | ||
3686 | } | ||
3687 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) | ||
3688 | { | ||
3689 | return 0x1U << 0U; | ||
3690 | } | ||
3691 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) | ||
3692 | { | ||
3693 | return (r >> 0U) & 0x1U; | ||
3694 | } | ||
3695 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) | ||
3696 | { | ||
3697 | return 0x00000001U; | ||
3698 | } | ||
3699 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) | ||
3700 | { | ||
3701 | return 0x1U; | ||
3702 | } | ||
3703 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) | ||
3704 | { | ||
3705 | return 0x00000000U; | ||
3706 | } | ||
3707 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) | ||
3708 | { | ||
3709 | return 0x0U; | ||
3710 | } | ||
3711 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) | ||
3712 | { | ||
3713 | return 0x1U << 31U; | ||
3714 | } | ||
3715 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) | ||
3716 | { | ||
3717 | return 0x80000000U; | ||
3718 | } | ||
3719 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) | ||
3720 | { | ||
3721 | return 0x0U; | ||
3722 | } | ||
3723 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) | ||
3724 | { | ||
3725 | return 0x1U << 3U; | ||
3726 | } | ||
3727 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) | ||
3728 | { | ||
3729 | return 0x8U; | ||
3730 | } | ||
3731 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) | ||
3732 | { | ||
3733 | return 0x0U; | ||
3734 | } | ||
3735 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) | ||
3736 | { | ||
3737 | return 0x40000000U; | ||
3738 | } | ||
3739 | static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) | ||
3740 | { | ||
3741 | return 0x00504708U; | ||
3742 | } | ||
3743 | static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) | ||
3744 | { | ||
3745 | return 0x0050470cU; | ||
3746 | } | ||
3747 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) | ||
3748 | { | ||
3749 | return 0x00504710U; | ||
3750 | } | ||
3751 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) | ||
3752 | { | ||
3753 | return 0x00504714U; | ||
3754 | } | ||
3755 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) | ||
3756 | { | ||
3757 | return 0x00504718U; | ||
3758 | } | ||
3759 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) | ||
3760 | { | ||
3761 | return 0x0050471cU; | ||
3762 | } | ||
3763 | static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) | ||
3764 | { | ||
3765 | return 0x00419e90U; | ||
3766 | } | ||
3767 | static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) | ||
3768 | { | ||
3769 | return 0x00419e94U; | ||
3770 | } | ||
3771 | static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) | ||
3772 | { | ||
3773 | return 0x00419e80U; | ||
3774 | } | ||
3775 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) | ||
3776 | { | ||
3777 | return 0x00504700U; | ||
3778 | } | ||
3779 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) | ||
3780 | { | ||
3781 | return (r >> 0U) & 0x1U; | ||
3782 | } | ||
3783 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) | ||
3784 | { | ||
3785 | return (r >> 4U) & 0x1U; | ||
3786 | } | ||
3787 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) | ||
3788 | { | ||
3789 | return 0x00000001U; | ||
3790 | } | ||
3791 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) | ||
3792 | { | ||
3793 | return 0x00504730U; | ||
3794 | } | ||
3795 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) | ||
3796 | { | ||
3797 | return (r >> 0U) & 0xffffU; | ||
3798 | } | ||
3799 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) | ||
3800 | { | ||
3801 | return 0x00000000U; | ||
3802 | } | ||
3803 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) | ||
3804 | { | ||
3805 | return 0x0U; | ||
3806 | } | ||
3807 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) | ||
3808 | { | ||
3809 | return 0xffU << 16U; | ||
3810 | } | ||
3811 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) | ||
3812 | { | ||
3813 | return 0xfU << 24U; | ||
3814 | } | ||
3815 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) | ||
3816 | { | ||
3817 | return 0x0U; | ||
3818 | } | ||
3819 | static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) | ||
3820 | { | ||
3821 | return 0x0050460cU; | ||
3822 | } | ||
3823 | static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) | ||
3824 | { | ||
3825 | return (r >> 0U) & 0x1U; | ||
3826 | } | ||
3827 | static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) | ||
3828 | { | ||
3829 | return (r >> 1U) & 0x1U; | ||
3830 | } | ||
3831 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) | ||
3832 | { | ||
3833 | return 0x00504738U; | ||
3834 | } | ||
3835 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) | ||
3836 | { | ||
3837 | return 0x005043a0U; | ||
3838 | } | ||
3839 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) | ||
3840 | { | ||
3841 | return 0x00419ba0U; | ||
3842 | } | ||
3843 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) | ||
3844 | { | ||
3845 | return 0x1U << 4U; | ||
3846 | } | ||
3847 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) | ||
3848 | { | ||
3849 | return (v & 0x1U) << 4U; | ||
3850 | } | ||
3851 | static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) | ||
3852 | { | ||
3853 | return 0x005043b0U; | ||
3854 | } | ||
3855 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) | ||
3856 | { | ||
3857 | return 0x00419bb0U; | ||
3858 | } | ||
3859 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) | ||
3860 | { | ||
3861 | return 0x1U << 0U; | ||
3862 | } | ||
3863 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) | ||
3864 | { | ||
3865 | return (v & 0x1U) << 0U; | ||
3866 | } | ||
3867 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) | ||
3868 | { | ||
3869 | return 0x0041be08U; | ||
3870 | } | ||
3871 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) | ||
3872 | { | ||
3873 | return 0x4U; | ||
3874 | } | ||
3875 | static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) | ||
3876 | { | ||
3877 | return 0x0041bf00U + i*4U; | ||
3878 | } | ||
3879 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) | ||
3880 | { | ||
3881 | return 0x0041bfd0U; | ||
3882 | } | ||
3883 | static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) | ||
3884 | { | ||
3885 | return (v & 0xffU) << 0U; | ||
3886 | } | ||
3887 | static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) | ||
3888 | { | ||
3889 | return (v & 0xffU) << 8U; | ||
3890 | } | ||
3891 | static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) | ||
3892 | { | ||
3893 | return (v & 0x1fU) << 16U; | ||
3894 | } | ||
3895 | static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) | ||
3896 | { | ||
3897 | return (v & 0x7U) << 21U; | ||
3898 | } | ||
3899 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) | ||
3900 | { | ||
3901 | return 0x0041bfd4U; | ||
3902 | } | ||
3903 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) | ||
3904 | { | ||
3905 | return (v & 0xffffffU) << 0U; | ||
3906 | } | ||
3907 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) | ||
3908 | { | ||
3909 | return 0x0041bfb0U + i*4U; | ||
3910 | } | ||
3911 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) | ||
3912 | { | ||
3913 | return 0x00000005U; | ||
3914 | } | ||
3915 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) | ||
3916 | { | ||
3917 | return (v & 0xffU) << 0U; | ||
3918 | } | ||
3919 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) | ||
3920 | { | ||
3921 | return (v & 0xffU) << 8U; | ||
3922 | } | ||
3923 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) | ||
3924 | { | ||
3925 | return (v & 0xffU) << 16U; | ||
3926 | } | ||
3927 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) | ||
3928 | { | ||
3929 | return (v & 0xffU) << 24U; | ||
3930 | } | ||
3931 | static inline u32 gr_bes_zrop_settings_r(void) | ||
3932 | { | ||
3933 | return 0x00408850U; | ||
3934 | } | ||
3935 | static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) | ||
3936 | { | ||
3937 | return (v & 0xfU) << 0U; | ||
3938 | } | ||
3939 | static inline u32 gr_be0_crop_debug3_r(void) | ||
3940 | { | ||
3941 | return 0x00410108U; | ||
3942 | } | ||
3943 | static inline u32 gr_bes_crop_debug3_r(void) | ||
3944 | { | ||
3945 | return 0x00408908U; | ||
3946 | } | ||
3947 | static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) | ||
3948 | { | ||
3949 | return 0x1U << 31U; | ||
3950 | } | ||
3951 | static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) | ||
3952 | { | ||
3953 | return 0x1U << 1U; | ||
3954 | } | ||
3955 | static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) | ||
3956 | { | ||
3957 | return 0x0U; | ||
3958 | } | ||
3959 | static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) | ||
3960 | { | ||
3961 | return 0x2U; | ||
3962 | } | ||
3963 | static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) | ||
3964 | { | ||
3965 | return 0x1U << 2U; | ||
3966 | } | ||
3967 | static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) | ||
3968 | { | ||
3969 | return 0x0U; | ||
3970 | } | ||
3971 | static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) | ||
3972 | { | ||
3973 | return 0x4U; | ||
3974 | } | ||
3975 | static inline u32 gr_bes_crop_settings_r(void) | ||
3976 | { | ||
3977 | return 0x00408958U; | ||
3978 | } | ||
3979 | static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) | ||
3980 | { | ||
3981 | return (v & 0xfU) << 0U; | ||
3982 | } | ||
3983 | static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) | ||
3984 | { | ||
3985 | return 0x00000020U; | ||
3986 | } | ||
3987 | static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) | ||
3988 | { | ||
3989 | return 0x00000020U; | ||
3990 | } | ||
3991 | static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) | ||
3992 | { | ||
3993 | return 0x000000c0U; | ||
3994 | } | ||
3995 | static inline u32 gr_zcull_subregion_qty_v(void) | ||
3996 | { | ||
3997 | return 0x00000010U; | ||
3998 | } | ||
3999 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) | ||
4000 | { | ||
4001 | return 0x00419a00U; | ||
4002 | } | ||
4003 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) | ||
4004 | { | ||
4005 | return (v & 0x1U) << 19U; | ||
4006 | } | ||
4007 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) | ||
4008 | { | ||
4009 | return 0x1U << 19U; | ||
4010 | } | ||
4011 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) | ||
4012 | { | ||
4013 | return 0x00419bf0U; | ||
4014 | } | ||
4015 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) | ||
4016 | { | ||
4017 | return (v & 0x1U) << 5U; | ||
4018 | } | ||
4019 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) | ||
4020 | { | ||
4021 | return 0x1U << 5U; | ||
4022 | } | ||
4023 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) | ||
4024 | { | ||
4025 | return (v & 0x1U) << 10U; | ||
4026 | } | ||
4027 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) | ||
4028 | { | ||
4029 | return 0x1U << 10U; | ||
4030 | } | ||
4031 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) | ||
4032 | { | ||
4033 | return 0x00584200U; | ||
4034 | } | ||
4035 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) | ||
4036 | { | ||
4037 | return 0x00584204U; | ||
4038 | } | ||
4039 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) | ||
4040 | { | ||
4041 | return 0x00584208U; | ||
4042 | } | ||
4043 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) | ||
4044 | { | ||
4045 | return 0x00584210U; | ||
4046 | } | ||
4047 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) | ||
4048 | { | ||
4049 | return 0x00584214U; | ||
4050 | } | ||
4051 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) | ||
4052 | { | ||
4053 | return 0x00584218U; | ||
4054 | } | ||
4055 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) | ||
4056 | { | ||
4057 | return 0x0058421cU; | ||
4058 | } | ||
4059 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) | ||
4060 | { | ||
4061 | return 0x0058420cU; | ||
4062 | } | ||
4063 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) | ||
4064 | { | ||
4065 | return 0x00584220U; | ||
4066 | } | ||
4067 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) | ||
4068 | { | ||
4069 | return 0x00584224U; | ||
4070 | } | ||
4071 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) | ||
4072 | { | ||
4073 | return 0x00584228U; | ||
4074 | } | ||
4075 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) | ||
4076 | { | ||
4077 | return 0x0058422cU; | ||
4078 | } | ||
4079 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) | ||
4080 | { | ||
4081 | return 0x00584230U; | ||
4082 | } | ||
4083 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) | ||
4084 | { | ||
4085 | return 0x00584234U; | ||
4086 | } | ||
4087 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) | ||
4088 | { | ||
4089 | return 0x00584238U; | ||
4090 | } | ||
4091 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) | ||
4092 | { | ||
4093 | return 0x0058423cU; | ||
4094 | } | ||
4095 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) | ||
4096 | { | ||
4097 | return 0x00584600U; | ||
4098 | } | ||
4099 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) | ||
4100 | { | ||
4101 | return 0x00584604U; | ||
4102 | } | ||
4103 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) | ||
4104 | { | ||
4105 | return 0x00584624U; | ||
4106 | } | ||
4107 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) | ||
4108 | { | ||
4109 | return 0x00584628U; | ||
4110 | } | ||
4111 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) | ||
4112 | { | ||
4113 | return 0x0058462cU; | ||
4114 | } | ||
4115 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) | ||
4116 | { | ||
4117 | return 0x00584630U; | ||
4118 | } | ||
4119 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) | ||
4120 | { | ||
4121 | return 0x00584634U; | ||
4122 | } | ||
4123 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) | ||
4124 | { | ||
4125 | return 0x00584638U; | ||
4126 | } | ||
4127 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) | ||
4128 | { | ||
4129 | return 0x0058463cU; | ||
4130 | } | ||
4131 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) | ||
4132 | { | ||
4133 | return 0x00584640U; | ||
4134 | } | ||
4135 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) | ||
4136 | { | ||
4137 | return 0x00584644U; | ||
4138 | } | ||
4139 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) | ||
4140 | { | ||
4141 | return 0x00584648U; | ||
4142 | } | ||
4143 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) | ||
4144 | { | ||
4145 | return 0x0058464cU; | ||
4146 | } | ||
4147 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) | ||
4148 | { | ||
4149 | return 0x00584650U; | ||
4150 | } | ||
4151 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) | ||
4152 | { | ||
4153 | return 0x00584654U; | ||
4154 | } | ||
4155 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) | ||
4156 | { | ||
4157 | return 0x00584658U; | ||
4158 | } | ||
4159 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) | ||
4160 | { | ||
4161 | return 0x0058465cU; | ||
4162 | } | ||
4163 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) | ||
4164 | { | ||
4165 | return 0x00584660U; | ||
4166 | } | ||
4167 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) | ||
4168 | { | ||
4169 | return 0x00584614U; | ||
4170 | } | ||
4171 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) | ||
4172 | { | ||
4173 | return 0x00584618U; | ||
4174 | } | ||
4175 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) | ||
4176 | { | ||
4177 | return 0x0058461cU; | ||
4178 | } | ||
4179 | static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) | ||
4180 | { | ||
4181 | return 0x00584620U; | ||
4182 | } | ||
4183 | static inline u32 gr_fe_pwr_mode_r(void) | ||
4184 | { | ||
4185 | return 0x00404170U; | ||
4186 | } | ||
4187 | static inline u32 gr_fe_pwr_mode_mode_auto_f(void) | ||
4188 | { | ||
4189 | return 0x0U; | ||
4190 | } | ||
4191 | static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) | ||
4192 | { | ||
4193 | return 0x2U; | ||
4194 | } | ||
4195 | static inline u32 gr_fe_pwr_mode_req_v(u32 r) | ||
4196 | { | ||
4197 | return (r >> 4U) & 0x1U; | ||
4198 | } | ||
4199 | static inline u32 gr_fe_pwr_mode_req_send_f(void) | ||
4200 | { | ||
4201 | return 0x10U; | ||
4202 | } | ||
4203 | static inline u32 gr_fe_pwr_mode_req_done_v(void) | ||
4204 | { | ||
4205 | return 0x00000000U; | ||
4206 | } | ||
4207 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) | ||
4208 | { | ||
4209 | return 0x00418880U; | ||
4210 | } | ||
4211 | static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) | ||
4212 | { | ||
4213 | return 0x1U << 0U; | ||
4214 | } | ||
4215 | static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) | ||
4216 | { | ||
4217 | return 0x1U << 11U; | ||
4218 | } | ||
4219 | static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) | ||
4220 | { | ||
4221 | return 0x1U << 1U; | ||
4222 | } | ||
4223 | static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) | ||
4224 | { | ||
4225 | return 0x1U << 2U; | ||
4226 | } | ||
4227 | static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) | ||
4228 | { | ||
4229 | return 0x3U << 3U; | ||
4230 | } | ||
4231 | static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) | ||
4232 | { | ||
4233 | return 0x3U << 5U; | ||
4234 | } | ||
4235 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) | ||
4236 | { | ||
4237 | return 0x3U << 28U; | ||
4238 | } | ||
4239 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) | ||
4240 | { | ||
4241 | return 0x1U << 30U; | ||
4242 | } | ||
4243 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) | ||
4244 | { | ||
4245 | return 0x1U << 31U; | ||
4246 | } | ||
4247 | static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) | ||
4248 | { | ||
4249 | return 0x00418890U; | ||
4250 | } | ||
4251 | static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) | ||
4252 | { | ||
4253 | return 0x00418894U; | ||
4254 | } | ||
4255 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) | ||
4256 | { | ||
4257 | return 0x004188b0U; | ||
4258 | } | ||
4259 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) | ||
4260 | { | ||
4261 | return (r >> 16U) & 0x1U; | ||
4262 | } | ||
4263 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) | ||
4264 | { | ||
4265 | return 0x00000001U; | ||
4266 | } | ||
4267 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) | ||
4268 | { | ||
4269 | return 0x004188b4U; | ||
4270 | } | ||
4271 | static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) | ||
4272 | { | ||
4273 | return 0x004188b8U; | ||
4274 | } | ||
4275 | static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) | ||
4276 | { | ||
4277 | return 0x004188acU; | ||
4278 | } | ||
4279 | static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) | ||
4280 | { | ||
4281 | return 0x00419e84U; | ||
4282 | } | ||
4283 | static inline u32 gr_fe_gfxp_wfi_timeout_r(void) | ||
4284 | { | ||
4285 | return 0x004041c0U; | ||
4286 | } | ||
4287 | static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) | ||
4288 | { | ||
4289 | return (v & 0xffffffffU) << 0U; | ||
4290 | } | ||
4291 | static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) | ||
4292 | { | ||
4293 | return 0x0U; | ||
4294 | } | ||
4295 | static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) | ||
4296 | { | ||
4297 | return 0x00419bd8U; | ||
4298 | } | ||
4299 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) | ||
4300 | { | ||
4301 | return (v & 0x7U) << 8U; | ||
4302 | } | ||
4303 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) | ||
4304 | { | ||
4305 | return 0x7U << 8U; | ||
4306 | } | ||
4307 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) | ||
4308 | { | ||
4309 | return 0x100U; | ||
4310 | } | ||
4311 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) | ||
4312 | { | ||
4313 | return 0x00419ba4U; | ||
4314 | } | ||
4315 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) | ||
4316 | { | ||
4317 | return 0x3U << 11U; | ||
4318 | } | ||
4319 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) | ||
4320 | { | ||
4321 | return 0x1000U; | ||
4322 | } | ||
4323 | static inline u32 gr_gpcs_tc_debug0_r(void) | ||
4324 | { | ||
4325 | return 0x00418708U; | ||
4326 | } | ||
4327 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) | ||
4328 | { | ||
4329 | return (v & 0x1ffU) << 0U; | ||
4330 | } | ||
4331 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) | ||
4332 | { | ||
4333 | return 0x1ffU << 0U; | ||
4334 | } | ||
4335 | static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) | ||
4336 | { | ||
4337 | return 0x00500324U; | ||
4338 | } | ||
4339 | static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) | ||
4340 | { | ||
4341 | return (v & 0x1U) << 0U; | ||
4342 | } | ||
4343 | static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) | ||
4344 | { | ||
4345 | return 0x1U << 0U; | ||
4346 | } | ||
4347 | static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) | ||
4348 | { | ||
4349 | return (v & 0x1U) << 1U; | ||
4350 | } | ||
4351 | static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) | ||
4352 | { | ||
4353 | return 0x1U << 1U; | ||
4354 | } | ||
4355 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) | ||
4356 | { | ||
4357 | return 0x00500314U; | ||
4358 | } | ||
4359 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v) | ||
4360 | { | ||
4361 | return (v & 0x1U) << 0U; | ||
4362 | } | ||
4363 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) | ||
4364 | { | ||
4365 | return 0x1U << 0U; | ||
4366 | } | ||
4367 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) | ||
4368 | { | ||
4369 | return (v & 0x1U) << 2U; | ||
4370 | } | ||
4371 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) | ||
4372 | { | ||
4373 | return 0x1U << 2U; | ||
4374 | } | ||
4375 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) | ||
4376 | { | ||
4377 | return (v & 0x1U) << 1U; | ||
4378 | } | ||
4379 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) | ||
4380 | { | ||
4381 | return 0x1U << 1U; | ||
4382 | } | ||
4383 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) | ||
4384 | { | ||
4385 | return (v & 0x1U) << 3U; | ||
4386 | } | ||
4387 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) | ||
4388 | { | ||
4389 | return 0x1U << 3U; | ||
4390 | } | ||
4391 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) | ||
4392 | { | ||
4393 | return (v & 0x1U) << 18U; | ||
4394 | } | ||
4395 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
4396 | { | ||
4397 | return 0x1U << 18U; | ||
4398 | } | ||
4399 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) | ||
4400 | { | ||
4401 | return (v & 0x1U) << 16U; | ||
4402 | } | ||
4403 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
4404 | { | ||
4405 | return 0x1U << 16U; | ||
4406 | } | ||
4407 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) | ||
4408 | { | ||
4409 | return (v & 0x1U) << 19U; | ||
4410 | } | ||
4411 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) | ||
4412 | { | ||
4413 | return 0x1U << 19U; | ||
4414 | } | ||
4415 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) | ||
4416 | { | ||
4417 | return (v & 0x1U) << 17U; | ||
4418 | } | ||
4419 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) | ||
4420 | { | ||
4421 | return 0x1U << 17U; | ||
4422 | } | ||
4423 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) | ||
4424 | { | ||
4425 | return (v & 0x1U) << 30U; | ||
4426 | } | ||
4427 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void) | ||
4428 | { | ||
4429 | return 0x40000000U; | ||
4430 | } | ||
4431 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void) | ||
4432 | { | ||
4433 | return 0x00500320U; | ||
4434 | } | ||
4435 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v) | ||
4436 | { | ||
4437 | return (v & 0xffffffffU) << 0U; | ||
4438 | } | ||
4439 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void) | ||
4440 | { | ||
4441 | return 0x00500318U; | ||
4442 | } | ||
4443 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void) | ||
4444 | { | ||
4445 | return 16U; | ||
4446 | } | ||
4447 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) | ||
4448 | { | ||
4449 | return (v & 0xffffU) << 0U; | ||
4450 | } | ||
4451 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) | ||
4452 | { | ||
4453 | return 0xffffU << 0U; | ||
4454 | } | ||
4455 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) | ||
4456 | { | ||
4457 | return (r >> 0U) & 0xffffU; | ||
4458 | } | ||
4459 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void) | ||
4460 | { | ||
4461 | return 16U; | ||
4462 | } | ||
4463 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v) | ||
4464 | { | ||
4465 | return (v & 0xffffU) << 16U; | ||
4466 | } | ||
4467 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) | ||
4468 | { | ||
4469 | return 0xffffU << 16U; | ||
4470 | } | ||
4471 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) | ||
4472 | { | ||
4473 | return (r >> 16U) & 0xffffU; | ||
4474 | } | ||
4475 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void) | ||
4476 | { | ||
4477 | return 0x0050031cU; | ||
4478 | } | ||
4479 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void) | ||
4480 | { | ||
4481 | return 16U; | ||
4482 | } | ||
4483 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) | ||
4484 | { | ||
4485 | return (v & 0xffffU) << 0U; | ||
4486 | } | ||
4487 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) | ||
4488 | { | ||
4489 | return 0xffffU << 0U; | ||
4490 | } | ||
4491 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) | ||
4492 | { | ||
4493 | return (r >> 0U) & 0xffffU; | ||
4494 | } | ||
4495 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void) | ||
4496 | { | ||
4497 | return 16U; | ||
4498 | } | ||
4499 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v) | ||
4500 | { | ||
4501 | return (v & 0xffffU) << 16U; | ||
4502 | } | ||
4503 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) | ||
4504 | { | ||
4505 | return 0xffffU << 16U; | ||
4506 | } | ||
4507 | static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) | ||
4508 | { | ||
4509 | return (r >> 16U) & 0xffffU; | ||
4510 | } | ||
4511 | static inline u32 gr_gpc0_gpccs_hww_esr_r(void) | ||
4512 | { | ||
4513 | return 0x00502c98U; | ||
4514 | } | ||
4515 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) | ||
4516 | { | ||
4517 | return (v & 0x1U) << 0U; | ||
4518 | } | ||
4519 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) | ||
4520 | { | ||
4521 | return 0x1U << 0U; | ||
4522 | } | ||
4523 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) | ||
4524 | { | ||
4525 | return 0x1U; | ||
4526 | } | ||
4527 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) | ||
4528 | { | ||
4529 | return (v & 0x1U) << 1U; | ||
4530 | } | ||
4531 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) | ||
4532 | { | ||
4533 | return 0x1U << 1U; | ||
4534 | } | ||
4535 | static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) | ||
4536 | { | ||
4537 | return 0x2U; | ||
4538 | } | ||
4539 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) | ||
4540 | { | ||
4541 | return 0x00502678U; | ||
4542 | } | ||
4543 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) | ||
4544 | { | ||
4545 | return (v & 0x1U) << 0U; | ||
4546 | } | ||
4547 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) | ||
4548 | { | ||
4549 | return 0x1U << 0U; | ||
4550 | } | ||
4551 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) | ||
4552 | { | ||
4553 | return 0x1U; | ||
4554 | } | ||
4555 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) | ||
4556 | { | ||
4557 | return (v & 0x1U) << 1U; | ||
4558 | } | ||
4559 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) | ||
4560 | { | ||
4561 | return 0x1U << 1U; | ||
4562 | } | ||
4563 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) | ||
4564 | { | ||
4565 | return 0x2U; | ||
4566 | } | ||
4567 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) | ||
4568 | { | ||
4569 | return (v & 0x1U) << 4U; | ||
4570 | } | ||
4571 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) | ||
4572 | { | ||
4573 | return 0x1U << 4U; | ||
4574 | } | ||
4575 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) | ||
4576 | { | ||
4577 | return 0x10U; | ||
4578 | } | ||
4579 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) | ||
4580 | { | ||
4581 | return (v & 0x1U) << 5U; | ||
4582 | } | ||
4583 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) | ||
4584 | { | ||
4585 | return 0x1U << 5U; | ||
4586 | } | ||
4587 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) | ||
4588 | { | ||
4589 | return 0x20U; | ||
4590 | } | ||
4591 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) | ||
4592 | { | ||
4593 | return (v & 0x1U) << 10U; | ||
4594 | } | ||
4595 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
4596 | { | ||
4597 | return 0x1U << 10U; | ||
4598 | } | ||
4599 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) | ||
4600 | { | ||
4601 | return 0x400U; | ||
4602 | } | ||
4603 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) | ||
4604 | { | ||
4605 | return (v & 0x1U) << 8U; | ||
4606 | } | ||
4607 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
4608 | { | ||
4609 | return 0x1U << 8U; | ||
4610 | } | ||
4611 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) | ||
4612 | { | ||
4613 | return 0x100U; | ||
4614 | } | ||
4615 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) | ||
4616 | { | ||
4617 | return (v & 0x1U) << 11U; | ||
4618 | } | ||
4619 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) | ||
4620 | { | ||
4621 | return 0x1U << 11U; | ||
4622 | } | ||
4623 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) | ||
4624 | { | ||
4625 | return 0x800U; | ||
4626 | } | ||
4627 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) | ||
4628 | { | ||
4629 | return (v & 0x1U) << 9U; | ||
4630 | } | ||
4631 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) | ||
4632 | { | ||
4633 | return 0x1U << 9U; | ||
4634 | } | ||
4635 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) | ||
4636 | { | ||
4637 | return 0x200U; | ||
4638 | } | ||
4639 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) | ||
4640 | { | ||
4641 | return (v & 0x1U) << 31U; | ||
4642 | } | ||
4643 | static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) | ||
4644 | { | ||
4645 | return 0x80000000U; | ||
4646 | } | ||
4647 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) | ||
4648 | { | ||
4649 | return 0x00502684U; | ||
4650 | } | ||
4651 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) | ||
4652 | { | ||
4653 | return (v & 0x7fffffU) << 0U; | ||
4654 | } | ||
4655 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) | ||
4656 | { | ||
4657 | return 20U; | ||
4658 | } | ||
4659 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) | ||
4660 | { | ||
4661 | return (v & 0xfffffU) << 0U; | ||
4662 | } | ||
4663 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) | ||
4664 | { | ||
4665 | return 0xfffffU << 0U; | ||
4666 | } | ||
4667 | static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) | ||
4668 | { | ||
4669 | return (r >> 0U) & 0xfffffU; | ||
4670 | } | ||
4671 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) | ||
4672 | { | ||
4673 | return 0x0050267cU; | ||
4674 | } | ||
4675 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) | ||
4676 | { | ||
4677 | return 16U; | ||
4678 | } | ||
4679 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) | ||
4680 | { | ||
4681 | return (v & 0xffffU) << 0U; | ||
4682 | } | ||
4683 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) | ||
4684 | { | ||
4685 | return 0xffffU << 0U; | ||
4686 | } | ||
4687 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) | ||
4688 | { | ||
4689 | return (r >> 0U) & 0xffffU; | ||
4690 | } | ||
4691 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) | ||
4692 | { | ||
4693 | return 16U; | ||
4694 | } | ||
4695 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) | ||
4696 | { | ||
4697 | return (v & 0xffffU) << 16U; | ||
4698 | } | ||
4699 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) | ||
4700 | { | ||
4701 | return 0xffffU << 16U; | ||
4702 | } | ||
4703 | static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) | ||
4704 | { | ||
4705 | return (r >> 16U) & 0xffffU; | ||
4706 | } | ||
4707 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) | ||
4708 | { | ||
4709 | return 0x00502680U; | ||
4710 | } | ||
4711 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) | ||
4712 | { | ||
4713 | return (v & 0xffffU) << 0U; | ||
4714 | } | ||
4715 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) | ||
4716 | { | ||
4717 | return 0xffffU << 0U; | ||
4718 | } | ||
4719 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) | ||
4720 | { | ||
4721 | return (r >> 0U) & 0xffffU; | ||
4722 | } | ||
4723 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) | ||
4724 | { | ||
4725 | return 16U; | ||
4726 | } | ||
4727 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) | ||
4728 | { | ||
4729 | return (v & 0xffffU) << 16U; | ||
4730 | } | ||
4731 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) | ||
4732 | { | ||
4733 | return 0xffffU << 16U; | ||
4734 | } | ||
4735 | static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) | ||
4736 | { | ||
4737 | return (r >> 16U) & 0xffffU; | ||
4738 | } | ||
4739 | static inline u32 gr_fecs_falcon_ecc_status_r(void) | ||
4740 | { | ||
4741 | return 0x00409678U; | ||
4742 | } | ||
4743 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) | ||
4744 | { | ||
4745 | return (v & 0x1U) << 0U; | ||
4746 | } | ||
4747 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) | ||
4748 | { | ||
4749 | return 0x1U << 0U; | ||
4750 | } | ||
4751 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) | ||
4752 | { | ||
4753 | return 0x1U; | ||
4754 | } | ||
4755 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) | ||
4756 | { | ||
4757 | return (v & 0x1U) << 1U; | ||
4758 | } | ||
4759 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) | ||
4760 | { | ||
4761 | return 0x1U << 1U; | ||
4762 | } | ||
4763 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) | ||
4764 | { | ||
4765 | return 0x2U; | ||
4766 | } | ||
4767 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) | ||
4768 | { | ||
4769 | return (v & 0x1U) << 4U; | ||
4770 | } | ||
4771 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) | ||
4772 | { | ||
4773 | return 0x1U << 4U; | ||
4774 | } | ||
4775 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) | ||
4776 | { | ||
4777 | return 0x10U; | ||
4778 | } | ||
4779 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) | ||
4780 | { | ||
4781 | return (v & 0x1U) << 5U; | ||
4782 | } | ||
4783 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) | ||
4784 | { | ||
4785 | return 0x1U << 5U; | ||
4786 | } | ||
4787 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) | ||
4788 | { | ||
4789 | return 0x20U; | ||
4790 | } | ||
4791 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) | ||
4792 | { | ||
4793 | return (v & 0x1U) << 10U; | ||
4794 | } | ||
4795 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
4796 | { | ||
4797 | return 0x1U << 10U; | ||
4798 | } | ||
4799 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) | ||
4800 | { | ||
4801 | return 0x400U; | ||
4802 | } | ||
4803 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) | ||
4804 | { | ||
4805 | return (v & 0x1U) << 8U; | ||
4806 | } | ||
4807 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
4808 | { | ||
4809 | return 0x1U << 8U; | ||
4810 | } | ||
4811 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) | ||
4812 | { | ||
4813 | return 0x100U; | ||
4814 | } | ||
4815 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) | ||
4816 | { | ||
4817 | return (v & 0x1U) << 11U; | ||
4818 | } | ||
4819 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) | ||
4820 | { | ||
4821 | return 0x1U << 11U; | ||
4822 | } | ||
4823 | static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) | ||
4824 | { | ||
4825 | return 0x800U; | ||
4826 | } | ||
4827 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) | ||
4828 | { | ||
4829 | return (v & 0x1U) << 9U; | ||
4830 | } | ||
4831 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) | ||
4832 | { | ||
4833 | return 0x1U << 9U; | ||
4834 | } | ||
4835 | static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) | ||
4836 | { | ||
4837 | return 0x200U; | ||
4838 | } | ||
4839 | static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) | ||
4840 | { | ||
4841 | return (v & 0x1U) << 31U; | ||
4842 | } | ||
4843 | static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) | ||
4844 | { | ||
4845 | return 0x80000000U; | ||
4846 | } | ||
4847 | static inline u32 gr_fecs_falcon_ecc_address_r(void) | ||
4848 | { | ||
4849 | return 0x00409684U; | ||
4850 | } | ||
4851 | static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) | ||
4852 | { | ||
4853 | return (v & 0x7fffffU) << 0U; | ||
4854 | } | ||
4855 | static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) | ||
4856 | { | ||
4857 | return 20U; | ||
4858 | } | ||
4859 | static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) | ||
4860 | { | ||
4861 | return (v & 0xfffffU) << 0U; | ||
4862 | } | ||
4863 | static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) | ||
4864 | { | ||
4865 | return 0xfffffU << 0U; | ||
4866 | } | ||
4867 | static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) | ||
4868 | { | ||
4869 | return (r >> 0U) & 0xfffffU; | ||
4870 | } | ||
4871 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) | ||
4872 | { | ||
4873 | return 0x0040967cU; | ||
4874 | } | ||
4875 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) | ||
4876 | { | ||
4877 | return 16U; | ||
4878 | } | ||
4879 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) | ||
4880 | { | ||
4881 | return (v & 0xffffU) << 0U; | ||
4882 | } | ||
4883 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) | ||
4884 | { | ||
4885 | return 0xffffU << 0U; | ||
4886 | } | ||
4887 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) | ||
4888 | { | ||
4889 | return (r >> 0U) & 0xffffU; | ||
4890 | } | ||
4891 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) | ||
4892 | { | ||
4893 | return 16U; | ||
4894 | } | ||
4895 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) | ||
4896 | { | ||
4897 | return (v & 0xffffU) << 16U; | ||
4898 | } | ||
4899 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) | ||
4900 | { | ||
4901 | return 0xffffU << 16U; | ||
4902 | } | ||
4903 | static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) | ||
4904 | { | ||
4905 | return (r >> 16U) & 0xffffU; | ||
4906 | } | ||
4907 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) | ||
4908 | { | ||
4909 | return 0x00409680U; | ||
4910 | } | ||
4911 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) | ||
4912 | { | ||
4913 | return (v & 0xffffU) << 0U; | ||
4914 | } | ||
4915 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) | ||
4916 | { | ||
4917 | return 0xffffU << 0U; | ||
4918 | } | ||
4919 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) | ||
4920 | { | ||
4921 | return (r >> 0U) & 0xffffU; | ||
4922 | } | ||
4923 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) | ||
4924 | { | ||
4925 | return 16U; | ||
4926 | } | ||
4927 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) | ||
4928 | { | ||
4929 | return (v & 0xffffU) << 16U; | ||
4930 | } | ||
4931 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) | ||
4932 | { | ||
4933 | return 0xffffU << 16U; | ||
4934 | } | ||
4935 | static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) | ||
4936 | { | ||
4937 | return (r >> 16U) & 0xffffU; | ||
4938 | } | ||
4939 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h new file mode 100644 index 00000000..769bcf0c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | |||
@@ -0,0 +1,803 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ltc_gv11b_h_ | ||
57 | #define _hw_ltc_gv11b_h_ | ||
58 | |||
59 | static inline u32 ltc_pltcg_base_v(void) | ||
60 | { | ||
61 | return 0x00140000U; | ||
62 | } | ||
63 | static inline u32 ltc_pltcg_extent_v(void) | ||
64 | { | ||
65 | return 0x0017ffffU; | ||
66 | } | ||
67 | static inline u32 ltc_ltc0_ltss_v(void) | ||
68 | { | ||
69 | return 0x00140200U; | ||
70 | } | ||
71 | static inline u32 ltc_ltc0_lts0_v(void) | ||
72 | { | ||
73 | return 0x00140400U; | ||
74 | } | ||
75 | static inline u32 ltc_ltcs_ltss_v(void) | ||
76 | { | ||
77 | return 0x0017e200U; | ||
78 | } | ||
79 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | ||
80 | { | ||
81 | return 0x0014046cU; | ||
82 | } | ||
83 | static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) | ||
84 | { | ||
85 | return 0x00140518U; | ||
86 | } | ||
87 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) | ||
88 | { | ||
89 | return 0x0017e318U; | ||
90 | } | ||
91 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) | ||
92 | { | ||
93 | return 0x1U << 15U; | ||
94 | } | ||
95 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) | ||
96 | { | ||
97 | return 0x00140494U; | ||
98 | } | ||
99 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) | ||
100 | { | ||
101 | return (r >> 0U) & 0xffffU; | ||
102 | } | ||
103 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) | ||
104 | { | ||
105 | return (r >> 16U) & 0x3U; | ||
106 | } | ||
107 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) | ||
108 | { | ||
109 | return 0x00000000U; | ||
110 | } | ||
111 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) | ||
112 | { | ||
113 | return 0x00000001U; | ||
114 | } | ||
115 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) | ||
116 | { | ||
117 | return 0x00000002U; | ||
118 | } | ||
119 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) | ||
120 | { | ||
121 | return 0x0017e26cU; | ||
122 | } | ||
123 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) | ||
124 | { | ||
125 | return 0x1U; | ||
126 | } | ||
127 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) | ||
128 | { | ||
129 | return 0x2U; | ||
130 | } | ||
131 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) | ||
132 | { | ||
133 | return (r >> 2U) & 0x1U; | ||
134 | } | ||
135 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) | ||
136 | { | ||
137 | return 0x00000001U; | ||
138 | } | ||
139 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) | ||
140 | { | ||
141 | return 0x4U; | ||
142 | } | ||
143 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) | ||
144 | { | ||
145 | return 0x0014046cU; | ||
146 | } | ||
147 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | ||
148 | { | ||
149 | return 0x0017e270U; | ||
150 | } | ||
151 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x3ffffU) << 0U; | ||
154 | } | ||
155 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | ||
156 | { | ||
157 | return 0x0017e274U; | ||
158 | } | ||
159 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x3ffffU) << 0U; | ||
162 | } | ||
163 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) | ||
164 | { | ||
165 | return 0x0003ffffU; | ||
166 | } | ||
167 | static inline u32 ltc_ltcs_ltss_cbc_base_r(void) | ||
168 | { | ||
169 | return 0x0017e278U; | ||
170 | } | ||
171 | static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) | ||
172 | { | ||
173 | return 0x0000000bU; | ||
174 | } | ||
175 | static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) | ||
176 | { | ||
177 | return (r >> 0U) & 0x3ffffffU; | ||
178 | } | ||
179 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) | ||
180 | { | ||
181 | return 0x0017e27cU; | ||
182 | } | ||
183 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) | ||
184 | { | ||
185 | return (r >> 0U) & 0x1fU; | ||
186 | } | ||
187 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 24U; | ||
190 | } | ||
191 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) | ||
192 | { | ||
193 | return (r >> 24U) & 0x1U; | ||
194 | } | ||
195 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x1U) << 25U; | ||
198 | } | ||
199 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) | ||
200 | { | ||
201 | return (r >> 25U) & 0x1U; | ||
202 | } | ||
203 | static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) | ||
204 | { | ||
205 | return 0x0017e000U; | ||
206 | } | ||
207 | static inline u32 ltc_ltcs_ltss_cbc_param_r(void) | ||
208 | { | ||
209 | return 0x0017e280U; | ||
210 | } | ||
211 | static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) | ||
212 | { | ||
213 | return (r >> 0U) & 0xffffU; | ||
214 | } | ||
215 | static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) | ||
216 | { | ||
217 | return (r >> 24U) & 0xfU; | ||
218 | } | ||
219 | static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) | ||
220 | { | ||
221 | return (r >> 28U) & 0xfU; | ||
222 | } | ||
223 | static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) | ||
224 | { | ||
225 | return 0x0017e3f4U; | ||
226 | } | ||
227 | static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) | ||
228 | { | ||
229 | return (r >> 0U) & 0xffffU; | ||
230 | } | ||
231 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) | ||
232 | { | ||
233 | return 0x0017e2acU; | ||
234 | } | ||
235 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1fU) << 16U; | ||
238 | } | ||
239 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) | ||
240 | { | ||
241 | return 0x0017e338U; | ||
242 | } | ||
243 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xfU) << 0U; | ||
246 | } | ||
247 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) | ||
248 | { | ||
249 | return 0x0017e33cU + i*4U; | ||
250 | } | ||
251 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) | ||
252 | { | ||
253 | return 0x00000004U; | ||
254 | } | ||
255 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) | ||
256 | { | ||
257 | return 0x0017e34cU; | ||
258 | } | ||
259 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) | ||
260 | { | ||
261 | return 32U; | ||
262 | } | ||
263 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) | ||
264 | { | ||
265 | return (v & 0xffffffffU) << 0U; | ||
266 | } | ||
267 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) | ||
268 | { | ||
269 | return 0xffffffffU << 0U; | ||
270 | } | ||
271 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) | ||
272 | { | ||
273 | return (r >> 0U) & 0xffffffffU; | ||
274 | } | ||
275 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) | ||
276 | { | ||
277 | return 0x0017e204U; | ||
278 | } | ||
279 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) | ||
280 | { | ||
281 | return 8U; | ||
282 | } | ||
283 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) | ||
284 | { | ||
285 | return (v & 0xffU) << 0U; | ||
286 | } | ||
287 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) | ||
288 | { | ||
289 | return 0xffU << 0U; | ||
290 | } | ||
291 | static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) | ||
292 | { | ||
293 | return (r >> 0U) & 0xffU; | ||
294 | } | ||
295 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) | ||
296 | { | ||
297 | return 0x0017e2b0U; | ||
298 | } | ||
299 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) | ||
300 | { | ||
301 | return 0x10000000U; | ||
302 | } | ||
303 | static inline u32 ltc_ltcs_ltss_g_elpg_r(void) | ||
304 | { | ||
305 | return 0x0017e214U; | ||
306 | } | ||
307 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) | ||
308 | { | ||
309 | return (r >> 0U) & 0x1U; | ||
310 | } | ||
311 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) | ||
312 | { | ||
313 | return 0x00000001U; | ||
314 | } | ||
315 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) | ||
316 | { | ||
317 | return 0x1U; | ||
318 | } | ||
319 | static inline u32 ltc_ltc0_ltss_g_elpg_r(void) | ||
320 | { | ||
321 | return 0x00140214U; | ||
322 | } | ||
323 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) | ||
324 | { | ||
325 | return (r >> 0U) & 0x1U; | ||
326 | } | ||
327 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) | ||
328 | { | ||
329 | return 0x00000001U; | ||
330 | } | ||
331 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) | ||
332 | { | ||
333 | return 0x1U; | ||
334 | } | ||
335 | static inline u32 ltc_ltc1_ltss_g_elpg_r(void) | ||
336 | { | ||
337 | return 0x00142214U; | ||
338 | } | ||
339 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) | ||
340 | { | ||
341 | return (r >> 0U) & 0x1U; | ||
342 | } | ||
343 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) | ||
344 | { | ||
345 | return 0x00000001U; | ||
346 | } | ||
347 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) | ||
348 | { | ||
349 | return 0x1U; | ||
350 | } | ||
351 | static inline u32 ltc_ltcs_ltss_intr_r(void) | ||
352 | { | ||
353 | return 0x0017e20cU; | ||
354 | } | ||
355 | static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) | ||
356 | { | ||
357 | return 0x100U; | ||
358 | } | ||
359 | static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) | ||
360 | { | ||
361 | return 0x200U; | ||
362 | } | ||
363 | static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) | ||
364 | { | ||
365 | return 0x1U << 20U; | ||
366 | } | ||
367 | static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) | ||
368 | { | ||
369 | return 0x1U << 30U; | ||
370 | } | ||
371 | static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) | ||
372 | { | ||
373 | return 0x1000000U; | ||
374 | } | ||
375 | static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) | ||
376 | { | ||
377 | return 0x2000000U; | ||
378 | } | ||
379 | static inline u32 ltc_ltc0_lts0_intr_r(void) | ||
380 | { | ||
381 | return 0x0014040cU; | ||
382 | } | ||
383 | static inline u32 ltc_ltcs_ltss_intr3_r(void) | ||
384 | { | ||
385 | return 0x0017e388U; | ||
386 | } | ||
387 | static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) | ||
388 | { | ||
389 | return 0x1U << 7U; | ||
390 | } | ||
391 | static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) | ||
392 | { | ||
393 | return 0x1U << 8U; | ||
394 | } | ||
395 | static inline u32 ltc_ltc0_lts0_intr3_r(void) | ||
396 | { | ||
397 | return 0x00140588U; | ||
398 | } | ||
399 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void) | ||
400 | { | ||
401 | return 0x001404f0U; | ||
402 | } | ||
403 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) | ||
404 | { | ||
405 | return (v & 0x1U) << 1U; | ||
406 | } | ||
407 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) | ||
408 | { | ||
409 | return 0x1U << 1U; | ||
410 | } | ||
411 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) | ||
412 | { | ||
413 | return (v & 0x1U) << 3U; | ||
414 | } | ||
415 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) | ||
416 | { | ||
417 | return 0x1U << 3U; | ||
418 | } | ||
419 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) | ||
420 | { | ||
421 | return (v & 0x1U) << 5U; | ||
422 | } | ||
423 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) | ||
424 | { | ||
425 | return 0x1U << 5U; | ||
426 | } | ||
427 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) | ||
428 | { | ||
429 | return (v & 0x1U) << 0U; | ||
430 | } | ||
431 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) | ||
432 | { | ||
433 | return 0x1U << 0U; | ||
434 | } | ||
435 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) | ||
436 | { | ||
437 | return (v & 0x1U) << 2U; | ||
438 | } | ||
439 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) | ||
440 | { | ||
441 | return 0x1U << 2U; | ||
442 | } | ||
443 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) | ||
444 | { | ||
445 | return (v & 0x1U) << 4U; | ||
446 | } | ||
447 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) | ||
448 | { | ||
449 | return 0x1U << 4U; | ||
450 | } | ||
451 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) | ||
452 | { | ||
453 | return (v & 0x1U) << 18U; | ||
454 | } | ||
455 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
456 | { | ||
457 | return 0x1U << 18U; | ||
458 | } | ||
459 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) | ||
460 | { | ||
461 | return (v & 0x1U) << 16U; | ||
462 | } | ||
463 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
464 | { | ||
465 | return 0x1U << 16U; | ||
466 | } | ||
467 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) | ||
468 | { | ||
469 | return (v & 0x1U) << 19U; | ||
470 | } | ||
471 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) | ||
472 | { | ||
473 | return 0x1U << 19U; | ||
474 | } | ||
475 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) | ||
476 | { | ||
477 | return (v & 0x1U) << 17U; | ||
478 | } | ||
479 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) | ||
480 | { | ||
481 | return 0x1U << 17U; | ||
482 | } | ||
483 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) | ||
484 | { | ||
485 | return (v & 0x1U) << 30U; | ||
486 | } | ||
487 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void) | ||
488 | { | ||
489 | return 0x40000000U; | ||
490 | } | ||
491 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void) | ||
492 | { | ||
493 | return 0x001404fcU; | ||
494 | } | ||
495 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void) | ||
496 | { | ||
497 | return 0x001404f4U; | ||
498 | } | ||
499 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void) | ||
500 | { | ||
501 | return 16U; | ||
502 | } | ||
503 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) | ||
504 | { | ||
505 | return (v & 0xffffU) << 0U; | ||
506 | } | ||
507 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) | ||
508 | { | ||
509 | return 0xffffU << 0U; | ||
510 | } | ||
511 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) | ||
512 | { | ||
513 | return (r >> 0U) & 0xffffU; | ||
514 | } | ||
515 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void) | ||
516 | { | ||
517 | return 16U; | ||
518 | } | ||
519 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v) | ||
520 | { | ||
521 | return (v & 0xffffU) << 16U; | ||
522 | } | ||
523 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) | ||
524 | { | ||
525 | return 0xffffU << 16U; | ||
526 | } | ||
527 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) | ||
528 | { | ||
529 | return (r >> 16U) & 0xffffU; | ||
530 | } | ||
531 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void) | ||
532 | { | ||
533 | return 0x001404f8U; | ||
534 | } | ||
535 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void) | ||
536 | { | ||
537 | return 16U; | ||
538 | } | ||
539 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v) | ||
540 | { | ||
541 | return (v & 0xffffU) << 0U; | ||
542 | } | ||
543 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) | ||
544 | { | ||
545 | return 0xffffU << 0U; | ||
546 | } | ||
547 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) | ||
548 | { | ||
549 | return (r >> 0U) & 0xffffU; | ||
550 | } | ||
551 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void) | ||
552 | { | ||
553 | return 16U; | ||
554 | } | ||
555 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v) | ||
556 | { | ||
557 | return (v & 0xffffU) << 16U; | ||
558 | } | ||
559 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) | ||
560 | { | ||
561 | return 0xffffU << 16U; | ||
562 | } | ||
563 | static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) | ||
564 | { | ||
565 | return (r >> 16U) & 0xffffU; | ||
566 | } | ||
567 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) | ||
568 | { | ||
569 | return 0x0014051cU; | ||
570 | } | ||
571 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) | ||
572 | { | ||
573 | return 0xffU << 0U; | ||
574 | } | ||
575 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) | ||
576 | { | ||
577 | return (r >> 0U) & 0xffU; | ||
578 | } | ||
579 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) | ||
580 | { | ||
581 | return 0xffU << 16U; | ||
582 | } | ||
583 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) | ||
584 | { | ||
585 | return (r >> 16U) & 0xffU; | ||
586 | } | ||
587 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) | ||
588 | { | ||
589 | return 0x0017e2a0U; | ||
590 | } | ||
591 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
592 | { | ||
593 | return (r >> 0U) & 0x1U; | ||
594 | } | ||
595 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
596 | { | ||
597 | return 0x00000001U; | ||
598 | } | ||
599 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
600 | { | ||
601 | return 0x1U; | ||
602 | } | ||
603 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) | ||
604 | { | ||
605 | return (r >> 8U) & 0xfU; | ||
606 | } | ||
607 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) | ||
608 | { | ||
609 | return 0x00000003U; | ||
610 | } | ||
611 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) | ||
612 | { | ||
613 | return 0x300U; | ||
614 | } | ||
615 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) | ||
616 | { | ||
617 | return (r >> 28U) & 0x1U; | ||
618 | } | ||
619 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) | ||
620 | { | ||
621 | return 0x00000001U; | ||
622 | } | ||
623 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) | ||
624 | { | ||
625 | return 0x10000000U; | ||
626 | } | ||
627 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) | ||
628 | { | ||
629 | return (r >> 29U) & 0x1U; | ||
630 | } | ||
631 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) | ||
632 | { | ||
633 | return 0x00000001U; | ||
634 | } | ||
635 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) | ||
636 | { | ||
637 | return 0x20000000U; | ||
638 | } | ||
639 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) | ||
640 | { | ||
641 | return (r >> 30U) & 0x1U; | ||
642 | } | ||
643 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) | ||
644 | { | ||
645 | return 0x00000001U; | ||
646 | } | ||
647 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) | ||
648 | { | ||
649 | return 0x40000000U; | ||
650 | } | ||
651 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) | ||
652 | { | ||
653 | return 0x0017e2a4U; | ||
654 | } | ||
655 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
656 | { | ||
657 | return (r >> 0U) & 0x1U; | ||
658 | } | ||
659 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
660 | { | ||
661 | return 0x00000001U; | ||
662 | } | ||
663 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
664 | { | ||
665 | return 0x1U; | ||
666 | } | ||
667 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) | ||
668 | { | ||
669 | return (r >> 8U) & 0xfU; | ||
670 | } | ||
671 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) | ||
672 | { | ||
673 | return 0x00000003U; | ||
674 | } | ||
675 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) | ||
676 | { | ||
677 | return 0x300U; | ||
678 | } | ||
679 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) | ||
680 | { | ||
681 | return (r >> 16U) & 0x1U; | ||
682 | } | ||
683 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) | ||
684 | { | ||
685 | return 0x00000001U; | ||
686 | } | ||
687 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) | ||
688 | { | ||
689 | return 0x10000U; | ||
690 | } | ||
691 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) | ||
692 | { | ||
693 | return (r >> 28U) & 0x1U; | ||
694 | } | ||
695 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) | ||
696 | { | ||
697 | return 0x00000001U; | ||
698 | } | ||
699 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) | ||
700 | { | ||
701 | return 0x10000000U; | ||
702 | } | ||
703 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) | ||
704 | { | ||
705 | return (r >> 29U) & 0x1U; | ||
706 | } | ||
707 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) | ||
708 | { | ||
709 | return 0x00000001U; | ||
710 | } | ||
711 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) | ||
712 | { | ||
713 | return 0x20000000U; | ||
714 | } | ||
715 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) | ||
716 | { | ||
717 | return (r >> 30U) & 0x1U; | ||
718 | } | ||
719 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) | ||
720 | { | ||
721 | return 0x00000001U; | ||
722 | } | ||
723 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) | ||
724 | { | ||
725 | return 0x40000000U; | ||
726 | } | ||
727 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) | ||
728 | { | ||
729 | return 0x001402a0U; | ||
730 | } | ||
731 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
732 | { | ||
733 | return (r >> 0U) & 0x1U; | ||
734 | } | ||
735 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
736 | { | ||
737 | return 0x00000001U; | ||
738 | } | ||
739 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
740 | { | ||
741 | return 0x1U; | ||
742 | } | ||
743 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) | ||
744 | { | ||
745 | return 0x001402a4U; | ||
746 | } | ||
747 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
748 | { | ||
749 | return (r >> 0U) & 0x1U; | ||
750 | } | ||
751 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
752 | { | ||
753 | return 0x00000001U; | ||
754 | } | ||
755 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
756 | { | ||
757 | return 0x1U; | ||
758 | } | ||
759 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) | ||
760 | { | ||
761 | return 0x001422a0U; | ||
762 | } | ||
763 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
764 | { | ||
765 | return (r >> 0U) & 0x1U; | ||
766 | } | ||
767 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
768 | { | ||
769 | return 0x00000001U; | ||
770 | } | ||
771 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
772 | { | ||
773 | return 0x1U; | ||
774 | } | ||
775 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) | ||
776 | { | ||
777 | return 0x001422a4U; | ||
778 | } | ||
779 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
780 | { | ||
781 | return (r >> 0U) & 0x1U; | ||
782 | } | ||
783 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
784 | { | ||
785 | return 0x00000001U; | ||
786 | } | ||
787 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
788 | { | ||
789 | return 0x1U; | ||
790 | } | ||
791 | static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) | ||
792 | { | ||
793 | return 0x0014058cU; | ||
794 | } | ||
795 | static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) | ||
796 | { | ||
797 | return (r >> 0U) & 0xffffU; | ||
798 | } | ||
799 | static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) | ||
800 | { | ||
801 | return (r >> 16U) & 0x1fU; | ||
802 | } | ||
803 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h new file mode 100644 index 00000000..bff73076 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | |||
@@ -0,0 +1,251 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_mc_gv11b_h_ | ||
57 | #define _hw_mc_gv11b_h_ | ||
58 | |||
59 | static inline u32 mc_boot_0_r(void) | ||
60 | { | ||
61 | return 0x00000000U; | ||
62 | } | ||
63 | static inline u32 mc_boot_0_architecture_v(u32 r) | ||
64 | { | ||
65 | return (r >> 24U) & 0x1fU; | ||
66 | } | ||
67 | static inline u32 mc_boot_0_implementation_v(u32 r) | ||
68 | { | ||
69 | return (r >> 20U) & 0xfU; | ||
70 | } | ||
71 | static inline u32 mc_boot_0_major_revision_v(u32 r) | ||
72 | { | ||
73 | return (r >> 4U) & 0xfU; | ||
74 | } | ||
75 | static inline u32 mc_boot_0_minor_revision_v(u32 r) | ||
76 | { | ||
77 | return (r >> 0U) & 0xfU; | ||
78 | } | ||
79 | static inline u32 mc_intr_r(u32 i) | ||
80 | { | ||
81 | return 0x00000100U + i*4U; | ||
82 | } | ||
83 | static inline u32 mc_intr_pfifo_pending_f(void) | ||
84 | { | ||
85 | return 0x100U; | ||
86 | } | ||
87 | static inline u32 mc_intr_hub_pending_f(void) | ||
88 | { | ||
89 | return 0x200U; | ||
90 | } | ||
91 | static inline u32 mc_intr_pgraph_pending_f(void) | ||
92 | { | ||
93 | return 0x1000U; | ||
94 | } | ||
95 | static inline u32 mc_intr_pmu_pending_f(void) | ||
96 | { | ||
97 | return 0x1000000U; | ||
98 | } | ||
99 | static inline u32 mc_intr_ltc_pending_f(void) | ||
100 | { | ||
101 | return 0x2000000U; | ||
102 | } | ||
103 | static inline u32 mc_intr_priv_ring_pending_f(void) | ||
104 | { | ||
105 | return 0x40000000U; | ||
106 | } | ||
107 | static inline u32 mc_intr_pbus_pending_f(void) | ||
108 | { | ||
109 | return 0x10000000U; | ||
110 | } | ||
111 | static inline u32 mc_intr_en_r(u32 i) | ||
112 | { | ||
113 | return 0x00000140U + i*4U; | ||
114 | } | ||
115 | static inline u32 mc_intr_en_set_r(u32 i) | ||
116 | { | ||
117 | return 0x00000160U + i*4U; | ||
118 | } | ||
119 | static inline u32 mc_intr_en_clear_r(u32 i) | ||
120 | { | ||
121 | return 0x00000180U + i*4U; | ||
122 | } | ||
123 | static inline u32 mc_enable_r(void) | ||
124 | { | ||
125 | return 0x00000200U; | ||
126 | } | ||
127 | static inline u32 mc_enable_xbar_enabled_f(void) | ||
128 | { | ||
129 | return 0x4U; | ||
130 | } | ||
131 | static inline u32 mc_enable_l2_enabled_f(void) | ||
132 | { | ||
133 | return 0x8U; | ||
134 | } | ||
135 | static inline u32 mc_enable_pmedia_s(void) | ||
136 | { | ||
137 | return 1U; | ||
138 | } | ||
139 | static inline u32 mc_enable_pmedia_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 4U; | ||
142 | } | ||
143 | static inline u32 mc_enable_pmedia_m(void) | ||
144 | { | ||
145 | return 0x1U << 4U; | ||
146 | } | ||
147 | static inline u32 mc_enable_pmedia_v(u32 r) | ||
148 | { | ||
149 | return (r >> 4U) & 0x1U; | ||
150 | } | ||
151 | static inline u32 mc_enable_ce0_m(void) | ||
152 | { | ||
153 | return 0x1U << 6U; | ||
154 | } | ||
155 | static inline u32 mc_enable_pfifo_enabled_f(void) | ||
156 | { | ||
157 | return 0x100U; | ||
158 | } | ||
159 | static inline u32 mc_enable_pgraph_enabled_f(void) | ||
160 | { | ||
161 | return 0x1000U; | ||
162 | } | ||
163 | static inline u32 mc_enable_pwr_v(u32 r) | ||
164 | { | ||
165 | return (r >> 13U) & 0x1U; | ||
166 | } | ||
167 | static inline u32 mc_enable_pwr_disabled_v(void) | ||
168 | { | ||
169 | return 0x00000000U; | ||
170 | } | ||
171 | static inline u32 mc_enable_pwr_enabled_f(void) | ||
172 | { | ||
173 | return 0x2000U; | ||
174 | } | ||
175 | static inline u32 mc_enable_pfb_enabled_f(void) | ||
176 | { | ||
177 | return 0x100000U; | ||
178 | } | ||
179 | static inline u32 mc_enable_ce2_m(void) | ||
180 | { | ||
181 | return 0x1U << 21U; | ||
182 | } | ||
183 | static inline u32 mc_enable_ce2_enabled_f(void) | ||
184 | { | ||
185 | return 0x200000U; | ||
186 | } | ||
187 | static inline u32 mc_enable_blg_enabled_f(void) | ||
188 | { | ||
189 | return 0x8000000U; | ||
190 | } | ||
191 | static inline u32 mc_enable_perfmon_enabled_f(void) | ||
192 | { | ||
193 | return 0x10000000U; | ||
194 | } | ||
195 | static inline u32 mc_enable_hub_enabled_f(void) | ||
196 | { | ||
197 | return 0x20000000U; | ||
198 | } | ||
199 | static inline u32 mc_intr_ltc_r(void) | ||
200 | { | ||
201 | return 0x000001c0U; | ||
202 | } | ||
203 | static inline u32 mc_enable_pb_r(void) | ||
204 | { | ||
205 | return 0x00000204U; | ||
206 | } | ||
207 | static inline u32 mc_enable_pb_0_s(void) | ||
208 | { | ||
209 | return 1U; | ||
210 | } | ||
211 | static inline u32 mc_enable_pb_0_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x1U) << 0U; | ||
214 | } | ||
215 | static inline u32 mc_enable_pb_0_m(void) | ||
216 | { | ||
217 | return 0x1U << 0U; | ||
218 | } | ||
219 | static inline u32 mc_enable_pb_0_v(u32 r) | ||
220 | { | ||
221 | return (r >> 0U) & 0x1U; | ||
222 | } | ||
223 | static inline u32 mc_enable_pb_0_enabled_v(void) | ||
224 | { | ||
225 | return 0x00000001U; | ||
226 | } | ||
227 | static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) | ||
228 | { | ||
229 | return (v & 0x1U) << (0U + i*1U); | ||
230 | } | ||
231 | static inline u32 mc_elpg_enable_r(void) | ||
232 | { | ||
233 | return 0x0000020cU; | ||
234 | } | ||
235 | static inline u32 mc_elpg_enable_xbar_enabled_f(void) | ||
236 | { | ||
237 | return 0x4U; | ||
238 | } | ||
239 | static inline u32 mc_elpg_enable_pfb_enabled_f(void) | ||
240 | { | ||
241 | return 0x100000U; | ||
242 | } | ||
243 | static inline u32 mc_elpg_enable_hub_enabled_f(void) | ||
244 | { | ||
245 | return 0x20000000U; | ||
246 | } | ||
247 | static inline u32 mc_elpg_enable_l2_enabled_f(void) | ||
248 | { | ||
249 | return 0x8U; | ||
250 | } | ||
251 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h new file mode 100644 index 00000000..9b9017ee --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | |||
@@ -0,0 +1,659 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pbdma_gv11b_h_ | ||
57 | #define _hw_pbdma_gv11b_h_ | ||
58 | |||
59 | static inline u32 pbdma_gp_entry1_r(void) | ||
60 | { | ||
61 | return 0x10000004U; | ||
62 | } | ||
63 | static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) | ||
64 | { | ||
65 | return (r >> 0U) & 0xffU; | ||
66 | } | ||
67 | static inline u32 pbdma_gp_entry1_length_f(u32 v) | ||
68 | { | ||
69 | return (v & 0x1fffffU) << 10U; | ||
70 | } | ||
71 | static inline u32 pbdma_gp_entry1_length_v(u32 r) | ||
72 | { | ||
73 | return (r >> 10U) & 0x1fffffU; | ||
74 | } | ||
75 | static inline u32 pbdma_gp_base_r(u32 i) | ||
76 | { | ||
77 | return 0x00040048U + i*8192U; | ||
78 | } | ||
79 | static inline u32 pbdma_gp_base__size_1_v(void) | ||
80 | { | ||
81 | return 0x00000003U; | ||
82 | } | ||
83 | static inline u32 pbdma_gp_base_offset_f(u32 v) | ||
84 | { | ||
85 | return (v & 0x1fffffffU) << 3U; | ||
86 | } | ||
87 | static inline u32 pbdma_gp_base_rsvd_s(void) | ||
88 | { | ||
89 | return 3U; | ||
90 | } | ||
91 | static inline u32 pbdma_gp_base_hi_r(u32 i) | ||
92 | { | ||
93 | return 0x0004004cU + i*8192U; | ||
94 | } | ||
95 | static inline u32 pbdma_gp_base_hi_offset_f(u32 v) | ||
96 | { | ||
97 | return (v & 0xffU) << 0U; | ||
98 | } | ||
99 | static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1fU) << 16U; | ||
102 | } | ||
103 | static inline u32 pbdma_gp_fetch_r(u32 i) | ||
104 | { | ||
105 | return 0x00040050U + i*8192U; | ||
106 | } | ||
107 | static inline u32 pbdma_gp_get_r(u32 i) | ||
108 | { | ||
109 | return 0x00040014U + i*8192U; | ||
110 | } | ||
111 | static inline u32 pbdma_gp_put_r(u32 i) | ||
112 | { | ||
113 | return 0x00040000U + i*8192U; | ||
114 | } | ||
115 | static inline u32 pbdma_pb_fetch_r(u32 i) | ||
116 | { | ||
117 | return 0x00040054U + i*8192U; | ||
118 | } | ||
119 | static inline u32 pbdma_pb_fetch_hi_r(u32 i) | ||
120 | { | ||
121 | return 0x00040058U + i*8192U; | ||
122 | } | ||
123 | static inline u32 pbdma_get_r(u32 i) | ||
124 | { | ||
125 | return 0x00040018U + i*8192U; | ||
126 | } | ||
127 | static inline u32 pbdma_get_hi_r(u32 i) | ||
128 | { | ||
129 | return 0x0004001cU + i*8192U; | ||
130 | } | ||
131 | static inline u32 pbdma_put_r(u32 i) | ||
132 | { | ||
133 | return 0x0004005cU + i*8192U; | ||
134 | } | ||
135 | static inline u32 pbdma_put_hi_r(u32 i) | ||
136 | { | ||
137 | return 0x00040060U + i*8192U; | ||
138 | } | ||
139 | static inline u32 pbdma_pb_header_r(u32 i) | ||
140 | { | ||
141 | return 0x00040084U + i*8192U; | ||
142 | } | ||
143 | static inline u32 pbdma_pb_header_priv_user_f(void) | ||
144 | { | ||
145 | return 0x0U; | ||
146 | } | ||
147 | static inline u32 pbdma_pb_header_method_zero_f(void) | ||
148 | { | ||
149 | return 0x0U; | ||
150 | } | ||
151 | static inline u32 pbdma_pb_header_subchannel_zero_f(void) | ||
152 | { | ||
153 | return 0x0U; | ||
154 | } | ||
155 | static inline u32 pbdma_pb_header_level_main_f(void) | ||
156 | { | ||
157 | return 0x0U; | ||
158 | } | ||
159 | static inline u32 pbdma_pb_header_first_true_f(void) | ||
160 | { | ||
161 | return 0x400000U; | ||
162 | } | ||
163 | static inline u32 pbdma_pb_header_type_inc_f(void) | ||
164 | { | ||
165 | return 0x20000000U; | ||
166 | } | ||
167 | static inline u32 pbdma_pb_header_type_non_inc_f(void) | ||
168 | { | ||
169 | return 0x60000000U; | ||
170 | } | ||
171 | static inline u32 pbdma_hdr_shadow_r(u32 i) | ||
172 | { | ||
173 | return 0x00040118U + i*8192U; | ||
174 | } | ||
175 | static inline u32 pbdma_gp_shadow_0_r(u32 i) | ||
176 | { | ||
177 | return 0x00040110U + i*8192U; | ||
178 | } | ||
179 | static inline u32 pbdma_gp_shadow_1_r(u32 i) | ||
180 | { | ||
181 | return 0x00040114U + i*8192U; | ||
182 | } | ||
183 | static inline u32 pbdma_subdevice_r(u32 i) | ||
184 | { | ||
185 | return 0x00040094U + i*8192U; | ||
186 | } | ||
187 | static inline u32 pbdma_subdevice_id_f(u32 v) | ||
188 | { | ||
189 | return (v & 0xfffU) << 0U; | ||
190 | } | ||
191 | static inline u32 pbdma_subdevice_status_active_f(void) | ||
192 | { | ||
193 | return 0x10000000U; | ||
194 | } | ||
195 | static inline u32 pbdma_subdevice_channel_dma_enable_f(void) | ||
196 | { | ||
197 | return 0x20000000U; | ||
198 | } | ||
199 | static inline u32 pbdma_method0_r(u32 i) | ||
200 | { | ||
201 | return 0x000400c0U + i*8192U; | ||
202 | } | ||
203 | static inline u32 pbdma_method0_fifo_size_v(void) | ||
204 | { | ||
205 | return 0x00000004U; | ||
206 | } | ||
207 | static inline u32 pbdma_method0_addr_f(u32 v) | ||
208 | { | ||
209 | return (v & 0xfffU) << 2U; | ||
210 | } | ||
211 | static inline u32 pbdma_method0_addr_v(u32 r) | ||
212 | { | ||
213 | return (r >> 2U) & 0xfffU; | ||
214 | } | ||
215 | static inline u32 pbdma_method0_subch_v(u32 r) | ||
216 | { | ||
217 | return (r >> 16U) & 0x7U; | ||
218 | } | ||
219 | static inline u32 pbdma_method0_first_true_f(void) | ||
220 | { | ||
221 | return 0x400000U; | ||
222 | } | ||
223 | static inline u32 pbdma_method0_valid_true_f(void) | ||
224 | { | ||
225 | return 0x80000000U; | ||
226 | } | ||
227 | static inline u32 pbdma_method1_r(u32 i) | ||
228 | { | ||
229 | return 0x000400c8U + i*8192U; | ||
230 | } | ||
231 | static inline u32 pbdma_method2_r(u32 i) | ||
232 | { | ||
233 | return 0x000400d0U + i*8192U; | ||
234 | } | ||
235 | static inline u32 pbdma_method3_r(u32 i) | ||
236 | { | ||
237 | return 0x000400d8U + i*8192U; | ||
238 | } | ||
239 | static inline u32 pbdma_data0_r(u32 i) | ||
240 | { | ||
241 | return 0x000400c4U + i*8192U; | ||
242 | } | ||
243 | static inline u32 pbdma_acquire_r(u32 i) | ||
244 | { | ||
245 | return 0x00040030U + i*8192U; | ||
246 | } | ||
247 | static inline u32 pbdma_acquire_retry_man_2_f(void) | ||
248 | { | ||
249 | return 0x2U; | ||
250 | } | ||
251 | static inline u32 pbdma_acquire_retry_exp_2_f(void) | ||
252 | { | ||
253 | return 0x100U; | ||
254 | } | ||
255 | static inline u32 pbdma_acquire_timeout_exp_f(u32 v) | ||
256 | { | ||
257 | return (v & 0xfU) << 11U; | ||
258 | } | ||
259 | static inline u32 pbdma_acquire_timeout_exp_max_v(void) | ||
260 | { | ||
261 | return 0x0000000fU; | ||
262 | } | ||
263 | static inline u32 pbdma_acquire_timeout_exp_max_f(void) | ||
264 | { | ||
265 | return 0x7800U; | ||
266 | } | ||
267 | static inline u32 pbdma_acquire_timeout_man_f(u32 v) | ||
268 | { | ||
269 | return (v & 0xffffU) << 15U; | ||
270 | } | ||
271 | static inline u32 pbdma_acquire_timeout_man_max_v(void) | ||
272 | { | ||
273 | return 0x0000ffffU; | ||
274 | } | ||
275 | static inline u32 pbdma_acquire_timeout_man_max_f(void) | ||
276 | { | ||
277 | return 0x7fff8000U; | ||
278 | } | ||
279 | static inline u32 pbdma_acquire_timeout_en_enable_f(void) | ||
280 | { | ||
281 | return 0x80000000U; | ||
282 | } | ||
283 | static inline u32 pbdma_acquire_timeout_en_disable_f(void) | ||
284 | { | ||
285 | return 0x0U; | ||
286 | } | ||
287 | static inline u32 pbdma_status_r(u32 i) | ||
288 | { | ||
289 | return 0x00040100U + i*8192U; | ||
290 | } | ||
291 | static inline u32 pbdma_channel_r(u32 i) | ||
292 | { | ||
293 | return 0x00040120U + i*8192U; | ||
294 | } | ||
295 | static inline u32 pbdma_signature_r(u32 i) | ||
296 | { | ||
297 | return 0x00040010U + i*8192U; | ||
298 | } | ||
299 | static inline u32 pbdma_signature_hw_valid_f(void) | ||
300 | { | ||
301 | return 0xfaceU; | ||
302 | } | ||
303 | static inline u32 pbdma_signature_sw_zero_f(void) | ||
304 | { | ||
305 | return 0x0U; | ||
306 | } | ||
307 | static inline u32 pbdma_userd_r(u32 i) | ||
308 | { | ||
309 | return 0x00040008U + i*8192U; | ||
310 | } | ||
311 | static inline u32 pbdma_userd_target_vid_mem_f(void) | ||
312 | { | ||
313 | return 0x0U; | ||
314 | } | ||
315 | static inline u32 pbdma_userd_target_sys_mem_coh_f(void) | ||
316 | { | ||
317 | return 0x2U; | ||
318 | } | ||
319 | static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) | ||
320 | { | ||
321 | return 0x3U; | ||
322 | } | ||
323 | static inline u32 pbdma_userd_addr_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x7fffffU) << 9U; | ||
326 | } | ||
327 | static inline u32 pbdma_config_r(u32 i) | ||
328 | { | ||
329 | return 0x000400f4U + i*8192U; | ||
330 | } | ||
331 | static inline u32 pbdma_config_l2_evict_first_f(void) | ||
332 | { | ||
333 | return 0x0U; | ||
334 | } | ||
335 | static inline u32 pbdma_config_l2_evict_normal_f(void) | ||
336 | { | ||
337 | return 0x1U; | ||
338 | } | ||
339 | static inline u32 pbdma_config_l2_evict_last_f(void) | ||
340 | { | ||
341 | return 0x2U; | ||
342 | } | ||
343 | static inline u32 pbdma_config_ce_split_enable_f(void) | ||
344 | { | ||
345 | return 0x0U; | ||
346 | } | ||
347 | static inline u32 pbdma_config_ce_split_disable_f(void) | ||
348 | { | ||
349 | return 0x10U; | ||
350 | } | ||
351 | static inline u32 pbdma_config_auth_level_non_privileged_f(void) | ||
352 | { | ||
353 | return 0x0U; | ||
354 | } | ||
355 | static inline u32 pbdma_config_auth_level_privileged_f(void) | ||
356 | { | ||
357 | return 0x100U; | ||
358 | } | ||
359 | static inline u32 pbdma_config_userd_writeback_disable_f(void) | ||
360 | { | ||
361 | return 0x0U; | ||
362 | } | ||
363 | static inline u32 pbdma_config_userd_writeback_enable_f(void) | ||
364 | { | ||
365 | return 0x1000U; | ||
366 | } | ||
367 | static inline u32 pbdma_userd_hi_r(u32 i) | ||
368 | { | ||
369 | return 0x0004000cU + i*8192U; | ||
370 | } | ||
371 | static inline u32 pbdma_userd_hi_addr_f(u32 v) | ||
372 | { | ||
373 | return (v & 0xffU) << 0U; | ||
374 | } | ||
375 | static inline u32 pbdma_hce_ctrl_r(u32 i) | ||
376 | { | ||
377 | return 0x000400e4U + i*8192U; | ||
378 | } | ||
379 | static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) | ||
380 | { | ||
381 | return 0x20U; | ||
382 | } | ||
383 | static inline u32 pbdma_intr_0_r(u32 i) | ||
384 | { | ||
385 | return 0x00040108U + i*8192U; | ||
386 | } | ||
387 | static inline u32 pbdma_intr_0_memreq_v(u32 r) | ||
388 | { | ||
389 | return (r >> 0U) & 0x1U; | ||
390 | } | ||
391 | static inline u32 pbdma_intr_0_memreq_pending_f(void) | ||
392 | { | ||
393 | return 0x1U; | ||
394 | } | ||
395 | static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) | ||
396 | { | ||
397 | return 0x2U; | ||
398 | } | ||
399 | static inline u32 pbdma_intr_0_memack_extra_pending_f(void) | ||
400 | { | ||
401 | return 0x4U; | ||
402 | } | ||
403 | static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) | ||
404 | { | ||
405 | return 0x8U; | ||
406 | } | ||
407 | static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) | ||
408 | { | ||
409 | return 0x10U; | ||
410 | } | ||
411 | static inline u32 pbdma_intr_0_memflush_pending_f(void) | ||
412 | { | ||
413 | return 0x20U; | ||
414 | } | ||
415 | static inline u32 pbdma_intr_0_memop_pending_f(void) | ||
416 | { | ||
417 | return 0x40U; | ||
418 | } | ||
419 | static inline u32 pbdma_intr_0_lbconnect_pending_f(void) | ||
420 | { | ||
421 | return 0x80U; | ||
422 | } | ||
423 | static inline u32 pbdma_intr_0_lbreq_pending_f(void) | ||
424 | { | ||
425 | return 0x100U; | ||
426 | } | ||
427 | static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) | ||
428 | { | ||
429 | return 0x200U; | ||
430 | } | ||
431 | static inline u32 pbdma_intr_0_lback_extra_pending_f(void) | ||
432 | { | ||
433 | return 0x400U; | ||
434 | } | ||
435 | static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) | ||
436 | { | ||
437 | return 0x800U; | ||
438 | } | ||
439 | static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) | ||
440 | { | ||
441 | return 0x1000U; | ||
442 | } | ||
443 | static inline u32 pbdma_intr_0_gpfifo_pending_f(void) | ||
444 | { | ||
445 | return 0x2000U; | ||
446 | } | ||
447 | static inline u32 pbdma_intr_0_gpptr_pending_f(void) | ||
448 | { | ||
449 | return 0x4000U; | ||
450 | } | ||
451 | static inline u32 pbdma_intr_0_gpentry_pending_f(void) | ||
452 | { | ||
453 | return 0x8000U; | ||
454 | } | ||
455 | static inline u32 pbdma_intr_0_gpcrc_pending_f(void) | ||
456 | { | ||
457 | return 0x10000U; | ||
458 | } | ||
459 | static inline u32 pbdma_intr_0_pbptr_pending_f(void) | ||
460 | { | ||
461 | return 0x20000U; | ||
462 | } | ||
463 | static inline u32 pbdma_intr_0_pbentry_pending_f(void) | ||
464 | { | ||
465 | return 0x40000U; | ||
466 | } | ||
467 | static inline u32 pbdma_intr_0_pbcrc_pending_f(void) | ||
468 | { | ||
469 | return 0x80000U; | ||
470 | } | ||
471 | static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) | ||
472 | { | ||
473 | return 0x100000U; | ||
474 | } | ||
475 | static inline u32 pbdma_intr_0_method_pending_f(void) | ||
476 | { | ||
477 | return 0x200000U; | ||
478 | } | ||
479 | static inline u32 pbdma_intr_0_methodcrc_pending_f(void) | ||
480 | { | ||
481 | return 0x400000U; | ||
482 | } | ||
483 | static inline u32 pbdma_intr_0_device_pending_f(void) | ||
484 | { | ||
485 | return 0x800000U; | ||
486 | } | ||
487 | static inline u32 pbdma_intr_0_eng_reset_pending_f(void) | ||
488 | { | ||
489 | return 0x1000000U; | ||
490 | } | ||
491 | static inline u32 pbdma_intr_0_semaphore_pending_f(void) | ||
492 | { | ||
493 | return 0x2000000U; | ||
494 | } | ||
495 | static inline u32 pbdma_intr_0_acquire_pending_f(void) | ||
496 | { | ||
497 | return 0x4000000U; | ||
498 | } | ||
499 | static inline u32 pbdma_intr_0_pri_pending_f(void) | ||
500 | { | ||
501 | return 0x8000000U; | ||
502 | } | ||
503 | static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) | ||
504 | { | ||
505 | return 0x20000000U; | ||
506 | } | ||
507 | static inline u32 pbdma_intr_0_pbseg_pending_f(void) | ||
508 | { | ||
509 | return 0x40000000U; | ||
510 | } | ||
511 | static inline u32 pbdma_intr_0_signature_pending_f(void) | ||
512 | { | ||
513 | return 0x80000000U; | ||
514 | } | ||
515 | static inline u32 pbdma_intr_1_r(u32 i) | ||
516 | { | ||
517 | return 0x00040148U + i*8192U; | ||
518 | } | ||
519 | static inline u32 pbdma_intr_1_ctxnotvalid_m(void) | ||
520 | { | ||
521 | return 0x1U << 31U; | ||
522 | } | ||
523 | static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) | ||
524 | { | ||
525 | return 0x80000000U; | ||
526 | } | ||
527 | static inline u32 pbdma_intr_en_0_r(u32 i) | ||
528 | { | ||
529 | return 0x0004010cU + i*8192U; | ||
530 | } | ||
531 | static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) | ||
532 | { | ||
533 | return 0x100U; | ||
534 | } | ||
535 | static inline u32 pbdma_intr_en_1_r(u32 i) | ||
536 | { | ||
537 | return 0x0004014cU + i*8192U; | ||
538 | } | ||
539 | static inline u32 pbdma_intr_stall_r(u32 i) | ||
540 | { | ||
541 | return 0x0004013cU + i*8192U; | ||
542 | } | ||
543 | static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) | ||
544 | { | ||
545 | return 0x100U; | ||
546 | } | ||
547 | static inline u32 pbdma_intr_stall_1_r(u32 i) | ||
548 | { | ||
549 | return 0x00040140U + i*8192U; | ||
550 | } | ||
551 | static inline u32 pbdma_udma_nop_r(void) | ||
552 | { | ||
553 | return 0x00000008U; | ||
554 | } | ||
555 | static inline u32 pbdma_runlist_timeslice_r(u32 i) | ||
556 | { | ||
557 | return 0x000400f8U + i*8192U; | ||
558 | } | ||
559 | static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) | ||
560 | { | ||
561 | return 0x80U; | ||
562 | } | ||
563 | static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) | ||
564 | { | ||
565 | return 0x3000U; | ||
566 | } | ||
567 | static inline u32 pbdma_runlist_timeslice_enable_true_f(void) | ||
568 | { | ||
569 | return 0x10000000U; | ||
570 | } | ||
571 | static inline u32 pbdma_target_r(u32 i) | ||
572 | { | ||
573 | return 0x000400acU + i*8192U; | ||
574 | } | ||
575 | static inline u32 pbdma_target_engine_sw_f(void) | ||
576 | { | ||
577 | return 0x1fU; | ||
578 | } | ||
579 | static inline u32 pbdma_target_eng_ctx_valid_true_f(void) | ||
580 | { | ||
581 | return 0x10000U; | ||
582 | } | ||
583 | static inline u32 pbdma_target_eng_ctx_valid_false_f(void) | ||
584 | { | ||
585 | return 0x0U; | ||
586 | } | ||
587 | static inline u32 pbdma_target_ce_ctx_valid_true_f(void) | ||
588 | { | ||
589 | return 0x20000U; | ||
590 | } | ||
591 | static inline u32 pbdma_target_ce_ctx_valid_false_f(void) | ||
592 | { | ||
593 | return 0x0U; | ||
594 | } | ||
595 | static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) | ||
596 | { | ||
597 | return 0x0U; | ||
598 | } | ||
599 | static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) | ||
600 | { | ||
601 | return 0x1000000U; | ||
602 | } | ||
603 | static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) | ||
604 | { | ||
605 | return 0x2000000U; | ||
606 | } | ||
607 | static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) | ||
608 | { | ||
609 | return 0x3000000U; | ||
610 | } | ||
611 | static inline u32 pbdma_target_should_send_tsg_event_true_f(void) | ||
612 | { | ||
613 | return 0x20000000U; | ||
614 | } | ||
615 | static inline u32 pbdma_target_should_send_tsg_event_false_f(void) | ||
616 | { | ||
617 | return 0x0U; | ||
618 | } | ||
619 | static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) | ||
620 | { | ||
621 | return 0x80000000U; | ||
622 | } | ||
623 | static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) | ||
624 | { | ||
625 | return 0x0U; | ||
626 | } | ||
627 | static inline u32 pbdma_set_channel_info_r(u32 i) | ||
628 | { | ||
629 | return 0x000400fcU + i*8192U; | ||
630 | } | ||
631 | static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) | ||
632 | { | ||
633 | return 0x0U; | ||
634 | } | ||
635 | static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) | ||
636 | { | ||
637 | return 0x1U; | ||
638 | } | ||
639 | static inline u32 pbdma_set_channel_info_veid_f(u32 v) | ||
640 | { | ||
641 | return (v & 0x3fU) << 8U; | ||
642 | } | ||
643 | static inline u32 pbdma_timeout_r(u32 i) | ||
644 | { | ||
645 | return 0x0004012cU + i*8192U; | ||
646 | } | ||
647 | static inline u32 pbdma_timeout_period_m(void) | ||
648 | { | ||
649 | return 0xffffffffU << 0U; | ||
650 | } | ||
651 | static inline u32 pbdma_timeout_period_max_f(void) | ||
652 | { | ||
653 | return 0xffffffffU; | ||
654 | } | ||
655 | static inline u32 pbdma_timeout_period_init_f(void) | ||
656 | { | ||
657 | return 0x10000U; | ||
658 | } | ||
659 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h new file mode 100644 index 00000000..788a6ab6 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h | |||
@@ -0,0 +1,211 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_perf_gv11b_h_ | ||
57 | #define _hw_perf_gv11b_h_ | ||
58 | |||
59 | static inline u32 perf_pmasys_control_r(void) | ||
60 | { | ||
61 | return 0x0024a000U; | ||
62 | } | ||
63 | static inline u32 perf_pmasys_control_membuf_status_v(u32 r) | ||
64 | { | ||
65 | return (r >> 4U) & 0x1U; | ||
66 | } | ||
67 | static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) | ||
68 | { | ||
69 | return 0x00000001U; | ||
70 | } | ||
71 | static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) | ||
72 | { | ||
73 | return 0x10U; | ||
74 | } | ||
75 | static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x1U) << 5U; | ||
78 | } | ||
79 | static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) | ||
80 | { | ||
81 | return (r >> 5U) & 0x1U; | ||
82 | } | ||
83 | static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) | ||
84 | { | ||
85 | return 0x00000001U; | ||
86 | } | ||
87 | static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) | ||
88 | { | ||
89 | return 0x20U; | ||
90 | } | ||
91 | static inline u32 perf_pmasys_mem_block_r(void) | ||
92 | { | ||
93 | return 0x0024a070U; | ||
94 | } | ||
95 | static inline u32 perf_pmasys_mem_block_base_f(u32 v) | ||
96 | { | ||
97 | return (v & 0xfffffffU) << 0U; | ||
98 | } | ||
99 | static inline u32 perf_pmasys_mem_block_target_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x3U) << 28U; | ||
102 | } | ||
103 | static inline u32 perf_pmasys_mem_block_target_v(u32 r) | ||
104 | { | ||
105 | return (r >> 28U) & 0x3U; | ||
106 | } | ||
107 | static inline u32 perf_pmasys_mem_block_target_lfb_v(void) | ||
108 | { | ||
109 | return 0x00000000U; | ||
110 | } | ||
111 | static inline u32 perf_pmasys_mem_block_target_lfb_f(void) | ||
112 | { | ||
113 | return 0x0U; | ||
114 | } | ||
115 | static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) | ||
116 | { | ||
117 | return 0x00000002U; | ||
118 | } | ||
119 | static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) | ||
120 | { | ||
121 | return 0x20000000U; | ||
122 | } | ||
123 | static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) | ||
124 | { | ||
125 | return 0x00000003U; | ||
126 | } | ||
127 | static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) | ||
128 | { | ||
129 | return 0x30000000U; | ||
130 | } | ||
131 | static inline u32 perf_pmasys_mem_block_valid_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 31U; | ||
134 | } | ||
135 | static inline u32 perf_pmasys_mem_block_valid_v(u32 r) | ||
136 | { | ||
137 | return (r >> 31U) & 0x1U; | ||
138 | } | ||
139 | static inline u32 perf_pmasys_mem_block_valid_true_v(void) | ||
140 | { | ||
141 | return 0x00000001U; | ||
142 | } | ||
143 | static inline u32 perf_pmasys_mem_block_valid_true_f(void) | ||
144 | { | ||
145 | return 0x80000000U; | ||
146 | } | ||
147 | static inline u32 perf_pmasys_mem_block_valid_false_v(void) | ||
148 | { | ||
149 | return 0x00000000U; | ||
150 | } | ||
151 | static inline u32 perf_pmasys_mem_block_valid_false_f(void) | ||
152 | { | ||
153 | return 0x0U; | ||
154 | } | ||
155 | static inline u32 perf_pmasys_outbase_r(void) | ||
156 | { | ||
157 | return 0x0024a074U; | ||
158 | } | ||
159 | static inline u32 perf_pmasys_outbase_ptr_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x7ffffffU) << 5U; | ||
162 | } | ||
163 | static inline u32 perf_pmasys_outbaseupper_r(void) | ||
164 | { | ||
165 | return 0x0024a078U; | ||
166 | } | ||
167 | static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) | ||
168 | { | ||
169 | return (v & 0xffU) << 0U; | ||
170 | } | ||
171 | static inline u32 perf_pmasys_outsize_r(void) | ||
172 | { | ||
173 | return 0x0024a07cU; | ||
174 | } | ||
175 | static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x7ffffffU) << 5U; | ||
178 | } | ||
179 | static inline u32 perf_pmasys_mem_bytes_r(void) | ||
180 | { | ||
181 | return 0x0024a084U; | ||
182 | } | ||
183 | static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) | ||
184 | { | ||
185 | return (v & 0xfffffffU) << 4U; | ||
186 | } | ||
187 | static inline u32 perf_pmasys_mem_bump_r(void) | ||
188 | { | ||
189 | return 0x0024a088U; | ||
190 | } | ||
191 | static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) | ||
192 | { | ||
193 | return (v & 0xfffffffU) << 4U; | ||
194 | } | ||
195 | static inline u32 perf_pmasys_enginestatus_r(void) | ||
196 | { | ||
197 | return 0x0024a0a4U; | ||
198 | } | ||
199 | static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) | ||
200 | { | ||
201 | return (v & 0x1U) << 4U; | ||
202 | } | ||
203 | static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) | ||
204 | { | ||
205 | return 0x00000001U; | ||
206 | } | ||
207 | static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) | ||
208 | { | ||
209 | return 0x10U; | ||
210 | } | ||
211 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h new file mode 100644 index 00000000..456d6316 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h | |||
@@ -0,0 +1,63 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pram_gv11b_h_ | ||
57 | #define _hw_pram_gv11b_h_ | ||
58 | |||
59 | static inline u32 pram_data032_r(u32 i) | ||
60 | { | ||
61 | return 0x00700000U + i*4U; | ||
62 | } | ||
63 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h new file mode 100644 index 00000000..a653681d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | |||
@@ -0,0 +1,167 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pri_ringmaster_gv11b_h_ | ||
57 | #define _hw_pri_ringmaster_gv11b_h_ | ||
58 | |||
59 | static inline u32 pri_ringmaster_command_r(void) | ||
60 | { | ||
61 | return 0x0012004cU; | ||
62 | } | ||
63 | static inline u32 pri_ringmaster_command_cmd_m(void) | ||
64 | { | ||
65 | return 0x3fU << 0U; | ||
66 | } | ||
67 | static inline u32 pri_ringmaster_command_cmd_v(u32 r) | ||
68 | { | ||
69 | return (r >> 0U) & 0x3fU; | ||
70 | } | ||
71 | static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) | ||
72 | { | ||
73 | return 0x00000000U; | ||
74 | } | ||
75 | static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) | ||
76 | { | ||
77 | return 0x1U; | ||
78 | } | ||
79 | static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) | ||
80 | { | ||
81 | return 0x2U; | ||
82 | } | ||
83 | static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) | ||
84 | { | ||
85 | return 0x3U; | ||
86 | } | ||
87 | static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) | ||
88 | { | ||
89 | return 0x0U; | ||
90 | } | ||
91 | static inline u32 pri_ringmaster_command_data_r(void) | ||
92 | { | ||
93 | return 0x00120048U; | ||
94 | } | ||
95 | static inline u32 pri_ringmaster_start_results_r(void) | ||
96 | { | ||
97 | return 0x00120050U; | ||
98 | } | ||
99 | static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) | ||
100 | { | ||
101 | return (r >> 0U) & 0x1U; | ||
102 | } | ||
103 | static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) | ||
104 | { | ||
105 | return 0x00000001U; | ||
106 | } | ||
107 | static inline u32 pri_ringmaster_intr_status0_r(void) | ||
108 | { | ||
109 | return 0x00120058U; | ||
110 | } | ||
111 | static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) | ||
112 | { | ||
113 | return (r >> 0U) & 0x1U; | ||
114 | } | ||
115 | static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) | ||
116 | { | ||
117 | return (r >> 1U) & 0x1U; | ||
118 | } | ||
119 | static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) | ||
120 | { | ||
121 | return (r >> 2U) & 0x1U; | ||
122 | } | ||
123 | static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) | ||
124 | { | ||
125 | return (r >> 8U) & 0x1U; | ||
126 | } | ||
127 | static inline u32 pri_ringmaster_intr_status1_r(void) | ||
128 | { | ||
129 | return 0x0012005cU; | ||
130 | } | ||
131 | static inline u32 pri_ringmaster_global_ctl_r(void) | ||
132 | { | ||
133 | return 0x00120060U; | ||
134 | } | ||
135 | static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) | ||
136 | { | ||
137 | return 0x1U; | ||
138 | } | ||
139 | static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) | ||
140 | { | ||
141 | return 0x0U; | ||
142 | } | ||
143 | static inline u32 pri_ringmaster_enum_fbp_r(void) | ||
144 | { | ||
145 | return 0x00120074U; | ||
146 | } | ||
147 | static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) | ||
148 | { | ||
149 | return (r >> 0U) & 0x1fU; | ||
150 | } | ||
151 | static inline u32 pri_ringmaster_enum_gpc_r(void) | ||
152 | { | ||
153 | return 0x00120078U; | ||
154 | } | ||
155 | static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) | ||
156 | { | ||
157 | return (r >> 0U) & 0x1fU; | ||
158 | } | ||
159 | static inline u32 pri_ringmaster_enum_ltc_r(void) | ||
160 | { | ||
161 | return 0x0012006cU; | ||
162 | } | ||
163 | static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) | ||
164 | { | ||
165 | return (r >> 0U) & 0x1fU; | ||
166 | } | ||
167 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h new file mode 100644 index 00000000..47da22c0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | |||
@@ -0,0 +1,79 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pri_ringstation_gpc_gv11b_h_ | ||
57 | #define _hw_pri_ringstation_gpc_gv11b_h_ | ||
58 | |||
59 | static inline u32 pri_ringstation_gpc_master_config_r(u32 i) | ||
60 | { | ||
61 | return 0x00128300U + i*4U; | ||
62 | } | ||
63 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) | ||
64 | { | ||
65 | return 0x00128120U; | ||
66 | } | ||
67 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) | ||
68 | { | ||
69 | return 0x00128124U; | ||
70 | } | ||
71 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) | ||
72 | { | ||
73 | return 0x00128128U; | ||
74 | } | ||
75 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) | ||
76 | { | ||
77 | return 0x0012812cU; | ||
78 | } | ||
79 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h new file mode 100644 index 00000000..622b6d7b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | |||
@@ -0,0 +1,91 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pri_ringstation_sys_gv11b_h_ | ||
57 | #define _hw_pri_ringstation_sys_gv11b_h_ | ||
58 | |||
59 | static inline u32 pri_ringstation_sys_master_config_r(u32 i) | ||
60 | { | ||
61 | return 0x00122300U + i*4U; | ||
62 | } | ||
63 | static inline u32 pri_ringstation_sys_decode_config_r(void) | ||
64 | { | ||
65 | return 0x00122204U; | ||
66 | } | ||
67 | static inline u32 pri_ringstation_sys_decode_config_ring_m(void) | ||
68 | { | ||
69 | return 0x7U << 0U; | ||
70 | } | ||
71 | static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) | ||
72 | { | ||
73 | return 0x1U; | ||
74 | } | ||
75 | static inline u32 pri_ringstation_sys_priv_error_adr_r(void) | ||
76 | { | ||
77 | return 0x00122120U; | ||
78 | } | ||
79 | static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) | ||
80 | { | ||
81 | return 0x00122124U; | ||
82 | } | ||
83 | static inline u32 pri_ringstation_sys_priv_error_info_r(void) | ||
84 | { | ||
85 | return 0x00122128U; | ||
86 | } | ||
87 | static inline u32 pri_ringstation_sys_priv_error_code_r(void) | ||
88 | { | ||
89 | return 0x0012212cU; | ||
90 | } | ||
91 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h new file mode 100644 index 00000000..808fe316 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | |||
@@ -0,0 +1,187 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_proj_gv11b_h_ | ||
57 | #define _hw_proj_gv11b_h_ | ||
58 | |||
59 | static inline u32 proj_gpc_base_v(void) | ||
60 | { | ||
61 | return 0x00500000U; | ||
62 | } | ||
63 | static inline u32 proj_gpc_shared_base_v(void) | ||
64 | { | ||
65 | return 0x00418000U; | ||
66 | } | ||
67 | static inline u32 proj_gpc_stride_v(void) | ||
68 | { | ||
69 | return 0x00008000U; | ||
70 | } | ||
71 | static inline u32 proj_ltc_stride_v(void) | ||
72 | { | ||
73 | return 0x00002000U; | ||
74 | } | ||
75 | static inline u32 proj_lts_stride_v(void) | ||
76 | { | ||
77 | return 0x00000200U; | ||
78 | } | ||
79 | static inline u32 proj_fbpa_stride_v(void) | ||
80 | { | ||
81 | return 0x00004000U; | ||
82 | } | ||
83 | static inline u32 proj_ppc_in_gpc_base_v(void) | ||
84 | { | ||
85 | return 0x00003000U; | ||
86 | } | ||
87 | static inline u32 proj_ppc_in_gpc_shared_base_v(void) | ||
88 | { | ||
89 | return 0x00003e00U; | ||
90 | } | ||
91 | static inline u32 proj_ppc_in_gpc_stride_v(void) | ||
92 | { | ||
93 | return 0x00000200U; | ||
94 | } | ||
95 | static inline u32 proj_rop_base_v(void) | ||
96 | { | ||
97 | return 0x00410000U; | ||
98 | } | ||
99 | static inline u32 proj_rop_shared_base_v(void) | ||
100 | { | ||
101 | return 0x00408800U; | ||
102 | } | ||
103 | static inline u32 proj_rop_stride_v(void) | ||
104 | { | ||
105 | return 0x00000400U; | ||
106 | } | ||
107 | static inline u32 proj_tpc_in_gpc_base_v(void) | ||
108 | { | ||
109 | return 0x00004000U; | ||
110 | } | ||
111 | static inline u32 proj_tpc_in_gpc_stride_v(void) | ||
112 | { | ||
113 | return 0x00000800U; | ||
114 | } | ||
115 | static inline u32 proj_tpc_in_gpc_shared_base_v(void) | ||
116 | { | ||
117 | return 0x00001800U; | ||
118 | } | ||
119 | static inline u32 proj_smpc_base_v(void) | ||
120 | { | ||
121 | return 0x00000200U; | ||
122 | } | ||
123 | static inline u32 proj_smpc_shared_base_v(void) | ||
124 | { | ||
125 | return 0x00000300U; | ||
126 | } | ||
127 | static inline u32 proj_smpc_unique_base_v(void) | ||
128 | { | ||
129 | return 0x00000600U; | ||
130 | } | ||
131 | static inline u32 proj_smpc_stride_v(void) | ||
132 | { | ||
133 | return 0x00000100U; | ||
134 | } | ||
135 | static inline u32 proj_host_num_engines_v(void) | ||
136 | { | ||
137 | return 0x00000004U; | ||
138 | } | ||
139 | static inline u32 proj_host_num_pbdma_v(void) | ||
140 | { | ||
141 | return 0x00000003U; | ||
142 | } | ||
143 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) | ||
144 | { | ||
145 | return 0x00000004U; | ||
146 | } | ||
147 | static inline u32 proj_scal_litter_num_fbps_v(void) | ||
148 | { | ||
149 | return 0x00000001U; | ||
150 | } | ||
151 | static inline u32 proj_scal_litter_num_fbpas_v(void) | ||
152 | { | ||
153 | return 0x00000001U; | ||
154 | } | ||
155 | static inline u32 proj_scal_litter_num_gpcs_v(void) | ||
156 | { | ||
157 | return 0x00000001U; | ||
158 | } | ||
159 | static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) | ||
160 | { | ||
161 | return 0x00000002U; | ||
162 | } | ||
163 | static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) | ||
164 | { | ||
165 | return 0x00000002U; | ||
166 | } | ||
167 | static inline u32 proj_scal_litter_num_zcull_banks_v(void) | ||
168 | { | ||
169 | return 0x00000004U; | ||
170 | } | ||
171 | static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) | ||
172 | { | ||
173 | return 0x00000002U; | ||
174 | } | ||
175 | static inline u32 proj_scal_max_gpcs_v(void) | ||
176 | { | ||
177 | return 0x00000020U; | ||
178 | } | ||
179 | static inline u32 proj_scal_max_tpc_per_gpc_v(void) | ||
180 | { | ||
181 | return 0x00000008U; | ||
182 | } | ||
183 | static inline u32 proj_sm_stride_v(void) | ||
184 | { | ||
185 | return 0x00000080U; | ||
186 | } | ||
187 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h new file mode 100644 index 00000000..eba6d806 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | |||
@@ -0,0 +1,951 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_pwr_gv11b_h_ | ||
57 | #define _hw_pwr_gv11b_h_ | ||
58 | |||
59 | static inline u32 pwr_falcon_irqsset_r(void) | ||
60 | { | ||
61 | return 0x0010a000U; | ||
62 | } | ||
63 | static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) | ||
64 | { | ||
65 | return 0x40U; | ||
66 | } | ||
67 | static inline u32 pwr_falcon_irqsclr_r(void) | ||
68 | { | ||
69 | return 0x0010a004U; | ||
70 | } | ||
71 | static inline u32 pwr_falcon_irqstat_r(void) | ||
72 | { | ||
73 | return 0x0010a008U; | ||
74 | } | ||
75 | static inline u32 pwr_falcon_irqstat_halt_true_f(void) | ||
76 | { | ||
77 | return 0x10U; | ||
78 | } | ||
79 | static inline u32 pwr_falcon_irqstat_exterr_true_f(void) | ||
80 | { | ||
81 | return 0x20U; | ||
82 | } | ||
83 | static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) | ||
84 | { | ||
85 | return 0x40U; | ||
86 | } | ||
87 | static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) | ||
88 | { | ||
89 | return 0x800U; | ||
90 | } | ||
91 | static inline u32 pwr_falcon_irqmode_r(void) | ||
92 | { | ||
93 | return 0x0010a00cU; | ||
94 | } | ||
95 | static inline u32 pwr_falcon_irqmset_r(void) | ||
96 | { | ||
97 | return 0x0010a010U; | ||
98 | } | ||
99 | static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 0U; | ||
102 | } | ||
103 | static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) | ||
104 | { | ||
105 | return (v & 0x1U) << 1U; | ||
106 | } | ||
107 | static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x1U) << 2U; | ||
110 | } | ||
111 | static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) | ||
112 | { | ||
113 | return (v & 0x1U) << 3U; | ||
114 | } | ||
115 | static inline u32 pwr_falcon_irqmset_halt_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 4U; | ||
118 | } | ||
119 | static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) | ||
120 | { | ||
121 | return (v & 0x1U) << 5U; | ||
122 | } | ||
123 | static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) | ||
124 | { | ||
125 | return (v & 0x1U) << 6U; | ||
126 | } | ||
127 | static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) | ||
128 | { | ||
129 | return (v & 0x1U) << 7U; | ||
130 | } | ||
131 | static inline u32 pwr_falcon_irqmset_ext_f(u32 v) | ||
132 | { | ||
133 | return (v & 0xffU) << 8U; | ||
134 | } | ||
135 | static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) | ||
136 | { | ||
137 | return (v & 0x1U) << 8U; | ||
138 | } | ||
139 | static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 9U; | ||
142 | } | ||
143 | static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1U) << 11U; | ||
146 | } | ||
147 | static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) | ||
148 | { | ||
149 | return (v & 0x1U) << 12U; | ||
150 | } | ||
151 | static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x1U) << 13U; | ||
154 | } | ||
155 | static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) | ||
156 | { | ||
157 | return (v & 0x1U) << 14U; | ||
158 | } | ||
159 | static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x1U) << 15U; | ||
162 | } | ||
163 | static inline u32 pwr_falcon_irqmclr_r(void) | ||
164 | { | ||
165 | return 0x0010a014U; | ||
166 | } | ||
167 | static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) | ||
168 | { | ||
169 | return (v & 0x1U) << 0U; | ||
170 | } | ||
171 | static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) | ||
172 | { | ||
173 | return (v & 0x1U) << 1U; | ||
174 | } | ||
175 | static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x1U) << 2U; | ||
178 | } | ||
179 | static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) | ||
180 | { | ||
181 | return (v & 0x1U) << 3U; | ||
182 | } | ||
183 | static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1U) << 4U; | ||
186 | } | ||
187 | static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 5U; | ||
190 | } | ||
191 | static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1U) << 6U; | ||
194 | } | ||
195 | static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x1U) << 7U; | ||
198 | } | ||
199 | static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) | ||
200 | { | ||
201 | return (v & 0xffU) << 8U; | ||
202 | } | ||
203 | static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1U) << 8U; | ||
206 | } | ||
207 | static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) | ||
208 | { | ||
209 | return (v & 0x1U) << 9U; | ||
210 | } | ||
211 | static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x1U) << 11U; | ||
214 | } | ||
215 | static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) | ||
216 | { | ||
217 | return (v & 0x1U) << 12U; | ||
218 | } | ||
219 | static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1U) << 13U; | ||
222 | } | ||
223 | static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) | ||
224 | { | ||
225 | return (v & 0x1U) << 14U; | ||
226 | } | ||
227 | static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x1U) << 15U; | ||
230 | } | ||
231 | static inline u32 pwr_falcon_irqmask_r(void) | ||
232 | { | ||
233 | return 0x0010a018U; | ||
234 | } | ||
235 | static inline u32 pwr_falcon_irqdest_r(void) | ||
236 | { | ||
237 | return 0x0010a01cU; | ||
238 | } | ||
239 | static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x1U) << 0U; | ||
242 | } | ||
243 | static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) | ||
244 | { | ||
245 | return (v & 0x1U) << 1U; | ||
246 | } | ||
247 | static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) | ||
248 | { | ||
249 | return (v & 0x1U) << 2U; | ||
250 | } | ||
251 | static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) | ||
252 | { | ||
253 | return (v & 0x1U) << 3U; | ||
254 | } | ||
255 | static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) | ||
256 | { | ||
257 | return (v & 0x1U) << 4U; | ||
258 | } | ||
259 | static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) | ||
260 | { | ||
261 | return (v & 0x1U) << 5U; | ||
262 | } | ||
263 | static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) | ||
264 | { | ||
265 | return (v & 0x1U) << 6U; | ||
266 | } | ||
267 | static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) | ||
268 | { | ||
269 | return (v & 0x1U) << 7U; | ||
270 | } | ||
271 | static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) | ||
272 | { | ||
273 | return (v & 0xffU) << 8U; | ||
274 | } | ||
275 | static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) | ||
276 | { | ||
277 | return (v & 0x1U) << 8U; | ||
278 | } | ||
279 | static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) | ||
280 | { | ||
281 | return (v & 0x1U) << 9U; | ||
282 | } | ||
283 | static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) | ||
284 | { | ||
285 | return (v & 0x1U) << 11U; | ||
286 | } | ||
287 | static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) | ||
288 | { | ||
289 | return (v & 0x1U) << 12U; | ||
290 | } | ||
291 | static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) | ||
292 | { | ||
293 | return (v & 0x1U) << 13U; | ||
294 | } | ||
295 | static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x1U) << 14U; | ||
298 | } | ||
299 | static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) | ||
300 | { | ||
301 | return (v & 0x1U) << 15U; | ||
302 | } | ||
303 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) | ||
304 | { | ||
305 | return (v & 0x1U) << 16U; | ||
306 | } | ||
307 | static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1U) << 17U; | ||
310 | } | ||
311 | static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) | ||
312 | { | ||
313 | return (v & 0x1U) << 18U; | ||
314 | } | ||
315 | static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) | ||
316 | { | ||
317 | return (v & 0x1U) << 19U; | ||
318 | } | ||
319 | static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) | ||
320 | { | ||
321 | return (v & 0x1U) << 20U; | ||
322 | } | ||
323 | static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1U) << 21U; | ||
326 | } | ||
327 | static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) | ||
328 | { | ||
329 | return (v & 0x1U) << 22U; | ||
330 | } | ||
331 | static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) | ||
332 | { | ||
333 | return (v & 0x1U) << 23U; | ||
334 | } | ||
335 | static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) | ||
336 | { | ||
337 | return (v & 0xffU) << 24U; | ||
338 | } | ||
339 | static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) | ||
340 | { | ||
341 | return (v & 0x1U) << 24U; | ||
342 | } | ||
343 | static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) | ||
344 | { | ||
345 | return (v & 0x1U) << 25U; | ||
346 | } | ||
347 | static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) | ||
348 | { | ||
349 | return (v & 0x1U) << 27U; | ||
350 | } | ||
351 | static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) | ||
352 | { | ||
353 | return (v & 0x1U) << 28U; | ||
354 | } | ||
355 | static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) | ||
356 | { | ||
357 | return (v & 0x1U) << 29U; | ||
358 | } | ||
359 | static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) | ||
360 | { | ||
361 | return (v & 0x1U) << 30U; | ||
362 | } | ||
363 | static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) | ||
364 | { | ||
365 | return (v & 0x1U) << 31U; | ||
366 | } | ||
367 | static inline u32 pwr_falcon_curctx_r(void) | ||
368 | { | ||
369 | return 0x0010a050U; | ||
370 | } | ||
371 | static inline u32 pwr_falcon_nxtctx_r(void) | ||
372 | { | ||
373 | return 0x0010a054U; | ||
374 | } | ||
375 | static inline u32 pwr_falcon_mailbox0_r(void) | ||
376 | { | ||
377 | return 0x0010a040U; | ||
378 | } | ||
379 | static inline u32 pwr_falcon_mailbox1_r(void) | ||
380 | { | ||
381 | return 0x0010a044U; | ||
382 | } | ||
383 | static inline u32 pwr_falcon_itfen_r(void) | ||
384 | { | ||
385 | return 0x0010a048U; | ||
386 | } | ||
387 | static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) | ||
388 | { | ||
389 | return 0x1U; | ||
390 | } | ||
391 | static inline u32 pwr_falcon_idlestate_r(void) | ||
392 | { | ||
393 | return 0x0010a04cU; | ||
394 | } | ||
395 | static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) | ||
396 | { | ||
397 | return (r >> 0U) & 0x1U; | ||
398 | } | ||
399 | static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) | ||
400 | { | ||
401 | return (r >> 1U) & 0x7fffU; | ||
402 | } | ||
403 | static inline u32 pwr_falcon_os_r(void) | ||
404 | { | ||
405 | return 0x0010a080U; | ||
406 | } | ||
407 | static inline u32 pwr_falcon_engctl_r(void) | ||
408 | { | ||
409 | return 0x0010a0a4U; | ||
410 | } | ||
411 | static inline u32 pwr_falcon_cpuctl_r(void) | ||
412 | { | ||
413 | return 0x0010a100U; | ||
414 | } | ||
415 | static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) | ||
416 | { | ||
417 | return (v & 0x1U) << 1U; | ||
418 | } | ||
419 | static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) | ||
420 | { | ||
421 | return (v & 0x1U) << 4U; | ||
422 | } | ||
423 | static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) | ||
424 | { | ||
425 | return 0x1U << 4U; | ||
426 | } | ||
427 | static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) | ||
428 | { | ||
429 | return (r >> 4U) & 0x1U; | ||
430 | } | ||
431 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) | ||
432 | { | ||
433 | return (v & 0x1U) << 6U; | ||
434 | } | ||
435 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) | ||
436 | { | ||
437 | return 0x1U << 6U; | ||
438 | } | ||
439 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) | ||
440 | { | ||
441 | return (r >> 6U) & 0x1U; | ||
442 | } | ||
443 | static inline u32 pwr_falcon_cpuctl_alias_r(void) | ||
444 | { | ||
445 | return 0x0010a130U; | ||
446 | } | ||
447 | static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) | ||
448 | { | ||
449 | return (v & 0x1U) << 1U; | ||
450 | } | ||
451 | static inline u32 pwr_pmu_scpctl_stat_r(void) | ||
452 | { | ||
453 | return 0x0010ac08U; | ||
454 | } | ||
455 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) | ||
456 | { | ||
457 | return (v & 0x1U) << 20U; | ||
458 | } | ||
459 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) | ||
460 | { | ||
461 | return 0x1U << 20U; | ||
462 | } | ||
463 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) | ||
464 | { | ||
465 | return (r >> 20U) & 0x1U; | ||
466 | } | ||
467 | static inline u32 pwr_falcon_imemc_r(u32 i) | ||
468 | { | ||
469 | return 0x0010a180U + i*16U; | ||
470 | } | ||
471 | static inline u32 pwr_falcon_imemc_offs_f(u32 v) | ||
472 | { | ||
473 | return (v & 0x3fU) << 2U; | ||
474 | } | ||
475 | static inline u32 pwr_falcon_imemc_blk_f(u32 v) | ||
476 | { | ||
477 | return (v & 0xffU) << 8U; | ||
478 | } | ||
479 | static inline u32 pwr_falcon_imemc_aincw_f(u32 v) | ||
480 | { | ||
481 | return (v & 0x1U) << 24U; | ||
482 | } | ||
483 | static inline u32 pwr_falcon_imemd_r(u32 i) | ||
484 | { | ||
485 | return 0x0010a184U + i*16U; | ||
486 | } | ||
487 | static inline u32 pwr_falcon_imemt_r(u32 i) | ||
488 | { | ||
489 | return 0x0010a188U + i*16U; | ||
490 | } | ||
491 | static inline u32 pwr_falcon_sctl_r(void) | ||
492 | { | ||
493 | return 0x0010a240U; | ||
494 | } | ||
495 | static inline u32 pwr_falcon_mmu_phys_sec_r(void) | ||
496 | { | ||
497 | return 0x00100ce4U; | ||
498 | } | ||
499 | static inline u32 pwr_falcon_bootvec_r(void) | ||
500 | { | ||
501 | return 0x0010a104U; | ||
502 | } | ||
503 | static inline u32 pwr_falcon_bootvec_vec_f(u32 v) | ||
504 | { | ||
505 | return (v & 0xffffffffU) << 0U; | ||
506 | } | ||
507 | static inline u32 pwr_falcon_dmactl_r(void) | ||
508 | { | ||
509 | return 0x0010a10cU; | ||
510 | } | ||
511 | static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) | ||
512 | { | ||
513 | return 0x1U << 1U; | ||
514 | } | ||
515 | static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) | ||
516 | { | ||
517 | return 0x1U << 2U; | ||
518 | } | ||
519 | static inline u32 pwr_falcon_hwcfg_r(void) | ||
520 | { | ||
521 | return 0x0010a108U; | ||
522 | } | ||
523 | static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) | ||
524 | { | ||
525 | return (r >> 0U) & 0x1ffU; | ||
526 | } | ||
527 | static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) | ||
528 | { | ||
529 | return (r >> 9U) & 0x1ffU; | ||
530 | } | ||
531 | static inline u32 pwr_falcon_dmatrfbase_r(void) | ||
532 | { | ||
533 | return 0x0010a110U; | ||
534 | } | ||
535 | static inline u32 pwr_falcon_dmatrfbase1_r(void) | ||
536 | { | ||
537 | return 0x0010a128U; | ||
538 | } | ||
539 | static inline u32 pwr_falcon_dmatrfmoffs_r(void) | ||
540 | { | ||
541 | return 0x0010a114U; | ||
542 | } | ||
543 | static inline u32 pwr_falcon_dmatrfcmd_r(void) | ||
544 | { | ||
545 | return 0x0010a118U; | ||
546 | } | ||
547 | static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) | ||
548 | { | ||
549 | return (v & 0x1U) << 4U; | ||
550 | } | ||
551 | static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) | ||
552 | { | ||
553 | return (v & 0x1U) << 5U; | ||
554 | } | ||
555 | static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) | ||
556 | { | ||
557 | return (v & 0x7U) << 8U; | ||
558 | } | ||
559 | static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) | ||
560 | { | ||
561 | return (v & 0x7U) << 12U; | ||
562 | } | ||
563 | static inline u32 pwr_falcon_dmatrffboffs_r(void) | ||
564 | { | ||
565 | return 0x0010a11cU; | ||
566 | } | ||
567 | static inline u32 pwr_falcon_exterraddr_r(void) | ||
568 | { | ||
569 | return 0x0010a168U; | ||
570 | } | ||
571 | static inline u32 pwr_falcon_exterrstat_r(void) | ||
572 | { | ||
573 | return 0x0010a16cU; | ||
574 | } | ||
575 | static inline u32 pwr_falcon_exterrstat_valid_m(void) | ||
576 | { | ||
577 | return 0x1U << 31U; | ||
578 | } | ||
579 | static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) | ||
580 | { | ||
581 | return (r >> 31U) & 0x1U; | ||
582 | } | ||
583 | static inline u32 pwr_falcon_exterrstat_valid_true_v(void) | ||
584 | { | ||
585 | return 0x00000001U; | ||
586 | } | ||
587 | static inline u32 pwr_pmu_falcon_icd_cmd_r(void) | ||
588 | { | ||
589 | return 0x0010a200U; | ||
590 | } | ||
591 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) | ||
592 | { | ||
593 | return 4U; | ||
594 | } | ||
595 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) | ||
596 | { | ||
597 | return (v & 0xfU) << 0U; | ||
598 | } | ||
599 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) | ||
600 | { | ||
601 | return 0xfU << 0U; | ||
602 | } | ||
603 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) | ||
604 | { | ||
605 | return (r >> 0U) & 0xfU; | ||
606 | } | ||
607 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) | ||
608 | { | ||
609 | return 0x8U; | ||
610 | } | ||
611 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) | ||
612 | { | ||
613 | return 0xeU; | ||
614 | } | ||
615 | static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) | ||
616 | { | ||
617 | return (v & 0x1fU) << 8U; | ||
618 | } | ||
619 | static inline u32 pwr_pmu_falcon_icd_rdata_r(void) | ||
620 | { | ||
621 | return 0x0010a20cU; | ||
622 | } | ||
623 | static inline u32 pwr_falcon_dmemc_r(u32 i) | ||
624 | { | ||
625 | return 0x0010a1c0U + i*8U; | ||
626 | } | ||
627 | static inline u32 pwr_falcon_dmemc_offs_f(u32 v) | ||
628 | { | ||
629 | return (v & 0x3fU) << 2U; | ||
630 | } | ||
631 | static inline u32 pwr_falcon_dmemc_offs_m(void) | ||
632 | { | ||
633 | return 0x3fU << 2U; | ||
634 | } | ||
635 | static inline u32 pwr_falcon_dmemc_blk_f(u32 v) | ||
636 | { | ||
637 | return (v & 0xffU) << 8U; | ||
638 | } | ||
639 | static inline u32 pwr_falcon_dmemc_blk_m(void) | ||
640 | { | ||
641 | return 0xffU << 8U; | ||
642 | } | ||
643 | static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) | ||
644 | { | ||
645 | return (v & 0x1U) << 24U; | ||
646 | } | ||
647 | static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) | ||
648 | { | ||
649 | return (v & 0x1U) << 25U; | ||
650 | } | ||
651 | static inline u32 pwr_falcon_dmemd_r(u32 i) | ||
652 | { | ||
653 | return 0x0010a1c4U + i*8U; | ||
654 | } | ||
655 | static inline u32 pwr_pmu_new_instblk_r(void) | ||
656 | { | ||
657 | return 0x0010a480U; | ||
658 | } | ||
659 | static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) | ||
660 | { | ||
661 | return (v & 0xfffffffU) << 0U; | ||
662 | } | ||
663 | static inline u32 pwr_pmu_new_instblk_target_fb_f(void) | ||
664 | { | ||
665 | return 0x0U; | ||
666 | } | ||
667 | static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) | ||
668 | { | ||
669 | return 0x20000000U; | ||
670 | } | ||
671 | static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) | ||
672 | { | ||
673 | return 0x30000000U; | ||
674 | } | ||
675 | static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) | ||
676 | { | ||
677 | return (v & 0x1U) << 30U; | ||
678 | } | ||
679 | static inline u32 pwr_pmu_mutex_id_r(void) | ||
680 | { | ||
681 | return 0x0010a488U; | ||
682 | } | ||
683 | static inline u32 pwr_pmu_mutex_id_value_v(u32 r) | ||
684 | { | ||
685 | return (r >> 0U) & 0xffU; | ||
686 | } | ||
687 | static inline u32 pwr_pmu_mutex_id_value_init_v(void) | ||
688 | { | ||
689 | return 0x00000000U; | ||
690 | } | ||
691 | static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) | ||
692 | { | ||
693 | return 0x000000ffU; | ||
694 | } | ||
695 | static inline u32 pwr_pmu_mutex_id_release_r(void) | ||
696 | { | ||
697 | return 0x0010a48cU; | ||
698 | } | ||
699 | static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) | ||
700 | { | ||
701 | return (v & 0xffU) << 0U; | ||
702 | } | ||
703 | static inline u32 pwr_pmu_mutex_id_release_value_m(void) | ||
704 | { | ||
705 | return 0xffU << 0U; | ||
706 | } | ||
707 | static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) | ||
708 | { | ||
709 | return 0x00000000U; | ||
710 | } | ||
711 | static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) | ||
712 | { | ||
713 | return 0x0U; | ||
714 | } | ||
715 | static inline u32 pwr_pmu_mutex_r(u32 i) | ||
716 | { | ||
717 | return 0x0010a580U + i*4U; | ||
718 | } | ||
719 | static inline u32 pwr_pmu_mutex__size_1_v(void) | ||
720 | { | ||
721 | return 0x00000010U; | ||
722 | } | ||
723 | static inline u32 pwr_pmu_mutex_value_f(u32 v) | ||
724 | { | ||
725 | return (v & 0xffU) << 0U; | ||
726 | } | ||
727 | static inline u32 pwr_pmu_mutex_value_v(u32 r) | ||
728 | { | ||
729 | return (r >> 0U) & 0xffU; | ||
730 | } | ||
731 | static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) | ||
732 | { | ||
733 | return 0x0U; | ||
734 | } | ||
735 | static inline u32 pwr_pmu_queue_head_r(u32 i) | ||
736 | { | ||
737 | return 0x0010a800U + i*4U; | ||
738 | } | ||
739 | static inline u32 pwr_pmu_queue_head__size_1_v(void) | ||
740 | { | ||
741 | return 0x00000008U; | ||
742 | } | ||
743 | static inline u32 pwr_pmu_queue_head_address_f(u32 v) | ||
744 | { | ||
745 | return (v & 0xffffffffU) << 0U; | ||
746 | } | ||
747 | static inline u32 pwr_pmu_queue_head_address_v(u32 r) | ||
748 | { | ||
749 | return (r >> 0U) & 0xffffffffU; | ||
750 | } | ||
751 | static inline u32 pwr_pmu_queue_tail_r(u32 i) | ||
752 | { | ||
753 | return 0x0010a820U + i*4U; | ||
754 | } | ||
755 | static inline u32 pwr_pmu_queue_tail__size_1_v(void) | ||
756 | { | ||
757 | return 0x00000008U; | ||
758 | } | ||
759 | static inline u32 pwr_pmu_queue_tail_address_f(u32 v) | ||
760 | { | ||
761 | return (v & 0xffffffffU) << 0U; | ||
762 | } | ||
763 | static inline u32 pwr_pmu_queue_tail_address_v(u32 r) | ||
764 | { | ||
765 | return (r >> 0U) & 0xffffffffU; | ||
766 | } | ||
767 | static inline u32 pwr_pmu_msgq_head_r(void) | ||
768 | { | ||
769 | return 0x0010a4c8U; | ||
770 | } | ||
771 | static inline u32 pwr_pmu_msgq_head_val_f(u32 v) | ||
772 | { | ||
773 | return (v & 0xffffffffU) << 0U; | ||
774 | } | ||
775 | static inline u32 pwr_pmu_msgq_head_val_v(u32 r) | ||
776 | { | ||
777 | return (r >> 0U) & 0xffffffffU; | ||
778 | } | ||
779 | static inline u32 pwr_pmu_msgq_tail_r(void) | ||
780 | { | ||
781 | return 0x0010a4ccU; | ||
782 | } | ||
783 | static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) | ||
784 | { | ||
785 | return (v & 0xffffffffU) << 0U; | ||
786 | } | ||
787 | static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) | ||
788 | { | ||
789 | return (r >> 0U) & 0xffffffffU; | ||
790 | } | ||
791 | static inline u32 pwr_pmu_idle_mask_r(u32 i) | ||
792 | { | ||
793 | return 0x0010a504U + i*16U; | ||
794 | } | ||
795 | static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) | ||
796 | { | ||
797 | return 0x1U; | ||
798 | } | ||
799 | static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) | ||
800 | { | ||
801 | return 0x200000U; | ||
802 | } | ||
803 | static inline u32 pwr_pmu_idle_count_r(u32 i) | ||
804 | { | ||
805 | return 0x0010a508U + i*16U; | ||
806 | } | ||
807 | static inline u32 pwr_pmu_idle_count_value_f(u32 v) | ||
808 | { | ||
809 | return (v & 0x7fffffffU) << 0U; | ||
810 | } | ||
811 | static inline u32 pwr_pmu_idle_count_value_v(u32 r) | ||
812 | { | ||
813 | return (r >> 0U) & 0x7fffffffU; | ||
814 | } | ||
815 | static inline u32 pwr_pmu_idle_count_reset_f(u32 v) | ||
816 | { | ||
817 | return (v & 0x1U) << 31U; | ||
818 | } | ||
819 | static inline u32 pwr_pmu_idle_ctrl_r(u32 i) | ||
820 | { | ||
821 | return 0x0010a50cU + i*16U; | ||
822 | } | ||
823 | static inline u32 pwr_pmu_idle_ctrl_value_m(void) | ||
824 | { | ||
825 | return 0x3U << 0U; | ||
826 | } | ||
827 | static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) | ||
828 | { | ||
829 | return 0x2U; | ||
830 | } | ||
831 | static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) | ||
832 | { | ||
833 | return 0x3U; | ||
834 | } | ||
835 | static inline u32 pwr_pmu_idle_ctrl_filter_m(void) | ||
836 | { | ||
837 | return 0x1U << 2U; | ||
838 | } | ||
839 | static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) | ||
840 | { | ||
841 | return 0x0U; | ||
842 | } | ||
843 | static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) | ||
844 | { | ||
845 | return 0x0010a9f0U + i*8U; | ||
846 | } | ||
847 | static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) | ||
848 | { | ||
849 | return 0x0010a9f4U + i*8U; | ||
850 | } | ||
851 | static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) | ||
852 | { | ||
853 | return 0x0010aa30U + i*8U; | ||
854 | } | ||
855 | static inline u32 pwr_pmu_debug_r(u32 i) | ||
856 | { | ||
857 | return 0x0010a5c0U + i*4U; | ||
858 | } | ||
859 | static inline u32 pwr_pmu_debug__size_1_v(void) | ||
860 | { | ||
861 | return 0x00000004U; | ||
862 | } | ||
863 | static inline u32 pwr_pmu_mailbox_r(u32 i) | ||
864 | { | ||
865 | return 0x0010a450U + i*4U; | ||
866 | } | ||
867 | static inline u32 pwr_pmu_mailbox__size_1_v(void) | ||
868 | { | ||
869 | return 0x0000000cU; | ||
870 | } | ||
871 | static inline u32 pwr_pmu_bar0_addr_r(void) | ||
872 | { | ||
873 | return 0x0010a7a0U; | ||
874 | } | ||
875 | static inline u32 pwr_pmu_bar0_data_r(void) | ||
876 | { | ||
877 | return 0x0010a7a4U; | ||
878 | } | ||
879 | static inline u32 pwr_pmu_bar0_ctl_r(void) | ||
880 | { | ||
881 | return 0x0010a7acU; | ||
882 | } | ||
883 | static inline u32 pwr_pmu_bar0_timeout_r(void) | ||
884 | { | ||
885 | return 0x0010a7a8U; | ||
886 | } | ||
887 | static inline u32 pwr_pmu_bar0_fecs_error_r(void) | ||
888 | { | ||
889 | return 0x0010a988U; | ||
890 | } | ||
891 | static inline u32 pwr_pmu_bar0_error_status_r(void) | ||
892 | { | ||
893 | return 0x0010a7b0U; | ||
894 | } | ||
895 | static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) | ||
896 | { | ||
897 | return 0x0010a6c0U + i*4U; | ||
898 | } | ||
899 | static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) | ||
900 | { | ||
901 | return 0x0010a6e8U + i*4U; | ||
902 | } | ||
903 | static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) | ||
904 | { | ||
905 | return 0x0010a710U + i*4U; | ||
906 | } | ||
907 | static inline u32 pwr_pmu_pg_intren_r(u32 i) | ||
908 | { | ||
909 | return 0x0010a760U + i*4U; | ||
910 | } | ||
911 | static inline u32 pwr_fbif_transcfg_r(u32 i) | ||
912 | { | ||
913 | return 0x0010ae00U + i*4U; | ||
914 | } | ||
915 | static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) | ||
916 | { | ||
917 | return 0x0U; | ||
918 | } | ||
919 | static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) | ||
920 | { | ||
921 | return 0x1U; | ||
922 | } | ||
923 | static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) | ||
924 | { | ||
925 | return 0x2U; | ||
926 | } | ||
927 | static inline u32 pwr_fbif_transcfg_mem_type_s(void) | ||
928 | { | ||
929 | return 1U; | ||
930 | } | ||
931 | static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) | ||
932 | { | ||
933 | return (v & 0x1U) << 2U; | ||
934 | } | ||
935 | static inline u32 pwr_fbif_transcfg_mem_type_m(void) | ||
936 | { | ||
937 | return 0x1U << 2U; | ||
938 | } | ||
939 | static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) | ||
940 | { | ||
941 | return (r >> 2U) & 0x1U; | ||
942 | } | ||
943 | static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) | ||
944 | { | ||
945 | return 0x0U; | ||
946 | } | ||
947 | static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) | ||
948 | { | ||
949 | return 0x4U; | ||
950 | } | ||
951 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h new file mode 100644 index 00000000..1191e580 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | |||
@@ -0,0 +1,775 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_ram_gv11b_h_ | ||
57 | #define _hw_ram_gv11b_h_ | ||
58 | |||
59 | static inline u32 ram_in_ramfc_s(void) | ||
60 | { | ||
61 | return 4096U; | ||
62 | } | ||
63 | static inline u32 ram_in_ramfc_w(void) | ||
64 | { | ||
65 | return 0U; | ||
66 | } | ||
67 | static inline u32 ram_in_page_dir_base_target_f(u32 v) | ||
68 | { | ||
69 | return (v & 0x3U) << 0U; | ||
70 | } | ||
71 | static inline u32 ram_in_page_dir_base_target_w(void) | ||
72 | { | ||
73 | return 128U; | ||
74 | } | ||
75 | static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) | ||
76 | { | ||
77 | return 0x0U; | ||
78 | } | ||
79 | static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) | ||
80 | { | ||
81 | return 0x2U; | ||
82 | } | ||
83 | static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) | ||
84 | { | ||
85 | return 0x3U; | ||
86 | } | ||
87 | static inline u32 ram_in_page_dir_base_vol_w(void) | ||
88 | { | ||
89 | return 128U; | ||
90 | } | ||
91 | static inline u32 ram_in_page_dir_base_vol_true_f(void) | ||
92 | { | ||
93 | return 0x4U; | ||
94 | } | ||
95 | static inline u32 ram_in_page_dir_base_vol_false_f(void) | ||
96 | { | ||
97 | return 0x0U; | ||
98 | } | ||
99 | static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 4U; | ||
102 | } | ||
103 | static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) | ||
104 | { | ||
105 | return 0x1U << 4U; | ||
106 | } | ||
107 | static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) | ||
108 | { | ||
109 | return 128U; | ||
110 | } | ||
111 | static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) | ||
112 | { | ||
113 | return 0x10U; | ||
114 | } | ||
115 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 5U; | ||
118 | } | ||
119 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) | ||
120 | { | ||
121 | return 0x1U << 5U; | ||
122 | } | ||
123 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) | ||
124 | { | ||
125 | return 128U; | ||
126 | } | ||
127 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) | ||
128 | { | ||
129 | return 0x20U; | ||
130 | } | ||
131 | static inline u32 ram_in_big_page_size_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 11U; | ||
134 | } | ||
135 | static inline u32 ram_in_big_page_size_m(void) | ||
136 | { | ||
137 | return 0x1U << 11U; | ||
138 | } | ||
139 | static inline u32 ram_in_big_page_size_w(void) | ||
140 | { | ||
141 | return 128U; | ||
142 | } | ||
143 | static inline u32 ram_in_big_page_size_128kb_f(void) | ||
144 | { | ||
145 | return 0x0U; | ||
146 | } | ||
147 | static inline u32 ram_in_big_page_size_64kb_f(void) | ||
148 | { | ||
149 | return 0x800U; | ||
150 | } | ||
151 | static inline u32 ram_in_page_dir_base_lo_f(u32 v) | ||
152 | { | ||
153 | return (v & 0xfffffU) << 12U; | ||
154 | } | ||
155 | static inline u32 ram_in_page_dir_base_lo_w(void) | ||
156 | { | ||
157 | return 128U; | ||
158 | } | ||
159 | static inline u32 ram_in_page_dir_base_hi_f(u32 v) | ||
160 | { | ||
161 | return (v & 0xffffffffU) << 0U; | ||
162 | } | ||
163 | static inline u32 ram_in_page_dir_base_hi_w(void) | ||
164 | { | ||
165 | return 129U; | ||
166 | } | ||
167 | static inline u32 ram_in_engine_cs_w(void) | ||
168 | { | ||
169 | return 132U; | ||
170 | } | ||
171 | static inline u32 ram_in_engine_cs_wfi_v(void) | ||
172 | { | ||
173 | return 0x00000000U; | ||
174 | } | ||
175 | static inline u32 ram_in_engine_cs_wfi_f(void) | ||
176 | { | ||
177 | return 0x0U; | ||
178 | } | ||
179 | static inline u32 ram_in_engine_cs_fg_v(void) | ||
180 | { | ||
181 | return 0x00000001U; | ||
182 | } | ||
183 | static inline u32 ram_in_engine_cs_fg_f(void) | ||
184 | { | ||
185 | return 0x8U; | ||
186 | } | ||
187 | static inline u32 ram_in_engine_wfi_mode_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 2U; | ||
190 | } | ||
191 | static inline u32 ram_in_engine_wfi_mode_w(void) | ||
192 | { | ||
193 | return 132U; | ||
194 | } | ||
195 | static inline u32 ram_in_engine_wfi_mode_physical_v(void) | ||
196 | { | ||
197 | return 0x00000000U; | ||
198 | } | ||
199 | static inline u32 ram_in_engine_wfi_mode_virtual_v(void) | ||
200 | { | ||
201 | return 0x00000001U; | ||
202 | } | ||
203 | static inline u32 ram_in_engine_wfi_target_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x3U) << 0U; | ||
206 | } | ||
207 | static inline u32 ram_in_engine_wfi_target_w(void) | ||
208 | { | ||
209 | return 132U; | ||
210 | } | ||
211 | static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) | ||
212 | { | ||
213 | return 0x00000002U; | ||
214 | } | ||
215 | static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) | ||
216 | { | ||
217 | return 0x00000003U; | ||
218 | } | ||
219 | static inline u32 ram_in_engine_wfi_target_local_mem_v(void) | ||
220 | { | ||
221 | return 0x00000000U; | ||
222 | } | ||
223 | static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) | ||
224 | { | ||
225 | return (v & 0xfffffU) << 12U; | ||
226 | } | ||
227 | static inline u32 ram_in_engine_wfi_ptr_lo_w(void) | ||
228 | { | ||
229 | return 132U; | ||
230 | } | ||
231 | static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) | ||
232 | { | ||
233 | return (v & 0xffU) << 0U; | ||
234 | } | ||
235 | static inline u32 ram_in_engine_wfi_ptr_hi_w(void) | ||
236 | { | ||
237 | return 133U; | ||
238 | } | ||
239 | static inline u32 ram_in_engine_wfi_veid_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x3fU) << 0U; | ||
242 | } | ||
243 | static inline u32 ram_in_engine_wfi_veid_w(void) | ||
244 | { | ||
245 | return 134U; | ||
246 | } | ||
247 | static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) | ||
248 | { | ||
249 | return (v & 0xffffffffU) << 0U; | ||
250 | } | ||
251 | static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) | ||
252 | { | ||
253 | return 136U; | ||
254 | } | ||
255 | static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) | ||
256 | { | ||
257 | return (v & 0x1ffffU) << 0U; | ||
258 | } | ||
259 | static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) | ||
260 | { | ||
261 | return 137U; | ||
262 | } | ||
263 | static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) | ||
264 | { | ||
265 | return (v & 0x3U) << (0U + i*0U); | ||
266 | } | ||
267 | static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) | ||
268 | { | ||
269 | return 0x00000040U; | ||
270 | } | ||
271 | static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) | ||
272 | { | ||
273 | return 0x00000000U; | ||
274 | } | ||
275 | static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) | ||
276 | { | ||
277 | return 0x00000001U; | ||
278 | } | ||
279 | static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) | ||
280 | { | ||
281 | return 0x00000002U; | ||
282 | } | ||
283 | static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) | ||
284 | { | ||
285 | return 0x00000003U; | ||
286 | } | ||
287 | static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) | ||
288 | { | ||
289 | return (v & 0x1U) << (2U + i*0U); | ||
290 | } | ||
291 | static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) | ||
292 | { | ||
293 | return 0x00000040U; | ||
294 | } | ||
295 | static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) | ||
296 | { | ||
297 | return 0x00000001U; | ||
298 | } | ||
299 | static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) | ||
300 | { | ||
301 | return 0x00000000U; | ||
302 | } | ||
303 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) | ||
304 | { | ||
305 | return (v & 0x1U) << (4U + i*0U); | ||
306 | } | ||
307 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) | ||
308 | { | ||
309 | return 0x00000040U; | ||
310 | } | ||
311 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) | ||
312 | { | ||
313 | return 0x00000001U; | ||
314 | } | ||
315 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) | ||
316 | { | ||
317 | return 0x00000000U; | ||
318 | } | ||
319 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) | ||
320 | { | ||
321 | return (v & 0x1U) << (5U + i*0U); | ||
322 | } | ||
323 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) | ||
324 | { | ||
325 | return 0x00000040U; | ||
326 | } | ||
327 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) | ||
328 | { | ||
329 | return 0x00000001U; | ||
330 | } | ||
331 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) | ||
332 | { | ||
333 | return 0x00000000U; | ||
334 | } | ||
335 | static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) | ||
336 | { | ||
337 | return (v & 0x1U) << (10U + i*0U); | ||
338 | } | ||
339 | static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) | ||
340 | { | ||
341 | return 0x00000040U; | ||
342 | } | ||
343 | static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) | ||
344 | { | ||
345 | return 0x00000000U; | ||
346 | } | ||
347 | static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) | ||
348 | { | ||
349 | return 0x00000001U; | ||
350 | } | ||
351 | static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) | ||
352 | { | ||
353 | return (v & 0x1U) << (11U + i*0U); | ||
354 | } | ||
355 | static inline u32 ram_in_sc_big_page_size__size_1_v(void) | ||
356 | { | ||
357 | return 0x00000040U; | ||
358 | } | ||
359 | static inline u32 ram_in_sc_big_page_size_64kb_v(void) | ||
360 | { | ||
361 | return 0x00000001U; | ||
362 | } | ||
363 | static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) | ||
364 | { | ||
365 | return (v & 0xfffffU) << (12U + i*0U); | ||
366 | } | ||
367 | static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) | ||
368 | { | ||
369 | return 0x00000040U; | ||
370 | } | ||
371 | static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) | ||
372 | { | ||
373 | return (v & 0xffffffffU) << (0U + i*0U); | ||
374 | } | ||
375 | static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) | ||
376 | { | ||
377 | return 0x00000040U; | ||
378 | } | ||
379 | static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) | ||
380 | { | ||
381 | return (v & 0x3U) << 0U; | ||
382 | } | ||
383 | static inline u32 ram_in_sc_page_dir_base_target_0_w(void) | ||
384 | { | ||
385 | return 168U; | ||
386 | } | ||
387 | static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) | ||
388 | { | ||
389 | return (v & 0x1U) << 2U; | ||
390 | } | ||
391 | static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) | ||
392 | { | ||
393 | return 168U; | ||
394 | } | ||
395 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) | ||
396 | { | ||
397 | return (v & 0x1U) << 4U; | ||
398 | } | ||
399 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) | ||
400 | { | ||
401 | return 168U; | ||
402 | } | ||
403 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) | ||
404 | { | ||
405 | return (v & 0x1U) << 5U; | ||
406 | } | ||
407 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) | ||
408 | { | ||
409 | return 168U; | ||
410 | } | ||
411 | static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) | ||
412 | { | ||
413 | return (v & 0x1U) << 10U; | ||
414 | } | ||
415 | static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) | ||
416 | { | ||
417 | return 168U; | ||
418 | } | ||
419 | static inline u32 ram_in_sc_big_page_size_0_f(u32 v) | ||
420 | { | ||
421 | return (v & 0x1U) << 11U; | ||
422 | } | ||
423 | static inline u32 ram_in_sc_big_page_size_0_w(void) | ||
424 | { | ||
425 | return 168U; | ||
426 | } | ||
427 | static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) | ||
428 | { | ||
429 | return (v & 0xfffffU) << 12U; | ||
430 | } | ||
431 | static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) | ||
432 | { | ||
433 | return 168U; | ||
434 | } | ||
435 | static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) | ||
436 | { | ||
437 | return (v & 0xffffffffU) << 0U; | ||
438 | } | ||
439 | static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) | ||
440 | { | ||
441 | return 169U; | ||
442 | } | ||
443 | static inline u32 ram_in_base_shift_v(void) | ||
444 | { | ||
445 | return 0x0000000cU; | ||
446 | } | ||
447 | static inline u32 ram_in_alloc_size_v(void) | ||
448 | { | ||
449 | return 0x00001000U; | ||
450 | } | ||
451 | static inline u32 ram_fc_size_val_v(void) | ||
452 | { | ||
453 | return 0x00000200U; | ||
454 | } | ||
455 | static inline u32 ram_fc_gp_put_w(void) | ||
456 | { | ||
457 | return 0U; | ||
458 | } | ||
459 | static inline u32 ram_fc_userd_w(void) | ||
460 | { | ||
461 | return 2U; | ||
462 | } | ||
463 | static inline u32 ram_fc_userd_hi_w(void) | ||
464 | { | ||
465 | return 3U; | ||
466 | } | ||
467 | static inline u32 ram_fc_signature_w(void) | ||
468 | { | ||
469 | return 4U; | ||
470 | } | ||
471 | static inline u32 ram_fc_gp_get_w(void) | ||
472 | { | ||
473 | return 5U; | ||
474 | } | ||
475 | static inline u32 ram_fc_pb_get_w(void) | ||
476 | { | ||
477 | return 6U; | ||
478 | } | ||
479 | static inline u32 ram_fc_pb_get_hi_w(void) | ||
480 | { | ||
481 | return 7U; | ||
482 | } | ||
483 | static inline u32 ram_fc_pb_top_level_get_w(void) | ||
484 | { | ||
485 | return 8U; | ||
486 | } | ||
487 | static inline u32 ram_fc_pb_top_level_get_hi_w(void) | ||
488 | { | ||
489 | return 9U; | ||
490 | } | ||
491 | static inline u32 ram_fc_acquire_w(void) | ||
492 | { | ||
493 | return 12U; | ||
494 | } | ||
495 | static inline u32 ram_fc_sem_addr_hi_w(void) | ||
496 | { | ||
497 | return 14U; | ||
498 | } | ||
499 | static inline u32 ram_fc_sem_addr_lo_w(void) | ||
500 | { | ||
501 | return 15U; | ||
502 | } | ||
503 | static inline u32 ram_fc_sem_payload_lo_w(void) | ||
504 | { | ||
505 | return 16U; | ||
506 | } | ||
507 | static inline u32 ram_fc_sem_payload_hi_w(void) | ||
508 | { | ||
509 | return 39U; | ||
510 | } | ||
511 | static inline u32 ram_fc_sem_execute_w(void) | ||
512 | { | ||
513 | return 17U; | ||
514 | } | ||
515 | static inline u32 ram_fc_gp_base_w(void) | ||
516 | { | ||
517 | return 18U; | ||
518 | } | ||
519 | static inline u32 ram_fc_gp_base_hi_w(void) | ||
520 | { | ||
521 | return 19U; | ||
522 | } | ||
523 | static inline u32 ram_fc_gp_fetch_w(void) | ||
524 | { | ||
525 | return 20U; | ||
526 | } | ||
527 | static inline u32 ram_fc_pb_fetch_w(void) | ||
528 | { | ||
529 | return 21U; | ||
530 | } | ||
531 | static inline u32 ram_fc_pb_fetch_hi_w(void) | ||
532 | { | ||
533 | return 22U; | ||
534 | } | ||
535 | static inline u32 ram_fc_pb_put_w(void) | ||
536 | { | ||
537 | return 23U; | ||
538 | } | ||
539 | static inline u32 ram_fc_pb_put_hi_w(void) | ||
540 | { | ||
541 | return 24U; | ||
542 | } | ||
543 | static inline u32 ram_fc_pb_header_w(void) | ||
544 | { | ||
545 | return 33U; | ||
546 | } | ||
547 | static inline u32 ram_fc_pb_count_w(void) | ||
548 | { | ||
549 | return 34U; | ||
550 | } | ||
551 | static inline u32 ram_fc_subdevice_w(void) | ||
552 | { | ||
553 | return 37U; | ||
554 | } | ||
555 | static inline u32 ram_fc_target_w(void) | ||
556 | { | ||
557 | return 43U; | ||
558 | } | ||
559 | static inline u32 ram_fc_hce_ctrl_w(void) | ||
560 | { | ||
561 | return 57U; | ||
562 | } | ||
563 | static inline u32 ram_fc_chid_w(void) | ||
564 | { | ||
565 | return 58U; | ||
566 | } | ||
567 | static inline u32 ram_fc_chid_id_f(u32 v) | ||
568 | { | ||
569 | return (v & 0xfffU) << 0U; | ||
570 | } | ||
571 | static inline u32 ram_fc_chid_id_w(void) | ||
572 | { | ||
573 | return 0U; | ||
574 | } | ||
575 | static inline u32 ram_fc_config_w(void) | ||
576 | { | ||
577 | return 61U; | ||
578 | } | ||
579 | static inline u32 ram_fc_runlist_timeslice_w(void) | ||
580 | { | ||
581 | return 62U; | ||
582 | } | ||
583 | static inline u32 ram_fc_set_channel_info_w(void) | ||
584 | { | ||
585 | return 63U; | ||
586 | } | ||
587 | static inline u32 ram_userd_base_shift_v(void) | ||
588 | { | ||
589 | return 0x00000009U; | ||
590 | } | ||
591 | static inline u32 ram_userd_chan_size_v(void) | ||
592 | { | ||
593 | return 0x00000200U; | ||
594 | } | ||
595 | static inline u32 ram_userd_put_w(void) | ||
596 | { | ||
597 | return 16U; | ||
598 | } | ||
599 | static inline u32 ram_userd_get_w(void) | ||
600 | { | ||
601 | return 17U; | ||
602 | } | ||
603 | static inline u32 ram_userd_ref_w(void) | ||
604 | { | ||
605 | return 18U; | ||
606 | } | ||
607 | static inline u32 ram_userd_put_hi_w(void) | ||
608 | { | ||
609 | return 19U; | ||
610 | } | ||
611 | static inline u32 ram_userd_ref_threshold_w(void) | ||
612 | { | ||
613 | return 20U; | ||
614 | } | ||
615 | static inline u32 ram_userd_top_level_get_w(void) | ||
616 | { | ||
617 | return 22U; | ||
618 | } | ||
619 | static inline u32 ram_userd_top_level_get_hi_w(void) | ||
620 | { | ||
621 | return 23U; | ||
622 | } | ||
623 | static inline u32 ram_userd_get_hi_w(void) | ||
624 | { | ||
625 | return 24U; | ||
626 | } | ||
627 | static inline u32 ram_userd_gp_get_w(void) | ||
628 | { | ||
629 | return 34U; | ||
630 | } | ||
631 | static inline u32 ram_userd_gp_put_w(void) | ||
632 | { | ||
633 | return 35U; | ||
634 | } | ||
635 | static inline u32 ram_userd_gp_top_level_get_w(void) | ||
636 | { | ||
637 | return 22U; | ||
638 | } | ||
639 | static inline u32 ram_userd_gp_top_level_get_hi_w(void) | ||
640 | { | ||
641 | return 23U; | ||
642 | } | ||
643 | static inline u32 ram_rl_entry_size_v(void) | ||
644 | { | ||
645 | return 0x00000010U; | ||
646 | } | ||
647 | static inline u32 ram_rl_entry_type_f(u32 v) | ||
648 | { | ||
649 | return (v & 0x1U) << 0U; | ||
650 | } | ||
651 | static inline u32 ram_rl_entry_type_channel_v(void) | ||
652 | { | ||
653 | return 0x00000000U; | ||
654 | } | ||
655 | static inline u32 ram_rl_entry_type_tsg_v(void) | ||
656 | { | ||
657 | return 0x00000001U; | ||
658 | } | ||
659 | static inline u32 ram_rl_entry_id_f(u32 v) | ||
660 | { | ||
661 | return (v & 0xfffU) << 0U; | ||
662 | } | ||
663 | static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) | ||
664 | { | ||
665 | return (v & 0x1U) << 1U; | ||
666 | } | ||
667 | static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) | ||
668 | { | ||
669 | return (v & 0x3U) << 4U; | ||
670 | } | ||
671 | static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) | ||
672 | { | ||
673 | return 0x00000003U; | ||
674 | } | ||
675 | static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) | ||
676 | { | ||
677 | return 0x00000002U; | ||
678 | } | ||
679 | static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) | ||
680 | { | ||
681 | return 0x00000000U; | ||
682 | } | ||
683 | static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) | ||
684 | { | ||
685 | return (v & 0x3U) << 6U; | ||
686 | } | ||
687 | static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) | ||
688 | { | ||
689 | return 0x00000000U; | ||
690 | } | ||
691 | static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) | ||
692 | { | ||
693 | return 0x00000001U; | ||
694 | } | ||
695 | static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) | ||
696 | { | ||
697 | return 0x00000002U; | ||
698 | } | ||
699 | static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) | ||
700 | { | ||
701 | return 0x00000003U; | ||
702 | } | ||
703 | static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) | ||
704 | { | ||
705 | return (v & 0xffffffU) << 8U; | ||
706 | } | ||
707 | static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) | ||
708 | { | ||
709 | return (v & 0xffffffffU) << 0U; | ||
710 | } | ||
711 | static inline u32 ram_rl_entry_chid_f(u32 v) | ||
712 | { | ||
713 | return (v & 0xfffU) << 0U; | ||
714 | } | ||
715 | static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) | ||
716 | { | ||
717 | return (v & 0xfffffU) << 12U; | ||
718 | } | ||
719 | static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) | ||
720 | { | ||
721 | return (v & 0xffffffffU) << 0U; | ||
722 | } | ||
723 | static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) | ||
724 | { | ||
725 | return (v & 0xfU) << 16U; | ||
726 | } | ||
727 | static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) | ||
728 | { | ||
729 | return 0x00000003U; | ||
730 | } | ||
731 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) | ||
732 | { | ||
733 | return (v & 0xffU) << 24U; | ||
734 | } | ||
735 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) | ||
736 | { | ||
737 | return 0x00000080U; | ||
738 | } | ||
739 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) | ||
740 | { | ||
741 | return 0x00000000U; | ||
742 | } | ||
743 | static inline u32 ram_rl_entry_tsg_length_f(u32 v) | ||
744 | { | ||
745 | return (v & 0xffU) << 0U; | ||
746 | } | ||
747 | static inline u32 ram_rl_entry_tsg_length_init_v(void) | ||
748 | { | ||
749 | return 0x00000000U; | ||
750 | } | ||
751 | static inline u32 ram_rl_entry_tsg_length_min_v(void) | ||
752 | { | ||
753 | return 0x00000001U; | ||
754 | } | ||
755 | static inline u32 ram_rl_entry_tsg_length_max_v(void) | ||
756 | { | ||
757 | return 0x00000080U; | ||
758 | } | ||
759 | static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) | ||
760 | { | ||
761 | return (v & 0xfffU) << 0U; | ||
762 | } | ||
763 | static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) | ||
764 | { | ||
765 | return 0x00000008U; | ||
766 | } | ||
767 | static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) | ||
768 | { | ||
769 | return 0x00000008U; | ||
770 | } | ||
771 | static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) | ||
772 | { | ||
773 | return 0x0000000cU; | ||
774 | } | ||
775 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h new file mode 100644 index 00000000..8f8981e8 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | |||
@@ -0,0 +1,435 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_therm_gv11b_h_ | ||
57 | #define _hw_therm_gv11b_h_ | ||
58 | |||
59 | static inline u32 therm_use_a_r(void) | ||
60 | { | ||
61 | return 0x00020798U; | ||
62 | } | ||
63 | static inline u32 therm_use_a_ext_therm_0_enable_f(void) | ||
64 | { | ||
65 | return 0x1U; | ||
66 | } | ||
67 | static inline u32 therm_use_a_ext_therm_1_enable_f(void) | ||
68 | { | ||
69 | return 0x2U; | ||
70 | } | ||
71 | static inline u32 therm_use_a_ext_therm_2_enable_f(void) | ||
72 | { | ||
73 | return 0x4U; | ||
74 | } | ||
75 | static inline u32 therm_evt_ext_therm_0_r(void) | ||
76 | { | ||
77 | return 0x00020700U; | ||
78 | } | ||
79 | static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) | ||
80 | { | ||
81 | return (v & 0x3fU) << 24U; | ||
82 | } | ||
83 | static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) | ||
84 | { | ||
85 | return 0x00000001U; | ||
86 | } | ||
87 | static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) | ||
88 | { | ||
89 | return (v & 0x3U) << 30U; | ||
90 | } | ||
91 | static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) | ||
92 | { | ||
93 | return 0x00000000U; | ||
94 | } | ||
95 | static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) | ||
96 | { | ||
97 | return 0x00000001U; | ||
98 | } | ||
99 | static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) | ||
100 | { | ||
101 | return 0x00000002U; | ||
102 | } | ||
103 | static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) | ||
104 | { | ||
105 | return 0x00000003U; | ||
106 | } | ||
107 | static inline u32 therm_evt_ext_therm_1_r(void) | ||
108 | { | ||
109 | return 0x00020704U; | ||
110 | } | ||
111 | static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) | ||
112 | { | ||
113 | return (v & 0x3fU) << 24U; | ||
114 | } | ||
115 | static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) | ||
116 | { | ||
117 | return 0x00000002U; | ||
118 | } | ||
119 | static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) | ||
120 | { | ||
121 | return (v & 0x3U) << 30U; | ||
122 | } | ||
123 | static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) | ||
124 | { | ||
125 | return 0x00000000U; | ||
126 | } | ||
127 | static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) | ||
128 | { | ||
129 | return 0x00000001U; | ||
130 | } | ||
131 | static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) | ||
132 | { | ||
133 | return 0x00000002U; | ||
134 | } | ||
135 | static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) | ||
136 | { | ||
137 | return 0x00000003U; | ||
138 | } | ||
139 | static inline u32 therm_evt_ext_therm_2_r(void) | ||
140 | { | ||
141 | return 0x00020708U; | ||
142 | } | ||
143 | static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x3fU) << 24U; | ||
146 | } | ||
147 | static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) | ||
148 | { | ||
149 | return 0x00000003U; | ||
150 | } | ||
151 | static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x3U) << 30U; | ||
154 | } | ||
155 | static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) | ||
156 | { | ||
157 | return 0x00000000U; | ||
158 | } | ||
159 | static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) | ||
160 | { | ||
161 | return 0x00000001U; | ||
162 | } | ||
163 | static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) | ||
164 | { | ||
165 | return 0x00000002U; | ||
166 | } | ||
167 | static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) | ||
168 | { | ||
169 | return 0x00000003U; | ||
170 | } | ||
171 | static inline u32 therm_weight_1_r(void) | ||
172 | { | ||
173 | return 0x00020024U; | ||
174 | } | ||
175 | static inline u32 therm_config1_r(void) | ||
176 | { | ||
177 | return 0x00020050U; | ||
178 | } | ||
179 | static inline u32 therm_config2_r(void) | ||
180 | { | ||
181 | return 0x00020130U; | ||
182 | } | ||
183 | static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1U) << 24U; | ||
186 | } | ||
187 | static inline u32 therm_config2_grad_enable_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 31U; | ||
190 | } | ||
191 | static inline u32 therm_gate_ctrl_r(u32 i) | ||
192 | { | ||
193 | return 0x00020200U + i*4U; | ||
194 | } | ||
195 | static inline u32 therm_gate_ctrl_eng_clk_m(void) | ||
196 | { | ||
197 | return 0x3U << 0U; | ||
198 | } | ||
199 | static inline u32 therm_gate_ctrl_eng_clk_run_f(void) | ||
200 | { | ||
201 | return 0x0U; | ||
202 | } | ||
203 | static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) | ||
204 | { | ||
205 | return 0x1U; | ||
206 | } | ||
207 | static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) | ||
208 | { | ||
209 | return 0x2U; | ||
210 | } | ||
211 | static inline u32 therm_gate_ctrl_blk_clk_m(void) | ||
212 | { | ||
213 | return 0x3U << 2U; | ||
214 | } | ||
215 | static inline u32 therm_gate_ctrl_blk_clk_run_f(void) | ||
216 | { | ||
217 | return 0x0U; | ||
218 | } | ||
219 | static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) | ||
220 | { | ||
221 | return 0x4U; | ||
222 | } | ||
223 | static inline u32 therm_gate_ctrl_idle_holdoff_m(void) | ||
224 | { | ||
225 | return 0x1U << 4U; | ||
226 | } | ||
227 | static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) | ||
228 | { | ||
229 | return 0x0U; | ||
230 | } | ||
231 | static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) | ||
232 | { | ||
233 | return 0x10U; | ||
234 | } | ||
235 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1fU) << 8U; | ||
238 | } | ||
239 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) | ||
240 | { | ||
241 | return 0x1fU << 8U; | ||
242 | } | ||
243 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) | ||
244 | { | ||
245 | return 0x200U; | ||
246 | } | ||
247 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) | ||
248 | { | ||
249 | return (v & 0x7U) << 13U; | ||
250 | } | ||
251 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) | ||
252 | { | ||
253 | return 0x7U << 13U; | ||
254 | } | ||
255 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) | ||
256 | { | ||
257 | return 0x2000U; | ||
258 | } | ||
259 | static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) | ||
260 | { | ||
261 | return (v & 0xfU) << 16U; | ||
262 | } | ||
263 | static inline u32 therm_gate_ctrl_eng_delay_before_m(void) | ||
264 | { | ||
265 | return 0xfU << 16U; | ||
266 | } | ||
267 | static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) | ||
268 | { | ||
269 | return 0x40000U; | ||
270 | } | ||
271 | static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) | ||
272 | { | ||
273 | return (v & 0xfU) << 20U; | ||
274 | } | ||
275 | static inline u32 therm_gate_ctrl_eng_delay_after_m(void) | ||
276 | { | ||
277 | return 0xfU << 20U; | ||
278 | } | ||
279 | static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) | ||
280 | { | ||
281 | return 0x0U; | ||
282 | } | ||
283 | static inline u32 therm_fecs_idle_filter_r(void) | ||
284 | { | ||
285 | return 0x00020288U; | ||
286 | } | ||
287 | static inline u32 therm_fecs_idle_filter_value_m(void) | ||
288 | { | ||
289 | return 0xffffffffU << 0U; | ||
290 | } | ||
291 | static inline u32 therm_fecs_idle_filter_value__prod_f(void) | ||
292 | { | ||
293 | return 0x0U; | ||
294 | } | ||
295 | static inline u32 therm_hubmmu_idle_filter_r(void) | ||
296 | { | ||
297 | return 0x0002028cU; | ||
298 | } | ||
299 | static inline u32 therm_hubmmu_idle_filter_value_m(void) | ||
300 | { | ||
301 | return 0xffffffffU << 0U; | ||
302 | } | ||
303 | static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) | ||
304 | { | ||
305 | return 0x0U; | ||
306 | } | ||
307 | static inline u32 therm_clk_slowdown_r(u32 i) | ||
308 | { | ||
309 | return 0x00020160U + i*4U; | ||
310 | } | ||
311 | static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) | ||
312 | { | ||
313 | return (v & 0x3fU) << 16U; | ||
314 | } | ||
315 | static inline u32 therm_clk_slowdown_idle_factor_m(void) | ||
316 | { | ||
317 | return 0x3fU << 16U; | ||
318 | } | ||
319 | static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) | ||
320 | { | ||
321 | return (r >> 16U) & 0x3fU; | ||
322 | } | ||
323 | static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) | ||
324 | { | ||
325 | return 0x0U; | ||
326 | } | ||
327 | static inline u32 therm_grad_stepping_table_r(u32 i) | ||
328 | { | ||
329 | return 0x000202c8U + i*4U; | ||
330 | } | ||
331 | static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) | ||
332 | { | ||
333 | return (v & 0x3fU) << 0U; | ||
334 | } | ||
335 | static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) | ||
336 | { | ||
337 | return 0x3fU << 0U; | ||
338 | } | ||
339 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) | ||
340 | { | ||
341 | return 0x1U; | ||
342 | } | ||
343 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) | ||
344 | { | ||
345 | return 0x2U; | ||
346 | } | ||
347 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) | ||
348 | { | ||
349 | return 0x6U; | ||
350 | } | ||
351 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) | ||
352 | { | ||
353 | return 0xeU; | ||
354 | } | ||
355 | static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) | ||
356 | { | ||
357 | return (v & 0x3fU) << 6U; | ||
358 | } | ||
359 | static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) | ||
360 | { | ||
361 | return 0x3fU << 6U; | ||
362 | } | ||
363 | static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) | ||
364 | { | ||
365 | return (v & 0x3fU) << 12U; | ||
366 | } | ||
367 | static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) | ||
368 | { | ||
369 | return 0x3fU << 12U; | ||
370 | } | ||
371 | static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) | ||
372 | { | ||
373 | return (v & 0x3fU) << 18U; | ||
374 | } | ||
375 | static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) | ||
376 | { | ||
377 | return 0x3fU << 18U; | ||
378 | } | ||
379 | static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) | ||
380 | { | ||
381 | return (v & 0x3fU) << 24U; | ||
382 | } | ||
383 | static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) | ||
384 | { | ||
385 | return 0x3fU << 24U; | ||
386 | } | ||
387 | static inline u32 therm_grad_stepping0_r(void) | ||
388 | { | ||
389 | return 0x000202c0U; | ||
390 | } | ||
391 | static inline u32 therm_grad_stepping0_feature_s(void) | ||
392 | { | ||
393 | return 1U; | ||
394 | } | ||
395 | static inline u32 therm_grad_stepping0_feature_f(u32 v) | ||
396 | { | ||
397 | return (v & 0x1U) << 0U; | ||
398 | } | ||
399 | static inline u32 therm_grad_stepping0_feature_m(void) | ||
400 | { | ||
401 | return 0x1U << 0U; | ||
402 | } | ||
403 | static inline u32 therm_grad_stepping0_feature_v(u32 r) | ||
404 | { | ||
405 | return (r >> 0U) & 0x1U; | ||
406 | } | ||
407 | static inline u32 therm_grad_stepping0_feature_enable_f(void) | ||
408 | { | ||
409 | return 0x1U; | ||
410 | } | ||
411 | static inline u32 therm_grad_stepping1_r(void) | ||
412 | { | ||
413 | return 0x000202c4U; | ||
414 | } | ||
415 | static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) | ||
416 | { | ||
417 | return (v & 0x1ffffU) << 0U; | ||
418 | } | ||
419 | static inline u32 therm_clk_timing_r(u32 i) | ||
420 | { | ||
421 | return 0x000203c0U + i*4U; | ||
422 | } | ||
423 | static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) | ||
424 | { | ||
425 | return (v & 0x1U) << 16U; | ||
426 | } | ||
427 | static inline u32 therm_clk_timing_grad_slowdown_m(void) | ||
428 | { | ||
429 | return 0x1U << 16U; | ||
430 | } | ||
431 | static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) | ||
432 | { | ||
433 | return 0x10000U; | ||
434 | } | ||
435 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h new file mode 100644 index 00000000..61440213 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h | |||
@@ -0,0 +1,115 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_timer_gv11b_h_ | ||
57 | #define _hw_timer_gv11b_h_ | ||
58 | |||
59 | static inline u32 timer_pri_timeout_r(void) | ||
60 | { | ||
61 | return 0x00009080U; | ||
62 | } | ||
63 | static inline u32 timer_pri_timeout_period_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xffffffU) << 0U; | ||
66 | } | ||
67 | static inline u32 timer_pri_timeout_period_m(void) | ||
68 | { | ||
69 | return 0xffffffU << 0U; | ||
70 | } | ||
71 | static inline u32 timer_pri_timeout_period_v(u32 r) | ||
72 | { | ||
73 | return (r >> 0U) & 0xffffffU; | ||
74 | } | ||
75 | static inline u32 timer_pri_timeout_en_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x1U) << 31U; | ||
78 | } | ||
79 | static inline u32 timer_pri_timeout_en_m(void) | ||
80 | { | ||
81 | return 0x1U << 31U; | ||
82 | } | ||
83 | static inline u32 timer_pri_timeout_en_v(u32 r) | ||
84 | { | ||
85 | return (r >> 31U) & 0x1U; | ||
86 | } | ||
87 | static inline u32 timer_pri_timeout_en_en_enabled_f(void) | ||
88 | { | ||
89 | return 0x80000000U; | ||
90 | } | ||
91 | static inline u32 timer_pri_timeout_en_en_disabled_f(void) | ||
92 | { | ||
93 | return 0x0U; | ||
94 | } | ||
95 | static inline u32 timer_pri_timeout_save_0_r(void) | ||
96 | { | ||
97 | return 0x00009084U; | ||
98 | } | ||
99 | static inline u32 timer_pri_timeout_save_1_r(void) | ||
100 | { | ||
101 | return 0x00009088U; | ||
102 | } | ||
103 | static inline u32 timer_pri_timeout_fecs_errcode_r(void) | ||
104 | { | ||
105 | return 0x0000908cU; | ||
106 | } | ||
107 | static inline u32 timer_time_0_r(void) | ||
108 | { | ||
109 | return 0x00009400U; | ||
110 | } | ||
111 | static inline u32 timer_time_1_r(void) | ||
112 | { | ||
113 | return 0x00009410U; | ||
114 | } | ||
115 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h new file mode 100644 index 00000000..89e4aebb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | |||
@@ -0,0 +1,235 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_top_gv11b_h_ | ||
57 | #define _hw_top_gv11b_h_ | ||
58 | |||
59 | static inline u32 top_num_gpcs_r(void) | ||
60 | { | ||
61 | return 0x00022430U; | ||
62 | } | ||
63 | static inline u32 top_num_gpcs_value_v(u32 r) | ||
64 | { | ||
65 | return (r >> 0U) & 0x1fU; | ||
66 | } | ||
67 | static inline u32 top_tpc_per_gpc_r(void) | ||
68 | { | ||
69 | return 0x00022434U; | ||
70 | } | ||
71 | static inline u32 top_tpc_per_gpc_value_v(u32 r) | ||
72 | { | ||
73 | return (r >> 0U) & 0x1fU; | ||
74 | } | ||
75 | static inline u32 top_num_fbps_r(void) | ||
76 | { | ||
77 | return 0x00022438U; | ||
78 | } | ||
79 | static inline u32 top_num_fbps_value_v(u32 r) | ||
80 | { | ||
81 | return (r >> 0U) & 0x1fU; | ||
82 | } | ||
83 | static inline u32 top_ltc_per_fbp_r(void) | ||
84 | { | ||
85 | return 0x00022450U; | ||
86 | } | ||
87 | static inline u32 top_ltc_per_fbp_value_v(u32 r) | ||
88 | { | ||
89 | return (r >> 0U) & 0x1fU; | ||
90 | } | ||
91 | static inline u32 top_slices_per_ltc_r(void) | ||
92 | { | ||
93 | return 0x0002245cU; | ||
94 | } | ||
95 | static inline u32 top_slices_per_ltc_value_v(u32 r) | ||
96 | { | ||
97 | return (r >> 0U) & 0x1fU; | ||
98 | } | ||
99 | static inline u32 top_num_ltcs_r(void) | ||
100 | { | ||
101 | return 0x00022454U; | ||
102 | } | ||
103 | static inline u32 top_num_ces_r(void) | ||
104 | { | ||
105 | return 0x00022444U; | ||
106 | } | ||
107 | static inline u32 top_num_ces_value_v(u32 r) | ||
108 | { | ||
109 | return (r >> 0U) & 0x1fU; | ||
110 | } | ||
111 | static inline u32 top_device_info_r(u32 i) | ||
112 | { | ||
113 | return 0x00022700U + i*4U; | ||
114 | } | ||
115 | static inline u32 top_device_info__size_1_v(void) | ||
116 | { | ||
117 | return 0x00000040U; | ||
118 | } | ||
119 | static inline u32 top_device_info_chain_v(u32 r) | ||
120 | { | ||
121 | return (r >> 31U) & 0x1U; | ||
122 | } | ||
123 | static inline u32 top_device_info_chain_enable_v(void) | ||
124 | { | ||
125 | return 0x00000001U; | ||
126 | } | ||
127 | static inline u32 top_device_info_engine_enum_v(u32 r) | ||
128 | { | ||
129 | return (r >> 26U) & 0xfU; | ||
130 | } | ||
131 | static inline u32 top_device_info_runlist_enum_v(u32 r) | ||
132 | { | ||
133 | return (r >> 21U) & 0xfU; | ||
134 | } | ||
135 | static inline u32 top_device_info_intr_enum_v(u32 r) | ||
136 | { | ||
137 | return (r >> 15U) & 0x1fU; | ||
138 | } | ||
139 | static inline u32 top_device_info_reset_enum_v(u32 r) | ||
140 | { | ||
141 | return (r >> 9U) & 0x1fU; | ||
142 | } | ||
143 | static inline u32 top_device_info_type_enum_v(u32 r) | ||
144 | { | ||
145 | return (r >> 2U) & 0x1fffffffU; | ||
146 | } | ||
147 | static inline u32 top_device_info_type_enum_graphics_v(void) | ||
148 | { | ||
149 | return 0x00000000U; | ||
150 | } | ||
151 | static inline u32 top_device_info_type_enum_graphics_f(void) | ||
152 | { | ||
153 | return 0x0U; | ||
154 | } | ||
155 | static inline u32 top_device_info_type_enum_copy2_v(void) | ||
156 | { | ||
157 | return 0x00000003U; | ||
158 | } | ||
159 | static inline u32 top_device_info_type_enum_copy2_f(void) | ||
160 | { | ||
161 | return 0xcU; | ||
162 | } | ||
163 | static inline u32 top_device_info_type_enum_lce_v(void) | ||
164 | { | ||
165 | return 0x00000013U; | ||
166 | } | ||
167 | static inline u32 top_device_info_type_enum_lce_f(void) | ||
168 | { | ||
169 | return 0x4cU; | ||
170 | } | ||
171 | static inline u32 top_device_info_engine_v(u32 r) | ||
172 | { | ||
173 | return (r >> 5U) & 0x1U; | ||
174 | } | ||
175 | static inline u32 top_device_info_runlist_v(u32 r) | ||
176 | { | ||
177 | return (r >> 4U) & 0x1U; | ||
178 | } | ||
179 | static inline u32 top_device_info_intr_v(u32 r) | ||
180 | { | ||
181 | return (r >> 3U) & 0x1U; | ||
182 | } | ||
183 | static inline u32 top_device_info_reset_v(u32 r) | ||
184 | { | ||
185 | return (r >> 2U) & 0x1U; | ||
186 | } | ||
187 | static inline u32 top_device_info_entry_v(u32 r) | ||
188 | { | ||
189 | return (r >> 0U) & 0x3U; | ||
190 | } | ||
191 | static inline u32 top_device_info_entry_not_valid_v(void) | ||
192 | { | ||
193 | return 0x00000000U; | ||
194 | } | ||
195 | static inline u32 top_device_info_entry_enum_v(void) | ||
196 | { | ||
197 | return 0x00000002U; | ||
198 | } | ||
199 | static inline u32 top_device_info_entry_data_v(void) | ||
200 | { | ||
201 | return 0x00000001U; | ||
202 | } | ||
203 | static inline u32 top_device_info_data_type_v(u32 r) | ||
204 | { | ||
205 | return (r >> 30U) & 0x1U; | ||
206 | } | ||
207 | static inline u32 top_device_info_data_type_enum2_v(void) | ||
208 | { | ||
209 | return 0x00000000U; | ||
210 | } | ||
211 | static inline u32 top_device_info_data_inst_id_v(u32 r) | ||
212 | { | ||
213 | return (r >> 26U) & 0xfU; | ||
214 | } | ||
215 | static inline u32 top_device_info_data_pri_base_v(u32 r) | ||
216 | { | ||
217 | return (r >> 12U) & 0xfffU; | ||
218 | } | ||
219 | static inline u32 top_device_info_data_pri_base_align_v(void) | ||
220 | { | ||
221 | return 0x0000000cU; | ||
222 | } | ||
223 | static inline u32 top_device_info_data_fault_id_enum_v(u32 r) | ||
224 | { | ||
225 | return (r >> 3U) & 0x7fU; | ||
226 | } | ||
227 | static inline u32 top_device_info_data_fault_id_v(u32 r) | ||
228 | { | ||
229 | return (r >> 2U) & 0x1U; | ||
230 | } | ||
231 | static inline u32 top_device_info_data_fault_id_valid_v(void) | ||
232 | { | ||
233 | return 0x00000001U; | ||
234 | } | ||
235 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h new file mode 100644 index 00000000..e3749690 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h | |||
@@ -0,0 +1,95 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_usermode_gv11b_h_ | ||
57 | #define _hw_usermode_gv11b_h_ | ||
58 | |||
59 | static inline u32 usermode_cfg0_r(void) | ||
60 | { | ||
61 | return 0x00810000; | ||
62 | } | ||
63 | static inline u32 usermode_cfg0_usermode_class_id_f(u32 v) | ||
64 | { | ||
65 | return (v & 0xffff) << 0; | ||
66 | } | ||
67 | static inline u32 usermode_cfg0_usermode_class_id_value_v(void) | ||
68 | { | ||
69 | return 0x0000c361; | ||
70 | } | ||
71 | static inline u32 usermode_time_0_r(void) | ||
72 | { | ||
73 | return 0x00810080; | ||
74 | } | ||
75 | static inline u32 usermode_time_0_nsec_f(u32 v) | ||
76 | { | ||
77 | return (v & 0x7ffffff) << 5; | ||
78 | } | ||
79 | static inline u32 usermode_time_1_r(void) | ||
80 | { | ||
81 | return 0x00810084; | ||
82 | } | ||
83 | static inline u32 usermode_time_1_nsec_f(u32 v) | ||
84 | { | ||
85 | return (v & 0x1fffffff) << 0; | ||
86 | } | ||
87 | static inline u32 usermode_notify_channel_pending_r(void) | ||
88 | { | ||
89 | return 0x00810090; | ||
90 | } | ||
91 | static inline u32 usermode_notify_channel_pending_id_f(u32 v) | ||
92 | { | ||
93 | return (v & 0xffffffff) << 0; | ||
94 | } | ||
95 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h new file mode 100644 index 00000000..f8c7dbbd --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef __NVGPU_IO_T19X_H__ | ||
23 | #define __NVGPU_IO_T19X_H__ | ||
24 | |||
25 | #ifdef __KERNEL__ | ||
26 | #include "linux/io_t19x.h" | ||
27 | #endif | ||
28 | |||
29 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h new file mode 100644 index 00000000..f71a6ecf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef __NVGPU_IO_T19X_LINUX_H__ | ||
18 | #define __NVGPU_IO_T19X_LINUX_H__ | ||
19 | |||
20 | #include <nvgpu/types.h> | ||
21 | |||
22 | struct gk20a; | ||
23 | |||
24 | void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v); | ||
25 | |||
26 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h new file mode 100644 index 00000000..a105c6dc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h | |||
@@ -0,0 +1,27 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef __NVGPU_MODULE_T19X_H__ | ||
18 | #define __NVGPU_MODULE_T19X_H__ | ||
19 | |||
20 | struct gk20a; | ||
21 | |||
22 | void t19x_init_support(struct gk20a *g); | ||
23 | void t19x_remove_support(struct gk20a *g); | ||
24 | void t19x_lockout_registers(struct gk20a *g); | ||
25 | void t19x_restore_registers(struct gk20a *g); | ||
26 | |||
27 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h new file mode 100644 index 00000000..a306bfb8 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | #ifndef NVGPU_OS_LINUX_T19X_H | ||
17 | #define NVGPU_OS_LINUX_T19X_H | ||
18 | |||
19 | #include <linux/compiler.h> | ||
20 | |||
21 | struct nvgpu_os_linux_t19x { | ||
22 | void __iomem *usermode_regs; | ||
23 | void __iomem *usermode_regs_saved; | ||
24 | }; | ||
25 | |||
26 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h new file mode 100644 index 00000000..c94176cc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | #ifndef __NVGPU_PCI_T19X_H__ | ||
17 | #define __NVGPU_PCI_T19X_H__ | ||
18 | |||
19 | struct nvgpu_os_linux; | ||
20 | |||
21 | void t19x_nvgpu_pci_init_support(struct nvgpu_os_linux *l); | ||
22 | |||
23 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h new file mode 100644 index 00000000..4b499882 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __NVGPU_NVHOST_T19X_H__ | ||
24 | #define __NVGPU_NVHOST_T19X_H__ | ||
25 | |||
26 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
27 | #include <nvgpu/types.h> | ||
28 | |||
29 | struct nvgpu_nvhost_dev; | ||
30 | |||
31 | int nvgpu_nvhost_syncpt_unit_interface_get_aperture( | ||
32 | struct nvgpu_nvhost_dev *nvhost_dev, | ||
33 | u64 *base, size_t *size); | ||
34 | u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); | ||
35 | |||
36 | #endif | ||
37 | #endif /* __NVGPU_NVHOST_T19X_H__ */ | ||