diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 43 |
2 files changed, 60 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 0323dce4..10b220b7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -171,6 +171,17 @@ struct vbios_clocks_table_1x_header { | |||
171 | u16 cntr_sampling_periodms; | 171 | u16 cntr_sampling_periodms; |
172 | } __packed; | 172 | } __packed; |
173 | 173 | ||
174 | #define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09 | ||
175 | struct vbios_clocks_table_35_header { | ||
176 | u8 version; | ||
177 | u8 header_size; | ||
178 | u8 entry_size; | ||
179 | u8 entry_count; | ||
180 | u8 clocks_hal; | ||
181 | u16 cntr_sampling_periodms; | ||
182 | u16 reference_window; | ||
183 | } __packed; | ||
184 | |||
174 | #define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 | 185 | #define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 |
175 | struct vbios_clocks_table_1x_entry { | 186 | struct vbios_clocks_table_1x_entry { |
176 | u8 flags0; | 187 | u8 flags0; |
@@ -179,6 +190,15 @@ struct vbios_clocks_table_1x_entry { | |||
179 | u16 param2; | 190 | u16 param2; |
180 | } __packed; | 191 | } __packed; |
181 | 192 | ||
193 | #define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11 0x0B | ||
194 | struct vbios_clocks_table_35_entry { | ||
195 | u8 flags0; | ||
196 | u16 param0; | ||
197 | u32 param1; | ||
198 | u16 param2; | ||
199 | u16 param3; | ||
200 | } __packed; | ||
201 | |||
182 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F | 202 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F |
183 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 | 203 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 |
184 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 | 204 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 |
@@ -212,6 +232,17 @@ struct vbios_clocks_table_1x_entry { | |||
212 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 | 232 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 |
213 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 | 233 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 |
214 | 234 | ||
235 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_MASK 0xF | ||
236 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_SHIFT 0 | ||
237 | |||
238 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_MASK 0xF0 | ||
239 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_SHIFT 4 | ||
240 | |||
241 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_MASK 0xFF | ||
242 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_SHIFT 0 | ||
243 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK 0xFF00 | ||
244 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08 | ||
245 | |||
215 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 | 246 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 |
216 | struct vbios_clock_programming_table_1x_header { | 247 | struct vbios_clock_programming_table_1x_header { |
217 | u8 version; | 248 | u8 version; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index cdab649e..b94db25c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | |||
@@ -118,48 +118,63 @@ struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { | |||
118 | short freq_delta_min_mhz; | 118 | short freq_delta_min_mhz; |
119 | short freq_delta_max_mhz; | 119 | short freq_delta_max_mhz; |
120 | struct ctrl_clk_clk_delta deltas; | 120 | struct ctrl_clk_clk_delta deltas; |
121 | }; | ||
122 | |||
123 | struct nv_pmu_clk_clk_domain_30_prog_boardobj_set { | ||
124 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
121 | u8 noise_unaware_ordering_index; | 125 | u8 noise_unaware_ordering_index; |
122 | u8 noise_aware_ordering_index; | 126 | u8 noise_aware_ordering_index; |
123 | }; | 127 | }; |
124 | 128 | ||
125 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { | 129 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { |
126 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
127 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | 130 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ |
128 | u32 slave_idxs_mask; | 131 | u32 slave_idxs_mask; |
129 | }; | 132 | }; |
130 | 133 | ||
134 | struct nv_pmu_clk_clk_domain_30_master_boardobj_set { | ||
135 | struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super; | ||
136 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master; | ||
137 | }; | ||
138 | |||
139 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { | ||
140 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
141 | u8 master_idx; | ||
142 | }; | ||
143 | |||
144 | struct nv_pmu_clk_clk_domain_30_slave_boardobj_set { | ||
145 | struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super; | ||
146 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave; | ||
147 | }; | ||
148 | |||
131 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set { | 149 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set { |
132 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | 150 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; |
133 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | 151 | u8 pre_volt_ordering_index; |
134 | u8 dummy; | 152 | u8 post_volt_ordering_index; |
153 | u8 clk_pos; | ||
154 | u8 clk_vf_curve_count; | ||
135 | }; | 155 | }; |
136 | 156 | ||
137 | struct nv_pmu_clk_clk_domain_35_master_boardobj_set { | 157 | struct nv_pmu_clk_clk_domain_35_master_boardobj_set { |
138 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super; | 158 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super; |
139 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | 159 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master; |
140 | u32 master_slave_domains_grp_mask; | 160 | u32 master_slave_domains_grp_mask; |
141 | }; | 161 | }; |
142 | 162 | ||
143 | 163 | ||
144 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { | ||
145 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
146 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
147 | u8 master_idx; | ||
148 | }; | ||
149 | |||
150 | struct nv_pmu_clk_clk_domain_35_slave_boardobj_set { | 164 | struct nv_pmu_clk_clk_domain_35_slave_boardobj_set { |
151 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super; | 165 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super; |
152 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | 166 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave; |
153 | u8 master_idx; | ||
154 | }; | 167 | }; |
168 | |||
155 | union nv_pmu_clk_clk_domain_boardobj_set_union { | 169 | union nv_pmu_clk_clk_domain_boardobj_set_union { |
156 | struct nv_pmu_boardobj board_obj; | 170 | struct nv_pmu_boardobj board_obj; |
157 | struct nv_pmu_clk_clk_domain_boardobj_set super; | 171 | struct nv_pmu_clk_clk_domain_boardobj_set super; |
158 | struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; | 172 | struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; |
159 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; | 173 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; |
160 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; | 174 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; |
161 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; | 175 | struct nv_pmu_clk_clk_domain_30_prog_boardobj_set v30_prog; |
162 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; | 176 | struct nv_pmu_clk_clk_domain_30_master_boardobj_set v30_master; |
177 | struct nv_pmu_clk_clk_domain_30_slave_boardobj_set v30_slave; | ||
163 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog; | 178 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog; |
164 | struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master; | 179 | struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master; |
165 | struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave; | 180 | struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave; |