diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmu.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | 62 |
4 files changed, 0 insertions, 119 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h index 1622849a..71ecc24a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h +++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | |||
@@ -41,12 +41,6 @@ struct falc_dma_addr { | |||
41 | u8 dma_offset; | 41 | u8 dma_offset; |
42 | }; | 42 | }; |
43 | 43 | ||
44 | struct pmu_mem_v0 { | ||
45 | u32 dma_base; | ||
46 | u8 dma_offset; | ||
47 | u8 dma_idx; | ||
48 | }; | ||
49 | |||
50 | struct pmu_mem_v1 { | 44 | struct pmu_mem_v1 { |
51 | u32 dma_base; | 45 | u32 dma_base; |
52 | u8 dma_offset; | 46 | u8 dma_offset; |
@@ -54,12 +48,6 @@ struct pmu_mem_v1 { | |||
54 | u16 fb_size; | 48 | u16 fb_size; |
55 | }; | 49 | }; |
56 | 50 | ||
57 | struct pmu_mem_v2 { | ||
58 | struct falc_dma_addr dma_addr; | ||
59 | u8 dma_idx; | ||
60 | u16 fb_size; | ||
61 | }; | ||
62 | |||
63 | struct pmu_mem_desc_v0 { | 51 | struct pmu_mem_desc_v0 { |
64 | struct falc_u64 dma_addr; | 52 | struct falc_u64 dma_addr; |
65 | u16 dma_sizemax; | 53 | u16 dma_sizemax; |
@@ -78,15 +66,6 @@ struct flcn_mem_desc_v0 { | |||
78 | 66 | ||
79 | #define nv_flcn_mem_desc flcn_mem_desc_v0 | 67 | #define nv_flcn_mem_desc flcn_mem_desc_v0 |
80 | 68 | ||
81 | struct pmu_allocation_v0 { | ||
82 | u8 pad[3]; | ||
83 | u8 fb_mem_use; | ||
84 | struct { | ||
85 | struct pmu_dmem dmem; | ||
86 | struct pmu_mem_v0 fb; | ||
87 | } alloc; | ||
88 | }; | ||
89 | |||
90 | struct pmu_allocation_v1 { | 69 | struct pmu_allocation_v1 { |
91 | struct { | 70 | struct { |
92 | struct pmu_dmem dmem; | 71 | struct pmu_dmem dmem; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 5e9983b0..5e34abe6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -269,14 +269,12 @@ struct pmu_sequence { | |||
269 | u32 desc; | 269 | u32 desc; |
270 | struct pmu_msg *msg; | 270 | struct pmu_msg *msg; |
271 | union { | 271 | union { |
272 | struct pmu_allocation_v0 in_v0; | ||
273 | struct pmu_allocation_v1 in_v1; | 272 | struct pmu_allocation_v1 in_v1; |
274 | struct pmu_allocation_v2 in_v2; | 273 | struct pmu_allocation_v2 in_v2; |
275 | struct pmu_allocation_v3 in_v3; | 274 | struct pmu_allocation_v3 in_v3; |
276 | }; | 275 | }; |
277 | struct nvgpu_mem *in_mem; | 276 | struct nvgpu_mem *in_mem; |
278 | union { | 277 | union { |
279 | struct pmu_allocation_v0 out_v0; | ||
280 | struct pmu_allocation_v1 out_v1; | 278 | struct pmu_allocation_v1 out_v1; |
281 | struct pmu_allocation_v2 out_v2; | 279 | struct pmu_allocation_v2 out_v2; |
282 | struct pmu_allocation_v3 out_v3; | 280 | struct pmu_allocation_v3 out_v3; |
@@ -351,7 +349,6 @@ struct nvgpu_pmu { | |||
351 | 349 | ||
352 | union { | 350 | union { |
353 | struct pmu_perfmon_counter_v2 perfmon_counter_v2; | 351 | struct pmu_perfmon_counter_v2 perfmon_counter_v2; |
354 | struct pmu_perfmon_counter_v0 perfmon_counter_v0; | ||
355 | }; | 352 | }; |
356 | u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM]; | 353 | u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM]; |
357 | 354 | ||
@@ -371,9 +368,6 @@ struct nvgpu_pmu { | |||
371 | 368 | ||
372 | bool zbc_ready; | 369 | bool zbc_ready; |
373 | union { | 370 | union { |
374 | struct pmu_cmdline_args_v0 args_v0; | ||
375 | struct pmu_cmdline_args_v1 args_v1; | ||
376 | struct pmu_cmdline_args_v2 args_v2; | ||
377 | struct pmu_cmdline_args_v3 args_v3; | 371 | struct pmu_cmdline_args_v3 args_v3; |
378 | struct pmu_cmdline_args_v4 args_v4; | 372 | struct pmu_cmdline_args_v4 args_v4; |
379 | struct pmu_cmdline_args_v5 args_v5; | 373 | struct pmu_cmdline_args_v5 args_v5; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h index bcf4c8b6..91e89365 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h | |||
@@ -44,15 +44,6 @@ enum { | |||
44 | PMU_PERFMON_CMD_ID_INIT = 2 | 44 | PMU_PERFMON_CMD_ID_INIT = 2 |
45 | }; | 45 | }; |
46 | 46 | ||
47 | struct pmu_perfmon_counter_v0 { | ||
48 | u8 index; | ||
49 | u8 flags; | ||
50 | u8 group_id; | ||
51 | u8 valid; | ||
52 | u16 upper_threshold; /* units of 0.01% */ | ||
53 | u16 lower_threshold; /* units of 0.01% */ | ||
54 | }; | ||
55 | |||
56 | struct pmu_perfmon_counter_v2 { | 47 | struct pmu_perfmon_counter_v2 { |
57 | u8 index; | 48 | u8 index; |
58 | u8 flags; | 49 | u8 flags; |
@@ -96,14 +87,6 @@ struct pmu_perfmon_cmd_start_v1 { | |||
96 | struct pmu_allocation_v1 counter_alloc; | 87 | struct pmu_allocation_v1 counter_alloc; |
97 | }; | 88 | }; |
98 | 89 | ||
99 | struct pmu_perfmon_cmd_start_v0 { | ||
100 | u8 cmd_type; | ||
101 | u8 group_id; | ||
102 | u8 state_id; | ||
103 | u8 flags; | ||
104 | struct pmu_allocation_v0 counter_alloc; | ||
105 | }; | ||
106 | |||
107 | struct pmu_perfmon_cmd_stop { | 90 | struct pmu_perfmon_cmd_stop { |
108 | u8 cmd_type; | 91 | u8 cmd_type; |
109 | }; | 92 | }; |
@@ -141,26 +124,13 @@ struct pmu_perfmon_cmd_init_v1 { | |||
141 | u16 sample_buffer; | 124 | u16 sample_buffer; |
142 | }; | 125 | }; |
143 | 126 | ||
144 | struct pmu_perfmon_cmd_init_v0 { | ||
145 | u8 cmd_type; | ||
146 | u8 to_decrease_count; | ||
147 | u8 base_counter_id; | ||
148 | u32 sample_period_us; | ||
149 | struct pmu_allocation_v0 counter_alloc; | ||
150 | u8 num_counters; | ||
151 | u8 samples_in_moving_avg; | ||
152 | u16 sample_buffer; | ||
153 | }; | ||
154 | |||
155 | struct pmu_perfmon_cmd { | 127 | struct pmu_perfmon_cmd { |
156 | union { | 128 | union { |
157 | u8 cmd_type; | 129 | u8 cmd_type; |
158 | struct pmu_perfmon_cmd_start_v0 start_v0; | ||
159 | struct pmu_perfmon_cmd_start_v1 start_v1; | 130 | struct pmu_perfmon_cmd_start_v1 start_v1; |
160 | struct pmu_perfmon_cmd_start_v2 start_v2; | 131 | struct pmu_perfmon_cmd_start_v2 start_v2; |
161 | struct pmu_perfmon_cmd_start_v3 start_v3; | 132 | struct pmu_perfmon_cmd_start_v3 start_v3; |
162 | struct pmu_perfmon_cmd_stop stop; | 133 | struct pmu_perfmon_cmd_stop stop; |
163 | struct pmu_perfmon_cmd_init_v0 init_v0; | ||
164 | struct pmu_perfmon_cmd_init_v1 init_v1; | 134 | struct pmu_perfmon_cmd_init_v1 init_v1; |
165 | struct pmu_perfmon_cmd_init_v2 init_v2; | 135 | struct pmu_perfmon_cmd_init_v2 init_v2; |
166 | struct pmu_perfmon_cmd_init_v3 init_v3; | 136 | struct pmu_perfmon_cmd_init_v3 init_v3; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h index 91ef1bda..8e38db31 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | |||
@@ -26,33 +26,6 @@ | |||
26 | #include "gpmuif_cmn.h" | 26 | #include "gpmuif_cmn.h" |
27 | 27 | ||
28 | /* Make sure size of this structure is a multiple of 4 bytes */ | 28 | /* Make sure size of this structure is a multiple of 4 bytes */ |
29 | struct pmu_cmdline_args_v0 { | ||
30 | u32 cpu_freq_hz; | ||
31 | u32 falc_trace_size; | ||
32 | u32 falc_trace_dma_base; | ||
33 | u32 falc_trace_dma_idx; | ||
34 | struct pmu_mem_v0 gc6_ctx; | ||
35 | }; | ||
36 | |||
37 | struct pmu_cmdline_args_v1 { | ||
38 | u32 cpu_freq_hz; | ||
39 | u32 falc_trace_size; | ||
40 | u32 falc_trace_dma_base; | ||
41 | u32 falc_trace_dma_idx; | ||
42 | u8 secure_mode; | ||
43 | struct pmu_mem_v1 gc6_ctx; | ||
44 | }; | ||
45 | |||
46 | struct pmu_cmdline_args_v2 { | ||
47 | u32 cpu_freq_hz; | ||
48 | u32 falc_trace_size; | ||
49 | u32 falc_trace_dma_base; | ||
50 | u32 falc_trace_dma_idx; | ||
51 | u8 secure_mode; | ||
52 | u8 raise_priv_sec; | ||
53 | struct pmu_mem_v1 gc6_ctx; | ||
54 | }; | ||
55 | |||
56 | struct pmu_cmdline_args_v3 { | 29 | struct pmu_cmdline_args_v3 { |
57 | u32 reserved; | 30 | u32 reserved; |
58 | u32 cpu_freq_hz; | 31 | u32 cpu_freq_hz; |
@@ -118,21 +91,6 @@ enum { | |||
118 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, | 91 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, |
119 | }; | 92 | }; |
120 | 93 | ||
121 | struct pmu_init_msg_pmu_v0 { | ||
122 | u8 msg_type; | ||
123 | u8 pad; | ||
124 | |||
125 | struct { | ||
126 | u16 size; | ||
127 | u16 offset; | ||
128 | u8 index; | ||
129 | u8 pad; | ||
130 | } queue_info[PMU_QUEUE_COUNT]; | ||
131 | |||
132 | u16 sw_managed_area_offset; | ||
133 | u16 sw_managed_area_size; | ||
134 | }; | ||
135 | |||
136 | struct pmu_init_msg_pmu_v1 { | 94 | struct pmu_init_msg_pmu_v1 { |
137 | u8 msg_type; | 95 | u8 msg_type; |
138 | u8 pad; | 96 | u8 pad; |
@@ -148,22 +106,6 @@ struct pmu_init_msg_pmu_v1 { | |||
148 | u16 sw_managed_area_offset; | 106 | u16 sw_managed_area_offset; |
149 | u16 sw_managed_area_size; | 107 | u16 sw_managed_area_size; |
150 | }; | 108 | }; |
151 | struct pmu_init_msg_pmu_v2 { | ||
152 | u8 msg_type; | ||
153 | u8 pad; | ||
154 | u16 os_debug_entry_point; | ||
155 | |||
156 | struct { | ||
157 | u16 size; | ||
158 | u16 offset; | ||
159 | u8 index; | ||
160 | u8 pad; | ||
161 | } queue_info[PMU_QUEUE_COUNT]; | ||
162 | |||
163 | u16 sw_managed_area_offset; | ||
164 | u16 sw_managed_area_size; | ||
165 | u8 dummy[18]; | ||
166 | }; | ||
167 | 109 | ||
168 | #define PMU_QUEUE_COUNT_FOR_V4 5 | 110 | #define PMU_QUEUE_COUNT_FOR_V4 5 |
169 | #define PMU_QUEUE_COUNT_FOR_V3 3 | 111 | #define PMU_QUEUE_COUNT_FOR_V3 3 |
@@ -200,9 +142,7 @@ struct pmu_init_msg_pmu_v4 { | |||
200 | }; | 142 | }; |
201 | 143 | ||
202 | union pmu_init_msg_pmu { | 144 | union pmu_init_msg_pmu { |
203 | struct pmu_init_msg_pmu_v0 v0; | ||
204 | struct pmu_init_msg_pmu_v1 v1; | 145 | struct pmu_init_msg_pmu_v1 v1; |
205 | struct pmu_init_msg_pmu_v2 v2; | ||
206 | struct pmu_init_msg_pmu_v3 v3; | 146 | struct pmu_init_msg_pmu_v3 v3; |
207 | struct pmu_init_msg_pmu_v4 v4; | 147 | struct pmu_init_msg_pmu_v4 v4; |
208 | }; | 148 | }; |
@@ -211,8 +151,6 @@ struct pmu_init_msg { | |||
211 | union { | 151 | union { |
212 | u8 msg_type; | 152 | u8 msg_type; |
213 | struct pmu_init_msg_pmu_v1 pmu_init_v1; | 153 | struct pmu_init_msg_pmu_v1 pmu_init_v1; |
214 | struct pmu_init_msg_pmu_v0 pmu_init_v0; | ||
215 | struct pmu_init_msg_pmu_v2 pmu_init_v2; | ||
216 | struct pmu_init_msg_pmu_v3 pmu_init_v3; | 154 | struct pmu_init_msg_pmu_v3 pmu_init_v3; |
217 | struct pmu_init_msg_pmu_v4 pmu_init_v4; | 155 | struct pmu_init_msg_pmu_v4 pmu_init_v4; |
218 | }; | 156 | }; |