diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/atomic.h | 98 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h | 137 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/semaphore.h | 12 |
3 files changed, 237 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/atomic.h index 700e29fe..c7a5fcd9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/atomic.h +++ b/drivers/gpu/nvgpu/include/nvgpu/atomic.h | |||
@@ -9,12 +9,102 @@ | |||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
11 | * more details. | 11 | * more details. |
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
12 | */ | 15 | */ |
13 | #ifndef __NVGPU_ATOMIC_H__ | 16 | #ifndef __NVGPU_ATOMIC_H__ |
14 | #define __NVGPU_ATOMIC_H__ | 17 | #define __NVGPU_ATOMIC_H__ |
15 | 18 | ||
16 | #ifdef __KERNEL__ | 19 | #include <nvgpu/linux/atomic.h> |
17 | #include <linux/atomic.h> | 20 | |
18 | #endif | 21 | #define NVGPU_ATOMIC_INIT(i) __nvgpu_atomic_init(i) |
22 | #define NVGPU_ATOMIC64_INIT(i) __nvgpu_atomic64_init(i) | ||
23 | |||
24 | static inline void nvgpu_atomic_set(nvgpu_atomic_t *v, int i) | ||
25 | { | ||
26 | __nvgpu_atomic_set(v, i); | ||
27 | } | ||
28 | static inline int nvgpu_atomic_read(nvgpu_atomic_t *v) | ||
29 | { | ||
30 | return __nvgpu_atomic_read(v); | ||
31 | } | ||
32 | static inline void nvgpu_atomic_inc(nvgpu_atomic_t *v) | ||
33 | { | ||
34 | __nvgpu_atomic_inc(v); | ||
35 | } | ||
36 | static inline int nvgpu_atomic_inc_return(nvgpu_atomic_t *v) | ||
37 | { | ||
38 | return __nvgpu_atomic_inc_return(v); | ||
39 | } | ||
40 | static inline void nvgpu_atomic_dec(nvgpu_atomic_t *v) | ||
41 | { | ||
42 | __nvgpu_atomic_dec(v); | ||
43 | } | ||
44 | static inline int nvgpu_atomic_dec_return(nvgpu_atomic_t *v) | ||
45 | { | ||
46 | return __nvgpu_atomic_dec_return(v); | ||
47 | } | ||
48 | static inline int nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) | ||
49 | { | ||
50 | return __nvgpu_atomic_cmpxchg(v, old, new); | ||
51 | } | ||
52 | static inline int nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) | ||
53 | { | ||
54 | return __nvgpu_atomic_xchg(v, new); | ||
55 | } | ||
56 | static inline bool nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) | ||
57 | { | ||
58 | return __nvgpu_atomic_inc_and_test(v); | ||
59 | } | ||
60 | static inline bool nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) | ||
61 | { | ||
62 | return __nvgpu_atomic_dec_and_test(v); | ||
63 | } | ||
64 | static inline int nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) | ||
65 | { | ||
66 | return __nvgpu_atomic_add_return(i, v); | ||
67 | } | ||
68 | static inline void nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) | ||
69 | { | ||
70 | return __nvgpu_atomic64_set(v, i); | ||
71 | } | ||
72 | static inline long nvgpu_atomic64_read(nvgpu_atomic64_t *v) | ||
73 | { | ||
74 | return __nvgpu_atomic64_read(v); | ||
75 | } | ||
76 | static inline void nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) | ||
77 | { | ||
78 | __nvgpu_atomic64_add(x, v); | ||
79 | } | ||
80 | static inline void nvgpu_atomic64_inc(nvgpu_atomic64_t *v) | ||
81 | { | ||
82 | __nvgpu_atomic64_inc(v); | ||
83 | } | ||
84 | static inline long nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) | ||
85 | { | ||
86 | return __nvgpu_atomic64_inc_return(v); | ||
87 | } | ||
88 | static inline void nvgpu_atomic64_dec(nvgpu_atomic64_t *v) | ||
89 | { | ||
90 | __nvgpu_atomic64_dec(v); | ||
91 | } | ||
92 | static inline void nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) | ||
93 | { | ||
94 | __nvgpu_atomic64_dec_return(v); | ||
95 | } | ||
96 | static inline long nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, long old, | ||
97 | long new) | ||
98 | { | ||
99 | return __nvgpu_atomic64_cmpxchg(v, old, new); | ||
100 | } | ||
101 | static inline void nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) | ||
102 | { | ||
103 | __nvgpu_atomic64_sub(x, v); | ||
104 | } | ||
105 | static inline long nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) | ||
106 | { | ||
107 | return __nvgpu_atomic64_sub_return(x, v); | ||
108 | } | ||
19 | 109 | ||
20 | #endif | 110 | #endif /* __NVGPU_ATOMIC_H__ */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h new file mode 100644 index 00000000..c6dd4650 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/atomic.h | |||
@@ -0,0 +1,137 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | #ifndef __NVGPU_ATOMIC_LINUX_H__ | ||
17 | #define __NVGPU_ATOMIC_LINUX_H__ | ||
18 | |||
19 | #include <linux/atomic.h> | ||
20 | |||
21 | typedef struct nvgpu_atomic { | ||
22 | atomic_t atomic_var; | ||
23 | } nvgpu_atomic_t; | ||
24 | |||
25 | typedef struct nvgpu_atomic64 { | ||
26 | atomic64_t atomic_var; | ||
27 | } nvgpu_atomic64_t; | ||
28 | |||
29 | #define __nvgpu_atomic_init(i) { ATOMIC_INIT(i) } | ||
30 | #define __nvgpu_atomic64_init(i) { ATOMIC64_INIT(i) } | ||
31 | |||
32 | static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i) | ||
33 | { | ||
34 | atomic_set(&v->atomic_var, i); | ||
35 | } | ||
36 | |||
37 | static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v) | ||
38 | { | ||
39 | return atomic_read(&v->atomic_var); | ||
40 | } | ||
41 | |||
42 | static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v) | ||
43 | { | ||
44 | atomic_inc(&v->atomic_var); | ||
45 | } | ||
46 | |||
47 | static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v) | ||
48 | { | ||
49 | return atomic_inc_return(&v->atomic_var); | ||
50 | } | ||
51 | |||
52 | static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v) | ||
53 | { | ||
54 | atomic_dec(&v->atomic_var); | ||
55 | } | ||
56 | |||
57 | static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v) | ||
58 | { | ||
59 | return atomic_dec_return(&v->atomic_var); | ||
60 | } | ||
61 | |||
62 | static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) | ||
63 | { | ||
64 | return atomic_cmpxchg(&v->atomic_var, old, new); | ||
65 | } | ||
66 | |||
67 | static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) | ||
68 | { | ||
69 | return atomic_xchg(&v->atomic_var, new); | ||
70 | } | ||
71 | |||
72 | static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) | ||
73 | { | ||
74 | return atomic_inc_and_test(&v->atomic_var); | ||
75 | } | ||
76 | |||
77 | static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) | ||
78 | { | ||
79 | return atomic_dec_and_test(&v->atomic_var); | ||
80 | } | ||
81 | |||
82 | static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) | ||
83 | { | ||
84 | return atomic_add_return(i, &v->atomic_var); | ||
85 | } | ||
86 | |||
87 | static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) | ||
88 | { | ||
89 | atomic64_set(&v->atomic_var, i); | ||
90 | } | ||
91 | |||
92 | static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v) | ||
93 | { | ||
94 | return atomic64_read(&v->atomic_var); | ||
95 | } | ||
96 | |||
97 | static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) | ||
98 | { | ||
99 | atomic64_add(x, &v->atomic_var); | ||
100 | } | ||
101 | |||
102 | static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v) | ||
103 | { | ||
104 | atomic64_inc(&v->atomic_var); | ||
105 | } | ||
106 | |||
107 | static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) | ||
108 | { | ||
109 | return atomic64_inc_return(&v->atomic_var); | ||
110 | } | ||
111 | |||
112 | static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v) | ||
113 | { | ||
114 | atomic64_dec(&v->atomic_var); | ||
115 | } | ||
116 | |||
117 | static inline void __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) | ||
118 | { | ||
119 | atomic64_dec_return(&v->atomic_var); | ||
120 | } | ||
121 | |||
122 | static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, | ||
123 | long old, long new) | ||
124 | { | ||
125 | return atomic64_cmpxchg(&v->atomic_var, old, new); | ||
126 | } | ||
127 | |||
128 | static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) | ||
129 | { | ||
130 | atomic64_sub(x, &v->atomic_var); | ||
131 | } | ||
132 | |||
133 | static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) | ||
134 | { | ||
135 | return atomic64_sub_return(x, &v->atomic_var); | ||
136 | } | ||
137 | #endif /*__NVGPU_ATOMIC_LINUX_H__ */ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h index faa8d945..90261d81 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h +++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h | |||
@@ -48,7 +48,7 @@ struct nvgpu_semaphore_sea; | |||
48 | struct nvgpu_semaphore_int { | 48 | struct nvgpu_semaphore_int { |
49 | int idx; /* Semaphore index. */ | 49 | int idx; /* Semaphore index. */ |
50 | u32 offset; /* Offset into the pool. */ | 50 | u32 offset; /* Offset into the pool. */ |
51 | atomic_t next_value; /* Next available value. */ | 51 | nvgpu_atomic_t next_value; /* Next available value. */ |
52 | u32 nr_incrs; /* Number of increments programmed. */ | 52 | u32 nr_incrs; /* Number of increments programmed. */ |
53 | struct nvgpu_semaphore_pool *p; /* Pool that owns this sema. */ | 53 | struct nvgpu_semaphore_pool *p; /* Pool that owns this sema. */ |
54 | struct channel_gk20a *ch; /* Channel that owns this sema. */ | 54 | struct channel_gk20a *ch; /* Channel that owns this sema. */ |
@@ -70,7 +70,7 @@ nvgpu_semaphore_int_from_hw_sema_list(struct nvgpu_list_node *node) | |||
70 | struct nvgpu_semaphore { | 70 | struct nvgpu_semaphore { |
71 | struct nvgpu_semaphore_int *hw_sema; | 71 | struct nvgpu_semaphore_int *hw_sema; |
72 | 72 | ||
73 | atomic_t value; | 73 | nvgpu_atomic_t value; |
74 | int incremented; | 74 | int incremented; |
75 | 75 | ||
76 | struct kref ref; | 76 | struct kref ref; |
@@ -242,7 +242,7 @@ static inline bool nvgpu_semaphore_is_released(struct nvgpu_semaphore *s) | |||
242 | * the value of the semaphore then the semaphore has been signaled | 242 | * the value of the semaphore then the semaphore has been signaled |
243 | * (a.k.a. released). | 243 | * (a.k.a. released). |
244 | */ | 244 | */ |
245 | return (int)sema_val >= atomic_read(&s->value); | 245 | return (int)sema_val >= nvgpu_atomic_read(&s->value); |
246 | } | 246 | } |
247 | 247 | ||
248 | static inline bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s) | 248 | static inline bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s) |
@@ -252,12 +252,12 @@ static inline bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s) | |||
252 | 252 | ||
253 | static inline u32 nvgpu_semaphore_get_value(struct nvgpu_semaphore *s) | 253 | static inline u32 nvgpu_semaphore_get_value(struct nvgpu_semaphore *s) |
254 | { | 254 | { |
255 | return (u32)atomic_read(&s->value); | 255 | return (u32)nvgpu_atomic_read(&s->value); |
256 | } | 256 | } |
257 | 257 | ||
258 | static inline u32 nvgpu_semaphore_next_value(struct nvgpu_semaphore *s) | 258 | static inline u32 nvgpu_semaphore_next_value(struct nvgpu_semaphore *s) |
259 | { | 259 | { |
260 | return (u32)atomic_read(&s->hw_sema->next_value); | 260 | return (u32)nvgpu_atomic_read(&s->hw_sema->next_value); |
261 | } | 261 | } |
262 | 262 | ||
263 | /* | 263 | /* |
@@ -320,7 +320,7 @@ static inline void nvgpu_semaphore_incr(struct nvgpu_semaphore *s) | |||
320 | { | 320 | { |
321 | BUG_ON(s->incremented); | 321 | BUG_ON(s->incremented); |
322 | 322 | ||
323 | atomic_set(&s->value, atomic_add_return(1, &s->hw_sema->next_value)); | 323 | nvgpu_atomic_set(&s->value, nvgpu_atomic_add_return(1, &s->hw_sema->next_value)); |
324 | s->incremented = 1; | 324 | s->incremented = 1; |
325 | 325 | ||
326 | gpu_sema_verbose_dbg(s->hw_sema->p->sema_sea->gk20a, | 326 | gpu_sema_verbose_dbg(s->hw_sema->p->sema_sea->gk20a, |