diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/bios.h | 156 |
1 files changed, 155 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h index 83d972e3..d3a677f8 100644 --- a/drivers/gpu/nvgpu/include/bios.h +++ b/drivers/gpu/nvgpu/include/bios.h | |||
@@ -501,5 +501,159 @@ struct vbios_memory_clock_base_entry_11 { | |||
501 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK 0x3 | 501 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK 0x3 |
502 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 | 502 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 |
503 | 503 | ||
504 | #endif | 504 | #define VBIOS_POWER_SENSORS_VERSION_2X 0x20 |
505 | #define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008 | ||
506 | |||
507 | struct pwr_sensors_2x_header { | ||
508 | u8 version; | ||
509 | u8 header_size; | ||
510 | u8 table_entry_size; | ||
511 | u8 num_table_entries; | ||
512 | u32 ba_script_pointer; | ||
513 | }; | ||
514 | |||
515 | #define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015 | ||
516 | |||
517 | struct pwr_sensors_2x_entry { | ||
518 | u8 flags0; | ||
519 | u32 class_param0; | ||
520 | u32 sensor_param0; | ||
521 | u32 sensor_param1; | ||
522 | u32 sensor_param2; | ||
523 | u32 sensor_param3; | ||
524 | }; | ||
525 | |||
526 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
527 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
528 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001 | ||
529 | |||
530 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF | ||
531 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 | ||
532 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK 0x100 | ||
533 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT 8 | ||
534 | |||
535 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK 0xFFFF | ||
536 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT 0 | ||
537 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK 0xFFFF0000 | ||
538 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT 16 | ||
539 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK 0xFFFF | ||
540 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT 0 | ||
541 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK 0xFFFF0000 | ||
542 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT 16 | ||
543 | |||
544 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK 0xFFFF | ||
545 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT 0 | ||
546 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK 0xFF0000 | ||
547 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT 16 | ||
548 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK 0xFFFF | ||
549 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT 0 | ||
550 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 | ||
551 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 | ||
552 | |||
553 | #define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20 | ||
554 | #define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006 | ||
555 | |||
556 | struct pwr_topology_2x_header { | ||
557 | u8 version; | ||
558 | u8 header_size; | ||
559 | u8 table_entry_size; | ||
560 | u8 num_table_entries; | ||
561 | u8 rel_entry_size; | ||
562 | u8 num_rel_entries; | ||
563 | }; | ||
564 | |||
565 | #define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016 | ||
566 | |||
567 | struct pwr_topology_2x_entry { | ||
568 | u8 flags0; | ||
569 | u8 pwr_rail; | ||
570 | u32 param0; | ||
571 | u32 curr_corr_slope; | ||
572 | u32 curr_corr_offset; | ||
573 | u32 param1; | ||
574 | u32 param2; | ||
575 | }; | ||
576 | |||
577 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
578 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
579 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR 0x00000001 | ||
580 | |||
581 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF | ||
582 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 | ||
583 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 | ||
584 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 | ||
585 | |||
586 | #define VBIOS_POWER_POLICY_VERSION_3X 0x30 | ||
587 | #define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025 | ||
588 | |||
589 | struct pwr_policy_3x_header_struct { | ||
590 | u8 version; | ||
591 | u8 header_size; | ||
592 | u8 table_entry_size; | ||
593 | u8 num_table_entries; | ||
594 | u16 base_sample_period; | ||
595 | u16 min_client_sample_period; | ||
596 | u8 table_rel_entry_size; | ||
597 | u8 num_table_rel_entries; | ||
598 | u8 tgp_policy_idx; | ||
599 | u8 rtp_policy_idx; | ||
600 | u8 mxm_policy_idx; | ||
601 | u8 dnotifier_policy_idx; | ||
602 | u32 d2_limit; | ||
603 | u32 d3_limit; | ||
604 | u32 d4_limit; | ||
605 | u32 d5_limit; | ||
606 | u8 low_sampling_mult; | ||
607 | u8 pwr_tgt_policy_idx; | ||
608 | u8 pwr_tgt_floor_policy_idx; | ||
609 | u8 sm_bus_policy_idx; | ||
610 | u8 table_viol_entry_size; | ||
611 | u8 num_table_viol_entries; | ||
612 | }; | ||
613 | |||
614 | #define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002E | ||
615 | |||
616 | struct pwr_policy_3x_entry_struct { | ||
617 | u8 flags0; | ||
618 | u8 ch_idx; | ||
619 | u32 limit_min; | ||
620 | u32 limit_rated; | ||
621 | u32 limit_max; | ||
622 | u32 param0; | ||
623 | u32 param1; | ||
624 | u32 param2; | ||
625 | u32 param3; | ||
626 | u32 limit_batt; | ||
627 | u8 flags1; | ||
628 | u8 past_length; | ||
629 | u8 next_length; | ||
630 | u16 ratio_min; | ||
631 | u16 ratio_max; | ||
632 | u8 sample_mult; | ||
633 | u32 filter_param; | ||
634 | }; | ||
635 | |||
636 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
637 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
638 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005 | ||
639 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 | ||
640 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 | ||
641 | |||
642 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK 0x1 | ||
643 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT 0 | ||
644 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK 0x2 | ||
645 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT 1 | ||
646 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK 0x3C | ||
647 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT 2 | ||
648 | |||
649 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK 0xFF | ||
650 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT 0 | ||
651 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00 | ||
652 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8 | ||
653 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000 | ||
654 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16 | ||
655 | |||
656 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF | ||
657 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 | ||
505 | 658 | ||
659 | #endif | ||