diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index fe9a70db..8f4c8564 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | |||
@@ -226,6 +226,7 @@ struct nv_pmu_clk_lut_device_desc { | |||
226 | 226 | ||
227 | struct nv_pmu_clk_regime_desc { | 227 | struct nv_pmu_clk_regime_desc { |
228 | u8 regime_id; | 228 | u8 regime_id; |
229 | u8 target_regime_id_override; | ||
229 | u16 fixed_freq_regime_limit_mhz; | 230 | u16 fixed_freq_regime_limit_mhz; |
230 | }; | 231 | }; |
231 | 232 | ||
@@ -389,6 +390,12 @@ struct nv_pmu_clk_load { | |||
389 | struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; | 390 | struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; |
390 | } payload; | 391 | } payload; |
391 | }; | 392 | }; |
393 | |||
394 | struct nv_pmu_clk_freq_effective_avg { | ||
395 | u32 clkDomainMask; | ||
396 | u32 freqkHz[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS]; | ||
397 | }; | ||
398 | |||
392 | /* CLK_FREQ_CONTROLLER */ | 399 | /* CLK_FREQ_CONTROLLER */ |
393 | #define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003) | 400 | #define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003) |
394 | 401 | ||
@@ -432,6 +439,10 @@ union nv_pmu_clk_clk_freq_controller_boardobj_set_union { | |||
432 | 439 | ||
433 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); | 440 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); |
434 | 441 | ||
442 | #define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_EFFECTIVE_AVG (0x00000004) | ||
443 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_NO (0x00000000) | ||
444 | #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_YES (0x00000004) | ||
445 | |||
435 | /* CLK CMD ID definitions. */ | 446 | /* CLK CMD ID definitions. */ |
436 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000001) | 447 | #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000001) |
437 | #define NV_PMU_CLK_CMD_ID_RPC (0x00000000) | 448 | #define NV_PMU_CLK_CMD_ID_RPC (0x00000000) |
@@ -441,7 +452,6 @@ NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); | |||
441 | #define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000000) | 452 | #define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000000) |
442 | #define NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG (0x00000002) | 453 | #define NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG (0x00000002) |
443 | 454 | ||
444 | |||
445 | struct nv_pmu_clk_cmd_rpc { | 455 | struct nv_pmu_clk_cmd_rpc { |
446 | u8 cmd_type; | 456 | u8 cmd_type; |
447 | u8 pad[3]; | 457 | u8 pad[3]; |
@@ -476,6 +486,7 @@ struct nv_pmu_clk_rpc { | |||
476 | struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; | 486 | struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; |
477 | struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1; | 487 | struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1; |
478 | struct nv_pmu_clk_load clk_load; | 488 | struct nv_pmu_clk_load clk_load; |
489 | struct nv_pmu_clk_freq_effective_avg clk_freq_effective_avg; | ||
479 | } params; | 490 | } params; |
480 | }; | 491 | }; |
481 | 492 | ||