diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmu.h | 328 |
1 files changed, 328 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h new file mode 100644 index 00000000..0fcc5710 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -0,0 +1,328 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __NVGPU_PMU_H__ | ||
15 | #define __NVGPU_PMU_H__ | ||
16 | |||
17 | #include <nvgpu/kmem.h> | ||
18 | #include <nvgpu/nvgpu_mem.h> | ||
19 | #include <nvgpu/allocator.h> | ||
20 | #include <nvgpu/lock.h> | ||
21 | #include <nvgpu/cond.h> | ||
22 | #include <nvgpu/thread.h> | ||
23 | #include <nvgpu/nvgpu_common.h> | ||
24 | #include <nvgpu/flcnif_cmn.h> | ||
25 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | ||
26 | |||
27 | #define nvgpu_pmu_dbg(g, fmt, args...) \ | ||
28 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##args) | ||
29 | |||
30 | /* defined by pmu hw spec */ | ||
31 | #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) | ||
32 | #define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024) | ||
33 | #define GK20A_PMU_SEQ_BUF_SIZE 4096 | ||
34 | |||
35 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ | ||
36 | #define GK20A_PMU_DMEM_BLKSIZE2 8 | ||
37 | |||
38 | #define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6 | ||
39 | #define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD | ||
40 | |||
41 | /* Falcon Register index */ | ||
42 | #define PMU_FALCON_REG_R0 (0) | ||
43 | #define PMU_FALCON_REG_R1 (1) | ||
44 | #define PMU_FALCON_REG_R2 (2) | ||
45 | #define PMU_FALCON_REG_R3 (3) | ||
46 | #define PMU_FALCON_REG_R4 (4) | ||
47 | #define PMU_FALCON_REG_R5 (5) | ||
48 | #define PMU_FALCON_REG_R6 (6) | ||
49 | #define PMU_FALCON_REG_R7 (7) | ||
50 | #define PMU_FALCON_REG_R8 (8) | ||
51 | #define PMU_FALCON_REG_R9 (9) | ||
52 | #define PMU_FALCON_REG_R10 (10) | ||
53 | #define PMU_FALCON_REG_R11 (11) | ||
54 | #define PMU_FALCON_REG_R12 (12) | ||
55 | #define PMU_FALCON_REG_R13 (13) | ||
56 | #define PMU_FALCON_REG_R14 (14) | ||
57 | #define PMU_FALCON_REG_R15 (15) | ||
58 | #define PMU_FALCON_REG_IV0 (16) | ||
59 | #define PMU_FALCON_REG_IV1 (17) | ||
60 | #define PMU_FALCON_REG_UNDEFINED (18) | ||
61 | #define PMU_FALCON_REG_EV (19) | ||
62 | #define PMU_FALCON_REG_SP (20) | ||
63 | #define PMU_FALCON_REG_PC (21) | ||
64 | #define PMU_FALCON_REG_IMB (22) | ||
65 | #define PMU_FALCON_REG_DMB (23) | ||
66 | #define PMU_FALCON_REG_CSW (24) | ||
67 | #define PMU_FALCON_REG_CCR (25) | ||
68 | #define PMU_FALCON_REG_SEC (26) | ||
69 | #define PMU_FALCON_REG_CTX (27) | ||
70 | #define PMU_FALCON_REG_EXCI (28) | ||
71 | #define PMU_FALCON_REG_RSVD0 (29) | ||
72 | #define PMU_FALCON_REG_RSVD1 (30) | ||
73 | #define PMU_FALCON_REG_RSVD2 (31) | ||
74 | #define PMU_FALCON_REG_SIZE (32) | ||
75 | |||
76 | /* Choices for pmu_state */ | ||
77 | #define PMU_STATE_OFF 0 /* PMU is off */ | ||
78 | #define PMU_STATE_STARTING 1 /* PMU is on, but not booted */ | ||
79 | #define PMU_STATE_INIT_RECEIVED 2 /* PMU init message received */ | ||
80 | #define PMU_STATE_ELPG_BOOTING 3 /* PMU is booting */ | ||
81 | #define PMU_STATE_ELPG_BOOTED 4 /* ELPG is initialized */ | ||
82 | #define PMU_STATE_LOADING_PG_BUF 5 /* Loading PG buf */ | ||
83 | #define PMU_STATE_LOADING_ZBC 6 /* Loading ZBC buf */ | ||
84 | #define PMU_STATE_STARTED 7 /* Fully unitialized */ | ||
85 | #define PMU_STATE_EXIT 8 /* Exit PMU state machine */ | ||
86 | |||
87 | #define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32 | ||
88 | #define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64 | ||
89 | |||
90 | #define PMU_MAX_NUM_SEQUENCES (256) | ||
91 | #define PMU_SEQ_BIT_SHIFT (5) | ||
92 | #define PMU_SEQ_TBL_SIZE \ | ||
93 | (PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT) | ||
94 | |||
95 | #define PMU_INVALID_SEQ_DESC (~0) | ||
96 | |||
97 | enum { | ||
98 | GK20A_PMU_DMAIDX_UCODE = 0, | ||
99 | GK20A_PMU_DMAIDX_VIRT = 1, | ||
100 | GK20A_PMU_DMAIDX_PHYS_VID = 2, | ||
101 | GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3, | ||
102 | GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4, | ||
103 | GK20A_PMU_DMAIDX_RSVD = 5, | ||
104 | GK20A_PMU_DMAIDX_PELPG = 6, | ||
105 | GK20A_PMU_DMAIDX_END = 7 | ||
106 | }; | ||
107 | |||
108 | enum { | ||
109 | PMU_SEQ_STATE_FREE = 0, | ||
110 | PMU_SEQ_STATE_PENDING, | ||
111 | PMU_SEQ_STATE_USED, | ||
112 | PMU_SEQ_STATE_CANCELLED | ||
113 | }; | ||
114 | |||
115 | typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32, | ||
116 | u32); | ||
117 | |||
118 | struct pmu_ucode_desc { | ||
119 | u32 descriptor_size; | ||
120 | u32 image_size; | ||
121 | u32 tools_version; | ||
122 | u32 app_version; | ||
123 | char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH]; | ||
124 | u32 bootloader_start_offset; | ||
125 | u32 bootloader_size; | ||
126 | u32 bootloader_imem_offset; | ||
127 | u32 bootloader_entry_point; | ||
128 | u32 app_start_offset; | ||
129 | u32 app_size; | ||
130 | u32 app_imem_offset; | ||
131 | u32 app_imem_entry; | ||
132 | u32 app_dmem_offset; | ||
133 | /* Offset from appStartOffset */ | ||
134 | u32 app_resident_code_offset; | ||
135 | /* Exact size of the resident code | ||
136 | * ( potentially contains CRC inside at the end ) | ||
137 | */ | ||
138 | u32 app_resident_code_size; | ||
139 | /* Offset from appStartOffset */ | ||
140 | u32 app_resident_data_offset; | ||
141 | /* Exact size of the resident code | ||
142 | * ( potentially contains CRC inside at the end ) | ||
143 | */ | ||
144 | u32 app_resident_data_size; | ||
145 | u32 nb_overlays; | ||
146 | struct {u32 start; u32 size; } load_ovl[GK20A_PMU_UCODE_NB_MAX_OVERLAY]; | ||
147 | u32 compressed; | ||
148 | }; | ||
149 | |||
150 | struct pmu_ucode_desc_v1 { | ||
151 | u32 descriptor_size; | ||
152 | u32 image_size; | ||
153 | u32 tools_version; | ||
154 | u32 app_version; | ||
155 | char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH]; | ||
156 | u32 bootloader_start_offset; | ||
157 | u32 bootloader_size; | ||
158 | u32 bootloader_imem_offset; | ||
159 | u32 bootloader_entry_point; | ||
160 | u32 app_start_offset; | ||
161 | u32 app_size; | ||
162 | u32 app_imem_offset; | ||
163 | u32 app_imem_entry; | ||
164 | u32 app_dmem_offset; | ||
165 | u32 app_resident_code_offset; | ||
166 | u32 app_resident_code_size; | ||
167 | u32 app_resident_data_offset; | ||
168 | u32 app_resident_data_size; | ||
169 | u32 nb_imem_overlays; | ||
170 | u32 nb_dmem_overlays; | ||
171 | struct {u32 start; u32 size; } load_ovl[64]; | ||
172 | u32 compressed; | ||
173 | }; | ||
174 | |||
175 | struct pmu_queue { | ||
176 | |||
177 | /* used by hw, for BIOS/SMI queue */ | ||
178 | u32 mutex_id; | ||
179 | u32 mutex_lock; | ||
180 | /* used by sw, for LPQ/HPQ queue */ | ||
181 | struct nvgpu_mutex mutex; | ||
182 | |||
183 | /* current write position */ | ||
184 | u32 position; | ||
185 | /* physical dmem offset where this queue begins */ | ||
186 | u32 offset; | ||
187 | /* logical queue identifier */ | ||
188 | u32 id; | ||
189 | /* physical queue index */ | ||
190 | u32 index; | ||
191 | /* in bytes */ | ||
192 | u32 size; | ||
193 | |||
194 | /* open-flag */ | ||
195 | u32 oflag; | ||
196 | bool opened; /* opened implies locked */ | ||
197 | }; | ||
198 | |||
199 | struct pmu_mutex { | ||
200 | u32 id; | ||
201 | u32 index; | ||
202 | u32 ref_cnt; | ||
203 | }; | ||
204 | |||
205 | struct pmu_sequence { | ||
206 | u8 id; | ||
207 | u32 state; | ||
208 | u32 desc; | ||
209 | struct pmu_msg *msg; | ||
210 | union { | ||
211 | struct pmu_allocation_v0 in_v0; | ||
212 | struct pmu_allocation_v1 in_v1; | ||
213 | struct pmu_allocation_v2 in_v2; | ||
214 | struct pmu_allocation_v3 in_v3; | ||
215 | }; | ||
216 | struct nvgpu_mem *in_mem; | ||
217 | union { | ||
218 | struct pmu_allocation_v0 out_v0; | ||
219 | struct pmu_allocation_v1 out_v1; | ||
220 | struct pmu_allocation_v2 out_v2; | ||
221 | struct pmu_allocation_v3 out_v3; | ||
222 | }; | ||
223 | struct nvgpu_mem *out_mem; | ||
224 | u8 *out_payload; | ||
225 | pmu_callback callback; | ||
226 | void *cb_params; | ||
227 | }; | ||
228 | |||
229 | struct nvgpu_pg_init { | ||
230 | bool state_change; | ||
231 | struct nvgpu_cond wq; | ||
232 | struct nvgpu_thread state_task; | ||
233 | }; | ||
234 | |||
235 | struct nvgpu_pmu { | ||
236 | struct gk20a *g; | ||
237 | struct nvgpu_falcon *flcn; | ||
238 | |||
239 | union { | ||
240 | struct pmu_ucode_desc *desc; | ||
241 | struct pmu_ucode_desc_v1 *desc_v1; | ||
242 | }; | ||
243 | struct nvgpu_mem ucode; | ||
244 | |||
245 | struct nvgpu_mem pg_buf; | ||
246 | |||
247 | /* TBD: remove this if ZBC seq is fixed */ | ||
248 | struct nvgpu_mem seq_buf; | ||
249 | struct nvgpu_mem trace_buf; | ||
250 | struct nvgpu_mem wpr_buf; | ||
251 | bool buf_loaded; | ||
252 | |||
253 | struct pmu_sha1_gid gid_info; | ||
254 | |||
255 | struct pmu_queue queue[PMU_QUEUE_COUNT]; | ||
256 | |||
257 | struct pmu_sequence *seq; | ||
258 | unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE]; | ||
259 | u32 next_seq_desc; | ||
260 | |||
261 | struct pmu_mutex *mutex; | ||
262 | u32 mutex_cnt; | ||
263 | |||
264 | struct nvgpu_mutex pmu_copy_lock; | ||
265 | struct nvgpu_mutex pmu_seq_lock; | ||
266 | |||
267 | struct nvgpu_allocator dmem; | ||
268 | |||
269 | u32 *ucode_image; | ||
270 | bool pmu_ready; | ||
271 | |||
272 | u32 zbc_save_done; | ||
273 | |||
274 | u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; | ||
275 | |||
276 | u32 elpg_stat; | ||
277 | |||
278 | u32 mscg_stat; | ||
279 | u32 mscg_transition_state; | ||
280 | |||
281 | int pmu_state; | ||
282 | |||
283 | #define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1 /* msec */ | ||
284 | struct nvgpu_pg_init pg_init; | ||
285 | struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */ | ||
286 | struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */ | ||
287 | /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */ | ||
288 | int elpg_refcnt; | ||
289 | |||
290 | union { | ||
291 | struct pmu_perfmon_counter_v2 perfmon_counter_v2; | ||
292 | struct pmu_perfmon_counter_v0 perfmon_counter_v0; | ||
293 | }; | ||
294 | u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM]; | ||
295 | |||
296 | bool initialized; | ||
297 | |||
298 | void (*remove_support)(struct nvgpu_pmu *pmu); | ||
299 | bool sw_ready; | ||
300 | bool perfmon_ready; | ||
301 | |||
302 | u32 sample_buffer; | ||
303 | u32 load_shadow; | ||
304 | u32 load_avg; | ||
305 | |||
306 | struct nvgpu_mutex isr_mutex; | ||
307 | bool isr_enabled; | ||
308 | |||
309 | bool zbc_ready; | ||
310 | union { | ||
311 | struct pmu_cmdline_args_v0 args_v0; | ||
312 | struct pmu_cmdline_args_v1 args_v1; | ||
313 | struct pmu_cmdline_args_v2 args_v2; | ||
314 | struct pmu_cmdline_args_v3 args_v3; | ||
315 | struct pmu_cmdline_args_v4 args_v4; | ||
316 | struct pmu_cmdline_args_v5 args_v5; | ||
317 | }; | ||
318 | unsigned long perfmon_events_cnt; | ||
319 | bool perfmon_sampling_enabled; | ||
320 | u8 pmu_mode; /*Added for GM20b, and ACR*/ | ||
321 | u32 falcon_id; | ||
322 | u32 aelpg_param[5]; | ||
323 | u32 override_done; | ||
324 | |||
325 | struct nvgpu_firmware *fw; | ||
326 | }; | ||
327 | |||
328 | #endif /* __NVGPU_PMU_H__ */ | ||