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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/bios.h9
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h14
2 files changed, 21 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index eec057f2..0619fcb9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -137,6 +137,9 @@ struct vin_descriptor_entry_10 {
137#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 137#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7
138#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 138#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0
139 139
140#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_MASK 0xF0
141#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_SHIFT 4
142
140#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 143#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8
141#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 144#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3
142 145
@@ -152,6 +155,12 @@ struct vin_descriptor_entry_10 {
152#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 155#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000
153#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 156#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18
154 157
158#define NV_VIN_DESC_VIN_CAL_OFFSET_MASK 0x7F
159#define NV_VIN_DESC_VIN_CAL_OFFSET_SHIFT 0
160
161#define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80
162#define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7
163
155#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07 164#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07
156struct vbios_clocks_table_1x_header { 165struct vbios_clocks_table_1x_header {
157 u8 version; 166 u8 version;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
index 63bce913..e0a3313b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
@@ -251,14 +251,24 @@ struct nv_pmu_clk_clk_vin_device_boardobj_set {
251 struct nv_pmu_boardobj super; 251 struct nv_pmu_boardobj super;
252 u8 id; 252 u8 id;
253 u8 volt_domain; 253 u8 volt_domain;
254 u32 slope;
255 u32 intercept;
256 u32 flls_shared_mask; 254 u32 flls_shared_mask;
257}; 255};
258 256
257struct nv_pmu_clk_clk_vin_device_v10_boardobj_set {
258 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
259 struct ctrl_clk_vin_device_info_data_v10 data;
260};
261
262struct nv_pmu_clk_clk_vin_device_v20_boardobj_set {
263 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
264 struct ctrl_clk_vin_device_info_data_v20 data;
265};
266
259union nv_pmu_clk_clk_vin_device_boardobj_set_union { 267union nv_pmu_clk_clk_vin_device_boardobj_set_union {
260 struct nv_pmu_boardobj board_obj; 268 struct nv_pmu_boardobj board_obj;
261 struct nv_pmu_clk_clk_vin_device_boardobj_set super; 269 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
270 struct nv_pmu_clk_clk_vin_device_v10_boardobj_set v10;
271 struct nv_pmu_clk_clk_vin_device_v20_boardobj_set v20;
262}; 272};
263 273
264NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device); 274NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device);