2 files changed, 17 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
index 6abb5e33..e33dce94 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
@@ -123,6 +123,8 @@ enum {
         TEGRA_VGPU_CMD_RESUME = 83,
         TEGRA_VGPU_CMD_GET_ECC_INFO = 84,
         TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85,
+        TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE = 88,
+        TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE = 89,
 };
 
 struct tegra_vgpu_connect_params {
@@ -617,6 +619,15 @@ struct tegra_vgpu_tsg_bind_channel_ex_params {
         u32 runqueue_sel;
 };
 
+struct tegra_vgpu_fb_set_mmu_debug_mode_params {
+        u8 enable;
+};
+
+struct tegra_vgpu_gr_set_mmu_debug_mode_params {
+        u64 ch_handle;
+        u8 enable;
+};
+
 struct tegra_vgpu_cmd_msg {
         u32 cmd;
         int ret;
@@ -679,6 +690,8 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling;
                 struct tegra_vgpu_ecc_info_params ecc_info;
                 struct tegra_vgpu_ecc_counter_params ecc_counter;
+                struct tegra_vgpu_fb_set_mmu_debug_mode_params fb_set_mmu_debug_mode;
+                struct tegra_vgpu_gr_set_mmu_debug_mode_params gr_set_mmu_debug_mode;
                 char padding[192];
         } params;
 };
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h
index 15ab879e..ecdb8964 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,6 +39,7 @@ struct vm_gk20a;
 struct nvgpu_gr_ctx;
 struct nvgpu_cpu_time_correlation_sample;
 struct vgpu_ecc_stat;
+struct channel_gk20a;
 
 struct vgpu_priv_data {
         u64 virt_handle;
@@ -104,4 +105,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g);
 
 bool vgpu_is_reduced_bar1(struct gk20a *g);
 
+int vgpu_gr_set_mmu_debug_mode(struct gk20a *g,
+                        struct channel_gk20a *ch, bool enable);
 #endif