diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h new file mode 100644 index 00000000..1e608d96 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h | |||
@@ -0,0 +1,110 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __VGPU_COMMON_H__ | ||
24 | #define __VGPU_COMMON_H__ | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | #include <nvgpu/thread.h> | ||
28 | #include <nvgpu/log.h> | ||
29 | #include <nvgpu/vgpu/tegra_vgpu.h> | ||
30 | |||
31 | struct device; | ||
32 | struct tegra_vgpu_gr_intr_info; | ||
33 | struct tegra_vgpu_fifo_intr_info; | ||
34 | struct tegra_vgpu_cmd_msg; | ||
35 | struct nvgpu_mem; | ||
36 | struct gk20a; | ||
37 | struct vm_gk20a; | ||
38 | struct nvgpu_gr_ctx; | ||
39 | struct nvgpu_cpu_time_correlation_sample; | ||
40 | |||
41 | struct vgpu_priv_data { | ||
42 | u64 virt_handle; | ||
43 | struct nvgpu_thread intr_handler; | ||
44 | struct tegra_vgpu_constants_params constants; | ||
45 | }; | ||
46 | |||
47 | struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g); | ||
48 | |||
49 | static inline u64 vgpu_get_handle(struct gk20a *g) | ||
50 | { | ||
51 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
52 | |||
53 | if (unlikely(!priv)) { | ||
54 | nvgpu_err(g, "invalid vgpu_priv_data in %s", __func__); | ||
55 | return INT_MAX; | ||
56 | } | ||
57 | |||
58 | return priv->virt_handle; | ||
59 | } | ||
60 | |||
61 | int vgpu_comm_init(struct gk20a *g); | ||
62 | void vgpu_comm_deinit(void); | ||
63 | int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | ||
64 | size_t size_out); | ||
65 | u64 vgpu_connect(void); | ||
66 | int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); | ||
67 | int vgpu_intr_thread(void *dev_id); | ||
68 | void vgpu_remove_support_common(struct gk20a *g); | ||
69 | void vgpu_detect_chip(struct gk20a *g); | ||
70 | int vgpu_init_gpu_characteristics(struct gk20a *g); | ||
71 | int vgpu_read_ptimer(struct gk20a *g, u64 *value); | ||
72 | int vgpu_get_timestamps_zipper(struct gk20a *g, | ||
73 | u32 source_id, u32 count, | ||
74 | struct nvgpu_cpu_time_correlation_sample *samples); | ||
75 | int vgpu_init_hal(struct gk20a *g); | ||
76 | int vgpu_get_constants(struct gk20a *g); | ||
77 | u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem); | ||
78 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | ||
79 | int vgpu_gr_nonstall_isr(struct gk20a *g, | ||
80 | struct tegra_vgpu_gr_nonstall_intr_info *info); | ||
81 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
82 | struct nvgpu_gr_ctx *gr_ctx, | ||
83 | struct vm_gk20a *vm, | ||
84 | u32 class, | ||
85 | u32 flags); | ||
86 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
87 | struct nvgpu_gr_ctx *gr_ctx); | ||
88 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | ||
89 | struct tegra_vgpu_sm_esr_info *info); | ||
90 | int vgpu_gr_init_ctx_state(struct gk20a *g); | ||
91 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); | ||
92 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | ||
93 | struct tegra_vgpu_fifo_nonstall_intr_info *info); | ||
94 | int vgpu_ce2_nonstall_isr(struct gk20a *g, | ||
95 | struct tegra_vgpu_ce2_nonstall_intr_info *info); | ||
96 | u32 vgpu_ce_get_num_pce(struct gk20a *g); | ||
97 | int vgpu_init_mm_support(struct gk20a *g); | ||
98 | int vgpu_init_gr_support(struct gk20a *g); | ||
99 | int vgpu_init_fifo_support(struct gk20a *g); | ||
100 | |||
101 | int vgpu_gp10b_init_hal(struct gk20a *g); | ||
102 | int vgpu_gv11b_init_hal(struct gk20a *g); | ||
103 | |||
104 | int vgpu_read_ptimer(struct gk20a *g, u64 *value); | ||
105 | int vgpu_get_timestamps_zipper(struct gk20a *g, | ||
106 | u32 source_id, u32 count, | ||
107 | struct nvgpu_cpu_time_correlation_sample *samples); | ||
108 | bool vgpu_is_reduced_bar1(struct gk20a *g); | ||
109 | |||
110 | #endif | ||