diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h (renamed from drivers/gpu/nvgpu/include/bios.h) | 66 |
1 files changed, 60 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index bcb24343..c6465313 100644 --- a/drivers/gpu/nvgpu/include/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -1,7 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * vbios tables support | 2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | ||
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | 3 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -13,10 +11,58 @@ | |||
13 | * more details. | 11 | * more details. |
14 | */ | 12 | */ |
15 | 13 | ||
16 | #ifndef NVGPU_INCLUDE_BIOS_H | 14 | #ifndef NVGPU_BIOS_H |
17 | #define NVGPU_INCLUDE_BIOS_H | 15 | #define NVGPU_BIOS_H |
16 | |||
17 | #include <linux/types.h> | ||
18 | |||
19 | struct gk20a; | ||
20 | |||
21 | #define PERF_PTRS_WIDTH 0x4 | ||
22 | #define PERF_PTRS_WIDTH_16 0x2 | ||
23 | |||
24 | enum { | ||
25 | CLOCKS_TABLE = 2, | ||
26 | CLOCK_PROGRAMMING_TABLE, | ||
27 | FLL_TABLE, | ||
28 | VIN_TABLE, | ||
29 | FREQUENCY_CONTROLLER_TABLE | ||
30 | }; | ||
18 | 31 | ||
19 | #include "gk20a/gk20a.h" | 32 | enum { |
33 | PERFORMANCE_TABLE = 0, | ||
34 | MEMORY_CLOCK_TABLE, | ||
35 | MEMORY_TWEAK_TABLE, | ||
36 | POWER_CONTROL_TABLE, | ||
37 | THERMAL_CONTROL_TABLE, | ||
38 | THERMAL_DEVICE_TABLE, | ||
39 | THERMAL_COOLERS_TABLE, | ||
40 | PERFORMANCE_SETTINGS_SCRIPT, | ||
41 | CONTINUOUS_VIRTUAL_BINNING_TABLE, | ||
42 | POWER_SENSORS_TABLE = 0xA, | ||
43 | POWER_CAPPING_TABLE = 0xB, | ||
44 | POWER_TOPOLOGY_TABLE = 0xF, | ||
45 | THERMAL_CHANNEL_TABLE = 0x12, | ||
46 | VOLTAGE_RAIL_TABLE = 26, | ||
47 | VOLTAGE_DEVICE_TABLE, | ||
48 | VOLTAGE_POLICY_TABLE, | ||
49 | LOWPOWER_TABLE, | ||
50 | LOWPOWER_GR_TABLE = 32, | ||
51 | LOWPOWER_MS_TABLE = 33, | ||
52 | }; | ||
53 | |||
54 | enum { | ||
55 | VP_FIELD_TABLE = 0, | ||
56 | VP_FIELD_REGISTER, | ||
57 | VP_TRANSLATION_TABLE, | ||
58 | }; | ||
59 | |||
60 | struct bit_token { | ||
61 | u8 token_id; | ||
62 | u8 data_version; | ||
63 | u16 data_size; | ||
64 | u16 data_ptr; | ||
65 | } __packed; | ||
20 | 66 | ||
21 | #define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) | 67 | #define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) |
22 | 68 | ||
@@ -988,5 +1034,13 @@ struct nvgpu_bios_lpwr_gr_table_1x_entry { | |||
988 | 1034 | ||
989 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) | 1035 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) |
990 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 | 1036 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 |
1037 | int nvgpu_bios_parse_rom(struct gk20a *g); | ||
1038 | u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset); | ||
1039 | s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset); | ||
1040 | u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset); | ||
1041 | u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset); | ||
1042 | void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g, | ||
1043 | struct bit_token *ptoken, u8 table_id); | ||
1044 | int nvgpu_bios_execute_script(struct gk20a *g, u32 offset); | ||
991 | 1045 | ||
992 | #endif | 1046 | #endif |