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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
index f34fc5e7..4e6f2cd1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
@@ -117,6 +117,7 @@ enum {
117 TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78, 117 TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78,
118 TEGRA_VGPU_CMD_MAP_SYNCPT = 79, 118 TEGRA_VGPU_CMD_MAP_SYNCPT = 79,
119 TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80, 119 TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80,
120 TEGRA_VGPU_CMD_UPDATE_PC_SAMPLING = 81,
120}; 121};
121 122
122struct tegra_vgpu_connect_params { 123struct tegra_vgpu_connect_params {
@@ -354,12 +355,21 @@ enum {
354 TEGRA_VGPU_CTXSW_MODE_CTXSW, 355 TEGRA_VGPU_CTXSW_MODE_CTXSW,
355}; 356};
356 357
358enum {
359 TEGRA_VGPU_DISABLE_SAMPLING = 0,
360 TEGRA_VGPU_ENABLE_SAMPLING,
361};
357struct tegra_vgpu_channel_set_ctxsw_mode { 362struct tegra_vgpu_channel_set_ctxsw_mode {
358 u64 handle; 363 u64 handle;
359 u64 gpu_va; 364 u64 gpu_va;
360 u32 mode; 365 u32 mode;
361}; 366};
362 367
368struct tegra_vgpu_channel_update_pc_sampling {
369 u64 handle;
370 u32 mode;
371};
372
363struct tegra_vgpu_channel_free_hwpm_ctx { 373struct tegra_vgpu_channel_free_hwpm_ctx {
364 u64 handle; 374 u64 handle;
365}; 375};
@@ -638,6 +648,7 @@ struct tegra_vgpu_cmd_msg {
638 struct tegra_vgpu_free_ctx_header_params free_ctx_header; 648 struct tegra_vgpu_free_ctx_header_params free_ctx_header;
639 struct tegra_vgpu_map_syncpt_params map_syncpt; 649 struct tegra_vgpu_map_syncpt_params map_syncpt;
640 struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex; 650 struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex;
651 struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling;
641 char padding[192]; 652 char padding[192];
642 } params; 653 } params;
643}; 654};