diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 410 |
2 files changed, 416 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index ad5b3db3..4f31e3e2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -46,6 +46,15 @@ struct gk20a; | |||
46 | #define NVGPU_ECC_ENABLED_TEX 10 | 46 | #define NVGPU_ECC_ENABLED_TEX 10 |
47 | /* L2 ECC is enabled */ | 47 | /* L2 ECC is enabled */ |
48 | #define NVGPU_ECC_ENABLED_LTC 11 | 48 | #define NVGPU_ECC_ENABLED_LTC 11 |
49 | /* SM L1 DATA ECC is enabled */ | ||
50 | #define NVGPU_ECC_ENABLED_SM_L1_DATA 12 | ||
51 | /* SM L1 TAG ECC is enabled */ | ||
52 | #define NVGPU_ECC_ENABLED_SM_L1_TAG 13 | ||
53 | /* SM CBU ECC is enabled */ | ||
54 | #define NVGPU_ECC_ENABLED_SM_CBU 14 | ||
55 | /* SM ICAHE ECC is enabled */ | ||
56 | #define NVGPU_ECC_ENABLED_SM_ICACHE 15 | ||
57 | |||
49 | /* | 58 | /* |
50 | * MM flags. | 59 | * MM flags. |
51 | */ | 60 | */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 805d8b0e..29999163 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -916,6 +916,366 @@ static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 | |||
916 | { | 916 | { |
917 | return (r >> 0U) & 0xffffU; | 917 | return (r >> 0U) & 0xffffU; |
918 | } | 918 | } |
919 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r(void) | ||
920 | { | ||
921 | return 0x00419b54U; | ||
922 | } | ||
923 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) | ||
924 | { | ||
925 | return (v & 0x1U) << 0U; | ||
926 | } | ||
927 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f(void) | ||
928 | { | ||
929 | return 0x1U; | ||
930 | } | ||
931 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) | ||
932 | { | ||
933 | return (v & 0x1U) << 1U; | ||
934 | } | ||
935 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f(void) | ||
936 | { | ||
937 | return 0x2U; | ||
938 | } | ||
939 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) | ||
940 | { | ||
941 | return (v & 0x1U) << 2U; | ||
942 | } | ||
943 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f(void) | ||
944 | { | ||
945 | return 0x4U; | ||
946 | } | ||
947 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) | ||
948 | { | ||
949 | return (v & 0x1U) << 3U; | ||
950 | } | ||
951 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f(void) | ||
952 | { | ||
953 | return 0x8U; | ||
954 | } | ||
955 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) | ||
956 | { | ||
957 | return (v & 0x1U) << 4U; | ||
958 | } | ||
959 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_task_f(void) | ||
960 | { | ||
961 | return 0x10U; | ||
962 | } | ||
963 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) | ||
964 | { | ||
965 | return (v & 0x1U) << 5U; | ||
966 | } | ||
967 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_task_f(void) | ||
968 | { | ||
969 | return 0x20U; | ||
970 | } | ||
971 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) | ||
972 | { | ||
973 | return (v & 0x1U) << 6U; | ||
974 | } | ||
975 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_task_f(void) | ||
976 | { | ||
977 | return 0x40U; | ||
978 | } | ||
979 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) | ||
980 | { | ||
981 | return (v & 0x1U) << 7U; | ||
982 | } | ||
983 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_task_f(void) | ||
984 | { | ||
985 | return 0x80U; | ||
986 | } | ||
987 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r(void) | ||
988 | { | ||
989 | return 0x00504354U; | ||
990 | } | ||
991 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) | ||
992 | { | ||
993 | return (v & 0x1U) << 0U; | ||
994 | } | ||
995 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f(void) | ||
996 | { | ||
997 | return 0x0U; | ||
998 | } | ||
999 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) | ||
1000 | { | ||
1001 | return (v & 0x1U) << 1U; | ||
1002 | } | ||
1003 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f(void) | ||
1004 | { | ||
1005 | return 0x0U; | ||
1006 | } | ||
1007 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) | ||
1008 | { | ||
1009 | return (v & 0x1U) << 2U; | ||
1010 | } | ||
1011 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f(void) | ||
1012 | { | ||
1013 | return 0x0U; | ||
1014 | } | ||
1015 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) | ||
1016 | { | ||
1017 | return (v & 0x1U) << 3U; | ||
1018 | } | ||
1019 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f(void) | ||
1020 | { | ||
1021 | return 0x0U; | ||
1022 | } | ||
1023 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) | ||
1024 | { | ||
1025 | return (v & 0x1U) << 4U; | ||
1026 | } | ||
1027 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_init_f(void) | ||
1028 | { | ||
1029 | return 0x0U; | ||
1030 | } | ||
1031 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) | ||
1032 | { | ||
1033 | return (v & 0x1U) << 5U; | ||
1034 | } | ||
1035 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_init_f(void) | ||
1036 | { | ||
1037 | return 0x0U; | ||
1038 | } | ||
1039 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) | ||
1040 | { | ||
1041 | return (v & 0x1U) << 6U; | ||
1042 | } | ||
1043 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_init_f(void) | ||
1044 | { | ||
1045 | return 0x0U; | ||
1046 | } | ||
1047 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) | ||
1048 | { | ||
1049 | return (v & 0x1U) << 7U; | ||
1050 | } | ||
1051 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_init_f(void) | ||
1052 | { | ||
1053 | return 0x0U; | ||
1054 | } | ||
1055 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r(void) | ||
1056 | { | ||
1057 | return 0x00419b68U; | ||
1058 | } | ||
1059 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) | ||
1060 | { | ||
1061 | return (v & 0x1U) << 0U; | ||
1062 | } | ||
1063 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f(void) | ||
1064 | { | ||
1065 | return 0x1U; | ||
1066 | } | ||
1067 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) | ||
1068 | { | ||
1069 | return (v & 0x1U) << 1U; | ||
1070 | } | ||
1071 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_task_f(void) | ||
1072 | { | ||
1073 | return 0x2U; | ||
1074 | } | ||
1075 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r(void) | ||
1076 | { | ||
1077 | return 0x00504368U; | ||
1078 | } | ||
1079 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) | ||
1080 | { | ||
1081 | return (v & 0x1U) << 0U; | ||
1082 | } | ||
1083 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f(void) | ||
1084 | { | ||
1085 | return 0x0U; | ||
1086 | } | ||
1087 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) | ||
1088 | { | ||
1089 | return (v & 0x1U) << 1U; | ||
1090 | } | ||
1091 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_init_f(void) | ||
1092 | { | ||
1093 | return 0x0U; | ||
1094 | } | ||
1095 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r(void) | ||
1096 | { | ||
1097 | return 0x00419e20U; | ||
1098 | } | ||
1099 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) | ||
1100 | { | ||
1101 | return (v & 0x1U) << 0U; | ||
1102 | } | ||
1103 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f(void) | ||
1104 | { | ||
1105 | return 0x1U; | ||
1106 | } | ||
1107 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) | ||
1108 | { | ||
1109 | return (v & 0x1U) << 1U; | ||
1110 | } | ||
1111 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f(void) | ||
1112 | { | ||
1113 | return 0x2U; | ||
1114 | } | ||
1115 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r(void) | ||
1116 | { | ||
1117 | return 0x00504620U; | ||
1118 | } | ||
1119 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) | ||
1120 | { | ||
1121 | return (v & 0x1U) << 0U; | ||
1122 | } | ||
1123 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f(void) | ||
1124 | { | ||
1125 | return 0x0U; | ||
1126 | } | ||
1127 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) | ||
1128 | { | ||
1129 | return (v & 0x1U) << 1U; | ||
1130 | } | ||
1131 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f(void) | ||
1132 | { | ||
1133 | return 0x0U; | ||
1134 | } | ||
1135 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r(void) | ||
1136 | { | ||
1137 | return 0x00419e34U; | ||
1138 | } | ||
1139 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) | ||
1140 | { | ||
1141 | return (v & 0x1U) << 0U; | ||
1142 | } | ||
1143 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f(void) | ||
1144 | { | ||
1145 | return 0x1U; | ||
1146 | } | ||
1147 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) | ||
1148 | { | ||
1149 | return (v & 0x1U) << 1U; | ||
1150 | } | ||
1151 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_task_f(void) | ||
1152 | { | ||
1153 | return 0x2U; | ||
1154 | } | ||
1155 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) | ||
1156 | { | ||
1157 | return (v & 0x1U) << 2U; | ||
1158 | } | ||
1159 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f(void) | ||
1160 | { | ||
1161 | return 0x4U; | ||
1162 | } | ||
1163 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) | ||
1164 | { | ||
1165 | return (v & 0x1U) << 3U; | ||
1166 | } | ||
1167 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_task_f(void) | ||
1168 | { | ||
1169 | return 0x8U; | ||
1170 | } | ||
1171 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r(void) | ||
1172 | { | ||
1173 | return 0x00504634U; | ||
1174 | } | ||
1175 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) | ||
1176 | { | ||
1177 | return (v & 0x1U) << 0U; | ||
1178 | } | ||
1179 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f(void) | ||
1180 | { | ||
1181 | return 0x0U; | ||
1182 | } | ||
1183 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) | ||
1184 | { | ||
1185 | return (v & 0x1U) << 1U; | ||
1186 | } | ||
1187 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_init_f(void) | ||
1188 | { | ||
1189 | return 0x0U; | ||
1190 | } | ||
1191 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) | ||
1192 | { | ||
1193 | return (v & 0x1U) << 2U; | ||
1194 | } | ||
1195 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f(void) | ||
1196 | { | ||
1197 | return 0x0U; | ||
1198 | } | ||
1199 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) | ||
1200 | { | ||
1201 | return (v & 0x1U) << 3U; | ||
1202 | } | ||
1203 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_init_f(void) | ||
1204 | { | ||
1205 | return 0x0U; | ||
1206 | } | ||
1207 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_r(void) | ||
1208 | { | ||
1209 | return 0x00419e48U; | ||
1210 | } | ||
1211 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_f(u32 v) | ||
1212 | { | ||
1213 | return (v & 0x1U) << 0U; | ||
1214 | } | ||
1215 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_task_f(void) | ||
1216 | { | ||
1217 | return 0x1U; | ||
1218 | } | ||
1219 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) | ||
1220 | { | ||
1221 | return (v & 0x1U) << 1U; | ||
1222 | } | ||
1223 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_task_f(void) | ||
1224 | { | ||
1225 | return 0x2U; | ||
1226 | } | ||
1227 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_f(u32 v) | ||
1228 | { | ||
1229 | return (v & 0x1U) << 2U; | ||
1230 | } | ||
1231 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f(void) | ||
1232 | { | ||
1233 | return 0x4U; | ||
1234 | } | ||
1235 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) | ||
1236 | { | ||
1237 | return (v & 0x1U) << 3U; | ||
1238 | } | ||
1239 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_task_f(void) | ||
1240 | { | ||
1241 | return 0x8U; | ||
1242 | } | ||
1243 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_r(void) | ||
1244 | { | ||
1245 | return 0x00504648U; | ||
1246 | } | ||
1247 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_f(u32 v) | ||
1248 | { | ||
1249 | return (v & 0x1U) << 0U; | ||
1250 | } | ||
1251 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_init_f(void) | ||
1252 | { | ||
1253 | return 0x0U; | ||
1254 | } | ||
1255 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) | ||
1256 | { | ||
1257 | return (v & 0x1U) << 1U; | ||
1258 | } | ||
1259 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_init_f(void) | ||
1260 | { | ||
1261 | return 0x0U; | ||
1262 | } | ||
1263 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_f(u32 v) | ||
1264 | { | ||
1265 | return (v & 0x1U) << 2U; | ||
1266 | } | ||
1267 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f(void) | ||
1268 | { | ||
1269 | return 0x0U; | ||
1270 | } | ||
1271 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) | ||
1272 | { | ||
1273 | return (v & 0x1U) << 3U; | ||
1274 | } | ||
1275 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_init_f(void) | ||
1276 | { | ||
1277 | return 0x0U; | ||
1278 | } | ||
919 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) | 1279 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) |
920 | { | 1280 | { |
921 | return 0x005042c4U; | 1281 | return 0x005042c4U; |
@@ -1920,21 +2280,65 @@ static inline u32 gr_fecs_feature_override_ecc_r(void) | |||
1920 | { | 2280 | { |
1921 | return 0x00409658U; | 2281 | return 0x00409658U; |
1922 | } | 2282 | } |
2283 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) | ||
2284 | { | ||
2285 | return (r >> 0U) & 0x1U; | ||
2286 | } | ||
1923 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) | 2287 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) |
1924 | { | 2288 | { |
1925 | return (r >> 3U) & 0x1U; | 2289 | return (r >> 3U) & 0x1U; |
1926 | } | 2290 | } |
2291 | static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_v(u32 r) | ||
2292 | { | ||
2293 | return (r >> 4U) & 0x1U; | ||
2294 | } | ||
2295 | static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_override_v(u32 r) | ||
2296 | { | ||
2297 | return (r >> 7U) & 0x1U; | ||
2298 | } | ||
2299 | static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_v(u32 r) | ||
2300 | { | ||
2301 | return (r >> 8U) & 0x1U; | ||
2302 | } | ||
2303 | static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_override_v(u32 r) | ||
2304 | { | ||
2305 | return (r >> 11U) & 0x1U; | ||
2306 | } | ||
2307 | static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) | ||
2308 | { | ||
2309 | return (r >> 12U) & 0x1U; | ||
2310 | } | ||
1927 | static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) | 2311 | static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) |
1928 | { | 2312 | { |
1929 | return (r >> 15U) & 0x1U; | 2313 | return (r >> 15U) & 0x1U; |
1930 | } | 2314 | } |
1931 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) | 2315 | static inline u32 gr_fecs_feature_override_ecc_sm_cbu_v(u32 r) |
2316 | { | ||
2317 | return (r >> 20U) & 0x1U; | ||
2318 | } | ||
2319 | static inline u32 gr_fecs_feature_override_ecc_sm_cbu_override_v(u32 r) | ||
2320 | { | ||
2321 | return (r >> 23U) & 0x1U; | ||
2322 | } | ||
2323 | static inline u32 gr_fecs_feature_override_ecc_1_r(void) | ||
2324 | { | ||
2325 | return 0x0040965cU; | ||
2326 | } | ||
2327 | static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_v(u32 r) | ||
1932 | { | 2328 | { |
1933 | return (r >> 0U) & 0x1U; | 2329 | return (r >> 0U) & 0x1U; |
1934 | } | 2330 | } |
1935 | static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) | 2331 | static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(u32 r) |
1936 | { | 2332 | { |
1937 | return (r >> 12U) & 0x1U; | 2333 | return (r >> 1U) & 0x1U; |
2334 | } | ||
2335 | static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_v(u32 r) | ||
2336 | { | ||
2337 | return (r >> 2U) & 0x1U; | ||
2338 | } | ||
2339 | static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(u32 r) | ||
2340 | { | ||
2341 | return (r >> 3U) & 0x1U; | ||
1938 | } | 2342 | } |
1939 | static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) | 2343 | static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) |
1940 | { | 2344 | { |