8 files changed, 286 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index dfa4aaf2..aa435638 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1050,6 +1050,8 @@ struct gpu_ops {
                 void (*pmu_init_perfmon_counter)(struct gk20a *g);
                 void (*pmu_pg_idle_counter_config)(struct gk20a *g, u32 pg_engine_id);
                 u32  (*pmu_read_idle_counter)(struct gk20a *g, u32 counter_id);
+                u32  (*pmu_read_idle_intr_status)(struct gk20a *g);
+                void (*pmu_clear_idle_intr_status)(struct gk20a *g);
                 void (*pmu_reset_idle_counter)(struct gk20a *g, u32 counter_id);
                 void (*pmu_dump_elpg_stats)(struct nvgpu_pmu *pmu);
                 void (*pmu_dump_falcon_stats)(struct nvgpu_pmu *pmu);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
index 71b73d2a..28457634 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
@@ -672,6 +672,46 @@ static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
         return 0x0U;
 }
+static inline u32 pwr_pmu_idle_threshold_r(u32 i)
+{
+        return 0x0010a8a0U + i*4U;
+}
+static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_r(void)
+{
+        return 0x0010a9e8U;
+}
+static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_r(void)
+{
+        return 0x0010a9ecU;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
+{
+        return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
 static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
 {
         return 0x0010a9f0U + i*8U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
index fa232644..2ca1f02b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
@@ -716,6 +716,54 @@ static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
         return 0x0U;
 }
+static inline u32 pwr_pmu_idle_threshold_r(u32 i)
+{
+        return 0x0010a8a0U + i*4U;
+}
+static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_r(void)
+{
+        return 0x0010a9e8U;
+}
+static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_r(void)
+{
+        return 0x0010a9ecU;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
+{
+        return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void)
+{
+        return 0x00000001U;
+}
 static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
 {
         return 0x0010a9f0U + i*8U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
index a9fbbd10..2e75fa6e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
@@ -724,6 +724,54 @@ static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
         return 0x0U;
 }
+static inline u32 pwr_pmu_idle_threshold_r(u32 i)
+{
+        return 0x0010a8a0U + i*4U;
+}
+static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_r(void)
+{
+        return 0x0010a9e8U;
+}
+static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_r(void)
+{
+        return 0x0010a9ecU;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
+{
+        return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void)
+{
+        return 0x00000001U;
+}
 static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
 {
         return 0x0010a9f0U + i*8U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
index 73a5c45c..c160e897 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
@@ -720,6 +720,54 @@ static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
         return 0x0U;
 }
+static inline u32 pwr_pmu_idle_threshold_r(u32 i)
+{
+        return 0x0010a8a0U + i*4U;
+}
+static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_r(void)
+{
+        return 0x0010a9e8U;
+}
+static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_r(void)
+{
+        return 0x0010a9ecU;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
+{
+        return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void)
+{
+        return 0x00000001U;
+}
 static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
 {
         return 0x0010a9f0U + i*8U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
index 4b0b0326..c719226c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
@@ -824,6 +824,54 @@ static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
         return 0x0U;
 }
+static inline u32 pwr_pmu_idle_threshold_r(u32 i)
+{
+        return 0x0010a8a0U + i*4U;
+}
+static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_r(void)
+{
+        return 0x0010a9e8U;
+}
+static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_r(void)
+{
+        return 0x0010a9ecU;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
+{
+        return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void)
+{
+        return 0x00000001U;
+}
 static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
 {
         return 0x0010a9f0U + i*8U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
index c16d44f1..295c6e95 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
@@ -880,6 +880,54 @@ static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
 {
         return 0x0U;
 }
+static inline u32 pwr_pmu_idle_threshold_r(u32 i)
+{
+        return 0x0010a8a0U + i*4U;
+}
+static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_r(void)
+{
+        return 0x0010a9e8U;
+}
+static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_r(void)
+{
+        return 0x0010a9ecU;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
+{
+        return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void)
+{
+        return 0x00000001U;
+}
 static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
 {
         return 0x0010a9f0U + i*8U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
index 7283755a..00194ec0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
@@ -144,6 +144,9 @@ enum {
 #define APCTRL_POWER_BREAKEVEN_DEFAULT_US                       (2000)
 #define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT                    (200)
 
+/* pmu load const defines */
+#define PMU_BUSY_CYCLES_NORM_MAX                (1000U)
+
 /* RPC */
 #define PMU_RPC_EXECUTE(_stat, _pmu, _unit, _func, _prpc, _size)\
         do {                                                 \
@@ -449,6 +452,7 @@ int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu,
 int nvgpu_pmu_init_perfmon_rpc(struct nvgpu_pmu *pmu);
 int nvgpu_pmu_load_norm(struct gk20a *g, u32 *load);
 int nvgpu_pmu_load_update(struct gk20a *g);
+int nvgpu_pmu_busy_cycles_norm(struct gk20a *g, u32 *norm);
 void nvgpu_pmu_reset_load_counters(struct gk20a *g);
 void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
                 u32 *total_cycles);