diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 58 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmu.h | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h | 18 |
3 files changed, 66 insertions, 38 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 6cfb6670..2920e281 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -167,6 +167,44 @@ struct gk20a; | |||
167 | struct nvgpu_falcon; | 167 | struct nvgpu_falcon; |
168 | struct nvgpu_falcon_bl_info; | 168 | struct nvgpu_falcon_bl_info; |
169 | 169 | ||
170 | struct nvgpu_falcon_queue { | ||
171 | |||
172 | /* Queue Type (queue_type) */ | ||
173 | u8 queue_type; | ||
174 | |||
175 | /* used by nvgpu, for command LPQ/HPQ */ | ||
176 | struct nvgpu_mutex mutex; | ||
177 | |||
178 | /* current write position */ | ||
179 | u32 position; | ||
180 | /* physical dmem offset where this queue begins */ | ||
181 | u32 offset; | ||
182 | /* logical queue identifier */ | ||
183 | u32 id; | ||
184 | /* physical queue index */ | ||
185 | u32 index; | ||
186 | /* in bytes */ | ||
187 | u32 size; | ||
188 | /* open-flag */ | ||
189 | u32 oflag; | ||
190 | |||
191 | /* queue type(DMEM-Q/FB-Q) specific ops */ | ||
192 | int (*rewind)(struct nvgpu_falcon *flcn, | ||
193 | struct nvgpu_falcon_queue *queue); | ||
194 | int (*pop)(struct nvgpu_falcon *flcn, | ||
195 | struct nvgpu_falcon_queue *queue, void *data, u32 size, | ||
196 | u32 *bytes_read); | ||
197 | int (*push)(struct nvgpu_falcon *flcn, | ||
198 | struct nvgpu_falcon_queue *queue, void *data, u32 size); | ||
199 | bool (*has_room)(struct nvgpu_falcon *flcn, | ||
200 | struct nvgpu_falcon_queue *queue, u32 size, | ||
201 | bool *need_rewind); | ||
202 | int (*tail)(struct nvgpu_falcon *flcn, | ||
203 | struct nvgpu_falcon_queue *queue, u32 *tail, bool set); | ||
204 | int (*head)(struct nvgpu_falcon *flcn, | ||
205 | struct nvgpu_falcon_queue *queue, u32 *head, bool set); | ||
206 | }; | ||
207 | |||
170 | struct nvgpu_falcon_version_ops { | 208 | struct nvgpu_falcon_version_ops { |
171 | void (*start_cpu_secure)(struct nvgpu_falcon *flcn); | 209 | void (*start_cpu_secure)(struct nvgpu_falcon *flcn); |
172 | void (*write_dmatrfbase)(struct nvgpu_falcon *flcn, u32 addr); | 210 | void (*write_dmatrfbase)(struct nvgpu_falcon *flcn, u32 addr); |
@@ -175,6 +213,11 @@ struct nvgpu_falcon_version_ops { | |||
175 | /* ops which are falcon engine specific */ | 213 | /* ops which are falcon engine specific */ |
176 | struct nvgpu_falcon_engine_dependency_ops { | 214 | struct nvgpu_falcon_engine_dependency_ops { |
177 | int (*reset_eng)(struct gk20a *g); | 215 | int (*reset_eng)(struct gk20a *g); |
216 | int (*queue_head)(struct gk20a *g, struct nvgpu_falcon_queue *queue, | ||
217 | u32 *head, bool set); | ||
218 | int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue, | ||
219 | u32 *tail, bool set); | ||
220 | void (*msgq_tail)(struct gk20a *g, u32 *tail, bool set); | ||
178 | }; | 221 | }; |
179 | 222 | ||
180 | struct nvgpu_falcon_ops { | 223 | struct nvgpu_falcon_ops { |
@@ -259,6 +302,21 @@ void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); | |||
259 | int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn, | 302 | int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn, |
260 | struct nvgpu_falcon_bl_info *bl_info); | 303 | struct nvgpu_falcon_bl_info *bl_info); |
261 | 304 | ||
305 | /* queue public functions */ | ||
306 | int nvgpu_flcn_queue_init(struct nvgpu_falcon *flcn, | ||
307 | struct nvgpu_falcon_queue *queue); | ||
308 | bool nvgpu_flcn_queue_is_empty(struct nvgpu_falcon *flcn, | ||
309 | struct nvgpu_falcon_queue *queue); | ||
310 | int nvgpu_flcn_queue_rewind(struct nvgpu_falcon *flcn, | ||
311 | struct nvgpu_falcon_queue *queue); | ||
312 | int nvgpu_flcn_queue_pop(struct nvgpu_falcon *flcn, | ||
313 | struct nvgpu_falcon_queue *queue, void *data, u32 size, | ||
314 | u32 *bytes_read); | ||
315 | int nvgpu_flcn_queue_push(struct nvgpu_falcon *flcn, | ||
316 | struct nvgpu_falcon_queue *queue, void *data, u32 size); | ||
317 | void nvgpu_flcn_queue_free(struct nvgpu_falcon *flcn, | ||
318 | struct nvgpu_falcon_queue *queue); | ||
319 | |||
262 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); | 320 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); |
263 | 321 | ||
264 | #endif /* __FALCON_H__ */ | 322 | #endif /* __FALCON_H__ */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 507b8133..4d1bf75a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <nvgpu/nvgpu_common.h> | 32 | #include <nvgpu/nvgpu_common.h> |
33 | #include <nvgpu/flcnif_cmn.h> | 33 | #include <nvgpu/flcnif_cmn.h> |
34 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | 34 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> |
35 | #include <nvgpu/falcon.h> | ||
35 | 36 | ||
36 | #define nvgpu_pmu_dbg(g, fmt, args...) \ | 37 | #define nvgpu_pmu_dbg(g, fmt, args...) \ |
37 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##args) | 38 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##args) |
@@ -266,30 +267,6 @@ struct pmu_ucode_desc_v1 { | |||
266 | u32 compressed; | 267 | u32 compressed; |
267 | }; | 268 | }; |
268 | 269 | ||
269 | struct pmu_queue { | ||
270 | |||
271 | /* used by hw, for BIOS/SMI queue */ | ||
272 | u32 mutex_id; | ||
273 | u32 mutex_lock; | ||
274 | /* used by sw, for LPQ/HPQ queue */ | ||
275 | struct nvgpu_mutex mutex; | ||
276 | |||
277 | /* current write position */ | ||
278 | u32 position; | ||
279 | /* physical dmem offset where this queue begins */ | ||
280 | u32 offset; | ||
281 | /* logical queue identifier */ | ||
282 | u32 id; | ||
283 | /* physical queue index */ | ||
284 | u32 index; | ||
285 | /* in bytes */ | ||
286 | u32 size; | ||
287 | |||
288 | /* open-flag */ | ||
289 | u32 oflag; | ||
290 | bool opened; /* opened implies locked */ | ||
291 | }; | ||
292 | |||
293 | struct pmu_mutex { | 270 | struct pmu_mutex { |
294 | u32 id; | 271 | u32 id; |
295 | u32 index; | 272 | u32 index; |
@@ -345,7 +322,7 @@ struct nvgpu_pmu { | |||
345 | 322 | ||
346 | struct pmu_sha1_gid gid_info; | 323 | struct pmu_sha1_gid gid_info; |
347 | 324 | ||
348 | struct pmu_queue queue[PMU_QUEUE_COUNT]; | 325 | struct nvgpu_falcon_queue queue[PMU_QUEUE_COUNT]; |
349 | 326 | ||
350 | struct pmu_sequence *seq; | 327 | struct pmu_sequence *seq; |
351 | unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE]; | 328 | unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE]; |
@@ -450,7 +427,6 @@ int nvgpu_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token); | |||
450 | 427 | ||
451 | int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id, | 428 | int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, u32 id, |
452 | union pmu_init_msg_pmu *init); | 429 | union pmu_init_msg_pmu *init); |
453 | bool nvgpu_pmu_queue_is_empty(struct nvgpu_pmu *pmu, struct pmu_queue *queue); | ||
454 | 430 | ||
455 | /* send a cmd to pmu */ | 431 | /* send a cmd to pmu */ |
456 | int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | 432 | int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h index 2284289e..68df80b4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h | |||
@@ -27,15 +27,11 @@ | |||
27 | * commands to the PMU | 27 | * commands to the PMU |
28 | */ | 28 | */ |
29 | /* write by sw, read by pmu, protected by sw mutex lock */ | 29 | /* write by sw, read by pmu, protected by sw mutex lock */ |
30 | #define PMU_COMMAND_QUEUE_HPQ 0 | 30 | #define PMU_COMMAND_QUEUE_HPQ 0U |
31 | /* write by sw, read by pmu, protected by sw mutex lock */ | 31 | /* write by sw, read by pmu, protected by sw mutex lock */ |
32 | #define PMU_COMMAND_QUEUE_LPQ 1 | 32 | #define PMU_COMMAND_QUEUE_LPQ 1U |
33 | /* read/write by sw/hw, protected by hw pmu mutex, id = 2 */ | ||
34 | #define PMU_COMMAND_QUEUE_BIOS 2 | ||
35 | /* read/write by sw/hw, protected by hw pmu mutex, id = 3 */ | ||
36 | #define PMU_COMMAND_QUEUE_SMI 3 | ||
37 | /* write by pmu, read by sw, accessed by interrupt handler, no lock */ | 33 | /* write by pmu, read by sw, accessed by interrupt handler, no lock */ |
38 | #define PMU_MESSAGE_QUEUE 4 | 34 | #define PMU_MESSAGE_QUEUE 4U |
39 | #define PMU_QUEUE_COUNT 5 | 35 | #define PMU_QUEUE_COUNT 5 |
40 | 36 | ||
41 | #define PMU_IS_COMMAND_QUEUE(id) \ | 37 | #define PMU_IS_COMMAND_QUEUE(id) \ |
@@ -48,15 +44,13 @@ | |||
48 | #define PMU_IS_MESSAGE_QUEUE(id) \ | 44 | #define PMU_IS_MESSAGE_QUEUE(id) \ |
49 | ((id) == PMU_MESSAGE_QUEUE) | 45 | ((id) == PMU_MESSAGE_QUEUE) |
50 | 46 | ||
51 | enum { | 47 | #define OFLAG_READ 0U |
52 | OFLAG_READ = 0, | 48 | #define OFLAG_WRITE 1U |
53 | OFLAG_WRITE | ||
54 | }; | ||
55 | 49 | ||
56 | #define QUEUE_SET (true) | 50 | #define QUEUE_SET (true) |
57 | #define QUEUE_GET (false) | 51 | #define QUEUE_GET (false) |
58 | 52 | ||
59 | #define QUEUE_ALIGNMENT (4) | 53 | #define QUEUE_ALIGNMENT (4U) |
60 | 54 | ||
61 | /* An enumeration containing all valid logical mutex identifiers */ | 55 | /* An enumeration containing all valid logical mutex identifiers */ |
62 | enum { | 56 | enum { |