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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/mm.h8
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h6
2 files changed, 6 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h
index bfce243c..45641092 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/mm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h
@@ -202,14 +202,12 @@ static inline int bar1_aperture_size_mb_gk20a(void)
202 * When not using unified address spaces, the bottom 56GB of the space are used 202 * When not using unified address spaces, the bottom 56GB of the space are used
203 * for small pages, and the remaining high memory is used for large pages. 203 * for small pages, and the remaining high memory is used for large pages.
204 */ 204 */
205static inline u64 __nv_gmmu_va_small_page_limit(void) 205static inline u64 nvgpu_gmmu_va_small_page_limit(void)
206{ 206{
207 return ((u64)SZ_1G * 56); 207 return ((u64)SZ_1G * 56U);
208} 208}
209 209
210u32 __get_pte_size_fixed_map(struct vm_gk20a *vm, 210u32 nvgpu_vm_get_pte_size(struct vm_gk20a *vm, u64 base, u64 size);
211 u64 base, u64 size);
212u32 __get_pte_size(struct vm_gk20a *vm, u64 base, u64 size);
213 211
214void nvgpu_init_mm_ce_context(struct gk20a *g); 212void nvgpu_init_mm_ce_context(struct gk20a *g);
215int nvgpu_init_mm_support(struct gk20a *g); 213int nvgpu_init_mm_support(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
index 2b8a5fd1..07a088f0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -56,7 +56,7 @@ enum nvgpu_aperture {
56 APERTURE_SYSMEM, 56 APERTURE_SYSMEM,
57 57
58 /* Don't use directly. Use APERTURE_SYSMEM, this is used internally. */ 58 /* Don't use directly. Use APERTURE_SYSMEM, this is used internally. */
59 __APERTURE_SYSMEM_COH, 59 APERTURE_SYSMEM_COH,
60 60
61 APERTURE_VIDMEM 61 APERTURE_VIDMEM
62}; 62};
@@ -211,7 +211,7 @@ static inline const char *nvgpu_aperture_str(struct gk20a *g,
211 return "INVAL"; 211 return "INVAL";
212 case APERTURE_SYSMEM: 212 case APERTURE_SYSMEM:
213 return "SYSMEM"; 213 return "SYSMEM";
214 case __APERTURE_SYSMEM_COH: 214 case APERTURE_SYSMEM_COH:
215 return "SYSCOH"; 215 return "SYSCOH";
216 case APERTURE_VIDMEM: 216 case APERTURE_VIDMEM:
217 return "VIDMEM"; 217 return "VIDMEM";
@@ -340,7 +340,7 @@ void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
340u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem); 340u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem);
341u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem); 341u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem);
342 342
343u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, 343u32 nvgpu_aperture_mask_coh(struct gk20a *g, enum nvgpu_aperture aperture,
344 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); 344 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask);
345u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, 345u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem,
346 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); 346 u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask);